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Fri, 30 May 2025 00:15:14 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG6gJi0iaX4mZIEKHwXNMovJS5+ablju5w00ZKAi2F9OioPz0xy9naqPdUuhjV8QJR/n29rWg== X-Received: by 2002:a17:907:9726:b0:ad8:adf5:f7f2 with SMTP id a640c23a62f3a-adb36be2347mr108540866b.31.1748589313422; Fri, 30 May 2025 00:15:13 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Xiaoyao Li , Zhao Liu Subject: [PULL 56/77] i386/tdx: Implement adjust_cpuid_features() for TDX Date: Fri, 30 May 2025 09:12:26 +0200 Message-ID: <20250530071250.2050910-57-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250530071250.2050910-1-pbonzini@redhat.com> References: <20250530071250.2050910-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -49 X-Spam_score: -5.0 X-Spam_bar: ----- X-Spam_report: (-5.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.902, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1748590006846116600 Content-Type: text/plain; charset="utf-8" From: Xiaoyao Li Maintain a TDX specific supported CPUID set, and use it to mask the common supported CPUID value of KVM. It can avoid newly added supported features (reported via KVM_GET_SUPPORTED_CPUID) for common VMs being falsely reported as supported for TDX. As the first step, initialize the TDX supported CPUID set with all the configurable CPUID bits. It's not complete because there are other CPUID bits are supported for TDX but not reported as directly configurable. E.g. the XFAM related bits, attribute related bits and fixed-1 bits. They will be handled in the future. Also, what matters are the CPUID bits related to QEMU's feature word. Only mask the CPUID leafs which are feature word leaf. Signed-off-by: Xiaoyao Li Reviewed-by: Zhao Liu Link: https://lore.kernel.org/r/20250508150002.689633-45-xiaoyao.li@intel.c= om Signed-off-by: Paolo Bonzini --- target/i386/cpu.h | 1 + target/i386/kvm/kvm_i386.h | 1 + target/i386/cpu.c | 16 ++++++++++++++++ target/i386/kvm/kvm.c | 2 +- target/i386/kvm/tdx.c | 34 ++++++++++++++++++++++++++++++++++ 5 files changed, 53 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index ad0e3d8cdd0..7ffcf91b014 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2502,6 +2502,7 @@ void cpu_set_apic_feature(CPUX86State *env); void host_cpuid(uint32_t function, uint32_t count, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx= ); bool cpu_has_x2apic_feature(CPUX86State *env); +bool is_feature_word_cpuid(uint32_t feature, uint32_t index, int reg); =20 static inline bool x86_has_cpuid_0x1f(X86CPU *cpu) { diff --git a/target/i386/kvm/kvm_i386.h b/target/i386/kvm/kvm_i386.h index dc696cb7238..484a1de84d5 100644 --- a/target/i386/kvm/kvm_i386.h +++ b/target/i386/kvm/kvm_i386.h @@ -62,6 +62,7 @@ void kvm_update_msi_routes_all(void *private, bool global, struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid, uint32_t function, uint32_t index); +uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg); uint32_t kvm_x86_build_cpuid(CPUX86State *env, struct kvm_cpuid_entry2 *en= tries, uint32_t cpuid_i); #endif /* CONFIG_KVM */ diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 6a97d7549ec..5aacb62f081 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1678,6 +1678,22 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D= { }, }; =20 +bool is_feature_word_cpuid(uint32_t feature, uint32_t index, int reg) +{ + FeatureWordInfo *wi; + FeatureWord w; + + for (w =3D 0; w < FEATURE_WORDS; w++) { + wi =3D &feature_word_info[w]; + if (wi->type =3D=3D CPUID_FEATURE_WORD && wi->cpuid.eax =3D=3D fea= ture && + (!wi->cpuid.needs_ecx || wi->cpuid.ecx =3D=3D index) && + wi->cpuid.reg =3D=3D reg) { + return true; + } + } + return false; +} + typedef struct FeatureMask { FeatureWord index; uint64_t mask; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 0d474634312..cd87f5502a3 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -394,7 +394,7 @@ static bool host_tsx_broken(void) =20 /* Returns the value for a specific register on the cpuid entry */ -static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int re= g) +uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg) { uint32_t ret =3D 0; switch (reg) { diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index 68ed3b9f987..e3b7ad6d146 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/tdx.c @@ -45,6 +45,7 @@ static TdxGuest *tdx_guest; =20 static struct kvm_tdx_capabilities *tdx_caps; +static struct kvm_cpuid2 *tdx_supported_cpuid; =20 /* Valid after kvm_arch_init()->confidential_guest_kvm_init()->tdx_kvm_ini= t() */ bool is_tdx_vm(void) @@ -366,6 +367,20 @@ static Notifier tdx_machine_done_notify =3D { .notify =3D tdx_finalize_vm, }; =20 +static void tdx_setup_supported_cpuid(void) +{ + if (tdx_supported_cpuid) { + return; + } + + tdx_supported_cpuid =3D g_malloc0(sizeof(*tdx_supported_cpuid) + + KVM_MAX_CPUID_ENTRIES * sizeof(struct kvm_cpuid_entry2= )); + + memcpy(tdx_supported_cpuid->entries, tdx_caps->cpuid.entries, + tdx_caps->cpuid.nent * sizeof(struct kvm_cpuid_entry2)); + tdx_supported_cpuid->nent =3D tdx_caps->cpuid.nent; +} + static int tdx_kvm_init(ConfidentialGuestSupport *cgs, Error **errp) { MachineState *ms =3D MACHINE(qdev_get_machine()); @@ -403,6 +418,8 @@ static int tdx_kvm_init(ConfidentialGuestSupport *cgs, = Error **errp) } } =20 + tdx_setup_supported_cpuid(); + /* TDX relies on KVM_HC_MAP_GPA_RANGE to handle TDG.VP.VMCALL = */ if (!kvm_enable_hypercall(BIT_ULL(KVM_HC_MAP_GPA_RANGE))) { return -EOPNOTSUPP; @@ -440,6 +457,22 @@ static void tdx_cpu_instance_init(X86ConfidentialGuest= *cg, CPUState *cpu) x86cpu->enable_cpuid_0x1f =3D true; } =20 +static uint32_t tdx_adjust_cpuid_features(X86ConfidentialGuest *cg, + uint32_t feature, uint32_t index, + int reg, uint32_t value) +{ + struct kvm_cpuid_entry2 *e; + + if (is_feature_word_cpuid(feature, index, reg)) { + e =3D cpuid_find_entry(tdx_supported_cpuid, feature, index); + if (e) { + value &=3D cpuid_entry_get_reg(e, reg); + } + } + + return value; +} + static int tdx_validate_attributes(TdxGuest *tdx, Error **errp) { if ((tdx->attributes & ~tdx_caps->supported_attrs)) { @@ -834,4 +867,5 @@ static void tdx_guest_class_init(ObjectClass *oc, const= void *data) klass->kvm_init =3D tdx_kvm_init; x86_klass->kvm_type =3D tdx_kvm_type; x86_klass->cpu_instance_init =3D tdx_cpu_instance_init; + x86_klass->adjust_cpuid_features =3D tdx_adjust_cpuid_features; } --=20 2.49.0