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Wed, 28 May 2025 13:01:55 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@dabbelt.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 4/4] hw/riscv/server_platform_ref.c: add riscv-iommu-sys Date: Wed, 28 May 2025 17:01:29 -0300 Message-ID: <20250528200129.1548259-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250528200129.1548259-1-dbarboza@ventanamicro.com> References: <20250528200129.1548259-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::82c; envelope-from=dbarboza@ventanamicro.com; helo=mail-qt1-x82c.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1748463015528116600 Content-Type: text/plain; charset="utf-8" Add an always present IOMMU platform device for the rvsp-ref board. The IRQs being used are similar to what the 'virt' board is using: IRQs 36 to 39, one IRQ for queue. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- hw/riscv/Kconfig | 1 + hw/riscv/server_platform_ref.c | 78 ++++++++++++++++++++++++++++++++-- 2 files changed, 75 insertions(+), 4 deletions(-) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index f626774c52..cd70095687 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -82,6 +82,7 @@ config SERVER_PLATFORM_REF select RISCV_ACLINT select RISCV_APLIC select RISCV_IMSIC + select RISCV_IOMMU =20 config SHAKTI_C bool diff --git a/hw/riscv/server_platform_ref.c b/hw/riscv/server_platform_ref.c index 5102286103..9740b395f6 100644 --- a/hw/riscv/server_platform_ref.c +++ b/hw/riscv/server_platform_ref.c @@ -31,6 +31,8 @@ #include "hw/riscv/riscv_hart.h" #include "hw/riscv/boot.h" #include "hw/riscv/numa.h" +#include "hw/riscv/iommu.h" +#include "hw/riscv/riscv-iommu-bits.h" #include "hw/intc/riscv_aclint.h" #include "hw/intc/riscv_aplic.h" #include "hw/intc/riscv_imsic.h" @@ -94,6 +96,7 @@ enum { RVSP_MROM, RVSP_RESET_SYSCON, RVSP_RTC, + RVSP_IOMMU_SYS, RVSP_ACLINT, RVSP_APLIC_M, RVSP_APLIC_S, @@ -112,6 +115,7 @@ enum { RVSP_UART0_IRQ =3D 10, RVSP_RTC_IRQ =3D 11, RVSP_PCIE_IRQ =3D 0x20, /* 32 to 35 */ + IOMMU_SYS_IRQ =3D 0x24 /* 36 to 39 */ }; =20 /* @@ -141,6 +145,7 @@ static const MemMapEntry rvsp_ref_memmap[] =3D { [RVSP_MROM] =3D { 0x1000, 0xf000 }, [RVSP_RESET_SYSCON] =3D { 0x100000, 0x1000 }, [RVSP_RTC] =3D { 0x101000, 0x1000 }, + [RVSP_IOMMU_SYS] =3D { 0102000, 0x1000 }, [RVSP_ACLINT] =3D { 0x2000000, 0x10000 }, [RVSP_PCIE_PIO] =3D { 0x3000000, 0x10000 }, [RVSP_APLIC_M] =3D { 0xc000000, APLIC_SIZE(RVSP_CPUS_MAX) }, @@ -638,9 +643,51 @@ static void create_fdt_sockets(RVSPMachineState *s, co= nst MemMapEntry *memmap, riscv_socket_fdt_write_distance_matrix(ms); } =20 +static void create_fdt_iommu_sys(RVSPMachineState *s, uint32_t irq_chip, + uint32_t msi_phandle, + uint32_t *iommu_sys_phandle) +{ + const char comp[] =3D "riscv,iommu"; + void *fdt =3D MACHINE(s)->fdt; + uint32_t iommu_phandle; + g_autofree char *iommu_node =3D NULL; + hwaddr addr =3D s->memmap[RVSP_IOMMU_SYS].base; + hwaddr size =3D s->memmap[RVSP_IOMMU_SYS].size; + uint32_t iommu_irq_map[RISCV_IOMMU_INTR_COUNT] =3D { + IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_CQ, + IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_FQ, + IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PM, + IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PQ, + }; + + iommu_node =3D g_strdup_printf("/soc/iommu@%"HWADDR_PRIx, + s->memmap[RVSP_IOMMU_SYS].base); + iommu_phandle =3D qemu_fdt_alloc_phandle(fdt); + qemu_fdt_add_subnode(fdt, iommu_node); + + qemu_fdt_setprop(fdt, iommu_node, "compatible", comp, sizeof(comp)); + qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1); + qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle); + + qemu_fdt_setprop_cells(fdt, iommu_node, "reg", + addr >> 32, addr, size >> 32, size); + qemu_fdt_setprop_cell(fdt, iommu_node, "interrupt-parent", irq_chip); + + qemu_fdt_setprop_cells(fdt, iommu_node, "interrupts", + iommu_irq_map[0], FDT_IRQ_TYPE_EDGE_LOW, + iommu_irq_map[1], FDT_IRQ_TYPE_EDGE_LOW, + iommu_irq_map[2], FDT_IRQ_TYPE_EDGE_LOW, + iommu_irq_map[3], FDT_IRQ_TYPE_EDGE_LOW); + + qemu_fdt_setprop_cell(fdt, iommu_node, "msi-parent", msi_phandle); + + *iommu_sys_phandle =3D iommu_phandle; +} + static void create_fdt_pcie(RVSPMachineState *s, const MemMapEntry *memmap, uint32_t irq_pcie_phandle, - uint32_t msi_pcie_phandle) + uint32_t msi_pcie_phandle, + uint32_t iommu_sys_phandle) { g_autofree char *name =3D NULL; MachineState *ms =3D MACHINE(s); @@ -675,6 +722,10 @@ static void create_fdt_pcie(RVSPMachineState *s, const= MemMapEntry *memmap, memmap[RVSP_PCIE_MMIO_HIGH].size); =20 create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle); + + qemu_fdt_setprop_cells(ms->fdt, name, "iommu-map", + 0, iommu_sys_phandle, 0, 0, 0, + iommu_sys_phandle, 0, 0xffff); } =20 static void create_fdt_reset(RVSPMachineState *s, const MemMapEntry *memma= p, @@ -768,12 +819,16 @@ static void create_fdt_flash(RVSPMachineState *s, con= st MemMapEntry *memmap) static void finalize_fdt(RVSPMachineState *s) { uint32_t phandle =3D 1, irq_mmio_phandle =3D 1, msi_pcie_phandle =3D 1; - uint32_t irq_pcie_phandle =3D 1; + uint32_t irq_pcie_phandle =3D 1, iommu_sys_phandle; =20 create_fdt_sockets(s, rvsp_ref_memmap, &phandle, &irq_mmio_phandle, &irq_pcie_phandle, &msi_pcie_phandle); =20 - create_fdt_pcie(s, rvsp_ref_memmap, irq_pcie_phandle, msi_pcie_phandle= ); + create_fdt_iommu_sys(s, irq_mmio_phandle, msi_pcie_phandle, + &iommu_sys_phandle); + + create_fdt_pcie(s, rvsp_ref_memmap, irq_pcie_phandle, + msi_pcie_phandle, iommu_sys_phandle); =20 create_fdt_reset(s, rvsp_ref_memmap, &phandle); =20 @@ -1078,7 +1133,7 @@ static void rvsp_ref_machine_init(MachineState *machi= ne) MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); MemoryRegion *reset_syscon_io =3D g_new(MemoryRegion, 1); - DeviceState *mmio_irqchip, *pcie_irqchip; + DeviceState *mmio_irqchip, *pcie_irqchip, *iommu_sys; int i, base_hartid, hart_count; int socket_count =3D riscv_socket_count(machine); =20 @@ -1196,6 +1251,21 @@ static void rvsp_ref_machine_init(MachineState *mach= ine) create_fdt(s, memmap); } =20 + iommu_sys =3D qdev_new(TYPE_RISCV_IOMMU_SYS); + object_property_set_uint(OBJECT(iommu_sys), "addr", + s->memmap[RVSP_IOMMU_SYS].base, + &error_fatal); + + object_property_set_uint(OBJECT(iommu_sys), "base-irq", + IOMMU_SYS_IRQ, + &error_fatal); + + object_property_set_link(OBJECT(iommu_sys), "irqchip", + OBJECT(mmio_irqchip), + &error_fatal); + + sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu_sys), &error_fatal); + s->machine_done.notify =3D rvsp_ref_machine_done; qemu_add_machine_init_done_notifier(&s->machine_done); } --=20 2.49.0