From nobody Sat Nov 15 18:49:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1748457886; cv=none; d=zohomail.com; s=zohoarc; b=IKM8GfQGdTbTpf6whTvIVp0HOptA62dhTxcKe9GF9DhIOO91Sg7j9KFkx09rEy0Cz9nL/noBoho6YTULOLoGqX1YoJ1zkxpT8mw/56mxHFaFygsfw68+WRthgxX0R2JJFJNUXML6rnddFnHXl4PgkzJHNLyGe2l4T17hy0ZXY+U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1748457886; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=N1EvtJG5mNTqGGcNevZ83Z0Oy3cFvMJyHR4hO17x8rQ=; b=kuFXIBSBcbHQnEQNc4mic/3DuJuLag6+TiCEIEJRbvsLKFQHHk9vzjpHgyQelEqTjVt5g0vuJN1Ikz8lSZsU/m4T0A5LQLriQt24l+PZrQgDR6/HAtD4+N8EmRMqQO6bjvL32RKIAgE40/0beX0mQ/PZ99AFsEHtFOIWsoPoDhQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1748457886652458.6201250001633; Wed, 28 May 2025 11:44:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uKLlO-0006Uy-Gs; Wed, 28 May 2025 14:44:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uKLlD-0006N8-BN for qemu-devel@nongnu.org; Wed, 28 May 2025 14:44:20 -0400 Received: from mail-vk1-xa35.google.com ([2607:f8b0:4864:20::a35]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uKLlB-0000NH-Nd for qemu-devel@nongnu.org; Wed, 28 May 2025 14:44:19 -0400 Received: by mail-vk1-xa35.google.com with SMTP id 71dfb90a1353d-5259331b31eso32113e0c.0 for ; Wed, 28 May 2025 11:44:17 -0700 (PDT) Received: from grind.. ([191.255.35.190]) by smtp.gmail.com with ESMTPSA id 71dfb90a1353d-53066945971sm1568512e0c.30.2025.05.28.11.44.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 May 2025 11:44:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1748457856; x=1749062656; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=N1EvtJG5mNTqGGcNevZ83Z0Oy3cFvMJyHR4hO17x8rQ=; b=muuGdoASU6EQL6LZpMZy7CNxcnQXGB7lxVcHPsXIsJ/MZhTqyWSierFP2HEcfelYcs neEFuMMgzkVSda3yjmWWndlYvBMhAxT3Ujy2EE7okivh4D1N+p+5TzXqjPS6CAqSqam7 uZMB6ioWQuWwz1UDfTMqIy9tkukDaCXu0pXqc3L7JIEAeNG05Ur+6l/Kcxb7Io2DqVMR 3Wmm9BZJQvnEdUpwdm0QM7g9rMgTaG2HnjT4+tkFpLFWGUop3XYn1vd+rv+BfxdxInSf GnQbCUbAdIjL4f3KVcOWqcMidNyqzgr+7C9oyZEBrjws1U8kSxPl8bi1pDD0P/zlEkAu MIQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748457856; x=1749062656; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=N1EvtJG5mNTqGGcNevZ83Z0Oy3cFvMJyHR4hO17x8rQ=; b=EwMGyXxE3VjhuIx+cxI//2RJNeZs1bvbE7d4DS3tSjyJ2+i+EWan7WRkUYk6zcMmxy cJJrkQm3dTeRnaguhWgBJLufnWZIPZX4e5QCPfog2h1slMxAlbQaXWGsURbbZJRva+t0 yn9b9HDwI0SWrLb15+FGHG3QU7pdxepb+xCIa+Bxqu9+gCJTSBEyDY38buHBYzH9+Qfn 99ii9sFfJfkRTrjrL8E0cv/NobPv/++Qq/VYi4OrKg3fMHGPoj/H24WPqmFBd0ceLPh6 XRRopP2nKrhovYbLhFZHYtq2aV00H1hNAvAM+bDE2xNbBi7wqblWjT8vChKMwkc0PBPu 4xDA== X-Gm-Message-State: AOJu0YwzMrYzCCgEAHNjWEUM/ImDjc97ob6hczmPW4IFw3LTk+YSOZbg a/dEnw01F7c80LR69X7BAsozEUuYNjeTqe8wBA1qZ1d5ugNhGK8hHMwAtSqgbWalkBlVNGHVYvU re5qc X-Gm-Gg: ASbGncsxFKQRqkxEVwPMjLjEGh55CeBc3jfAaI23QK83cAYQOhHL9aJHnLmpJDRDQSu B8PzU0azuTfmC7vIqOTBu3+AwVjUuUEa9CIe7bB2UeGnTE8Yf2sNJNj0RgyctJPbRvn4XU3JJGf BcLGGtYzGMgLiDhhbDySFBFjg9Ob7HYwWvrEFGuBUlbdw/SRkPFwduiLjJ/nIabTTtd5/5HV3IR lI3GWtcdKo6TJvilFPsgVaD50JV0PZY/07LsSaes+A7fph1HPB3yAJhU8XJSx2S69z5uVn3Kll4 XgItOH3NOt7MuYzdwcfZ1lZTNEh7MgCa7267dtQROl04CGDE7hWnng== X-Google-Smtp-Source: AGHT+IEZsqzOu2500pJHUdm7HK5pcS8IkH0h3efbu7mqBCrgxiKayChMsFZfot6DUH6UBJR9vFmMtA== X-Received: by 2002:a05:6122:6799:b0:52f:bef8:deee with SMTP id 71dfb90a1353d-52fbef8df52mr6343782e0c.8.1748457856087; Wed, 28 May 2025 11:44:16 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@dabbelt.com, ajones@ventanamicro.com, bjorn@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v2 1/3] target/riscv/tcg: restrict satp_mode changes in cpu_set_profile Date: Wed, 28 May 2025 15:44:05 -0300 Message-ID: <20250528184407.1451983-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250528184407.1451983-1-dbarboza@ventanamicro.com> References: <20250528184407.1451983-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::a35; envelope-from=dbarboza@ventanamicro.com; helo=mail-vk1-xa35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1748457887489116600 We're changing 'mmu' to true regardless of whether the profile is being enabled or not, and at the same time we're changing satp_mode to profile->enabled. This will promote a situation where we'll set mmu=3Don without a virtual memory mode, which is a mistake. Only touch 'mmu' and satp_mode if the profile is being enabled. Suggested-by: Andrew Jones Fixes: 55398025e7 ("target/riscv: add satp_mode profile support") Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Bj=C3=B6rn T=C3=B6pel Tested-by: Bj=C3=B6rn T=C3=B6pel --- target/riscv/tcg/tcg-cpu.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index a84cca48fc..857c625580 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -1339,16 +1339,16 @@ static void cpu_set_profile(Object *obj, Visitor *v= , const char *name, =20 if (profile->enabled) { cpu->env.priv_ver =3D profile->priv_spec; - } =20 #ifndef CONFIG_USER_ONLY - if (profile->satp_mode !=3D RISCV_PROFILE_ATTR_UNUSED) { - object_property_set_bool(obj, "mmu", true, NULL); - const char *satp_prop =3D satp_mode_str(profile->satp_mode, - riscv_cpu_is_32bit(cpu)); - object_property_set_bool(obj, satp_prop, profile->enabled, NULL); - } + if (profile->satp_mode !=3D RISCV_PROFILE_ATTR_UNUSED) { + object_property_set_bool(obj, "mmu", true, NULL); + const char *satp_prop =3D satp_mode_str(profile->satp_mode, + riscv_cpu_is_32bit(cpu)); + object_property_set_bool(obj, satp_prop, true, NULL); + } #endif + } =20 for (i =3D 0; misa_bits[i] !=3D 0; i++) { uint32_t bit =3D misa_bits[i]; --=20 2.49.0 From nobody Sat Nov 15 18:49:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1748457943; cv=none; d=zohomail.com; s=zohoarc; b=OD1DGbn2FtU4gVWFGM/h68ysUc5xyFC4Ax3YfbM8n82n1v+tL67/kkWY8BDWYPlNMpNECufyXFTMC4nb+7tDERKeGgjOFH/TUMtNMBSx7FJI/lqrPUoZwGxV/FkXnPB55TC2axMAYY8OwXn2DAcrbRzJP/OeTY24r6rK4oy/uiE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1748457943; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=3xvfwNtjb2BZpidyYY9f3GoOnOR8S7xgGDRa12AkpsY=; b=mWzy/KD2XA1pypqqiLqZxPYqT8zOkHp0m2Kz997PiFnb0y3NhOdQKpInKoseBVC0suzp9G7caLQYhXdCMvs8t1o6j4/gFEcDwDfeOykvweF/Ps8PC0V8jyMG+OvWy5lB5lBSMfHeWCHXMhsvLskW1fzQ3V0Ozo7Fd3eoooRI0K4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174845794359451.99485511846865; Wed, 28 May 2025 11:45:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uKLlP-0006X0-2y; Wed, 28 May 2025 14:44:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uKLlH-0006S5-F2 for qemu-devel@nongnu.org; Wed, 28 May 2025 14:44:24 -0400 Received: from mail-vk1-xa34.google.com ([2607:f8b0:4864:20::a34]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uKLlE-0000ON-Mt for qemu-devel@nongnu.org; Wed, 28 May 2025 14:44:23 -0400 Received: by mail-vk1-xa34.google.com with SMTP id 71dfb90a1353d-52e728960c3so30477e0c.2 for ; Wed, 28 May 2025 11:44:20 -0700 (PDT) Received: from grind.. ([191.255.35.190]) by smtp.gmail.com with ESMTPSA id 71dfb90a1353d-53066945971sm1568512e0c.30.2025.05.28.11.44.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 May 2025 11:44:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1748457859; x=1749062659; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3xvfwNtjb2BZpidyYY9f3GoOnOR8S7xgGDRa12AkpsY=; b=D0VmeCxo3yx+DpjDAn4t4d3O3J0rADAONCPDGlMXUAMuSzJ1gQ2TbTBgZs6RkcUtLi EtjFNLXr9qDp94hUsTCfnVcW8iCEshjzc0QqQtJrRI89XPVtcU4VNXqIP2LF0knW2U3O VmXDLnFXMPwnsgJMiLQHK2U6r40L0W8oddGQy01JD8xl5bh8zfNhMEosb2jnML+phWPu d3VwBrJ8+BYaVrwGUMMB5l42H33YHNNei/eq1td8suMKyOemUoLkbqXETXx/pXVoeGG9 W8pXpNseXTRBb3Jok2l+nnTqSXvQcJTUkHUt4A1DI/QPYt1h3haOVkVIPGVuJ5wvSG5j qtmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748457859; x=1749062659; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3xvfwNtjb2BZpidyYY9f3GoOnOR8S7xgGDRa12AkpsY=; b=PiVrSQuuwXQVu6ce8WUap91l5RfIJLFwYAWB65wGkzWoXeWcRJgHVWuKsNVc8gWqNF 1K9+81PiiWoWLtDeX5Sf9fyp2Era/sA0LQf12+HoCoSqRKEetd9XtahFIxQsQ+51A622 7TrFS8Rvj9hv89bwB+/kC2G80wVSw3TCenIcEVCP2UT/siDGlhch66GlgZep4SrP0TqC IzoyaiJVn4GOJdn1DUM2M/D7NIM/fY27npQ0mGUmlSr4EgSnYo/OqiTfxnFmVJ2mILp1 vJxlXwKvQj228xHnheu+rJ0lVUD4KiCYDeahTGy1qpxWfpAkRd1Vd2vJslmL8m9b7/Kc +UaA== X-Gm-Message-State: AOJu0YyDG5c5FYAkhDdSapQCrn2tZTxss2y9+eCIV1LU2PQnvLe739ce Kakh4BGU5/v5+RCoTskKsxyeYAwOb2GjVH3/qjDLAJKANh4WNWrBzJxGddZ6y5Qb1wDEeOy7H2A 5cG3K X-Gm-Gg: ASbGncvWgO1lKiuO1mT+wOkqxyNmWoKV1uI2K2BHgZazkbzSua70jofcQYiERVWEQEf YfM9sMYlx7Gth6foFyiVX63sU3V4scsbshr4ABFLiNr4jmeB/x0reclFO7l7f/QuavsqCu8S5Vl wVpb5IX4UG053868Lpy+nFNemnxMVqKkL3Uh+Jswl3eIUnzEI+4VFU++20zIiQyZ32w9lZaGQ3Y uzv42h39QOBv7J4UX4f03v2KoJAoKrIsy6FcWiE5WXfqz8ufFFIBYaQZ+PY08ix04SIvvUJeP70 zJJgGD0YnnikUhmHFpSjg4PHoSCNJM2cFlHyCpIhc+PzybN5BUCz4A== X-Google-Smtp-Source: AGHT+IEctjboTfnWlSPUm5JNhoGK86EgFmpw9vg5pThxW1BrM8ElHLfFYHBIs97vOwNs7iC2/aWzkA== X-Received: by 2002:a05:6122:d9e:b0:520:64ea:c479 with SMTP id 71dfb90a1353d-52f2c5ae0damr13794226e0c.10.1748457859211; Wed, 28 May 2025 11:44:19 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@dabbelt.com, ajones@ventanamicro.com, bjorn@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v2 2/3] target/riscv/tcg: decouple profile enablement from user prop Date: Wed, 28 May 2025 15:44:06 -0300 Message-ID: <20250528184407.1451983-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250528184407.1451983-1-dbarboza@ventanamicro.com> References: <20250528184407.1451983-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::a34; envelope-from=dbarboza@ventanamicro.com; helo=mail-vk1-xa34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1748457944483116600 We have code in riscv_cpu_add_profiles() to enable a profile right away in case a CPU chose the profile during its cpu_init(). But we're using the user callback option to do so, setting profile->user_set. Create a new helper that does all the grunt work to enable/disable a given profile. Use this new helper in the cases where we want a CPU to be compatible to a certain profile, leaving the user callback to be used exclusively by users. Fixes: fba92a92e3 ("target/riscv: add 'rva22u64' CPU") Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Bj=C3=B6rn T=C3=B6pel Tested-by: Bj=C3=B6rn T=C3=B6pel --- target/riscv/tcg/tcg-cpu.c | 127 +++++++++++++++++++------------------ 1 file changed, 67 insertions(+), 60 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 857c625580..f8489d79d7 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -1140,6 +1140,70 @@ static bool riscv_cpu_is_generic(Object *cpu_obj) return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; } =20 +static void riscv_cpu_set_profile(RISCVCPU *cpu, + RISCVCPUProfile *profile, + bool enabled) +{ + int i, ext_offset; + + if (profile->u_parent !=3D NULL) { + riscv_cpu_set_profile(cpu, profile->u_parent, enabled); + } + + if (profile->s_parent !=3D NULL) { + riscv_cpu_set_profile(cpu, profile->s_parent, enabled); + } + + profile->enabled =3D enabled; + + if (profile->enabled) { + cpu->env.priv_ver =3D profile->priv_spec; + +#ifndef CONFIG_USER_ONLY + if (profile->satp_mode !=3D RISCV_PROFILE_ATTR_UNUSED) { + object_property_set_bool(OBJECT(cpu), "mmu", true, NULL); + const char *satp_prop =3D satp_mode_str(profile->satp_mode, + riscv_cpu_is_32bit(cpu)); + object_property_set_bool(OBJECT(cpu), satp_prop, true, NULL); + } +#endif + } + + for (i =3D 0; misa_bits[i] !=3D 0; i++) { + uint32_t bit =3D misa_bits[i]; + + if (!(profile->misa_ext & bit)) { + continue; + } + + if (bit =3D=3D RVI && !profile->enabled) { + /* + * Disabling profiles will not disable the base + * ISA RV64I. + */ + continue; + } + + cpu_misa_ext_add_user_opt(bit, profile->enabled); + riscv_cpu_write_misa_bit(cpu, bit, profile->enabled); + } + + for (i =3D 0; profile->ext_offsets[i] !=3D RISCV_PROFILE_EXT_LIST_END;= i++) { + ext_offset =3D profile->ext_offsets[i]; + + if (profile->enabled) { + if (cpu_cfg_offset_is_named_feat(ext_offset)) { + riscv_cpu_enable_named_feat(cpu, ext_offset); + } + + cpu_bump_multi_ext_priv_ver(&cpu->env, ext_offset); + } + + cpu_cfg_ext_add_user_opt(ext_offset, profile->enabled); + isa_ext_update_enabled(cpu, ext_offset, profile->enabled); + } +} + /* * We'll get here via the following path: * @@ -1306,7 +1370,6 @@ static void cpu_set_profile(Object *obj, Visitor *v, = const char *name, RISCVCPUProfile *profile =3D opaque; RISCVCPU *cpu =3D RISCV_CPU(obj); bool value; - int i, ext_offset; =20 if (riscv_cpu_is_vendor(obj)) { error_setg(errp, "Profile %s is not available for vendor CPUs", @@ -1325,64 +1388,8 @@ static void cpu_set_profile(Object *obj, Visitor *v,= const char *name, } =20 profile->user_set =3D true; - profile->enabled =3D value; - - if (profile->u_parent !=3D NULL) { - object_property_set_bool(obj, profile->u_parent->name, - profile->enabled, NULL); - } - - if (profile->s_parent !=3D NULL) { - object_property_set_bool(obj, profile->s_parent->name, - profile->enabled, NULL); - } - - if (profile->enabled) { - cpu->env.priv_ver =3D profile->priv_spec; - -#ifndef CONFIG_USER_ONLY - if (profile->satp_mode !=3D RISCV_PROFILE_ATTR_UNUSED) { - object_property_set_bool(obj, "mmu", true, NULL); - const char *satp_prop =3D satp_mode_str(profile->satp_mode, - riscv_cpu_is_32bit(cpu)); - object_property_set_bool(obj, satp_prop, true, NULL); - } -#endif - } - - for (i =3D 0; misa_bits[i] !=3D 0; i++) { - uint32_t bit =3D misa_bits[i]; - - if (!(profile->misa_ext & bit)) { - continue; - } =20 - if (bit =3D=3D RVI && !profile->enabled) { - /* - * Disabling profiles will not disable the base - * ISA RV64I. - */ - continue; - } - - cpu_misa_ext_add_user_opt(bit, profile->enabled); - riscv_cpu_write_misa_bit(cpu, bit, profile->enabled); - } - - for (i =3D 0; profile->ext_offsets[i] !=3D RISCV_PROFILE_EXT_LIST_END;= i++) { - ext_offset =3D profile->ext_offsets[i]; - - if (profile->enabled) { - if (cpu_cfg_offset_is_named_feat(ext_offset)) { - riscv_cpu_enable_named_feat(cpu, ext_offset); - } - - cpu_bump_multi_ext_priv_ver(&cpu->env, ext_offset); - } - - cpu_cfg_ext_add_user_opt(ext_offset, profile->enabled); - isa_ext_update_enabled(cpu, ext_offset, profile->enabled); - } + riscv_cpu_set_profile(cpu, profile, value); } =20 static void cpu_get_profile(Object *obj, Visitor *v, const char *name, @@ -1397,7 +1404,7 @@ static void cpu_get_profile(Object *obj, Visitor *v, = const char *name, static void riscv_cpu_add_profiles(Object *cpu_obj) { for (int i =3D 0; riscv_profiles[i] !=3D NULL; i++) { - const RISCVCPUProfile *profile =3D riscv_profiles[i]; + RISCVCPUProfile *profile =3D riscv_profiles[i]; =20 object_property_add(cpu_obj, profile->name, "bool", cpu_get_profile, cpu_set_profile, @@ -1409,7 +1416,7 @@ static void riscv_cpu_add_profiles(Object *cpu_obj) * case. */ if (profile->enabled) { - object_property_set_bool(cpu_obj, profile->name, true, NULL); + riscv_cpu_set_profile(RISCV_CPU(cpu_obj), profile, true); } } } --=20 2.49.0 From nobody Sat Nov 15 18:49:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1748457921; cv=none; d=zohomail.com; s=zohoarc; b=WoaIn8RidqjBlkhpfJtcAhwGs91wQI5Yh68OLTNe+OllPuNLwrD3niN+N0+4qUnjUSjUT/mYPLc7Xk09KxGW+eZkPbwS4XY+6bqk79pLpzCX6G+AGfxJovRb3Jtg5pODQfSOwqVXkiNneZYzbSixWX01TK2PwqqB9TYAwoAPSCE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1748457921; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=8WKM/wEK8VP1ArVwfF5/+AK+ENcWWjOZhWhh/brMvSQ=; b=LAQ6cI9BZ++V++Q/9GvZecfQr5BzcgDr1eKo739FvY+uKcAFnGIXa6oPDIMluA8OzBZ+BNq853sS/Ab+V/z27iubYsr4PfC5PoBHo3IPyMeEjs+ARnLE6up4WI96lwjtpguCyxDB4GOr1CoErtEgVBc+pNo9N98jRq3V1JHVxNQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1748457921659992.5661616800431; Wed, 28 May 2025 11:45:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uKLlT-0006cA-Hn; Wed, 28 May 2025 14:44:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uKLlK-0006Sg-33 for qemu-devel@nongnu.org; Wed, 28 May 2025 14:44:27 -0400 Received: from mail-vk1-xa31.google.com ([2607:f8b0:4864:20::a31]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uKLlI-0000Op-3J for qemu-devel@nongnu.org; Wed, 28 May 2025 14:44:25 -0400 Received: by mail-vk1-xa31.google.com with SMTP id 71dfb90a1353d-52617ceae0dso31678e0c.0 for ; Wed, 28 May 2025 11:44:23 -0700 (PDT) Received: from grind.. ([191.255.35.190]) by smtp.gmail.com with ESMTPSA id 71dfb90a1353d-53066945971sm1568512e0c.30.2025.05.28.11.44.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 May 2025 11:44:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1748457862; x=1749062662; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8WKM/wEK8VP1ArVwfF5/+AK+ENcWWjOZhWhh/brMvSQ=; b=BjjJhZ/bnu2l6PW2sl+AJoopeAff0K8E79ERWFV/kLD6NNadOoPmC1zLE9BPs6gJ7a PkrekNDT5SjMlskWjgD9Vy5kyeDB5hT7XF26bBkkEoQc3Gelil3TZNPAF8IvwWS/NZY8 tiWbUUEslDADO+J+poemL7ksRVYP9T8UkC28AcIShQo9JdQeLj4lMnY7giikQmwy080B ezIfjfgHbF3QPvFmO1WPjtQEVIpOS5alNoT5daPmUVln0tONc8sFGUrs/nWGQ/r5L0Dd TKXKwVcXsj1H3BzJvYOIoTmxsEvq0Qz6btUYCvkCCv6SCeKsuQOXj5mF9tA4dhlRN321 HjXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748457862; x=1749062662; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8WKM/wEK8VP1ArVwfF5/+AK+ENcWWjOZhWhh/brMvSQ=; b=TmNCiNl21GYIx8xWpgB/TsySYNVeztxuKV7/vtKYkohuHiQkmmRM948rFTtupAxtuJ uD2KK3FOVDsxchB0q0iCBATv2G1miuG3o6PetlJRKtXXxp5LOXZeDZrPkhowZCbxI2oE 4s0tSp46tgylQOA5/NpzdJggaP4i/hGixx0QFAGUfQIlgoNq/+xZhBqmxi9aRgNaksFj +NK5aP0SpvaneTxufQIflkDZuJMHodlxToORizPzq4OS4U7IyHKUpMq4nGLN8mJ42jsN lADwjQwSyCGfWtnYA2C0356ZIXO9U7urT1up5iijhDFp8DvgxTeQRtf/W9rfsniBGJ/a 3dYQ== X-Gm-Message-State: AOJu0Yxs//Nm11pOIONHjWoSu65QvmhoucT8dj3PphRk4P3/mubJOLCs +Y6EIliETlw3Nu/ETDP4nCDsUEvo6fh80NtyIu4ZXAn8WvM0NEmHJ/3P3/GiFyRDD4/lkF3w+pd OmG4V X-Gm-Gg: ASbGncs0ppEmBezA0yB8fpRcyZAzQsSiUws1LWGuYnZgaalzl8VM/fe4cRB3ja3LxhX qiq4LfTi2PcXPcaJsrcNS+ju2bMblR6y3LsMNNx4OUdx9vuACAnLV00IaFzz2xkvvxtzo+GziBK EsUDVHdG4PICQSKTYfuzSMj506TitWmDrml1ngAuPCK6RzobpmsQrcT1K/toPpxY2qU758MuLAe PqQIXkBC8c6i5F/Ubno5RTBkUXx1W5usiBH3OCuHtuJDNAK9pEow9BgyJ6j5Urwjze7yYqWH73o 0XZqov6cX51WqfZBQnLscBVviqe3masWPiXtboK346lNtmA8huYm/Q== X-Google-Smtp-Source: AGHT+IFGuOkZpWVwMSV/N8u1s49VXLkJp2fUB+HaE9yGsmSzeVQ9PwC+zifJ2v6WBGOw23GL+X4BUQ== X-Received: by 2002:a05:6122:8c9:b0:520:6773:e5ea with SMTP id 71dfb90a1353d-52f2c57b328mr14982534e0c.7.1748457862497; Wed, 28 May 2025 11:44:22 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@dabbelt.com, ajones@ventanamicro.com, bjorn@rivosinc.com, Daniel Henrique Barboza , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= Subject: [PATCH v2 3/3] target/riscv: add profile->present flag Date: Wed, 28 May 2025 15:44:07 -0300 Message-ID: <20250528184407.1451983-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250528184407.1451983-1-dbarboza@ventanamicro.com> References: <20250528184407.1451983-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::a31; envelope-from=dbarboza@ventanamicro.com; helo=mail-vk1-xa31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1748457924257116600 Bj=C3=B6rn reported in [1] a case where a rv64 CPU is going through the profile code path to enable satp mode. In this case,the amount of extensions on top of the rv64 CPU made it compliant with the RVA22S64 profile during the validation of CPU 0. When the subsequent CPUs were initialized the static profile object has the 'enable' flag set, enabling the profile code path for those CPUs. This happens because we are initializing and realizing each CPU before going to the next, i.e. init and realize CPU0, then init and realize CPU1 and so on. If we change any persistent state during the validation of CPU N it will interfere with the init/realization of CPU N+1. We're using the 'enabled' profile flag to do two distinct things: inform cpu_init() that we want profile extensions to be enabled, and telling QMP that a profile is currently enabled in the CPU. We want to be flexible enough to recognize profile support for all CPUs that has the extension prerequisites, but we do not want to force the profile code path if a profile wasn't set too. Add a new 'present' flag for profiles that will coexist with the 'enabled' flag. Enabling a profile means "we want to switch on all its mandatory extensions". A profile is 'present' if we asserted during validation that the CPU has the needed prerequisites. This means that the case reported by Bj=C3=B6rn now results in RVA22S64.enabled=3Dfalse and RVA22S64.present=3Dtrue. QMP will recognize it as a RVA22 compliant CPU and we won't force the CPU into the profile path. [1] https://lore.kernel.org/qemu-riscv/87y0usiz22.fsf@all.your.base.are.bel= ong.to.us/ Reported-by: Bj=C3=B6rn T=C3=B6pel Fixes: 2af005d610 ("target/riscv/tcg: validate profiles during finalize") Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Bj=C3=B6rn T=C3=B6pel Tested-by: Bj=C3=B6rn T=C3=B6pel --- target/riscv/cpu.h | 15 +++++++++++++++ target/riscv/riscv-qmp-cmds.c | 2 +- target/riscv/tcg/tcg-cpu.c | 11 +++-------- 3 files changed, 19 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 229ade9ed9..2a6793e022 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -82,7 +82,22 @@ typedef struct riscv_cpu_profile { struct riscv_cpu_profile *s_parent; const char *name; uint32_t misa_ext; + /* + * The profile is enabled/disabled via command line or + * via cpu_init(). Enabling a profile will add all its + * mandatory extensions in the CPU during init(). + */ bool enabled; + /* + * The profile is present in the CPU, i.e. the current set of + * CPU extensions complies with it. A profile can be enabled + * and not present (e.g. the user disabled a mandatory extension) + * and the other way around (e.g. all mandatory extensions are + * present in a non-profile CPU). + * + * QMP uses this flag. + */ + bool present; bool user_set; int priv_spec; int satp_mode; diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c index d0a324364d..ad8efd180d 100644 --- a/target/riscv/riscv-qmp-cmds.c +++ b/target/riscv/riscv-qmp-cmds.c @@ -121,7 +121,7 @@ static void riscv_obj_add_profiles_qdict(Object *obj, Q= Dict *qdict_out) =20 for (int i =3D 0; riscv_profiles[i] !=3D NULL; i++) { profile =3D riscv_profiles[i]; - value =3D QOBJECT(qbool_from_bool(profile->enabled)); + value =3D QOBJECT(qbool_from_bool(profile->present)); =20 qdict_put_obj(qdict_out, profile->name, value); } diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index f8489d79d7..c5370a99f1 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -841,16 +841,11 @@ static void riscv_cpu_check_parent_profile(RISCVCPU *= cpu, RISCVCPUProfile *profile, RISCVCPUProfile *parent) { - const char *parent_name; - bool parent_enabled; - - if (!profile->enabled || !parent) { + if (!profile->present || !parent) { return; } =20 - parent_name =3D parent->name; - parent_enabled =3D object_property_get_bool(OBJECT(cpu), parent_name, = NULL); - profile->enabled =3D parent_enabled; + profile->present =3D parent->present; } =20 static void riscv_cpu_validate_profile(RISCVCPU *cpu, @@ -911,7 +906,7 @@ static void riscv_cpu_validate_profile(RISCVCPU *cpu, } } =20 - profile->enabled =3D profile_impl; + profile->present =3D profile_impl; =20 riscv_cpu_check_parent_profile(cpu, profile, profile->u_parent); riscv_cpu_check_parent_profile(cpu, profile, profile->s_parent); --=20 2.49.0