From nobody Sat Nov 15 19:02:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1748430511; cv=none; d=zohomail.com; s=zohoarc; b=bvitFxnGJhzlRJQQbTce2yywrVAVu5b2CKTsRplkFVzBb1vUp/Eg921LuWgP7Da6aEa0w2lgnATp9BrTAcU6qJITRRjh5Tq/a8pbRPI5afOJS8VSccmWZXA+9G0+7oR1G82kMWQkYHYegM3OejY3X0ZVSf9/IrJopePW3JgLtSg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1748430511; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=Fxv3FCx+IpIMLpRbDAbrBAxmxX6gEqjF97S7TU+9O+A=; b=GxwUq9Gu+t7ZZYwdycD0OSIAkTH7nr4P3TobWebbQ4/kMamvHm2yd4+boHsd2LN/xC4Ouudt6FpidLX0ox52N9tXqC7iCNyrDC41DTY0vjeltvU2zi2NEr8S6eFYZX+fa+87FujR87mVd4sUm3/1XvTao0dseAZtk9lf+lHZo6I= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1748430511223889.1856653263205; Wed, 28 May 2025 04:08:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uKEdt-0003xZ-CK; Wed, 28 May 2025 07:08:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uKEdr-0003wF-7e; Wed, 28 May 2025 07:08:15 -0400 Received: from [185.176.79.56] (helo=frasgout.his.huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uKEdp-0001TX-AL; Wed, 28 May 2025 07:08:14 -0400 Received: from mail.maildlp.com (unknown [172.18.186.231]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4b6msf32s7z6L4w8; Wed, 28 May 2025 19:06:46 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id E3FB6140519; Wed, 28 May 2025 19:07:58 +0800 (CST) Received: from SecurePC-101-06.china.huawei.com (10.122.19.247) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Wed, 28 May 2025 13:07:58 +0200 To: , Fan Ni , Peter Maydell , CC: , , , Yuquan Wang , Itaru Kitayama , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alireza Sanaee Subject: [PATCH v14 1/5] hw/cxl-host: Add an index field to CXLFixedMemoryWindow Date: Wed, 28 May 2025 12:07:22 +0100 Message-ID: <20250528110726.226389-2-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250528110726.226389-1-Jonathan.Cameron@huawei.com> References: <20250528110726.226389-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.19.247] X-ClientProxiedBy: lhrpeml100004.china.huawei.com (7.191.162.219) To frapeml500008.china.huawei.com (7.182.85.71) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1748430512767116600 Content-Type: text/plain; charset="utf-8" To enable these to be found in a fixed order, that order needs to be known. This will later be used to sort a list of these structures that address map and ACPI table entries are predictable. Reviewed-by: Li Zhijian Reviewed-by: Fan Ni Signed-off-by: Jonathan Cameron Tested-by: Itaru Kitayama Tested-by: Li Zhijian --- v14: Picked up tags. Thanks! --- include/hw/cxl/cxl.h | 1 + hw/cxl/cxl-host.c | 9 ++++++--- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h index 75e47b6864..b2bcce7ed6 100644 --- a/include/hw/cxl/cxl.h +++ b/include/hw/cxl/cxl.h @@ -27,6 +27,7 @@ typedef struct PXBCXLDev PXBCXLDev; =20 typedef struct CXLFixedWindow { + int index; uint64_t size; char **targets; PXBCXLDev *target_hbs[16]; diff --git a/hw/cxl/cxl-host.c b/hw/cxl/cxl-host.c index e010163174..b7aa429ddf 100644 --- a/hw/cxl/cxl-host.c +++ b/hw/cxl/cxl-host.c @@ -24,13 +24,15 @@ =20 static void cxl_fixed_memory_window_config(CXLState *cxl_state, CXLFixedMemoryWindowOptions *ob= ject, - Error **errp) + int index, Error **errp) { ERRP_GUARD(); g_autofree CXLFixedWindow *fw =3D g_malloc0(sizeof(*fw)); strList *target; int i; =20 + fw->index =3D index; + for (target =3D object->targets; target; target =3D target->next) { fw->num_targets++; } @@ -325,14 +327,15 @@ static void machine_set_cfmw(Object *obj, Visitor *v,= const char *name, CXLState *state =3D opaque; CXLFixedMemoryWindowOptionsList *cfmw_list =3D NULL; CXLFixedMemoryWindowOptionsList *it; + int index; =20 visit_type_CXLFixedMemoryWindowOptionsList(v, name, &cfmw_list, errp); if (!cfmw_list) { return; } =20 - for (it =3D cfmw_list; it; it =3D it->next) { - cxl_fixed_memory_window_config(state, it->value, errp); + for (it =3D cfmw_list, index =3D 0; it; it =3D it->next, index++) { + cxl_fixed_memory_window_config(state, it->value, index, errp); } state->cfmw_list =3D cfmw_list; } --=20 2.48.1 From nobody Sat Nov 15 19:02:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1748430545; cv=none; d=zohomail.com; s=zohoarc; b=dH2BCn4KXvXYq5pQ95Ep79nIv0+IrHpPlmKNNi/MekYAQHMiIbeMHj/XxIRJE/Zd+aVFjqT32lRrq4ZJNArW3ido9TWhSN2WvvxTkFGiDhvyb+OMZaKdPoG/vw+/odwLCaRsJ9KTcDRl2XLND61q6UD0ha+4gGJz94uEj4PrWU0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1748430545; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=IfAK9eV/qJB/zVBn1VMwYzZsYWFp0r4MnJCtNsXhqYs=; b=e/kIP7lIbYspOFryUbbgc0xjj4iH9O9FckEnrsePCMrGwkFbI7b3wUZttGG/Mv1Ihm4k43jRus9p4siqDANf7nAMfsnyCcT2NpNV8t5r4cs2PvLDv28KrZj2F3h1kNSrB32Yd5PlzUiI/zHJAS3kyw5Mt7X/mLmBCk3GeFSMAZc= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1748430545876382.419654933155; Wed, 28 May 2025 04:09:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uKEeZ-0004WF-Cw; Wed, 28 May 2025 07:08:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uKEeD-0004Aa-Et; Wed, 28 May 2025 07:08:40 -0400 Received: from [185.176.79.56] (helo=frasgout.his.huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uKEeA-0001V0-9k; Wed, 28 May 2025 07:08:36 -0400 Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4b6mvb3Kxgz6M4t6; Wed, 28 May 2025 19:08:27 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id EFBEC1404F4; Wed, 28 May 2025 19:08:29 +0800 (CST) Received: from SecurePC-101-06.china.huawei.com (10.122.19.247) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Wed, 28 May 2025 13:08:29 +0200 To: , Fan Ni , Peter Maydell , CC: , , , Yuquan Wang , Itaru Kitayama , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alireza Sanaee Subject: [PATCH v14 2/5] hw/cxl: Make the CXL fixed memory windows devices. Date: Wed, 28 May 2025 12:07:23 +0100 Message-ID: <20250528110726.226389-3-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250528110726.226389-1-Jonathan.Cameron@huawei.com> References: <20250528110726.226389-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.19.247] X-ClientProxiedBy: lhrpeml100004.china.huawei.com (7.191.162.219) To frapeml500008.china.huawei.com (7.182.85.71) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1748430547212116600 Content-Type: text/plain; charset="utf-8" Previously these somewhat device like structures were tracked using a list in the CXLState in each machine. This is proving restrictive in a few cases where we need to iterate through these without being aware of the machine type. Just make them sysbus devices. Restrict them to not user created as they need to be visible to early stages of machine init given effects on the memory map. This change both simplifies state tracking and enables features needed for performance optimization and hotness tracking by making it possible to retrieve the fixed memory window on actions elsewhere in the topology. In some cases the ordering of the Fixed Memory Windows matters. For those utility functions provide a GSList sorted by the window index. This ensures that we get consistency across: - ordering in the command line - ordering of the host PA ranges - ordering of ACPI CEDT structures describing the CFMWS. Other aspects don't have this constraint. For those direct iteration of the underlying hash structures is fine. Signed-off-by: Jonathan Cameron Reviewed-by: Li Zhijian Tested-by: Itaru Kitayama Tested-by: Li Zhijian --- v14: Drop some unnecessary checks on device type. (Zhijian) Use explicit pointer types given we know what they are at the caller. - cedt_build_cfmws - cxl_fmws_update Cleanup a few things that are left overs from earlier approaches: - Don't return unnecessarily at end of functions. - Drop return values that are unused and always zero. I think Peter Maydell suggested this a long time back when the original CXL support series was under review but not 100% sure. --- include/hw/cxl/cxl.h | 3 + include/hw/cxl/cxl_host.h | 4 +- hw/acpi/cxl.c | 76 ++++++++++---------- hw/cxl/cxl-host-stubs.c | 6 +- hw/cxl/cxl-host.c | 148 ++++++++++++++++++++++++++++++-------- hw/i386/pc.c | 51 ++++++------- 6 files changed, 194 insertions(+), 94 deletions(-) diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h index b2bcce7ed6..a610795c87 100644 --- a/include/hw/cxl/cxl.h +++ b/include/hw/cxl/cxl.h @@ -27,6 +27,7 @@ typedef struct PXBCXLDev PXBCXLDev; =20 typedef struct CXLFixedWindow { + SysBusDevice parent_obj; int index; uint64_t size; char **targets; @@ -38,6 +39,8 @@ typedef struct CXLFixedWindow { MemoryRegion mr; hwaddr base; } CXLFixedWindow; +#define TYPE_CXL_FMW "cxl-fmw" +OBJECT_DECLARE_SIMPLE_TYPE(CXLFixedWindow, CXL_FMW) =20 typedef struct CXLState { bool is_enabled; diff --git a/include/hw/cxl/cxl_host.h b/include/hw/cxl/cxl_host.h index c9bc9c7c50..6dce2cde07 100644 --- a/include/hw/cxl/cxl_host.h +++ b/include/hw/cxl/cxl_host.h @@ -14,8 +14,10 @@ #define CXL_HOST_H =20 void cxl_machine_init(Object *obj, CXLState *state); -void cxl_fmws_link_targets(CXLState *stat, Error **errp); +void cxl_fmws_link_targets(Error **errp); void cxl_hook_up_pxb_registers(PCIBus *bus, CXLState *state, Error **errp); +hwaddr cxl_fmws_set_memmap_and_update_mmio(hwaddr base, hwaddr max_addr); +GSList *cxl_fmws_get_all_sorted(void); =20 extern const MemoryRegionOps cfmws_ops; =20 diff --git a/hw/acpi/cxl.c b/hw/acpi/cxl.c index 9cd7905ea2..75d5b30bb8 100644 --- a/hw/acpi/cxl.c +++ b/hw/acpi/cxl.c @@ -22,6 +22,7 @@ #include "hw/pci/pci_bridge.h" #include "hw/pci/pci_host.h" #include "hw/cxl/cxl.h" +#include "hw/cxl/cxl_host.h" #include "hw/mem/memory-device.h" #include "hw/acpi/acpi.h" #include "hw/acpi/aml-build.h" @@ -135,55 +136,52 @@ static void cedt_build_chbs(GArray *table_data, PXBCX= LDev *cxl) * Interleave ways encoding in CXL 2.0 ECN: 3, 6, 12 and 16-way memory * interleaving. */ -static void cedt_build_cfmws(GArray *table_data, CXLState *cxls) +static void cedt_build_cfmws(CXLFixedWindow *fw, Aml *cedt) { - GList *it; + GArray *table_data =3D cedt->buf; + int i; =20 - for (it =3D cxls->fixed_windows; it; it =3D it->next) { - CXLFixedWindow *fw =3D it->data; - int i; - - /* Type */ - build_append_int_noprefix(table_data, 1, 1); + /* Type */ + build_append_int_noprefix(table_data, 1, 1); =20 - /* Reserved */ - build_append_int_noprefix(table_data, 0, 1); + /* Reserved */ + build_append_int_noprefix(table_data, 0, 1); =20 - /* Record Length */ - build_append_int_noprefix(table_data, 36 + 4 * fw->num_targets, 2); + /* Record Length */ + build_append_int_noprefix(table_data, 36 + 4 * fw->num_targets, 2); =20 - /* Reserved */ - build_append_int_noprefix(table_data, 0, 4); + /* Reserved */ + build_append_int_noprefix(table_data, 0, 4); =20 - /* Base HPA */ - build_append_int_noprefix(table_data, fw->mr.addr, 8); + /* Base HPA */ + build_append_int_noprefix(table_data, fw->mr.addr, 8); =20 - /* Window Size */ - build_append_int_noprefix(table_data, fw->size, 8); + /* Window Size */ + build_append_int_noprefix(table_data, fw->size, 8); =20 - /* Host Bridge Interleave Ways */ - build_append_int_noprefix(table_data, fw->enc_int_ways, 1); + /* Host Bridge Interleave Ways */ + build_append_int_noprefix(table_data, fw->enc_int_ways, 1); =20 - /* Host Bridge Interleave Arithmetic */ - build_append_int_noprefix(table_data, 0, 1); + /* Host Bridge Interleave Arithmetic */ + build_append_int_noprefix(table_data, 0, 1); =20 - /* Reserved */ - build_append_int_noprefix(table_data, 0, 2); + /* Reserved */ + build_append_int_noprefix(table_data, 0, 2); =20 - /* Host Bridge Interleave Granularity */ - build_append_int_noprefix(table_data, fw->enc_int_gran, 4); + /* Host Bridge Interleave Granularity */ + build_append_int_noprefix(table_data, fw->enc_int_gran, 4); =20 - /* Window Restrictions */ - build_append_int_noprefix(table_data, 0x0f, 2); /* No restrictions= */ + /* Window Restrictions */ + build_append_int_noprefix(table_data, 0x0f, 2); =20 - /* QTG ID */ - build_append_int_noprefix(table_data, 0, 2); + /* QTG ID */ + build_append_int_noprefix(table_data, 0, 2); =20 - /* Host Bridge List (list of UIDs - currently bus_nr) */ - for (i =3D 0; i < fw->num_targets; i++) { - g_assert(fw->target_hbs[i]); - build_append_int_noprefix(table_data, PXB_DEV(fw->target_hbs[i= ])->bus_nr, 4); - } + /* Host Bridge List (list of UIDs - currently bus_nr) */ + for (i =3D 0; i < fw->num_targets; i++) { + g_assert(fw->target_hbs[i]); + build_append_int_noprefix(table_data, + PXB_DEV(fw->target_hbs[i])->bus_nr, 4); } } =20 @@ -202,6 +200,7 @@ void cxl_build_cedt(GArray *table_offsets, GArray *tabl= e_data, BIOSLinker *linker, const char *oem_id, const char *oem_table_id, CXLState *cxl_state) { + GSList *cfmws_list, *iter; Aml *cedt; AcpiTable table =3D { .sig =3D "CEDT", .rev =3D 1, .oem_id =3D oem_id, .oem_table_id =3D oem_table_id }; @@ -213,7 +212,12 @@ void cxl_build_cedt(GArray *table_offsets, GArray *tab= le_data, /* reserve space for CEDT header */ =20 object_child_foreach_recursive(object_get_root(), cxl_foreach_pxb_hb, = cedt); - cedt_build_cfmws(cedt->buf, cxl_state); + + cfmws_list =3D cxl_fmws_get_all_sorted(); + for (iter =3D cfmws_list; iter; iter =3D iter->next) { + cedt_build_cfmws(CXL_FMW(iter->data), cedt); + } + g_slist_free(cfmws_list); =20 /* copy AML table into ACPI tables blob and patch header there */ g_array_append_vals(table_data, cedt->buf->data, cedt->buf->len); diff --git a/hw/cxl/cxl-host-stubs.c b/hw/cxl/cxl-host-stubs.c index cae4afcdde..13eb6bf6a4 100644 --- a/hw/cxl/cxl-host-stubs.c +++ b/hw/cxl/cxl-host-stubs.c @@ -8,8 +8,12 @@ #include "hw/cxl/cxl.h" #include "hw/cxl/cxl_host.h" =20 -void cxl_fmws_link_targets(CXLState *stat, Error **errp) {}; +void cxl_fmws_link_targets(Error **errp) {}; void cxl_machine_init(Object *obj, CXLState *state) {}; void cxl_hook_up_pxb_registers(PCIBus *bus, CXLState *state, Error **errp)= {}; +hwaddr cxl_fmws_set_memmap_and_update_mmio(hwaddr base, hwaddr max_addr) +{ + return base; +}; =20 const MemoryRegionOps cfmws_ops; diff --git a/hw/cxl/cxl-host.c b/hw/cxl/cxl-host.c index b7aa429ddf..016a4fdc6a 100644 --- a/hw/cxl/cxl-host.c +++ b/hw/cxl/cxl-host.c @@ -22,12 +22,12 @@ #include "hw/pci/pcie_port.h" #include "hw/pci-bridge/pci_expander_bridge.h" =20 -static void cxl_fixed_memory_window_config(CXLState *cxl_state, - CXLFixedMemoryWindowOptions *ob= ject, +static void cxl_fixed_memory_window_config(CXLFixedMemoryWindowOptions *ob= ject, int index, Error **errp) { ERRP_GUARD(); - g_autofree CXLFixedWindow *fw =3D g_malloc0(sizeof(*fw)); + DeviceState *dev =3D qdev_new(TYPE_CXL_FMW); + CXLFixedWindow *fw =3D CXL_FMW(dev); strList *target; int i; =20 @@ -67,35 +67,39 @@ static void cxl_fixed_memory_window_config(CXLState *cx= l_state, fw->targets[i] =3D g_strdup(target->value); } =20 - cxl_state->fixed_windows =3D g_list_append(cxl_state->fixed_windows, - g_steal_pointer(&fw)); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp); } =20 -void cxl_fmws_link_targets(CXLState *cxl_state, Error **errp) +static int cxl_fmws_link(Object *obj, void *opaque) { - if (cxl_state && cxl_state->fixed_windows) { - GList *it; - - for (it =3D cxl_state->fixed_windows; it; it =3D it->next) { - CXLFixedWindow *fw =3D it->data; - int i; - - for (i =3D 0; i < fw->num_targets; i++) { - Object *o; - bool ambig; - - o =3D object_resolve_path_type(fw->targets[i], - TYPE_PXB_CXL_DEV, - &ambig); - if (!o) { - error_setg(errp, "Could not resolve CXLFM target %s", - fw->targets[i]); - return; - } - fw->target_hbs[i] =3D PXB_CXL_DEV(o); - } + struct CXLFixedWindow *fw; + int i; + + if (!object_dynamic_cast(obj, TYPE_CXL_FMW)) { + return 0; + } + fw =3D CXL_FMW(obj); + + for (i =3D 0; i < fw->num_targets; i++) { + Object *o; + bool ambig; + + o =3D object_resolve_path_type(fw->targets[i], TYPE_PXB_CXL_DEV, + &ambig); + if (!o) { + error_setg(&error_fatal, "Could not resolve CXLFM target %s", + fw->targets[i]); + return 1; } + fw->target_hbs[i] =3D PXB_CXL_DEV(o); } + return 0; +} + +void cxl_fmws_link_targets(Error **errp) +{ + /* Order doesn't matter for this, so no need to build list */ + object_child_foreach_recursive(object_get_root(), cxl_fmws_link, NULL); } =20 static bool cxl_hdm_find_target(uint32_t *cache_mem, hwaddr addr, @@ -335,7 +339,7 @@ static void machine_set_cfmw(Object *obj, Visitor *v, c= onst char *name, } =20 for (it =3D cfmw_list, index =3D 0; it; it =3D it->next, index++) { - cxl_fixed_memory_window_config(state, it->value, index, errp); + cxl_fixed_memory_window_config(it->value, index, errp); } state->cfmw_list =3D cfmw_list; } @@ -373,3 +377,91 @@ void cxl_hook_up_pxb_registers(PCIBus *bus, CXLState *= state, Error **errp) } } } + +static void cxl_fmws_update(CXLFixedWindow *fw, hwaddr *base, hwaddr max_a= ddr) +{ + if (*base + fw->size <=3D max_addr) { + fw->base =3D *base; + sysbus_mmio_map(SYS_BUS_DEVICE(fw), 0, fw->base); + *base +=3D fw->size; + } +} + +static int cxl_fmws_find(Object *obj, void *opaque) +{ + GSList **list =3D opaque; + + if (!object_dynamic_cast(obj, TYPE_CXL_FMW)) { + return 0; + } + *list =3D g_slist_prepend(*list, obj); + + return 0; +} + +static GSList *cxl_fmws_get_all(void) +{ + GSList *list =3D NULL; + + object_child_foreach_recursive(object_get_root(), cxl_fmws_find, &list= ); + + return list; +} + +static gint cfmws_cmp(gconstpointer a, gconstpointer b, gpointer d) +{ + const struct CXLFixedWindow *ap =3D a; + const struct CXLFixedWindow *bp =3D b; + + return ap->index > bp->index; +} + +GSList *cxl_fmws_get_all_sorted(void) +{ + return g_slist_sort_with_data(cxl_fmws_get_all(), cfmws_cmp, NULL); +} + +hwaddr cxl_fmws_set_memmap_and_update_mmio(hwaddr base, hwaddr max_addr) +{ + GSList *cfmws_list, *iter; + + cfmws_list =3D cxl_fmws_get_all_sorted(); + for (iter =3D cfmws_list; iter; iter =3D iter->next) { + cxl_fmws_update(CXL_FMW(iter->data), &base, max_addr); + } + g_slist_free(cfmws_list); + + return base; +} + +static void cxl_fmw_realize(DeviceState *dev, Error **errp) +{ + CXLFixedWindow *fw =3D CXL_FMW(dev); + + memory_region_init_io(&fw->mr, OBJECT(dev), &cfmws_ops, fw, + "cxl-fixed-memory-region", fw->size); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &fw->mr); +} + +static void cxl_fmw_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->desc =3D "CXL Fixed Memory Window"; + dc->realize =3D cxl_fmw_realize; + /* Reason - created by machines as tightly coupled to machine memory m= ap */ + dc->user_creatable =3D false; +} + +static const TypeInfo cxl_fmw_info =3D { + .name =3D TYPE_CXL_FMW, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(CXLFixedWindow), + .class_init =3D cxl_fmw_class_init, +}; + +static void cxl_host_register_types(void) +{ + type_register_static(&cxl_fmw_info); +} +type_init(cxl_host_register_types) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 70656157ca..9978398876 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -630,7 +630,7 @@ void pc_machine_done(Notifier *notifier, void *data) &error_fatal); =20 if (pcms->cxl_devices_state.is_enabled) { - cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal); + cxl_fmws_link_targets(&error_fatal); } =20 /* set the number of CPUs */ @@ -739,20 +739,28 @@ static uint64_t pc_get_cxl_range_start(PCMachineState= *pcms) return cxl_base; } =20 -static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) +static int cxl_get_fmw_end(Object *obj, void *opaque) { - uint64_t start =3D pc_get_cxl_range_start(pcms) + MiB; + struct CXLFixedWindow *fw; + uint64_t *start =3D opaque; =20 - if (pcms->cxl_devices_state.fixed_windows) { - GList *it; - - start =3D ROUND_UP(start, 256 * MiB); - for (it =3D pcms->cxl_devices_state.fixed_windows; it; it =3D it->= next) { - CXLFixedWindow *fw =3D it->data; - start +=3D fw->size; - } + if (!object_dynamic_cast(obj, TYPE_CXL_FMW)) { + return 0; } + fw =3D CXL_FMW(obj); + + *start +=3D fw->size; =20 + return 0; +} + +static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) +{ + uint64_t start =3D pc_get_cxl_range_start(pcms) + MiB; + + /* Ordering doesn't matter so no need to build a sorted list */ + object_child_foreach_recursive(object_get_root(), cxl_get_fmw_end, + &start); return start; } =20 @@ -954,23 +962,10 @@ void pc_memory_init(PCMachineState *pcms, cxl_base =3D pc_get_cxl_range_start(pcms); memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); memory_region_add_subregion(system_memory, cxl_base, mr); - cxl_resv_end =3D cxl_base + cxl_size; - if (pcms->cxl_devices_state.fixed_windows) { - hwaddr cxl_fmw_base; - GList *it; - - cxl_fmw_base =3D ROUND_UP(cxl_base + cxl_size, 256 * MiB); - for (it =3D pcms->cxl_devices_state.fixed_windows; it; it =3D = it->next) { - CXLFixedWindow *fw =3D it->data; - - fw->base =3D cxl_fmw_base; - memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops= , fw, - "cxl-fixed-memory-region", fw->size); - memory_region_add_subregion(system_memory, fw->base, &fw->= mr); - cxl_fmw_base +=3D fw->size; - cxl_resv_end =3D cxl_fmw_base; - } - } + cxl_base =3D ROUND_UP(cxl_base + cxl_size, 256 * MiB); + + cxl_resv_end =3D cxl_fmws_set_memmap_and_update_mmio(cxl_base, + maxphysaddr); } =20 /* Initialize PC system firmware */ --=20 2.48.1 From nobody Sat Nov 15 19:02:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1748430575; cv=none; d=zohomail.com; s=zohoarc; b=kSw+indfI4pi2jVB5Ph+mdb9mnh8B/VbzFCqc1rDaInfvCIqt+lQ5BOOKGZWwe4yzsL+HFyW7r8RmrH7rDrjLw13nqQt/b5VlXbFuxNHmEhYtyXmjxzvVx7rzO3mEcYfrpRySK2FbWjH7WeZaXlnoY3QCUrVXvQwxDgcrOsN5GY= ARC-Message-Signature: i=1; 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Wed, 28 May 2025 13:09:00 +0200 To: , Fan Ni , Peter Maydell , CC: , , , Yuquan Wang , Itaru Kitayama , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alireza Sanaee Subject: [PATCH v14 3/5] hw/cxl-host: Allow split of establishing memory address and mmio setup. Date: Wed, 28 May 2025 12:07:24 +0100 Message-ID: <20250528110726.226389-4-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250528110726.226389-1-Jonathan.Cameron@huawei.com> References: <20250528110726.226389-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.19.247] X-ClientProxiedBy: lhrpeml100004.china.huawei.com (7.191.162.219) To frapeml500008.china.huawei.com (7.182.85.71) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1748430577316116600 Content-Type: text/plain; charset="utf-8" On arm/virt the memory map is set up before any devices are brought up. To enable this provide split functions to establish the fw->base and later to actually map it. Signed-off-by: Jonathan Cameron Tested-by: Itaru Kitayama Tested-by: Li Zhijian --- v14: Update wrt to changes in previous patch. Add a do_cfwms_set_memmap_and_update_mmio() utility function to reduce code duplication. (Zhijian) --- include/hw/cxl/cxl_host.h | 2 ++ hw/cxl/cxl-host-stubs.c | 2 ++ hw/cxl/cxl-host.c | 43 +++++++++++++++++++++++++++++++++++---- 3 files changed, 43 insertions(+), 4 deletions(-) diff --git a/include/hw/cxl/cxl_host.h b/include/hw/cxl/cxl_host.h index 6dce2cde07..aee9d573d6 100644 --- a/include/hw/cxl/cxl_host.h +++ b/include/hw/cxl/cxl_host.h @@ -16,6 +16,8 @@ void cxl_machine_init(Object *obj, CXLState *state); void cxl_fmws_link_targets(Error **errp); void cxl_hook_up_pxb_registers(PCIBus *bus, CXLState *state, Error **errp); +hwaddr cxl_fmws_set_memmap(hwaddr base, hwaddr max_addr); +void cxl_fmws_update_mmio(void); hwaddr cxl_fmws_set_memmap_and_update_mmio(hwaddr base, hwaddr max_addr); GSList *cxl_fmws_get_all_sorted(void); =20 diff --git a/hw/cxl/cxl-host-stubs.c b/hw/cxl/cxl-host-stubs.c index 13eb6bf6a4..d9e38618d6 100644 --- a/hw/cxl/cxl-host-stubs.c +++ b/hw/cxl/cxl-host-stubs.c @@ -11,6 +11,8 @@ void cxl_fmws_link_targets(Error **errp) {}; void cxl_machine_init(Object *obj, CXLState *state) {}; void cxl_hook_up_pxb_registers(PCIBus *bus, CXLState *state, Error **errp)= {}; +hwaddr cxl_fmws_set_memmap(hwaddr base, hwaddr max_addr) { return base; }; +void cxl_fmws_update_mmio(void) {}; hwaddr cxl_fmws_set_memmap_and_update_mmio(hwaddr base, hwaddr max_addr) { return base; diff --git a/hw/cxl/cxl-host.c b/hw/cxl/cxl-host.c index 016a4fdc6a..a1b9980035 100644 --- a/hw/cxl/cxl-host.c +++ b/hw/cxl/cxl-host.c @@ -378,11 +378,14 @@ void cxl_hook_up_pxb_registers(PCIBus *bus, CXLState = *state, Error **errp) } } =20 -static void cxl_fmws_update(CXLFixedWindow *fw, hwaddr *base, hwaddr max_a= ddr) +static void cxl_fmws_update(CXLFixedWindow *fw, hwaddr *base, hwaddr max_a= ddr, + bool update_mmio) { if (*base + fw->size <=3D max_addr) { fw->base =3D *base; - sysbus_mmio_map(SYS_BUS_DEVICE(fw), 0, fw->base); + if (update_mmio) { + sysbus_mmio_map(SYS_BUS_DEVICE(fw), 0, fw->base); + } *base +=3D fw->size; } } @@ -421,19 +424,51 @@ GSList *cxl_fmws_get_all_sorted(void) return g_slist_sort_with_data(cxl_fmws_get_all(), cfmws_cmp, NULL); } =20 -hwaddr cxl_fmws_set_memmap_and_update_mmio(hwaddr base, hwaddr max_addr) +static hwaddr do_cxl_fmws_set_memmap_and_update_mmio(hwaddr base, + hwaddr max_addr, + bool update_mmio) { GSList *cfmws_list, *iter; =20 cfmws_list =3D cxl_fmws_get_all_sorted(); for (iter =3D cfmws_list; iter; iter =3D iter->next) { - cxl_fmws_update(CXL_FMW(iter->data), &base, max_addr); + cxl_fmws_update(CXL_FMW(iter->data), &base, max_addr, update_mmio); } g_slist_free(cfmws_list); =20 return base; } =20 +hwaddr cxl_fmws_set_memmap(hwaddr base, hwaddr max_addr) +{ + return do_cxl_fmws_set_memmap_and_update_mmio(base, max_addr, false); +} + +hwaddr cxl_fmws_set_memmap_and_update_mmio(hwaddr base, hwaddr max_addr) +{ + return do_cxl_fmws_set_memmap_and_update_mmio(base, max_addr, true); +} + +static int cxl_fmws_mmio_map(Object *obj, void *opaque) +{ + struct CXLFixedWindow *fw; + + if (!object_dynamic_cast(obj, TYPE_CXL_FMW)) { + return 0; + } + fw =3D CXL_FMW(obj); + sysbus_mmio_map(SYS_BUS_DEVICE(fw), 0, fw->base); + + return 0; +} + +void cxl_fmws_update_mmio(void) +{ + /* Ordering is not required for this */ + object_child_foreach_recursive(object_get_root(), cxl_fmws_mmio_map, + NULL); +} + static void cxl_fmw_realize(DeviceState *dev, Error **errp) { CXLFixedWindow *fw =3D CXL_FMW(dev); --=20 2.48.1 From nobody Sat Nov 15 19:02:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1748430596; cv=none; d=zohomail.com; s=zohoarc; b=ABGFSZtHizBWFfb4HUcVXDb6nwyf3JUFCnBXQGExGAyY0lIYmiO7BuvM8c3fewwbtI7Non9L+oULmcMIVJwaDdJKS7qY8grhx5nrM32w4FYz6EKSL1hN8eTwamR7vN3pQ53KJRZs6R1ZSUSKxf4OenJv5vQ/oe5039tNzJXRgp4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1748430596; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Wed, 28 May 2025 07:09:38 -0400 Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4b6mrl0bQQz6L5Dr; Wed, 28 May 2025 19:05:59 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id 4EFA7140AF0; Wed, 28 May 2025 19:09:32 +0800 (CST) Received: from SecurePC-101-06.china.huawei.com (10.122.19.247) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Wed, 28 May 2025 13:09:31 +0200 To: , Fan Ni , Peter Maydell , CC: , , , Yuquan Wang , Itaru Kitayama , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alireza Sanaee Subject: [PATCH v14 4/5] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl Date: Wed, 28 May 2025 12:07:25 +0100 Message-ID: <20250528110726.226389-5-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250528110726.226389-1-Jonathan.Cameron@huawei.com> References: <20250528110726.226389-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.19.247] X-ClientProxiedBy: lhrpeml100004.china.huawei.com (7.191.162.219) To frapeml500008.china.huawei.com (7.182.85.71) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1748430597600116600 Content-Type: text/plain; charset="utf-8" Code based on i386/pc enablement. The memory layout places space for 16 host bridge register regions after the GIC_REDIST2 in the extended memmap. The CFMWs are placed above the extended memmap. Only create the CEDT table if cxl=3Don set for the machine. Signed-off-by: Jonathan Cameron Tested-by: Itaru Kitayama Tested-by: Li Zhijian --- include/hw/arm/virt.h | 4 ++++ hw/arm/virt-acpi-build.c | 34 ++++++++++++++++++++++++++++++++++ hw/arm/virt.c | 29 +++++++++++++++++++++++++++++ 3 files changed, 67 insertions(+) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 9a1b0f53d2..4375819ea0 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -36,6 +36,7 @@ #include "hw/arm/boot.h" #include "hw/arm/bsa.h" #include "hw/block/flash.h" +#include "hw/cxl/cxl.h" #include "system/kvm.h" #include "hw/intc/arm_gicv3_common.h" #include "qom/object.h" @@ -85,6 +86,7 @@ enum { /* indices of IO regions located after the RAM */ enum { VIRT_HIGH_GIC_REDIST2 =3D VIRT_LOWMEMMAP_LAST, + VIRT_CXL_HOST, VIRT_HIGH_PCIE_ECAM, VIRT_HIGH_PCIE_MMIO, }; @@ -140,6 +142,7 @@ struct VirtMachineState { bool secure; bool highmem; bool highmem_compact; + bool highmem_cxl; bool highmem_ecam; bool highmem_mmio; bool highmem_redists; @@ -174,6 +177,7 @@ struct VirtMachineState { char *oem_id; char *oem_table_id; bool ns_el2_virt_timer_irq; + CXLState cxl_devices_state; }; =20 #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 7e8e0f0298..589e221b89 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -39,10 +39,12 @@ #include "hw/acpi/aml-build.h" #include "hw/acpi/utils.h" #include "hw/acpi/pci.h" +#include "hw/acpi/cxl.h" #include "hw/acpi/memory_hotplug.h" #include "hw/acpi/generic_event_device.h" #include "hw/acpi/tpm.h" #include "hw/acpi/hmat.h" +#include "hw/cxl/cxl.h" #include "hw/pci/pcie_host.h" #include "hw/pci/pci.h" #include "hw/pci/pci_bus.h" @@ -119,10 +121,29 @@ static void acpi_dsdt_add_flash(Aml *scope, const Mem= MapEntry *flash_memmap) aml_append(scope, dev); } =20 +static void build_acpi0017(Aml *table) +{ + Aml *dev, *scope, *method; + + scope =3D aml_scope("_SB"); + dev =3D aml_device("CXLM"); + aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017"))); + + method =3D aml_method("_STA", 0, AML_NOTSERIALIZED); + aml_append(method, aml_return(aml_int(0x0B))); + aml_append(dev, method); + build_cxl_dsm_method(dev); + + aml_append(scope, dev); + aml_append(table, scope); +} + static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, uint32_t irq, VirtMachineState *vms) { int ecam_id =3D VIRT_ECAM_ID(vms->highmem_ecam); + bool cxl_present =3D false; + PCIBus *bus =3D vms->bus; struct GPEXConfig cfg =3D { .mmio32 =3D memmap[VIRT_PCIE_MMIO], .pio =3D memmap[VIRT_PCIE_PIO], @@ -136,6 +157,14 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMap= Entry *memmap, } =20 acpi_dsdt_add_gpex(scope, &cfg); + QLIST_FOREACH(bus, &vms->bus->child, sibling) { + if (pci_bus_is_cxl(bus)) { + cxl_present =3D true; + } + } + if (cxl_present) { + build_acpi0017(scope); + } } =20 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, @@ -963,6 +992,11 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildT= ables *tables) } } =20 + if (vms->cxl_devices_state.is_enabled) { + cxl_build_cedt(table_offsets, tables_blob, tables->linker, + vms->oem_id, vms->oem_table_id, &vms->cxl_devices_s= tate); + } + if (ms->nvdimms_state->is_enabled) { nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, ms->nvdimms_state, ms->ram_slots, vms->oem_id, diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 9a6cd085a3..e06d293edc 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -57,6 +57,7 @@ #include "qemu/error-report.h" #include "qemu/module.h" #include "hw/pci-host/gpex.h" +#include "hw/pci-bridge/pci_expander_bridge.h" #include "hw/virtio/virtio-pci.h" #include "hw/core/sysbus-fdt.h" #include "hw/platform-bus.h" @@ -86,6 +87,8 @@ #include "hw/virtio/virtio-md-pci.h" #include "hw/virtio/virtio-iommu.h" #include "hw/char/pl011.h" +#include "hw/cxl/cxl.h" +#include "hw/cxl/cxl_host.h" #include "qemu/guest-random.h" =20 static GlobalProperty arm_virt_compat[] =3D { @@ -220,6 +223,7 @@ static const MemMapEntry base_memmap[] =3D { static MemMapEntry extended_memmap[] =3D { /* Additional 64 MB redist region (can contain up to 512 redistributor= s) */ [VIRT_HIGH_GIC_REDIST2] =3D { 0x0, 64 * MiB }, + [VIRT_CXL_HOST] =3D { 0x0, 64 * KiB * 16 }, /* 16 UID */ [VIRT_HIGH_PCIE_ECAM] =3D { 0x0, 256 * MiB }, /* Second PCIe window */ [VIRT_HIGH_PCIE_MMIO] =3D { 0x0, DEFAULT_HIGH_PCIE_MMIO_SIZE }, @@ -1621,6 +1625,17 @@ static void create_pcie(VirtMachineState *vms) } } =20 +static void create_cxl_host_reg_region(VirtMachineState *vms) +{ + MemoryRegion *sysmem =3D get_system_memory(); + MemoryRegion *mr =3D &vms->cxl_devices_state.host_mr; + + memory_region_init(mr, OBJECT(vms), "cxl_host_reg", + vms->memmap[VIRT_CXL_HOST].size); + memory_region_add_subregion(sysmem, vms->memmap[VIRT_CXL_HOST].base, m= r); + vms->highmem_cxl =3D true; +} + static void create_platform_bus(VirtMachineState *vms) { DeviceState *dev; @@ -1737,6 +1752,12 @@ void virt_machine_done(Notifier *notifier, void *dat= a) struct arm_boot_info *info =3D &vms->bootinfo; AddressSpace *as =3D arm_boot_address_space(cpu, info); =20 + cxl_hook_up_pxb_registers(vms->bus, &vms->cxl_devices_state, + &error_fatal); + + if (vms->cxl_devices_state.is_enabled) { + cxl_fmws_link_targets(&error_fatal); + } /* * If the user provided a dtb, we assume the dynamic sysbus nodes * already are integrated there. This corresponds to a use case where @@ -1783,6 +1804,7 @@ static inline bool *virt_get_high_memmap_enabled(Virt= MachineState *vms, { bool *enabled_array[] =3D { &vms->highmem_redists, + &vms->highmem_cxl, &vms->highmem_ecam, &vms->highmem_mmio, }; @@ -1890,6 +1912,9 @@ static void virt_set_memmap(VirtMachineState *vms, in= t pa_bits) if (device_memory_size > 0) { machine_memory_devices_init(ms, device_memory_base, device_memory_= size); } + + cxl_fmws_set_memmap(ROUND_UP(vms->highest_gpa + 1, 256 * MiB), + BIT_ULL(pa_bits)); } =20 static VirtGICType finalize_gic_version_do(const char *accel_name, @@ -2340,6 +2365,8 @@ static void machvirt_init(MachineState *machine) memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, machine->ram); =20 + cxl_fmws_update_mmio(); + virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); =20 create_gic(vms, sysmem); @@ -2395,6 +2422,7 @@ static void machvirt_init(MachineState *machine) create_rtc(vms); =20 create_pcie(vms); + create_cxl_host_reg_region(vms); =20 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)= ) { vms->acpi_dev =3D create_acpi_ged(vms); @@ -3365,6 +3393,7 @@ static void virt_instance_init(Object *obj) =20 vms->oem_id =3D g_strndup(ACPI_BUILD_APPNAME6, 6); vms->oem_table_id =3D g_strndup(ACPI_BUILD_APPNAME8, 8); + cxl_machine_init(obj, &vms->cxl_devices_state); } =20 static const TypeInfo virt_machine_info =3D { --=20 2.48.1 From nobody Sat Nov 15 19:02:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1748430632; cv=none; d=zohomail.com; s=zohoarc; b=i392FjjoCVCP4mca44RByY4PugQWcPEm1rlBAvItdi0O3AxE7wG0WbAOYQkn14eSTeheZFf5ViM9ge6DdiKsk3i4/eZdlac32mANlRyZO0U1FqXQkQOFhZXTwFu+jg/RPfQwv8Sb0gHy89BWZG7NewVo+eitO/TS9ouA/6Pcqxw= ARC-Message-Signature: i=1; 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Wed, 28 May 2025 13:10:02 +0200 To: , Fan Ni , Peter Maydell , CC: , , , Yuquan Wang , Itaru Kitayama , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alireza Sanaee Subject: [PATCH v14 5/5] qtest/cxl: Add aarch64 virt test for CXL Date: Wed, 28 May 2025 12:07:26 +0100 Message-ID: <20250528110726.226389-6-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250528110726.226389-1-Jonathan.Cameron@huawei.com> References: <20250528110726.226389-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.19.247] X-ClientProxiedBy: lhrpeml100004.china.huawei.com (7.191.162.219) To frapeml500008.china.huawei.com (7.182.85.71) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1748430634117116600 Content-Type: text/plain; charset="utf-8" Add a single complex case for aarch64 virt machine. Given existing much more comprehensive tests for x86 cover the common functionality, a single test should be enough to verify that the aarch64 part continue to work. Tested-by: Itaru Kitayama Signed-off-by: Jonathan Cameron Tested-by: Li Zhijian --- v14: Tags only. --- tests/qtest/cxl-test.c | 59 ++++++++++++++++++++++++++++++++--------- tests/qtest/meson.build | 1 + 2 files changed, 47 insertions(+), 13 deletions(-) diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c index a600331843..c7189d6222 100644 --- a/tests/qtest/cxl-test.c +++ b/tests/qtest/cxl-test.c @@ -19,6 +19,12 @@ "-device pxb-cxl,id=3Dcxl.1,bus=3Dpcie.0,bus_nr=3D53 " \ "-M cxl-fmw.0.targets.0=3Dcxl.0,cxl-fmw.0.targets.1=3Dcxl.1,cxl-fmw.0.= size=3D4G " =20 +#define QEMU_VIRT_2PXB_CMD \ + "-machine virt,cxl=3Don -cpu max " \ + "-device pxb-cxl,id=3Dcxl.0,bus=3Dpcie.0,bus_nr=3D52 " \ + "-device pxb-cxl,id=3Dcxl.1,bus=3Dpcie.0,bus_nr=3D53 " \ + "-M cxl-fmw.0.targets.0=3Dcxl.0,cxl-fmw.0.targets.1=3Dcxl.1,cxl-fmw.0.= size=3D4G " + #define QEMU_RP \ "-device cxl-rp,id=3Drp0,bus=3Dcxl.0,chassis=3D0,slot=3D0 " =20 @@ -197,25 +203,52 @@ static void cxl_2pxb_4rp_4t3d(void) qtest_end(); rmdir(tmpfs); } + +static void cxl_virt_2pxb_4rp_4t3d(void) +{ + g_autoptr(GString) cmdline =3D g_string_new(NULL); + char template[] =3D "/tmp/cxl-test-XXXXXX"; + const char *tmpfs; + + tmpfs =3D mkdtemp(template); + + g_string_printf(cmdline, QEMU_VIRT_2PXB_CMD QEMU_4RP QEMU_4T3D, + tmpfs, tmpfs, tmpfs, tmpfs, tmpfs, tmpfs, + tmpfs, tmpfs); + + qtest_start(cmdline->str); + qtest_end(); + rmdir(tmpfs); +} #endif /* CONFIG_POSIX */ =20 int main(int argc, char **argv) { - g_test_init(&argc, &argv, NULL); + const char *arch =3D qtest_get_arch(); =20 - qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb); - qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb); - qtest_add_func("/pci/cxl/pxb_with_window", cxl_pxb_with_window); - qtest_add_func("/pci/cxl/pxb_x2_with_window", cxl_2pxb_with_window); - qtest_add_func("/pci/cxl/rp", cxl_root_port); - qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port); + g_test_init(&argc, &argv, NULL); + if (strcmp(arch, "i386") =3D=3D 0 || strcmp(arch, "x86_64") =3D=3D 0) { + qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb); + qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb); + qtest_add_func("/pci/cxl/pxb_with_window", cxl_pxb_with_window); + qtest_add_func("/pci/cxl/pxb_x2_with_window", cxl_2pxb_with_window= ); + qtest_add_func("/pci/cxl/rp", cxl_root_port); + qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port); #ifdef CONFIG_POSIX - qtest_add_func("/pci/cxl/type3_device", cxl_t3d_deprecated); - qtest_add_func("/pci/cxl/type3_device_pmem", cxl_t3d_persistent); - qtest_add_func("/pci/cxl/type3_device_vmem", cxl_t3d_volatile); - qtest_add_func("/pci/cxl/type3_device_vmem_lsa", cxl_t3d_volatile_lsa); - qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d); - qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", cxl_2pxb_4rp_4= t3d); + qtest_add_func("/pci/cxl/type3_device", cxl_t3d_deprecated); + qtest_add_func("/pci/cxl/type3_device_pmem", cxl_t3d_persistent); + qtest_add_func("/pci/cxl/type3_device_vmem", cxl_t3d_volatile); + qtest_add_func("/pci/cxl/type3_device_vmem_lsa", cxl_t3d_volatile_= lsa); + qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d); + qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", + cxl_2pxb_4rp_4t3d); #endif + } else if (strcmp(arch, "aarch64") =3D=3D 0) { +#ifdef CONFIG_POSIX + qtest_add_func("/pci/cxl/virt/pxb_x2_root_port_x4_type3_x4", + cxl_virt_2pxb_4rp_4t3d); +#endif + } + return g_test_run(); } diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 43e5a86699..3145c7b5fb 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -259,6 +259,7 @@ qtests_aarch64 =3D \ (config_all_accel.has_key('CONFIG_TCG') and = \ config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test']= : []) + \ (config_all_devices.has_key('CONFIG_ASPEED_SOC') ? qtests_aspeed64 : [])= + \ + qtests_cxl + = \ ['arm-cpu-features', 'numa-test', 'boot-serial-test', --=20 2.48.1