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Both hosts can simply use a 64-bit AND insn instead. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 1 - accel/tcg/translate-all.c | 2 -- tcg/aarch64/tcg-target.c.inc | 6 +----- tcg/i386/tcg-target.c.inc | 6 ++---- 4 files changed, 3 insertions(+), 12 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 3fa5a7aed2..e440c889c8 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -368,7 +368,6 @@ struct TCGContext { =20 int page_mask; uint8_t page_bits; - uint8_t tlb_dyn_max_bits; TCGBar guest_mo; =20 TCGRegSet reserved_regs; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 451b383aa8..6735a40ade 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -24,7 +24,6 @@ #include "tcg/tcg.h" #include "exec/mmap-lock.h" #include "tb-internal.h" -#include "tlb-bounds.h" #include "exec/tb-flush.h" #include "qemu/cacheinfo.h" #include "qemu/target-info.h" @@ -316,7 +315,6 @@ TranslationBlock *tb_gen_code(CPUState *cpu, TCGTBCPUSt= ate s) #ifdef CONFIG_SOFTMMU tcg_ctx->page_bits =3D TARGET_PAGE_BITS; tcg_ctx->page_mask =3D TARGET_PAGE_MASK; - tcg_ctx->tlb_dyn_max_bits =3D CPU_TLB_DYN_MAX_BITS; #endif tcg_ctx->guest_mo =3D cpu->cc->tcg_ops->guest_default_memory_order; =20 diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 4cb647cb34..6356a81c2a 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1661,7 +1661,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, unsigned s_mask =3D (1u << s_bits) - 1; unsigned mem_index =3D get_mmuidx(oi); TCGReg addr_adj; - TCGType mask_type; uint64_t compare_mask; =20 ldst =3D new_ldst_label(s); @@ -1669,9 +1668,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, ldst->oi =3D oi; ldst->addr_reg =3D addr_reg; =20 - mask_type =3D (s->page_bits + s->tlb_dyn_max_bits > 32 - ? TCG_TYPE_I64 : TCG_TYPE_I32); - /* Load cpu->neg.tlb.f[mmu_idx].{mask,table} into {tmp0,tmp1}. */ QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) !=3D 0); QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) !=3D 8); @@ -1679,7 +1675,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, tlb_mask_table_ofs(s, mem_index), 1, 0); =20 /* Extract the TLB index from the address into X0. */ - tcg_out_insn(s, 3502S, AND_LSR, mask_type =3D=3D TCG_TYPE_I64, + tcg_out_insn(s, 3502S, AND_LSR, TCG_TYPE_I64, TCG_REG_TMP0, TCG_REG_TMP0, addr_reg, s->page_bits - CPU_TLB_ENTRY_BITS); =20 diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 09fce27b06..2990912080 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -2199,10 +2199,8 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContex= t *s, HostAddress *h, trexw =3D (ttype =3D=3D TCG_TYPE_I32 ? 0 : P_REXW); if (TCG_TYPE_PTR =3D=3D TCG_TYPE_I64) { hrexw =3D P_REXW; - if (s->page_bits + s->tlb_dyn_max_bits > 32) { - tlbtype =3D TCG_TYPE_I64; - tlbrexw =3D P_REXW; - } + tlbtype =3D TCG_TYPE_I64; + tlbrexw =3D P_REXW; } } =20 --=20 2.43.0