From nobody Sat Nov 15 19:23:12 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1748412530; cv=none; d=zohomail.com; s=zohoarc; b=cA3Y7vpqF3pHx6dOySVejfvM1a7gWaZzgjrst7sk5jiB19Icj7uhhrxeqZ4x0xSfbjpwI9++SiU2kNKWE1qEuVqkccX7eol/XtdqqpFngavrl+mowWPnNd48mmyYzDwQv/08dAjU//jsp2V8YoSGczRoOo4KrXPmO8T3jHk9Wy8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1748412530; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=oTb/4tWMd43quVxgl9+pyQMUU9hrmjTh/LssXyv7Zh0=; b=Vh1ETRp62+QSSsMugx3CDcLRO3ZwB/6knTSP1V3ctHfZpW7+aVfo7NF4aogzBSbKTYrXB6t4VF7dF47RsAhv8ZCkBMqIbYBa6xO6JVkwX0bvkClUg27psvvJZ47igfolG3troYa66+aNuoHRtoK6XmhpLKzJ+5joquYZqRpGTfU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1748412530857273.5415592048678; Tue, 27 May 2025 23:08:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uK9xl-0007s6-5C; Wed, 28 May 2025 02:08:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uK9xj-0007l2-Ac for qemu-devel@nongnu.org; Wed, 28 May 2025 02:08:27 -0400 Received: from mgamail.intel.com ([198.175.65.11]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uK9xh-0000mi-Dl for qemu-devel@nongnu.org; Wed, 28 May 2025 02:08:26 -0400 Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 May 2025 23:08:25 -0700 Received: from spr-s2600bt.bj.intel.com ([10.240.192.127]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 May 2025 23:08:20 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1748412506; x=1779948506; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EMu1zSa7gFaBrB77RJllTGDdUmWEDp2pS9KkWV27FTQ=; b=P50qQF0NkquH+xVeKmmRkFAxs9VOqjogyMDucaKXCjqUfhJynBIx75jD kVvRzIMomRa/5sMIrvTUN+9mGz+GKpmFbr7WqJrlhBPYjWQfiZ+Q8ueLi RE0ASzPqAg6hUORPpm3CqCSAFmFYYlgjagL9RPEtIzaN22f7I2/UFjBQo PeOwCdoJx/IdVvDJY4y8y3RS4J3Td0RxB58sadCF7cfcbi4GtSRKPmlBX AfIvR3JsqYdegnGVXhiMFk/UHskj33KNdQDVtIiQyBwfu5vgv4NLeBZVq 99N5LWrqESLgrqAuBPhziv44akF8YwdDCGJwKL+I27cB5B3iyR3sxsju8 A==; X-CSE-ConnectionGUID: YvzxScoJShmKYy1tHL+qqA== X-CSE-MsgGUID: F84mIBQMQvehtWUzWp/EMQ== X-IronPort-AV: E=McAfee;i="6700,10204,11446"; a="60679009" X-IronPort-AV: E=Sophos;i="6.15,320,1739865600"; d="scan'208";a="60679009" X-CSE-ConnectionGUID: fCbggq8uQnW0KaMk4ZocEw== X-CSE-MsgGUID: 1hiGeCTCTEuVGmmiMhmCGA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,320,1739865600"; d="scan'208";a="143165183" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PATCH v1 6/6] iommufd: Implement query of host VTD IOMMU's capability Date: Wed, 28 May 2025 14:04:09 +0800 Message-Id: <20250528060409.3710008-7-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250528060409.3710008-1-zhenzhong.duan@intel.com> References: <20250528060409.3710008-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.11; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -72 X-Spam_score: -7.3 X-Spam_bar: ------- X-Spam_report: (-7.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.907, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1748412533088116600 Content-Type: text/plain; charset="utf-8" Implement query of HOST_IOMMU_DEVICE_CAP_[NESTING|FS1GP|ERRATA] for IOMMUFD backed host VTD IOMMU device. Query on these capabilities is not supported for legacy backend because the= re is no plan to support nesting with legacy backend backed host device. Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 1 + include/system/host_iommu_device.h | 7 ++++++ backends/iommufd.c | 39 ++++++++++++++++++++++++++++-- 3 files changed, 45 insertions(+), 2 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index e8b211e8b0..2cda744786 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -191,6 +191,7 @@ #define VTD_ECAP_PT (1ULL << 6) #define VTD_ECAP_SC (1ULL << 7) #define VTD_ECAP_MHMV (15ULL << 20) +#define VTD_ECAP_NEST (1ULL << 26) #define VTD_ECAP_SRS (1ULL << 31) #define VTD_ECAP_PASID (1ULL << 40) #define VTD_ECAP_SMTS (1ULL << 43) diff --git a/include/system/host_iommu_device.h b/include/system/host_iommu= _device.h index 10fccc10be..c2770cb469 100644 --- a/include/system/host_iommu_device.h +++ b/include/system/host_iommu_device.h @@ -29,6 +29,10 @@ typedef union VendorCaps { * * @hw_caps: host platform IOMMU capabilities (e.g. on IOMMUFD this repres= ents * the @out_capabilities value returned from IOMMU_GET_HW_INFO i= octl) + * + * @vendor_caps: host platform IOMMU vendor specific capabilities (e.g. on + * IOMMUFD this represents raw vendor data from data_uptr + * buffer returned from IOMMU_GET_HW_INFO ioctl) */ typedef struct HostIOMMUDeviceCaps { uint32_t type; @@ -116,6 +120,9 @@ struct HostIOMMUDeviceClass { */ #define HOST_IOMMU_DEVICE_CAP_IOMMU_TYPE 0 #define HOST_IOMMU_DEVICE_CAP_AW_BITS 1 +#define HOST_IOMMU_DEVICE_CAP_NESTING 2 +#define HOST_IOMMU_DEVICE_CAP_FS1GP 3 +#define HOST_IOMMU_DEVICE_CAP_ERRATA 4 =20 #define HOST_IOMMU_DEVICE_CAP_AW_BITS_MAX 64 #endif diff --git a/backends/iommufd.c b/backends/iommufd.c index b114fb08e7..63209659f3 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -21,6 +21,7 @@ #include "hw/vfio/vfio-device.h" #include #include +#include "hw/i386/intel_iommu_internal.h" =20 static void iommufd_backend_init(Object *obj) { @@ -364,6 +365,41 @@ bool host_iommu_device_iommufd_detach_hwpt(HostIOMMUDe= viceIOMMUFD *idev, return idevc->detach_hwpt(idev, errp); } =20 +static int hiod_iommufd_get_vtd_cap(HostIOMMUDevice *hiod, int cap, + Error **errp) +{ + struct iommu_hw_info_vtd *caps =3D &hiod->caps.vendor_caps.vtd; + + switch (cap) { + case HOST_IOMMU_DEVICE_CAP_NESTING: + return !!(caps->ecap_reg & VTD_ECAP_NEST); + case HOST_IOMMU_DEVICE_CAP_FS1GP: + return !!(caps->cap_reg & VTD_CAP_FS1GP); + case HOST_IOMMU_DEVICE_CAP_ERRATA: + return caps->flags & IOMMU_HW_INFO_VTD_ERRATA_772415_SPR17; + default: + error_setg(errp, "%s: unsupported capability %x", hiod->name, cap); + return -EINVAL; + } +} + +static int hiod_iommufd_get_vendor_cap(HostIOMMUDevice *hiod, int cap, + Error **errp) +{ + enum iommu_hw_info_type type =3D hiod->caps.type; + + switch (type) { + case IOMMU_HW_INFO_TYPE_INTEL_VTD: + return hiod_iommufd_get_vtd_cap(hiod, cap, errp); + case IOMMU_HW_INFO_TYPE_ARM_SMMUV3: + case IOMMU_HW_INFO_TYPE_NONE: + break; + } + + error_setg(errp, "%s: unsupported capability type %x", hiod->name, typ= e); + return -EINVAL; +} + static int hiod_iommufd_get_cap(HostIOMMUDevice *hiod, int cap, Error **er= rp) { HostIOMMUDeviceCaps *caps =3D &hiod->caps; @@ -374,8 +410,7 @@ static int hiod_iommufd_get_cap(HostIOMMUDevice *hiod, = int cap, Error **errp) case HOST_IOMMU_DEVICE_CAP_AW_BITS: return vfio_device_get_aw_bits(hiod->agent); default: - error_setg(errp, "%s: unsupported capability %x", hiod->name, cap); - return -EINVAL; + return hiod_iommufd_get_vendor_cap(hiod, cap, errp); } } =20 --=20 2.34.1