From nobody Sat Nov 15 20:35:35 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1748335529889627.2558127130301; Tue, 27 May 2025 01:45:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uJpve-0003E5-98; Tue, 27 May 2025 04:44:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uJpvb-0003DG-2z for qemu-devel@nongnu.org; Tue, 27 May 2025 04:44:55 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uJpvY-0000eS-TG for qemu-devel@nongnu.org; Tue, 27 May 2025 04:44:54 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxvOKBezVoRRj+AA--.18666S3; Tue, 27 May 2025 16:44:49 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMBx3xtyezVolPn0AA--.53554S7; Tue, 27 May 2025 16:44:48 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , Huacai Chen , qemu-devel@nongnu.org, Xianglai Li Subject: [PATCH v2 05/12] hw/intc/loongarch_ipi: Add kernel irqchip save and restore function Date: Tue, 27 May 2025 16:44:23 +0800 Message-Id: <20250527084430.3468174-6-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250527084430.3468174-1-maobibo@loongson.cn> References: <20250527084430.3468174-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMBx3xtyezVolPn0AA--.53554S7 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1748335531467116600 Content-Type: text/plain; charset="utf-8" Add save and store funtction if kvm_irqchip_in_kernel() return true, it is to get and set IPI irqchip state from KVM kernel. Signed-off-by: Bibo Mao --- hw/intc/loongarch_ipi.c | 20 ++++++++++++ hw/intc/loongarch_ipi_kvm.c | 56 +++++++++++++++++++++++++++++++++ include/hw/intc/loongarch_ipi.h | 2 ++ 3 files changed, 78 insertions(+) diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c index 60fc557a5d..1533a1ccd4 100644 --- a/hw/intc/loongarch_ipi.c +++ b/hw/intc/loongarch_ipi.c @@ -171,6 +171,24 @@ static void loongarch_ipi_cpu_unplug(HotplugHandler *h= otplug_dev, core->cpu =3D NULL; } =20 +static int loongarch_ipi_pre_save(void *opaque) +{ + if (kvm_irqchip_in_kernel()) { + return kvm_loongarch_ipi_pre_save(opaque); + } + + return 0; +} + +static int loongarch_ipi_post_load(void *opaque, int version_id) +{ + if (kvm_irqchip_in_kernel()) { + return kvm_loongarch_ipi_post_load(opaque, version_id); + } + + return 0; +} + static void loongarch_ipi_class_init(ObjectClass *klass, const void *data) { LoongsonIPICommonClass *licc =3D LOONGSON_IPI_COMMON_CLASS(klass); @@ -187,6 +205,8 @@ static void loongarch_ipi_class_init(ObjectClass *klass= , const void *data) licc->cpu_by_arch_id =3D loongarch_cpu_by_arch_id; hc->plug =3D loongarch_ipi_cpu_plug; hc->unplug =3D loongarch_ipi_cpu_unplug; + licc->pre_save =3D loongarch_ipi_pre_save; + licc->post_load =3D loongarch_ipi_post_load; } =20 static const TypeInfo loongarch_ipi_types[] =3D { diff --git a/hw/intc/loongarch_ipi_kvm.c b/hw/intc/loongarch_ipi_kvm.c index e8fcd3bd2f..b5b2b22045 100644 --- a/hw/intc/loongarch_ipi_kvm.c +++ b/hw/intc/loongarch_ipi_kvm.c @@ -11,6 +11,62 @@ #include "system/kvm.h" #include "target/loongarch/cpu.h" =20 +static void kvm_ipi_access_regs(int fd, uint64_t addr, + uint32_t *val, bool write) +{ + kvm_device_access(fd, KVM_DEV_LOONGARCH_IPI_GRP_REGS, + addr, val, write, &error_abort); +} + +static void kvm_loongarch_ipi_save_load_regs(void *opaque, bool write) +{ + LoongsonIPICommonState *ipi =3D (LoongsonIPICommonState *)opaque; + LoongarchIPIState *lis =3D LOONGARCH_IPI(opaque); + IPICore *cpu; + uint64_t attr; + int cpu_id =3D 0; + int fd =3D lis->dev_fd; + + for (cpu_id =3D 0; cpu_id < ipi->num_cpu; cpu_id++) { + cpu =3D &ipi->cpu[cpu_id]; + attr =3D (cpu_id << 16) | CORE_STATUS_OFF; + kvm_ipi_access_regs(fd, attr, &cpu->status, write); + + attr =3D (cpu_id << 16) | CORE_EN_OFF; + kvm_ipi_access_regs(fd, attr, &cpu->en, write); + + attr =3D (cpu_id << 16) | CORE_SET_OFF; + kvm_ipi_access_regs(fd, attr, &cpu->set, write); + + attr =3D (cpu_id << 16) | CORE_CLEAR_OFF; + kvm_ipi_access_regs(fd, attr, &cpu->clear, write); + + attr =3D (cpu_id << 16) | CORE_BUF_20; + kvm_ipi_access_regs(fd, attr, &cpu->buf[0], write); + + attr =3D (cpu_id << 16) | CORE_BUF_28; + kvm_ipi_access_regs(fd, attr, &cpu->buf[2], write); + + attr =3D (cpu_id << 16) | CORE_BUF_30; + kvm_ipi_access_regs(fd, attr, &cpu->buf[4], write); + + attr =3D (cpu_id << 16) | CORE_BUF_38; + kvm_ipi_access_regs(fd, attr, &cpu->buf[6], write); + } +} + +int kvm_loongarch_ipi_pre_save(void *opaque) +{ + kvm_loongarch_ipi_save_load_regs(opaque, false); + return 0; +} + +int kvm_loongarch_ipi_post_load(void *opaque, int version_id) +{ + kvm_loongarch_ipi_save_load_regs(opaque, true); + return 0; +} + void kvm_loongarch_ipi_realize(DeviceState *dev, Error **errp) { LoongarchIPIState *lis =3D LOONGARCH_IPI(dev); diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ip= i.h index a5bcac0c87..4982b2afc7 100644 --- a/include/hw/intc/loongarch_ipi.h +++ b/include/hw/intc/loongarch_ipi.h @@ -26,5 +26,7 @@ struct LoongarchIPIClass { }; =20 void kvm_loongarch_ipi_realize(DeviceState *dev, Error **errp); +int kvm_loongarch_ipi_pre_save(void *opaque); +int kvm_loongarch_ipi_post_load(void *opaque, int version_id); =20 #endif --=20 2.39.3