From nobody Sat Nov 15 18:49:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1748335570960973.466023344081; Tue, 27 May 2025 01:46:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uJpvX-0003Bb-An; Tue, 27 May 2025 04:44:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uJpvV-0003Ax-0B for qemu-devel@nongnu.org; Tue, 27 May 2025 04:44:49 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uJpvO-0000YN-12 for qemu-devel@nongnu.org; Tue, 27 May 2025 04:44:48 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Bx22p2ezVoKRj+AA--.46749S3; Tue, 27 May 2025 16:44:38 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMBx3xtyezVolPn0AA--.53554S3; Tue, 27 May 2025 16:44:37 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , Huacai Chen , qemu-devel@nongnu.org, Xianglai Li Subject: [PATCH v2 01/12] hw/intc/loongarch_extioi: Add kernel irqchip realize function Date: Tue, 27 May 2025 16:44:19 +0800 Message-Id: <20250527084430.3468174-2-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250527084430.3468174-1-maobibo@loongson.cn> References: <20250527084430.3468174-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMBx3xtyezVolPn0AA--.53554S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1748335572739116600 Content-Type: text/plain; charset="utf-8" Function kvm_loongarch_extioi_realize() is added if kvm_irqchip_in_kernel is set. It is to create and initialize ExtIOI device in kernel mode. Signed-off-by: Bibo Mao --- hw/intc/loongarch_extioi.c | 31 ++++++++++++-------- hw/intc/loongarch_extioi_kvm.c | 46 ++++++++++++++++++++++++++++++ hw/intc/meson.build | 2 ++ include/hw/intc/loongarch_extioi.h | 3 ++ 4 files changed, 70 insertions(+), 12 deletions(-) create mode 100644 hw/intc/loongarch_extioi_kvm.c diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c index 7c38c4c9b7..06fe30dd3a 100644 --- a/hw/intc/loongarch_extioi.c +++ b/hw/intc/loongarch_extioi.c @@ -12,6 +12,7 @@ #include "hw/irq.h" #include "hw/loongarch/virt.h" #include "system/address-spaces.h" +#include "system/kvm.h" #include "hw/intc/loongarch_extioi.h" #include "trace.h" =20 @@ -351,23 +352,29 @@ static void loongarch_extioi_realize(DeviceState *dev= , Error **errp) return; } =20 - for (i =3D 0; i < EXTIOI_IRQS; i++) { - sysbus_init_irq(sbd, &s->irq[i]); - } - - qdev_init_gpio_in(dev, extioi_setirq, EXTIOI_IRQS); - memory_region_init_io(&s->extioi_system_mem, OBJECT(s), &extioi_ops, - s, "extioi_system_mem", 0x900); - sysbus_init_mmio(sbd, &s->extioi_system_mem); - if (s->features & BIT(EXTIOI_HAS_VIRT_EXTENSION)) { - memory_region_init_io(&s->virt_extend, OBJECT(s), &extioi_virt_ops, - s, "extioi_virt", EXTIOI_VIRT_SIZE); - sysbus_init_mmio(sbd, &s->virt_extend); s->features |=3D EXTIOI_VIRT_HAS_FEATURES; } else { s->status |=3D BIT(EXTIOI_ENABLE); } + + if (kvm_irqchip_in_kernel()) { + kvm_loongarch_extioi_realize(dev, errp); + } else { + for (i =3D 0; i < EXTIOI_IRQS; i++) { + sysbus_init_irq(sbd, &s->irq[i]); + } + + qdev_init_gpio_in(dev, extioi_setirq, EXTIOI_IRQS); + memory_region_init_io(&s->extioi_system_mem, OBJECT(s), &extioi_op= s, + s, "extioi_system_mem", 0x900); + sysbus_init_mmio(sbd, &s->extioi_system_mem); + if (s->features & BIT(EXTIOI_HAS_VIRT_EXTENSION)) { + memory_region_init_io(&s->virt_extend, OBJECT(s), &extioi_virt= _ops, + s, "extioi_virt", EXTIOI_VIRT_SIZE); + sysbus_init_mmio(sbd, &s->virt_extend); + } + } } =20 static void loongarch_extioi_unrealize(DeviceState *dev) diff --git a/hw/intc/loongarch_extioi_kvm.c b/hw/intc/loongarch_extioi_kvm.c new file mode 100644 index 0000000000..833ec856ee --- /dev/null +++ b/hw/intc/loongarch_extioi_kvm.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * LoongArch EXTIOI interrupt kvm support + * + * Copyright (C) 2025 Loongson Technology Corporation Limited + */ + +#include "qemu/osdep.h" +#include "qemu/typedefs.h" +#include "hw/intc/loongarch_extioi.h" +#include "linux/kvm.h" +#include "qapi/error.h" +#include "system/kvm.h" + +void kvm_loongarch_extioi_realize(DeviceState *dev, Error **errp) +{ + LoongArchExtIOICommonState *lecs =3D LOONGARCH_EXTIOI_COMMON(dev); + LoongArchExtIOIState *les =3D LOONGARCH_EXTIOI(dev); + int ret; + + ret =3D kvm_create_device(kvm_state, KVM_DEV_TYPE_LOONGARCH_EIOINTC, f= alse); + if (ret < 0) { + fprintf(stderr, "create KVM_LOONGARCH_EIOINTC failed: %s\n", + strerror(-ret)); + abort(); + } + + les->dev_fd =3D ret; + ret =3D kvm_device_access(les->dev_fd, KVM_DEV_LOONGARCH_EXTIOI_GRP_CT= RL, + KVM_DEV_LOONGARCH_EXTIOI_CTRL_INIT_NUM_CPU, + &lecs->num_cpu, true, NULL); + if (ret < 0) { + fprintf(stderr, "KVM_LOONGARCH_EXTIOI_INIT_NUM_CPU failed: %s\n", + strerror(-ret)); + abort(); + } + + ret =3D kvm_device_access(les->dev_fd, KVM_DEV_LOONGARCH_EXTIOI_GRP_CT= RL, + KVM_DEV_LOONGARCH_EXTIOI_CTRL_INIT_FEATURE, + &lecs->features, true, NULL); + if (ret < 0) { + fprintf(stderr, "KVM_LOONGARCH_EXTIOI_INIT_FEATURE failed: %s\n", + strerror(-ret)); + abort(); + } +} diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 602da304b0..70e7548c52 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -74,3 +74,5 @@ specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true: fi= les('loongarch_ipi.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarc= h_pch_pic.c', 'loongarch_pic_common.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarc= h_pch_msi.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_EXTIOI', if_true: files('loongarch= _extioi.c', 'loongarch_extioi_common.c')) +specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_LOONGARCH_EXTIOI'], + if_true: files('loongarch_extioi_kvm.c')) diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch= _extioi.h index 4a6ae903e9..ed328433f6 100644 --- a/include/hw/intc/loongarch_extioi.h +++ b/include/hw/intc/loongarch_extioi.h @@ -15,6 +15,7 @@ OBJECT_DECLARE_TYPE(LoongArchExtIOIState, LoongArchExtIOI= Class, LOONGARCH_EXTIOI =20 struct LoongArchExtIOIState { LoongArchExtIOICommonState parent_obj; + int dev_fd; }; =20 struct LoongArchExtIOIClass { @@ -25,4 +26,6 @@ struct LoongArchExtIOIClass { ResettablePhases parent_phases; }; =20 +void kvm_loongarch_extioi_realize(DeviceState *dev, Error **errp); + #endif /* LOONGARCH_EXTIOI_H */ --=20 2.39.3 From nobody Sat Nov 15 18:49:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1748335630451309.37313972690663; Tue, 27 May 2025 01:47:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uJpvi-0003Fk-H5; Tue, 27 May 2025 04:45:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uJpvZ-0003Cl-R3 for qemu-devel@nongnu.org; Tue, 27 May 2025 04:44:54 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uJpvR-0000ZC-AG for qemu-devel@nongnu.org; Tue, 27 May 2025 04:44:53 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8DxDeN5ezVoLxj+AA--.46790S3; Tue, 27 May 2025 16:44:41 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMBx3xtyezVolPn0AA--.53554S4; Tue, 27 May 2025 16:44:40 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , Huacai Chen , qemu-devel@nongnu.org, Xianglai Li Subject: [PATCH v2 02/12] hw/intc/loongarch_extioi: Add kernel irqchip save and restore function Date: Tue, 27 May 2025 16:44:20 +0800 Message-Id: <20250527084430.3468174-3-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250527084430.3468174-1-maobibo@loongson.cn> References: <20250527084430.3468174-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMBx3xtyezVolPn0AA--.53554S4 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1748335631603116600 Content-Type: text/plain; charset="utf-8" Add save and store funtction if kvm_irqchip_in_kernel() return true, it is to get and set ExtIOI irqchip state from KVM kernel. Signed-off-by: Bibo Mao --- hw/intc/loongarch_extioi.c | 14 ++++ hw/intc/loongarch_extioi_kvm.c | 100 +++++++++++++++++++++++++++++ include/hw/intc/loongarch_extioi.h | 2 + 3 files changed, 116 insertions(+) diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c index 06fe30dd3a..c63c176f9c 100644 --- a/hw/intc/loongarch_extioi.c +++ b/hw/intc/loongarch_extioi.c @@ -393,11 +393,24 @@ static void loongarch_extioi_reset_hold(Object *obj, = ResetType type) } } =20 +static int vmstate_extioi_pre_save(void *opaque) +{ + if (kvm_irqchip_in_kernel()) { + return kvm_loongarch_extioi_pre_save(opaque); + } + + return 0; +} + static int vmstate_extioi_post_load(void *opaque, int version_id) { LoongArchExtIOICommonState *s =3D LOONGARCH_EXTIOI_COMMON(opaque); int i, start_irq; =20 + if (kvm_irqchip_in_kernel()) { + return kvm_loongarch_extioi_post_load(opaque, version_id); + } + for (i =3D 0; i < (EXTIOI_IRQS / 4); i++) { start_irq =3D i * 4; extioi_update_sw_coremap(s, start_irq, s->coremap[i], false); @@ -423,6 +436,7 @@ static void loongarch_extioi_class_init(ObjectClass *kl= ass, const void *data) &lec->parent_unrealize); resettable_class_set_parent_phases(rc, NULL, loongarch_extioi_reset_ho= ld, NULL, &lec->parent_phases); + lecc->pre_save =3D vmstate_extioi_pre_save; lecc->post_load =3D vmstate_extioi_post_load; } =20 diff --git a/hw/intc/loongarch_extioi_kvm.c b/hw/intc/loongarch_extioi_kvm.c index 833ec856ee..9c5649dd1a 100644 --- a/hw/intc/loongarch_extioi_kvm.c +++ b/hw/intc/loongarch_extioi_kvm.c @@ -12,6 +12,106 @@ #include "qapi/error.h" #include "system/kvm.h" =20 +static void kvm_extioi_access_regs(int fd, uint64_t addr, + void *val, bool write) +{ + kvm_device_access(fd, KVM_DEV_LOONGARCH_EXTIOI_GRP_REGS, + addr, val, write, &error_abort); +} + +static void kvm_extioi_access_sw_status(int fd, uint64_t addr, + void *val, bool write) +{ + kvm_device_access(fd, KVM_DEV_LOONGARCH_EXTIOI_GRP_SW_STATUS, + addr, val, write, &error_abort); +} + +static void kvm_extioi_save_load_sw_status(void *opaque, bool write) +{ + LoongArchExtIOICommonState *lecs =3D LOONGARCH_EXTIOI_COMMON(opaque); + LoongArchExtIOIState *les =3D LOONGARCH_EXTIOI(opaque); + int fd =3D les->dev_fd; + int addr; + + addr =3D KVM_DEV_LOONGARCH_EXTIOI_SW_STATUS_NUM_CPU; + kvm_extioi_access_sw_status(fd, addr, &lecs->num_cpu, write); + + addr =3D KVM_DEV_LOONGARCH_EXTIOI_SW_STATUS_FEATURE; + kvm_extioi_access_sw_status(fd, addr, &lecs->features, write); + + addr =3D KVM_DEV_LOONGARCH_EXTIOI_SW_STATUS_STATE; + kvm_extioi_access_sw_status(fd, addr, &lecs->status, write); +} + +static void kvm_extioi_save_load_regs(void *opaque, bool write) +{ + LoongArchExtIOICommonState *lecs =3D LOONGARCH_EXTIOI_COMMON(opaque); + LoongArchExtIOIState *les =3D LOONGARCH_EXTIOI(opaque); + int fd =3D les->dev_fd; + int addr, offset, cpuid; + + for (addr =3D EXTIOI_NODETYPE_START; addr < EXTIOI_NODETYPE_END; addr = +=3D 4) { + offset =3D (addr - EXTIOI_NODETYPE_START) / 4; + kvm_extioi_access_regs(fd, addr, &lecs->nodetype[offset], write); + } + + for (addr =3D EXTIOI_IPMAP_START; addr < EXTIOI_IPMAP_END; addr +=3D 4= ) { + offset =3D (addr - EXTIOI_IPMAP_START) / 4; + kvm_extioi_access_regs(fd, addr, &lecs->ipmap[offset], write); + } + + for (addr =3D EXTIOI_ENABLE_START; addr < EXTIOI_ENABLE_END; addr +=3D= 4) { + offset =3D (addr - EXTIOI_ENABLE_START) / 4; + kvm_extioi_access_regs(fd, addr, &lecs->enable[offset], write); + } + + for (addr =3D EXTIOI_BOUNCE_START; addr < EXTIOI_BOUNCE_END; addr +=3D= 4) { + offset =3D (addr - EXTIOI_BOUNCE_START) / 4; + kvm_extioi_access_regs(fd, addr, &lecs->bounce[offset], write); + } + + for (addr =3D EXTIOI_ISR_START; addr < EXTIOI_ISR_END; addr +=3D 4) { + offset =3D (addr - EXTIOI_ISR_START) / 4; + kvm_extioi_access_regs(fd, addr, &lecs->isr[offset], write); + } + + for (addr =3D EXTIOI_COREMAP_START; addr < EXTIOI_COREMAP_END; addr += =3D 4) { + offset =3D (addr - EXTIOI_COREMAP_START) / 4; + kvm_extioi_access_regs(fd, addr, &lecs->coremap[offset], write); + } + + for (cpuid =3D 0; cpuid < lecs->num_cpu; cpuid++) { + for (addr =3D EXTIOI_COREISR_START; + addr < EXTIOI_COREISR_END; addr +=3D 4) { + offset =3D (addr - EXTIOI_COREISR_START) / 4; + addr =3D (cpuid << 16) | addr; + kvm_extioi_access_regs(fd, addr, + &lecs->cpu[cpuid].coreisr[offset], writ= e); + } + } +} + +int kvm_loongarch_extioi_pre_save(void *opaque) +{ + kvm_extioi_save_load_regs(opaque, false); + kvm_extioi_save_load_sw_status(opaque, false); + return 0; +} + +int kvm_loongarch_extioi_post_load(void *opaque, int version_id) +{ + LoongArchExtIOIState *les =3D LOONGARCH_EXTIOI(opaque); + int fd =3D les->dev_fd; + + kvm_extioi_save_load_regs(opaque, true); + kvm_extioi_save_load_sw_status(opaque, true); + + kvm_device_access(fd, KVM_DEV_LOONGARCH_EXTIOI_GRP_CTRL, + KVM_DEV_LOONGARCH_EXTIOI_CTRL_LOAD_FINISHED, + NULL, true, &error_abort); + return 0; +} + void kvm_loongarch_extioi_realize(DeviceState *dev, Error **errp) { LoongArchExtIOICommonState *lecs =3D LOONGARCH_EXTIOI_COMMON(dev); diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch= _extioi.h index ed328433f6..5e9aa365e3 100644 --- a/include/hw/intc/loongarch_extioi.h +++ b/include/hw/intc/loongarch_extioi.h @@ -27,5 +27,7 @@ struct LoongArchExtIOIClass { }; =20 void kvm_loongarch_extioi_realize(DeviceState *dev, Error **errp); +int kvm_loongarch_extioi_pre_save(void *opaque); +int kvm_loongarch_extioi_post_load(void *opaque, int version_id); =20 #endif /* LOONGARCH_EXTIOI_H */ --=20 2.39.3 From nobody Sat Nov 15 18:49:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1748335551409986.4407379304512; Tue, 27 May 2025 01:45:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uJpvX-0003Br-L2; Tue, 27 May 2025 04:44:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uJpvV-0003B8-9K for qemu-devel@nongnu.org; Tue, 27 May 2025 04:44:49 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uJpvS-0000aY-0P for qemu-devel@nongnu.org; Tue, 27 May 2025 04:44:49 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Bx63F6ezVoNRj+AA--.16290S3; Tue, 27 May 2025 16:44:42 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMBx3xtyezVolPn0AA--.53554S5; Tue, 27 May 2025 16:44:42 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , Huacai Chen , qemu-devel@nongnu.org, Xianglai Li Subject: [PATCH v2 03/12] hw/intc/loongarch_ipi: Add kernel irqchip realize function Date: Tue, 27 May 2025 16:44:21 +0800 Message-Id: <20250527084430.3468174-4-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250527084430.3468174-1-maobibo@loongson.cn> References: <20250527084430.3468174-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMBx3xtyezVolPn0AA--.53554S5 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1748335552633116600 Content-Type: text/plain; charset="utf-8" Function kvm_loongarch_ipi_realize() is added if kvm_irqchip_in_kernel() return true. It is to create and initialize IPI device in kernel mode. Signed-off-by: Bibo Mao --- hw/intc/loongarch_ipi.c | 5 +++++ hw/intc/loongarch_ipi_kvm.c | 27 +++++++++++++++++++++++++++ hw/intc/loongson_ipi_common.c | 5 +++++ hw/intc/meson.build | 2 ++ include/hw/intc/loongarch_ipi.h | 3 +++ 5 files changed, 42 insertions(+) create mode 100644 hw/intc/loongarch_ipi_kvm.c diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c index 74372a2039..60fc557a5d 100644 --- a/hw/intc/loongarch_ipi.c +++ b/hw/intc/loongarch_ipi.c @@ -11,6 +11,7 @@ #include "qapi/error.h" #include "hw/intc/loongarch_ipi.h" #include "hw/qdev-properties.h" +#include "system/kvm.h" #include "target/loongarch/cpu.h" =20 static AddressSpace *get_iocsr_as(CPUState *cpu) @@ -91,6 +92,10 @@ static void loongarch_ipi_realize(DeviceState *dev, Erro= r **errp) lics->cpu[i].ipi =3D lics; qdev_init_gpio_out(dev, &lics->cpu[i].irq, 1); } + + if (kvm_irqchip_in_kernel()) { + kvm_loongarch_ipi_realize(dev, errp); + } } =20 static void loongarch_ipi_reset_hold(Object *obj, ResetType type) diff --git a/hw/intc/loongarch_ipi_kvm.c b/hw/intc/loongarch_ipi_kvm.c new file mode 100644 index 0000000000..e8fcd3bd2f --- /dev/null +++ b/hw/intc/loongarch_ipi_kvm.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * LoongArch IPI interrupt KVM support + * + * Copyright (C) 2025 Loongson Technology Corporation Limited + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/intc/loongarch_ipi.h" +#include "system/kvm.h" +#include "target/loongarch/cpu.h" + +void kvm_loongarch_ipi_realize(DeviceState *dev, Error **errp) +{ + LoongarchIPIState *lis =3D LOONGARCH_IPI(dev); + int ret; + + ret =3D kvm_create_device(kvm_state, KVM_DEV_TYPE_LOONGARCH_IPI, false= ); + if (ret < 0) { + fprintf(stderr, "IPI KVM_CREATE_DEVICE failed: %s\n", + strerror(-ret)); + abort(); + } + + lis->dev_fd =3D ret; +} diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c index f32661c40f..ff2cc8bc91 100644 --- a/hw/intc/loongson_ipi_common.c +++ b/hw/intc/loongson_ipi_common.c @@ -11,6 +11,7 @@ #include "hw/irq.h" #include "qemu/log.h" #include "migration/vmstate.h" +#include "system/kvm.h" #include "trace.h" =20 MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *d= ata, @@ -255,6 +256,10 @@ static void loongson_ipi_common_realize(DeviceState *d= ev, Error **errp) LoongsonIPICommonState *s =3D LOONGSON_IPI_COMMON(dev); SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); =20 + if (kvm_irqchip_in_kernel()) { + return; + } + memory_region_init_io(&s->ipi_iocsr_mem, OBJECT(dev), &loongson_ipi_iocsr_ops, s, "loongson_ipi_iocsr", 0x48); diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 70e7548c52..1cc999771d 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -71,6 +71,8 @@ specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files(= 'm68k_irqc.c')) specific_ss.add(when: 'CONFIG_LOONGSON_IPI_COMMON', if_true: files('loongs= on_ipi_common.c')) specific_ss.add(when: 'CONFIG_LOONGSON_IPI', if_true: files('loongson_ipi.= c')) specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true: files('loongarch_ip= i.c')) +specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_LOONGARCH_IPI'], + if_true: files('loongarch_ipi_kvm.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarc= h_pch_pic.c', 'loongarch_pic_common.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarc= h_pch_msi.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_EXTIOI', if_true: files('loongarch= _extioi.c', 'loongarch_extioi_common.c')) diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ip= i.h index a7c6bf85d3..a5bcac0c87 100644 --- a/include/hw/intc/loongarch_ipi.h +++ b/include/hw/intc/loongarch_ipi.h @@ -16,6 +16,7 @@ OBJECT_DECLARE_TYPE(LoongarchIPIState, LoongarchIPIClass,= LOONGARCH_IPI) =20 struct LoongarchIPIState { LoongsonIPICommonState parent_obj; + int dev_fd; }; =20 struct LoongarchIPIClass { @@ -24,4 +25,6 @@ struct LoongarchIPIClass { ResettablePhases parent_phases; }; =20 +void kvm_loongarch_ipi_realize(DeviceState *dev, Error **errp); + #endif --=20 2.39.3 From nobody Sat Nov 15 18:49:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1748335511868798.1953429063698; Tue, 27 May 2025 01:45:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uJpva-0003Cn-BW; Tue, 27 May 2025 04:44:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uJpvY-0003Bt-4g for qemu-devel@nongnu.org; Tue, 27 May 2025 04:44:52 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uJpvV-0000bD-0L for qemu-devel@nongnu.org; Tue, 27 May 2025 04:44:50 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxSWp9ezVoPBj+AA--.46540S3; Tue, 27 May 2025 16:44:45 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMBx3xtyezVolPn0AA--.53554S6; Tue, 27 May 2025 16:44:43 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , Huacai Chen , qemu-devel@nongnu.org, Xianglai Li Subject: [PATCH v2 04/12] hw/intc/loongson_ipi: Add load and save interface with ipi_common class Date: Tue, 27 May 2025 16:44:22 +0800 Message-Id: <20250527084430.3468174-5-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250527084430.3468174-1-maobibo@loongson.cn> References: <20250527084430.3468174-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMBx3xtyezVolPn0AA--.53554S6 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1748335514957116600 Content-Type: text/plain; charset="utf-8" Add pre_save and post_load interfaces with ipi_common class, here only framework ipi_common adds these interfaces. The defailed implementation is LoongArchIPI child device in later. Signed-off-by: Bibo Mao --- hw/intc/loongson_ipi_common.c | 28 +++++++++++++++++++++++++++ include/hw/intc/loongson_ipi_common.h | 2 ++ 2 files changed, 30 insertions(+) diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c index ff2cc8bc91..8cd78d4858 100644 --- a/hw/intc/loongson_ipi_common.c +++ b/hw/intc/loongson_ipi_common.c @@ -282,10 +282,38 @@ static void loongson_ipi_common_unrealize(DeviceState= *dev) g_free(s->cpu); } =20 +static int loongson_ipi_common_pre_save(void *opaque) +{ + IPICore *ipicore =3D (IPICore *)opaque; + LoongsonIPICommonState *s =3D ipicore->ipi; + LoongsonIPICommonClass *licc =3D LOONGSON_IPI_COMMON_GET_CLASS(s); + + if (licc->pre_save) { + return licc->pre_save(s); + } + + return 0; +} + +static int loongson_ipi_common_post_load(void *opaque, int version_id) +{ + IPICore *ipicore =3D (IPICore *)opaque; + LoongsonIPICommonState *s =3D ipicore->ipi; + LoongsonIPICommonClass *licc =3D LOONGSON_IPI_COMMON_GET_CLASS(s); + + if (licc->post_load) { + return licc->post_load(s, version_id); + } + + return 0; +} + static const VMStateDescription vmstate_ipi_core =3D { .name =3D "ipi-single", .version_id =3D 2, .minimum_version_id =3D 2, + .pre_save =3D loongson_ipi_common_pre_save, + .post_load =3D loongson_ipi_common_post_load, .fields =3D (const VMStateField[]) { VMSTATE_UINT32(status, IPICore), VMSTATE_UINT32(en, IPICore), diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongs= on_ipi_common.h index b587f9c571..e58ce2aa1c 100644 --- a/include/hw/intc/loongson_ipi_common.h +++ b/include/hw/intc/loongson_ipi_common.h @@ -48,6 +48,8 @@ struct LoongsonIPICommonClass { AddressSpace *(*get_iocsr_as)(CPUState *cpu); int (*cpu_by_arch_id)(LoongsonIPICommonState *lics, int64_t id, int *index, CPUState **pcs); + int (*pre_save)(void *opaque); + int (*post_load)(void *opaque, int version_id); }; =20 MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *d= ata, --=20 2.39.3 From nobody Sat Nov 15 18:49:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1748335529889627.2558127130301; Tue, 27 May 2025 01:45:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uJpve-0003E5-98; Tue, 27 May 2025 04:44:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uJpvb-0003DG-2z for qemu-devel@nongnu.org; Tue, 27 May 2025 04:44:55 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uJpvY-0000eS-TG for qemu-devel@nongnu.org; Tue, 27 May 2025 04:44:54 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxvOKBezVoRRj+AA--.18666S3; Tue, 27 May 2025 16:44:49 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMBx3xtyezVolPn0AA--.53554S7; Tue, 27 May 2025 16:44:48 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , Huacai Chen , qemu-devel@nongnu.org, Xianglai Li Subject: [PATCH v2 05/12] hw/intc/loongarch_ipi: Add kernel irqchip save and restore function Date: Tue, 27 May 2025 16:44:23 +0800 Message-Id: <20250527084430.3468174-6-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250527084430.3468174-1-maobibo@loongson.cn> References: <20250527084430.3468174-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMBx3xtyezVolPn0AA--.53554S7 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1748335531467116600 Content-Type: text/plain; charset="utf-8" Add save and store funtction if kvm_irqchip_in_kernel() return true, it is to get and set IPI irqchip state from KVM kernel. Signed-off-by: Bibo Mao --- hw/intc/loongarch_ipi.c | 20 ++++++++++++ hw/intc/loongarch_ipi_kvm.c | 56 +++++++++++++++++++++++++++++++++ include/hw/intc/loongarch_ipi.h | 2 ++ 3 files changed, 78 insertions(+) diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c index 60fc557a5d..1533a1ccd4 100644 --- a/hw/intc/loongarch_ipi.c +++ b/hw/intc/loongarch_ipi.c @@ -171,6 +171,24 @@ static void loongarch_ipi_cpu_unplug(HotplugHandler *h= otplug_dev, core->cpu =3D NULL; } =20 +static int loongarch_ipi_pre_save(void *opaque) +{ + if (kvm_irqchip_in_kernel()) { + return kvm_loongarch_ipi_pre_save(opaque); + } + + return 0; +} + +static int loongarch_ipi_post_load(void *opaque, int version_id) +{ + if (kvm_irqchip_in_kernel()) { + return kvm_loongarch_ipi_post_load(opaque, version_id); + } + + return 0; +} + static void loongarch_ipi_class_init(ObjectClass *klass, const void *data) { LoongsonIPICommonClass *licc =3D LOONGSON_IPI_COMMON_CLASS(klass); @@ -187,6 +205,8 @@ static void loongarch_ipi_class_init(ObjectClass *klass= , const void *data) licc->cpu_by_arch_id =3D loongarch_cpu_by_arch_id; hc->plug =3D loongarch_ipi_cpu_plug; hc->unplug =3D loongarch_ipi_cpu_unplug; + licc->pre_save =3D loongarch_ipi_pre_save; + licc->post_load =3D loongarch_ipi_post_load; } =20 static const TypeInfo loongarch_ipi_types[] =3D { diff --git a/hw/intc/loongarch_ipi_kvm.c b/hw/intc/loongarch_ipi_kvm.c index e8fcd3bd2f..b5b2b22045 100644 --- a/hw/intc/loongarch_ipi_kvm.c +++ b/hw/intc/loongarch_ipi_kvm.c @@ -11,6 +11,62 @@ #include "system/kvm.h" #include "target/loongarch/cpu.h" =20 +static void kvm_ipi_access_regs(int fd, uint64_t addr, + uint32_t *val, bool write) +{ + kvm_device_access(fd, KVM_DEV_LOONGARCH_IPI_GRP_REGS, + addr, val, write, &error_abort); +} + +static void kvm_loongarch_ipi_save_load_regs(void *opaque, bool write) +{ + LoongsonIPICommonState *ipi =3D (LoongsonIPICommonState *)opaque; + LoongarchIPIState *lis =3D LOONGARCH_IPI(opaque); + IPICore *cpu; + uint64_t attr; + int cpu_id =3D 0; + int fd =3D lis->dev_fd; + + for (cpu_id =3D 0; cpu_id < ipi->num_cpu; cpu_id++) { + cpu =3D &ipi->cpu[cpu_id]; + attr =3D (cpu_id << 16) | CORE_STATUS_OFF; + kvm_ipi_access_regs(fd, attr, &cpu->status, write); + + attr =3D (cpu_id << 16) | CORE_EN_OFF; + kvm_ipi_access_regs(fd, attr, &cpu->en, write); + + attr =3D (cpu_id << 16) | CORE_SET_OFF; + kvm_ipi_access_regs(fd, attr, &cpu->set, write); + + attr =3D (cpu_id << 16) | CORE_CLEAR_OFF; + kvm_ipi_access_regs(fd, attr, &cpu->clear, write); + + attr =3D (cpu_id << 16) | CORE_BUF_20; + kvm_ipi_access_regs(fd, attr, &cpu->buf[0], write); + + attr =3D (cpu_id << 16) | CORE_BUF_28; + kvm_ipi_access_regs(fd, attr, &cpu->buf[2], write); + + attr =3D (cpu_id << 16) | CORE_BUF_30; + kvm_ipi_access_regs(fd, attr, &cpu->buf[4], write); + + attr =3D (cpu_id << 16) | CORE_BUF_38; + kvm_ipi_access_regs(fd, attr, &cpu->buf[6], write); + } +} + +int kvm_loongarch_ipi_pre_save(void *opaque) +{ + kvm_loongarch_ipi_save_load_regs(opaque, false); + return 0; +} + +int kvm_loongarch_ipi_post_load(void *opaque, int version_id) +{ + kvm_loongarch_ipi_save_load_regs(opaque, true); + return 0; +} + void kvm_loongarch_ipi_realize(DeviceState *dev, Error **errp) { LoongarchIPIState *lis =3D LOONGARCH_IPI(dev); diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ip= i.h index a5bcac0c87..4982b2afc7 100644 --- a/include/hw/intc/loongarch_ipi.h +++ b/include/hw/intc/loongarch_ipi.h @@ -26,5 +26,7 @@ struct LoongarchIPIClass { }; =20 void kvm_loongarch_ipi_realize(DeviceState *dev, Error **errp); +int kvm_loongarch_ipi_pre_save(void *opaque); +int kvm_loongarch_ipi_post_load(void *opaque, int version_id); =20 #endif --=20 2.39.3 From nobody Sat Nov 15 18:49:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174833553443592.06184614073675; Tue, 27 May 2025 01:45:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uJpvh-0003Ex-0D; Tue, 27 May 2025 04:45:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uJpvc-0003Dy-Pa for qemu-devel@nongnu.org; Tue, 27 May 2025 04:44:56 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uJpva-0000eZ-OZ for qemu-devel@nongnu.org; Tue, 27 May 2025 04:44:56 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxCGqDezVoSxj+AA--.16324S3; Tue, 27 May 2025 16:44:51 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMBx3xtyezVolPn0AA--.53554S8; Tue, 27 May 2025 16:44:50 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , Huacai Chen , qemu-devel@nongnu.org, Xianglai Li Subject: [PATCH v2 06/12] hw/intc/loongarch_pch_msi: Inject MSI interrupt to kernel Date: Tue, 27 May 2025 16:44:24 +0800 Message-Id: <20250527084430.3468174-7-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250527084430.3468174-1-maobibo@loongson.cn> References: <20250527084430.3468174-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMBx3xtyezVolPn0AA--.53554S8 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1748335536588116600 Content-Type: text/plain; charset="utf-8" If kvm_irqchip_in_kernel() return true, MSI interrupt can be injected with API kvm_irqchip_send_msi() to KVM. Signed-off-by: Bibo Mao --- hw/intc/loongarch_pch_msi.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/intc/loongarch_pch_msi.c b/hw/intc/loongarch_pch_msi.c index 06eb944da0..f6d163158d 100644 --- a/hw/intc/loongarch_pch_msi.c +++ b/hw/intc/loongarch_pch_msi.c @@ -13,6 +13,7 @@ #include "hw/pci/msi.h" #include "hw/misc/unimp.h" #include "migration/vmstate.h" +#include "system/kvm.h" #include "trace.h" =20 static uint64_t loongarch_msi_mem_read(void *opaque, hwaddr addr, unsigned= size) @@ -26,6 +27,15 @@ static void loongarch_msi_mem_write(void *opaque, hwaddr= addr, LoongArchPCHMSI *s =3D (LoongArchPCHMSI *)opaque; int irq_num; =20 + if (kvm_irqchip_in_kernel()) { + MSIMessage msg; + + msg.address =3D addr; + msg.data =3D val; + kvm_irqchip_send_msi(kvm_state, msg); + return; + } + /* * vector number is irq number from upper extioi intc * need subtract irq base to get msi vector offset --=20 2.39.3 From nobody Sat Nov 15 18:49:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1748335528747365.0987285416503; Tue, 27 May 2025 01:45:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uJpvg-0003Et-W8; Tue, 27 May 2025 04:45:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uJpvd-0003E6-8v for qemu-devel@nongnu.org; Tue, 27 May 2025 04:44:57 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uJpvb-0000fN-41 for qemu-devel@nongnu.org; Tue, 27 May 2025 04:44:57 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Bx32uEezVoVRj+AA--.16358S3; Tue, 27 May 2025 16:44:52 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMBx3xtyezVolPn0AA--.53554S9; Tue, 27 May 2025 16:44:52 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , Huacai Chen , qemu-devel@nongnu.org, Xianglai Li Subject: [PATCH v2 07/12] hw/intc/loongarch_pch: Add kernel irqchip realize function Date: Tue, 27 May 2025 16:44:25 +0800 Message-Id: <20250527084430.3468174-8-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250527084430.3468174-1-maobibo@loongson.cn> References: <20250527084430.3468174-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMBx3xtyezVolPn0AA--.53554S9 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1748335531463116600 Content-Type: text/plain; charset="utf-8" Function kvm_loongarch_pic_realize() is added if kvm_irqchip_in_kernel() return true. It is to notify KVM kernel to create and initialize PCH PCI device in kernel mode. Signed-off-by: Bibo Mao --- hw/intc/loongarch_pch_pic.c | 14 ++++++++--- hw/intc/loongarch_pic_kvm.c | 38 +++++++++++++++++++++++++++++ hw/intc/meson.build | 2 ++ include/hw/intc/loongarch_pch_pic.h | 3 +++ 4 files changed, 53 insertions(+), 4 deletions(-) create mode 100644 hw/intc/loongarch_pic_kvm.c diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c index cbba2fc284..f454df576a 100644 --- a/hw/intc/loongarch_pch_pic.c +++ b/hw/intc/loongarch_pch_pic.c @@ -10,6 +10,7 @@ #include "qemu/log.h" #include "hw/irq.h" #include "hw/intc/loongarch_pch_pic.h" +#include "system/kvm.h" #include "trace.h" #include "qapi/error.h" =20 @@ -275,10 +276,15 @@ static void loongarch_pic_realize(DeviceState *dev, E= rror **errp) =20 qdev_init_gpio_out(dev, s->parent_irq, s->irq_num); qdev_init_gpio_in(dev, pch_pic_irq_handler, s->irq_num); - memory_region_init_io(&s->iomem, OBJECT(dev), - &loongarch_pch_pic_ops, - s, TYPE_LOONGARCH_PIC, VIRT_PCH_REG_SIZE); - sysbus_init_mmio(sbd, &s->iomem); + + if (kvm_irqchip_in_kernel()) { + kvm_loongarch_pic_realize(dev, errp); + } else { + memory_region_init_io(&s->iomem, OBJECT(dev), + &loongarch_pch_pic_ops, + s, TYPE_LOONGARCH_PIC, VIRT_PCH_REG_SIZE); + sysbus_init_mmio(sbd, &s->iomem); + } } =20 static void loongarch_pic_class_init(ObjectClass *klass, const void *data) diff --git a/hw/intc/loongarch_pic_kvm.c b/hw/intc/loongarch_pic_kvm.c new file mode 100644 index 0000000000..23db857b0e --- /dev/null +++ b/hw/intc/loongarch_pic_kvm.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * LoongArch kvm pch pic interrupt support + * + * Copyright (C) 2025 Loongson Technology Corporation Limited + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/boards.h" +#include "hw/intc/loongarch_pch_pic.h" +#include "hw/loongarch/virt.h" +#include "hw/pci-host/ls7a.h" +#include "system/kvm.h" + +void kvm_loongarch_pic_realize(DeviceState *dev, Error **errp) +{ + LoongarchPICState *lps =3D LOONGARCH_PIC(dev); + uint64_t pch_pic_base =3D VIRT_PCH_REG_BASE; + int ret; + + ret =3D kvm_create_device(kvm_state, KVM_DEV_TYPE_LOONGARCH_PCHPIC, fa= lse); + if (ret < 0) { + fprintf(stderr, "Create KVM_LOONGARCH_PCHPIC failed: %s\n", + strerror(-ret)); + abort(); + } + + lps->dev_fd =3D ret; + ret =3D kvm_device_access(lps->dev_fd, KVM_DEV_LOONGARCH_PCH_PIC_GRP_C= TRL, + KVM_DEV_LOONGARCH_PCH_PIC_CTRL_INIT, + &pch_pic_base, true, NULL); + if (ret < 0) { + fprintf(stderr, "KVM_LOONGARCH_PCH_PIC_INIT failed: %s\n", + strerror(-ret)); + abort(); + } +} diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 1cc999771d..3137521a4a 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -74,6 +74,8 @@ specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true: fi= les('loongarch_ipi.c')) specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_LOONGARCH_IPI'], if_true: files('loongarch_ipi_kvm.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarc= h_pch_pic.c', 'loongarch_pic_common.c')) +specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_LOONGARCH_PCH_PIC'], + if_true: files('loongarch_pic_kvm.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarc= h_pch_msi.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_EXTIOI', if_true: files('loongarch= _extioi.c', 'loongarch_extioi_common.c')) specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_LOONGARCH_EXTIOI'], diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarc= h_pch_pic.h index 839a59a43b..ef8334935d 100644 --- a/include/hw/intc/loongarch_pch_pic.h +++ b/include/hw/intc/loongarch_pch_pic.h @@ -16,6 +16,7 @@ OBJECT_DECLARE_TYPE(LoongarchPICState, LoongarchPICClass,= LOONGARCH_PIC) =20 struct LoongarchPICState { LoongArchPICCommonState parent_obj; + int dev_fd; }; =20 struct LoongarchPICClass { @@ -25,4 +26,6 @@ struct LoongarchPICClass { ResettablePhases parent_phases; }; =20 +void kvm_loongarch_pic_realize(DeviceState *dev, Error **errp); + #endif /* HW_LOONGARCH_PCH_PIC_H */ --=20 2.39.3 From nobody Sat Nov 15 18:49:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1748335568430323.5202800249116; Tue, 27 May 2025 01:46:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uJpvo-0003Nf-3I; Tue, 27 May 2025 04:45:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uJpvk-0003Kc-UD for qemu-devel@nongnu.org; Tue, 27 May 2025 04:45:05 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uJpvd-0000fZ-UH for qemu-devel@nongnu.org; Tue, 27 May 2025 04:45:04 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxLGuHezVoXhj+AA--.16428S3; Tue, 27 May 2025 16:44:55 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMBx3xtyezVolPn0AA--.53554S10; Tue, 27 May 2025 16:44:54 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , Huacai Chen , qemu-devel@nongnu.org, Xianglai Li Subject: [PATCH v2 08/12] ihw/intc/loongarch_pch: Add kernel irqchip save and restore function Date: Tue, 27 May 2025 16:44:26 +0800 Message-Id: <20250527084430.3468174-9-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250527084430.3468174-1-maobibo@loongson.cn> References: <20250527084430.3468174-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMBx3xtyezVolPn0AA--.53554S10 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1748335570788116600 Content-Type: text/plain; charset="utf-8" Add save and store funtction if kvm_irqchip_in_kernel() return true, it is to get and set PCH PCI irqchip state from KVM kernel. Signed-off-by: Bibo Mao --- hw/intc/loongarch_pch_pic.c | 22 ++++++++++ hw/intc/loongarch_pic_kvm.c | 58 ++++++++++++++++++++++++++ include/hw/intc/loongarch_pch_pic.h | 2 + include/hw/intc/loongarch_pic_common.h | 1 + 4 files changed, 83 insertions(+) diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c index f454df576a..5ac035d8b8 100644 --- a/hw/intc/loongarch_pch_pic.c +++ b/hw/intc/loongarch_pch_pic.c @@ -287,16 +287,38 @@ static void loongarch_pic_realize(DeviceState *dev, E= rror **errp) } } =20 +static int loongarch_pic_pre_save(LoongArchPICCommonState *opaque) +{ + if (kvm_irqchip_in_kernel()) { + return kvm_loongarch_pic_pre_save(opaque); + } + + return 0; +} + +static int loongarch_pic_post_load(LoongArchPICCommonState *opaque, + int version_id) +{ + if (kvm_irqchip_in_kernel()) { + return kvm_loongarch_pic_post_load(opaque, version_id); + } + + return 0; +} + static void loongarch_pic_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); LoongarchPICClass *lpc =3D LOONGARCH_PIC_CLASS(klass); + LoongArchPICCommonClass *lpcc =3D LOONGARCH_PIC_COMMON_CLASS(klass); ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 resettable_class_set_parent_phases(rc, NULL, loongarch_pic_reset_hold, NULL, &lpc->parent_phases); device_class_set_parent_realize(dc, loongarch_pic_realize, &lpc->parent_realize); + lpcc->pre_save =3D loongarch_pic_pre_save; + lpcc->post_load =3D loongarch_pic_post_load; } =20 static const TypeInfo loongarch_pic_types[] =3D { diff --git a/hw/intc/loongarch_pic_kvm.c b/hw/intc/loongarch_pic_kvm.c index 23db857b0e..bc9e8d408e 100644 --- a/hw/intc/loongarch_pic_kvm.c +++ b/hw/intc/loongarch_pic_kvm.c @@ -13,6 +13,64 @@ #include "hw/pci-host/ls7a.h" #include "system/kvm.h" =20 +static void kvm_pch_pic_access_regs(int fd, uint64_t addr, + void *val, bool write) +{ + kvm_device_access(fd, KVM_DEV_LOONGARCH_PCH_PIC_GRP_REGS, + addr, val, write, &error_abort); +} + +static void kvm_loongarch_pch_pic_save_load(void *opaque, bool write) +{ + LoongArchPICCommonState *s =3D LOONGARCH_PIC_COMMON(opaque); + LoongarchPICState *lps =3D LOONGARCH_PIC(opaque); + int fd =3D lps->dev_fd; + int addr, offset; + + kvm_pch_pic_access_regs(fd, VIRT_PCH_REG_BASE + PCH_PIC_INT_MASK, + &s->int_mask, write); + kvm_pch_pic_access_regs(fd, VIRT_PCH_REG_BASE + PCH_PIC_HTMSI_EN, + &s->htmsi_en, write); + kvm_pch_pic_access_regs(fd, VIRT_PCH_REG_BASE + PCH_PIC_INT_EDGE, + &s->intedge, write); + kvm_pch_pic_access_regs(fd, VIRT_PCH_REG_BASE + PCH_PIC_AUTO_CTRL0, + &s->auto_crtl0, write); + kvm_pch_pic_access_regs(fd, VIRT_PCH_REG_BASE + PCH_PIC_AUTO_CTRL1, + &s->auto_crtl1, write); + + for (addr =3D PCH_PIC_ROUTE_ENTRY; + addr < PCH_PIC_ROUTE_ENTRY_END; addr++) { + offset =3D addr - PCH_PIC_ROUTE_ENTRY; + kvm_pch_pic_access_regs(fd, addr + VIRT_PCH_REG_BASE, + &s->route_entry[offset], write); + } + + for (addr =3D PCH_PIC_HTMSI_VEC; addr < PCH_PIC_HTMSI_VEC_END; addr++)= { + offset =3D addr - PCH_PIC_HTMSI_VEC; + kvm_pch_pic_access_regs(fd, addr + VIRT_PCH_REG_BASE, + &s->htmsi_vector[offset], write); + } + + kvm_pch_pic_access_regs(fd, VIRT_PCH_REG_BASE + PCH_PIC_INT_REQUEST, + &s->intirr, write); + kvm_pch_pic_access_regs(fd, VIRT_PCH_REG_BASE + PCH_PIC_INT_STATUS, + &s->intisr, write); + kvm_pch_pic_access_regs(fd, VIRT_PCH_REG_BASE + PCH_PIC_INT_POL, + &s->int_polarity, write); +} + +int kvm_loongarch_pic_pre_save(void *opaque) +{ + kvm_loongarch_pch_pic_save_load(opaque, false); + return 0; +} + +int kvm_loongarch_pic_post_load(void *opaque, int version_id) +{ + kvm_loongarch_pch_pic_save_load(opaque, true); + return 0; +} + void kvm_loongarch_pic_realize(DeviceState *dev, Error **errp) { LoongarchPICState *lps =3D LOONGARCH_PIC(dev); diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarc= h_pch_pic.h index ef8334935d..99030d0be1 100644 --- a/include/hw/intc/loongarch_pch_pic.h +++ b/include/hw/intc/loongarch_pch_pic.h @@ -27,5 +27,7 @@ struct LoongarchPICClass { }; =20 void kvm_loongarch_pic_realize(DeviceState *dev, Error **errp); +int kvm_loongarch_pic_pre_save(void *opaque); +int kvm_loongarch_pic_post_load(void *opaque, int version_id); =20 #endif /* HW_LOONGARCH_PCH_PIC_H */ diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loong= arch_pic_common.h index 9349a055d0..f774c975d4 100644 --- a/include/hw/intc/loongarch_pic_common.h +++ b/include/hw/intc/loongarch_pic_common.h @@ -23,6 +23,7 @@ #define PCH_PIC_ROUTE_ENTRY_END 0x13f #define PCH_PIC_HTMSI_VEC 0x200 #define PCH_PIC_HTMSI_VEC_END 0x23f +#define PCH_PIC_INT_REQUEST 0x380 #define PCH_PIC_INT_STATUS 0x3a0 #define PCH_PIC_INT_POL 0x3e0 =20 --=20 2.39.3 From nobody Sat Nov 15 18:49:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1748335555673691.7629814289984; Tue, 27 May 2025 01:45:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uJpvl-0003KR-6C; Tue, 27 May 2025 04:45:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uJpvi-0003Fy-98 for qemu-devel@nongnu.org; Tue, 27 May 2025 04:45:02 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uJpvf-0000fo-VQ for qemu-devel@nongnu.org; Tue, 27 May 2025 04:45:01 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxWXGJezVoZBj+AA--.16590S3; Tue, 27 May 2025 16:44:57 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMBx3xtyezVolPn0AA--.53554S11; Tue, 27 May 2025 16:44:57 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , Huacai Chen , qemu-devel@nongnu.org, Xianglai Li Subject: [PATCH v2 09/12] hw/intc/loongarch_pch: Inject irq line interrupt to kernel Date: Tue, 27 May 2025 16:44:27 +0800 Message-Id: <20250527084430.3468174-10-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250527084430.3468174-1-maobibo@loongson.cn> References: <20250527084430.3468174-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMBx3xtyezVolPn0AA--.53554S11 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1748335556400116600 Content-Type: text/plain; charset="utf-8" If kvm_irqchip_in_kernel() return true, irq line interrupt can be injected with API kvm_set_irq() to KVM. Signed-off-by: Bibo Mao --- hw/intc/loongarch_pch_pic.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c index 5ac035d8b8..bd070e10ab 100644 --- a/hw/intc/loongarch_pch_pic.c +++ b/hw/intc/loongarch_pch_pic.c @@ -49,6 +49,11 @@ static void pch_pic_irq_handler(void *opaque, int irq, i= nt level) assert(irq < s->irq_num); trace_loongarch_pch_pic_irq_handler(irq, level); =20 + if (kvm_irqchip_in_kernel()) { + kvm_set_irq(kvm_state, irq, !!level); + return; + } + if (s->intedge & mask) { /* Edge triggered */ if (level) { --=20 2.39.3 From nobody Sat Nov 15 18:49:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1748335555988321.29991211629306; Tue, 27 May 2025 01:45:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uJpvm-0003Lu-5n; Tue, 27 May 2025 04:45:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uJpvj-0003I9-SC for qemu-devel@nongnu.org; Tue, 27 May 2025 04:45:03 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uJpvh-0000g0-IQ for qemu-devel@nongnu.org; Tue, 27 May 2025 04:45:03 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8DxbKyLezVoaBj+AA--.16510S3; Tue, 27 May 2025 16:44:59 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMBx3xtyezVolPn0AA--.53554S12; Tue, 27 May 2025 16:44:58 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , Huacai Chen , qemu-devel@nongnu.org, Xianglai Li Subject: [PATCH v2 10/12] target/loongarch: Report error with split kernel_irqchip option Date: Tue, 27 May 2025 16:44:28 +0800 Message-Id: <20250527084430.3468174-11-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250527084430.3468174-1-maobibo@loongson.cn> References: <20250527084430.3468174-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMBx3xtyezVolPn0AA--.53554S12 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1748335558457116600 Content-Type: text/plain; charset="utf-8" Option kernel_irqchip=3Dsplit is not supported on LoongArch virt machine, report error and exit if detect split kernel_irqchip option. Signed-off-by: Bibo Mao --- target/loongarch/kvm/kvm.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c index 1bda570482..6e04dfc999 100644 --- a/target/loongarch/kvm/kvm.c +++ b/target/loongarch/kvm/kvm.c @@ -1249,7 +1249,12 @@ int kvm_arch_init(MachineState *ms, KVMState *s) =20 int kvm_arch_irqchip_create(KVMState *s) { - return 0; + if (kvm_kernel_irqchip_split()) { + error_report("kernel_irqchip=3Dsplit is not supported on LoongArch= "); + exit(1); + } + + return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); } =20 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) --=20 2.39.3 From nobody Sat Nov 15 18:49:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1748335832923818.9224493341164; Tue, 27 May 2025 01:50:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uJq0W-0003KM-Iu; Tue, 27 May 2025 04:50:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uJq0T-0003KD-5e for qemu-devel@nongnu.org; Tue, 27 May 2025 04:49:57 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uJq0N-0001Jh-LO for qemu-devel@nongnu.org; Tue, 27 May 2025 04:49:56 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxDGuofDVo3hn+AA--.15887S3; Tue, 27 May 2025 16:49:44 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMBxHcWnfDVoH_z0AA--.40547S2; Tue, 27 May 2025 16:49:43 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , Huacai Chen , qemu-devel@nongnu.org, Xianglai Li Subject: [PATCH v2 11/12] hw/loongarch/virt: Disable emulation with IOCSR misc register Date: Tue, 27 May 2025 16:49:43 +0800 Message-Id: <20250527084943.3468289-1-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250527084430.3468174-1-maobibo@loongson.cn> References: <20250527084430.3468174-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMBxHcWnfDVoH_z0AA--.40547S2 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1748335833587116600 Content-Type: text/plain; charset="utf-8" Register IOCSR MISC_FUNC_REG is to enable features about EXTIOI irqchip. If EXTIOI is emulated in kernel, MISC_FUNC_REG register should be emulated in kernel also. Signed-off-by: Bibo Mao --- hw/loongarch/virt.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 1b504047db..69491fa31f 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -509,6 +509,10 @@ static MemTxResult virt_iocsr_misc_write(void *opaque,= hwaddr addr, =20 switch (addr) { case MISC_FUNC_REG: + if (kvm_irqchip_in_kernel()) { + return MEMTX_OK; + } + if (!virt_is_veiointc_enabled(lvms)) { return MEMTX_OK; } @@ -559,6 +563,10 @@ static MemTxResult virt_iocsr_misc_read(void *opaque, = hwaddr addr, ret =3D 0x303030354133ULL; /* "3A5000" */ break; case MISC_FUNC_REG: + if (kvm_irqchip_in_kernel()) { + return MEMTX_OK; + } + if (!virt_is_veiointc_enabled(lvms)) { ret |=3D BIT_ULL(IOCSRM_EXTIOI_EN); break; --=20 2.39.3 From nobody Sat Nov 15 18:49:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1748335858916198.75816987953056; Tue, 27 May 2025 01:50:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uJq10-0003Ru-9z; Tue, 27 May 2025 04:50:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uJq0r-0003R9-HX for qemu-devel@nongnu.org; Tue, 27 May 2025 04:50:21 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uJq0l-0001YA-DX for qemu-devel@nongnu.org; Tue, 27 May 2025 04:50:21 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Ax3eLFfDVo9Bn+AA--.43303S3; Tue, 27 May 2025 16:50:13 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMBxLsfEfDVoXPz0AA--.46111S2; Tue, 27 May 2025 16:50:12 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , Huacai Chen , qemu-devel@nongnu.org, Xianglai Li Subject: [PATCH v2 12/12] hw/loongarch/virt: Add kernel irqchip support Date: Tue, 27 May 2025 16:50:12 +0800 Message-Id: <20250527085012.3468338-1-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250527084430.3468174-1-maobibo@loongson.cn> References: <20250527084430.3468174-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMBxLsfEfDVoXPz0AA--.46111S2 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1748335860055116600 Content-Type: text/plain; charset="utf-8" If kvm_irqchip_in_kernel() return true, interrupt controller ExtIOI, IPI, PCH_PCI and PCH_MSI should be emlated in kernel. And it is not necessary to create memory region for these devices in user space. Signed-off-by: Bibo Mao --- hw/loongarch/virt.c | 57 ++++++++++++++++++++++---------------- target/loongarch/cpu.h | 1 + target/loongarch/kvm/kvm.c | 16 +++++++++++ 3 files changed, 50 insertions(+), 24 deletions(-) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 69491fa31f..abc8aa2d67 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -401,12 +401,6 @@ static void virt_irq_init(LoongArchVirtMachineState *l= vms) lvms->ipi =3D ipi; sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); =20 - /* IPI iocsr memory region */ - memory_region_add_subregion(&lvms->system_iocsr, SMP_IPI_MAILBOX, - sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 0)); - memory_region_add_subregion(&lvms->system_iocsr, MAIL_SEND_ADDR, - sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1)); - /* Create EXTIOI device */ extioi =3D qdev_new(TYPE_LOONGARCH_EXTIOI); lvms->extioi =3D extioi; @@ -414,12 +408,6 @@ static void virt_irq_init(LoongArchVirtMachineState *l= vms) qdev_prop_set_bit(extioi, "has-virtualization-extension", true); } sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal); - memory_region_add_subregion(&lvms->system_iocsr, APIC_BASE, - sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 0)); - if (virt_is_veiointc_enabled(lvms)) { - memory_region_add_subregion(&lvms->system_iocsr, EXTIOI_VIRT_BASE, - sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 1)); - } =20 virt_cpu_irq_init(lvms); pch_pic =3D qdev_new(TYPE_LOONGARCH_PIC); @@ -427,13 +415,6 @@ static void virt_irq_init(LoongArchVirtMachineState *l= vms) qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num); d =3D SYS_BUS_DEVICE(pch_pic); sysbus_realize_and_unref(d, &error_fatal); - memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE, - sysbus_mmio_get_region(d, 0)); - - /* Connect pch_pic irqs to extioi */ - for (i =3D 0; i < num; i++) { - qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i)); - } =20 pch_msi =3D qdev_new(TYPE_LOONGARCH_PCH_MSI); start =3D num; @@ -443,12 +424,40 @@ static void virt_irq_init(LoongArchVirtMachineState *= lvms) d =3D SYS_BUS_DEVICE(pch_msi); sysbus_realize_and_unref(d, &error_fatal); sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW); - for (i =3D 0; i < num; i++) { - /* Connect pch_msi irqs to extioi */ - qdev_connect_gpio_out(DEVICE(d), i, - qdev_get_gpio_in(extioi, i + start)); - } =20 + if (kvm_irqchip_in_kernel()) { + kvm_loongarch_init_irq_routing(); + } else { + /* IPI iocsr memory region */ + memory_region_add_subregion(&lvms->system_iocsr, SMP_IPI_MAILBOX, + sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 0)); + memory_region_add_subregion(&lvms->system_iocsr, MAIL_SEND_ADDR, + sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1)); + + /* EXTIOI iocsr memory region */ + memory_region_add_subregion(&lvms->system_iocsr, APIC_BASE, + sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 0)); + if (virt_is_veiointc_enabled(lvms)) { + memory_region_add_subregion(&lvms->system_iocsr, EXTIOI_VIRT_B= ASE, + sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 1)); + } + + /* PCH_PIC memory region */ + memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_B= ASE, + sysbus_mmio_get_region(SYS_BUS_DEVICE(pch_pic), 0)); + + /* Connect pch_pic irqs to extioi */ + for (i =3D 0; i < VIRT_PCH_PIC_IRQ_NUM; i++) { + qdev_connect_gpio_out(DEVICE(pch_pic), i, + qdev_get_gpio_in(extioi, i)); + } + + for (i =3D VIRT_PCH_PIC_IRQ_NUM; i < EXTIOI_IRQS; i++) { + /* Connect pch_msi irqs to extioi */ + qdev_connect_gpio_out(DEVICE(pch_msi), i - VIRT_PCH_PIC_IRQ_NU= M, + qdev_get_gpio_in(extioi, i)); + } + } virt_devices_init(pch_pic, lvms); } =20 diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 262bf87f7b..9538e8d61d 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -503,5 +503,6 @@ static inline void kvm_loongarch_cpu_post_init(LoongArc= hCPU *cpu) { } #endif +void kvm_loongarch_init_irq_routing(void); =20 #endif /* LOONGARCH_CPU_H */ diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c index 6e04dfc999..fdb4f86196 100644 --- a/target/loongarch/kvm/kvm.c +++ b/target/loongarch/kvm/kvm.c @@ -1236,6 +1236,22 @@ void kvm_arch_init_irq_routing(KVMState *s) { } =20 +void kvm_loongarch_init_irq_routing(void) +{ + int i; + + kvm_async_interrupts_allowed =3D true; + kvm_msi_via_irqfd_allowed =3D kvm_irqfds_enabled(); + if (kvm_has_gsi_routing()) { + for (i =3D 0; i < 64; ++i) { + kvm_irqchip_add_irq_route(kvm_state, i, 0, i); + } + + kvm_gsi_routing_allowed =3D true; + kvm_irqchip_commit_routes(kvm_state); + } +} + int kvm_arch_get_default_type(MachineState *ms) { return 0; --=20 2.39.3