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Date: Mon, 26 May 2025 10:55:20 +0200 Message-Id: <20250526085523.809003-2-chigot@adacore.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250526085523.809003-1-chigot@adacore.com> References: <20250526085523.809003-1-chigot@adacore.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=chigot@adacore.com; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @adacore.com) X-ZM-MESSAGEID: 1748249773048116600 Currently, arm booting processus assumes that the first_cpu is the CPU that will boot: `arm_load_kernel` is powering off all but the `first_cpu`; `do_cpu_reset` is setting the loader address only for this `first_cpu`. For most of the boards, this isn't an issue as the kernel is loaded and booted on the first CPU anyway. However, for zynqmp, the option "boot-cpu" allows to choose any CPUs. Create a new arm_boot_info entry `primary_cpu` recording which CPU will be boot first. This one is set when `arm_boot_kernel` is called. Signed-off-by: Cl=C3=A9ment Chigot Reviewed-by: Peter Maydell --- hw/arm/boot.c | 15 +++++++-------- include/hw/arm/boot.h | 3 +++ 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index f94b940bc3..8da4c67fa9 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -743,7 +743,7 @@ static void do_cpu_reset(void *opaque) } else { if (arm_feature(env, ARM_FEATURE_EL3) && (info->secure_boot || - (info->secure_board_setup && cs =3D=3D first_cpu))) { + (info->secure_board_setup && cpu =3D=3D info->primary= _cpu))) { /* Start this CPU in Secure SVC */ target_el =3D 3; } @@ -751,7 +751,7 @@ static void do_cpu_reset(void *opaque) =20 arm_emulate_firmware_reset(cs, target_el); =20 - if (cs =3D=3D first_cpu) { + if (cpu =3D=3D info->primary_cpu) { AddressSpace *as =3D arm_boot_address_space(cpu, info); =20 cpu_set_pc(cs, info->loader_start); @@ -1238,6 +1238,9 @@ void arm_load_kernel(ARMCPU *cpu, MachineState *ms, s= truct arm_boot_info *info) info->dtb_filename =3D ms->dtb; info->dtb_limit =3D 0; =20 + /* We assume the CPU passed as argument is the primary CPU. */ + info->primary_cpu =3D cpu; + /* Load the kernel. */ if (!info->kernel_filename || info->firmware_loaded) { arm_setup_firmware_boot(cpu, info); @@ -1287,12 +1290,8 @@ void arm_load_kernel(ARMCPU *cpu, MachineState *ms, = struct arm_boot_info *info) =20 object_property_set_int(cpuobj, "psci-conduit", info->psci_con= duit, &error_abort); - /* - * Secondary CPUs start in PSCI powered-down state. Like the - * code in do_cpu_reset(), we assume first_cpu is the primary - * CPU. - */ - if (cs !=3D first_cpu) { + /* Secondary CPUs start in PSCI powered-down state. */ + if (ARM_CPU(cs) !=3D info->primary_cpu) { object_property_set_bool(cpuobj, "start-powered-off", true, &error_abort); } diff --git a/include/hw/arm/boot.h b/include/hw/arm/boot.h index b12bf61ca8..a2e22bda8a 100644 --- a/include/hw/arm/boot.h +++ b/include/hw/arm/boot.h @@ -132,6 +132,9 @@ struct arm_boot_info { bool secure_board_setup; =20 arm_endianness endianness; + + /* CPU having load the kernel and that should be the first to boot. */ + ARMCPU *primary_cpu; }; =20 /** --=20 2.34.1