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Date: Mon, 26 May 2025 10:55:20 +0200 Message-Id: <20250526085523.809003-2-chigot@adacore.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250526085523.809003-1-chigot@adacore.com> References: <20250526085523.809003-1-chigot@adacore.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=chigot@adacore.com; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @adacore.com) X-ZM-MESSAGEID: 1748249773048116600 Currently, arm booting processus assumes that the first_cpu is the CPU that will boot: `arm_load_kernel` is powering off all but the `first_cpu`; `do_cpu_reset` is setting the loader address only for this `first_cpu`. For most of the boards, this isn't an issue as the kernel is loaded and booted on the first CPU anyway. However, for zynqmp, the option "boot-cpu" allows to choose any CPUs. Create a new arm_boot_info entry `primary_cpu` recording which CPU will be boot first. This one is set when `arm_boot_kernel` is called. Signed-off-by: Cl=C3=A9ment Chigot Reviewed-by: Peter Maydell --- hw/arm/boot.c | 15 +++++++-------- include/hw/arm/boot.h | 3 +++ 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index f94b940bc3..8da4c67fa9 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -743,7 +743,7 @@ static void do_cpu_reset(void *opaque) } else { if (arm_feature(env, ARM_FEATURE_EL3) && (info->secure_boot || - (info->secure_board_setup && cs =3D=3D first_cpu))) { + (info->secure_board_setup && cpu =3D=3D info->primary= _cpu))) { /* Start this CPU in Secure SVC */ target_el =3D 3; } @@ -751,7 +751,7 @@ static void do_cpu_reset(void *opaque) =20 arm_emulate_firmware_reset(cs, target_el); =20 - if (cs =3D=3D first_cpu) { + if (cpu =3D=3D info->primary_cpu) { AddressSpace *as =3D arm_boot_address_space(cpu, info); =20 cpu_set_pc(cs, info->loader_start); @@ -1238,6 +1238,9 @@ void arm_load_kernel(ARMCPU *cpu, MachineState *ms, s= truct arm_boot_info *info) info->dtb_filename =3D ms->dtb; info->dtb_limit =3D 0; =20 + /* We assume the CPU passed as argument is the primary CPU. */ + info->primary_cpu =3D cpu; + /* Load the kernel. */ if (!info->kernel_filename || info->firmware_loaded) { arm_setup_firmware_boot(cpu, info); @@ -1287,12 +1290,8 @@ void arm_load_kernel(ARMCPU *cpu, MachineState *ms, = struct arm_boot_info *info) =20 object_property_set_int(cpuobj, "psci-conduit", info->psci_con= duit, &error_abort); - /* - * Secondary CPUs start in PSCI powered-down state. Like the - * code in do_cpu_reset(), we assume first_cpu is the primary - * CPU. - */ - if (cs !=3D first_cpu) { + /* Secondary CPUs start in PSCI powered-down state. */ + if (ARM_CPU(cs) !=3D info->primary_cpu) { object_property_set_bool(cpuobj, "start-powered-off", true, &error_abort); } diff --git a/include/hw/arm/boot.h b/include/hw/arm/boot.h index b12bf61ca8..a2e22bda8a 100644 --- a/include/hw/arm/boot.h +++ b/include/hw/arm/boot.h @@ -132,6 +132,9 @@ struct arm_boot_info { bool secure_board_setup; =20 arm_endianness endianness; + + /* CPU having load the kernel and that should be the first to boot. */ + ARMCPU *primary_cpu; }; =20 /** --=20 2.34.1 From nobody Sat Nov 15 19:06:03 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=adacore.com ARC-Seal: i=1; a=rsa-sha256; t=1748249787; cv=none; d=zohomail.com; s=zohoarc; b=HeS0aaSFfM6MfSmk+nFpxXXA9pppNCWdT5NflQ0mqCFFDy4CES4IyMaNHGLpkdrdh3+qqbUWAf7neN4AElOwbigLPrA6xb6BmDB8GVgseZqcbOuYjzbOwNwN1Ux9NG21wAATylJkzCSBHZBTXPme0vF5DdNmGyuZ5/80djQzlGg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1748249787; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=g+yP9a/uVH74kLVGGvEGM7JayHygTFaXLhgBOX+A4es=; b=bU973cVFDUvqmF0w8fYlGQYEwiGDbiLAaftd3gY/4RUzezQEflgos0VRxqrD+zufJ46o+7G7EDthNHV8aeJKeXj3MfZbW1gmx0uvPesYOlkRKGV945X5KOhxCS29Zx/43b9M8vL6AyGsCtrsvwnAMIrrIDMhKkIWG0n3N6BwY7k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1748249787642761.0112438607716; Mon, 26 May 2025 01:56:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uJTca-0004U1-8o; Mon, 26 May 2025 04:55:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uJTcL-0004Re-8M for qemu-devel@nongnu.org; Mon, 26 May 2025 04:55:33 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uJTcI-00082x-RD for qemu-devel@nongnu.org; Mon, 26 May 2025 04:55:32 -0400 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-3a4dba2c767so294282f8f.1 for ; Mon, 26 May 2025 01:55:30 -0700 (PDT) Received: from chigot-Dell.telnowedge.local (lmontsouris-659-1-24-67.w81-250.abo.wanadoo.fr. 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Signed-off-by: Cl=C3=A9ment Chigot Reviewed-by: Peter Maydell --- hw/intc/arm_gic.c | 2 +- hw/intc/arm_gic_common.c | 1 + include/hw/intc/arm_gic.h | 2 ++ include/hw/intc/arm_gic_common.h | 2 ++ 4 files changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index d18bef40fc..899f133363 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -59,7 +59,7 @@ static const uint8_t gic_id_gicv2[] =3D { static inline int gic_get_current_cpu(GICState *s) { if (!qtest_enabled() && s->num_cpu > 1) { - return current_cpu->cpu_index; + return current_cpu->cpu_index - s->first_cpu_index; } return 0; } diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index 0f0c48d89a..ed5be05645 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -350,6 +350,7 @@ static void arm_gic_common_linux_init(ARMLinuxBootIf *o= bj, =20 static const Property arm_gic_common_properties[] =3D { DEFINE_PROP_UINT32("num-cpu", GICState, num_cpu, 1), + DEFINE_PROP_UINT32("first-cpu-index", GICState, first_cpu_index, 0), DEFINE_PROP_UINT32("num-irq", GICState, num_irq, 32), /* Revision can be 1 or 2 for GIC architecture specification * versions 1 or 2, or 0 to indicate the legacy 11MPCore GIC. diff --git a/include/hw/intc/arm_gic.h b/include/hw/intc/arm_gic.h index 48f6a51a70..6faccf8ef6 100644 --- a/include/hw/intc/arm_gic.h +++ b/include/hw/intc/arm_gic.h @@ -27,6 +27,8 @@ * implement the security extensions * + QOM property "has-virtualization-extensions": set true if the GIC sh= ould * implement the virtualization extensions + * + QOM property "first-cpu-index": index of the first cpu attached to t= he + * GIC. * + unnamed GPIO inputs: (where P is number of SPIs, i.e. num-irq - 32) * [0..P-1] SPIs * [P..P+31] PPIs for CPU 0 diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_com= mon.h index 97fea4102d..93a3cc2bf8 100644 --- a/include/hw/intc/arm_gic_common.h +++ b/include/hw/intc/arm_gic_common.h @@ -129,6 +129,8 @@ struct GICState { uint32_t num_lrs; =20 uint32_t num_cpu; + /* cpu_index of the first CPU, attached to this GIC. */ + uint32_t first_cpu_index; =20 MemoryRegion iomem; /* Distributor */ /* This is just so we can have an opaque pointer which identifies --=20 2.34.1 From nobody Sat Nov 15 19:06:03 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=adacore.com ARC-Seal: i=1; a=rsa-sha256; t=1748249818; cv=none; d=zohomail.com; s=zohoarc; b=N4P0qo8KYcIZTz3zHUYt9NslJO2q/+3VrvG67DXE3J+kxwHH8r/fcehaBPeNjd4mgh3KdE8iO9ZwIYN4meMiOrIIgqp5Sq0cVxiqW+eWM3YKR+XFksQcBFYAmf3KtrCwtXqASyCoyq8xjrpGOjTA76VhuqVK4zqq0+EIhLtsIP4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1748249818; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=e3t/nIVRg+2jwmgdqscl/THpDb4n/5JCjlQr5Qe7fL8=; b=Lo97PFw2TOfFVyAqBbgUOpp9TTM112eMJkZ8CmoFJRwYqsGv4j2PYnLywFg2nXqdfRsGFYggsdjHFiq7hOjPwzppraQwEQ1TO+dRfbPYn8yXXIE/5SsTLCZHdbHD7s4dh3HvIfJbloCMXL8iXkYF+lzlyoO8N+5wEjroiCuJwe4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1748249818968251.6995334208441; Mon, 26 May 2025 01:56:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uJTct-0004fG-6w; Mon, 26 May 2025 04:56:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uJTcM-0004Sc-P7 for qemu-devel@nongnu.org; Mon, 26 May 2025 04:55:34 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uJTcJ-000833-MH for qemu-devel@nongnu.org; Mon, 26 May 2025 04:55:34 -0400 Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-3a4c95fc276so2494125f8f.3 for ; Mon, 26 May 2025 01:55:31 -0700 (PDT) Received: from chigot-Dell.telnowedge.local (lmontsouris-659-1-24-67.w81-250.abo.wanadoo.fr. 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Signed-off-by: Cl=C3=A9ment Chigot --- hw/arm/xlnx-zynqmp.c | 88 +++++++++++++++++++++++++++++++++--- include/hw/arm/xlnx-zynqmp.h | 6 +++ 2 files changed, 87 insertions(+), 7 deletions(-) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index ec96a46eec..be33669f87 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -26,8 +26,6 @@ #include "target/arm/cpu-qom.h" #include "target/arm/gtimer.h" =20 -#define GIC_NUM_SPI_INTR 160 - #define ARM_PHYS_TIMER_PPI 30 #define ARM_VIRT_TIMER_PPI 27 #define ARM_HYP_TIMER_PPI 26 @@ -206,7 +204,7 @@ static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_region= s[] =3D { =20 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) { - return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; + return XLXN_ZYNQMP_GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_inde= x; } =20 static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s, @@ -377,6 +375,8 @@ static void xlnx_zynqmp_init(Object *obj) XlnxZynqMPState *s =3D XLNX_ZYNQMP(obj); int i; int num_apus =3D MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); + int num_rpus =3D MIN((int)(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS), + XLNX_ZYNQMP_NUM_RPU_CPUS); =20 object_initialize_child(obj, "apu-cluster", &s->apu_cluster, TYPE_CPU_CLUSTER); @@ -390,6 +390,12 @@ static void xlnx_zynqmp_init(Object *obj) =20 object_initialize_child(obj, "gic", &s->gic, gic_class_name()); =20 + if (num_rpus > 0) { + /* Do not create the rpu_gic in case we don't have rpus.. */ + object_initialize_child(obj, "rpu_gic", &s->rpu_gic, + gic_class_name()); + } + for (i =3D 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { object_initialize_child(obj, "gem[*]", &s->gem[i], TYPE_CADENCE_GE= M); object_initialize_child(obj, "gem-irq-orgate[*]", @@ -439,6 +445,13 @@ static void xlnx_zynqmp_init(Object *obj) object_initialize_child(obj, "qspi-irq-orgate", &s->qspi_irq_orgate, TYPE_OR_IRQ); =20 + for (i =3D 0; i < ARRAY_SIZE(s->splitter); i++) { + g_autofree char *name =3D g_strdup_printf("irq-splitter%d", i); + object_initialize_child(obj, name, &s->splitter[i], TYPE_SPLIT_IRQ= ); + } + + + for (i =3D 0; i < XLNX_ZYNQMP_NUM_USB; i++) { object_initialize_child(obj, "usb[*]", &s->usb[i], TYPE_USB_DWC3); } @@ -452,10 +465,13 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Err= or **errp) uint8_t i; uint64_t ram_size; int num_apus =3D MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); + int num_rpus =3D MIN((int)(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS), + XLNX_ZYNQMP_NUM_RPU_CPUS); const char *boot_cpu =3D s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; ram_addr_t ddr_low_size, ddr_high_size; - qemu_irq gic_spi[GIC_NUM_SPI_INTR]; + qemu_irq gic_spi[XLXN_ZYNQMP_GIC_NUM_SPI_INTR]; Error *err =3D NULL; + DeviceState *splitter; =20 ram_size =3D memory_region_size(s->ddr_ram); =20 @@ -502,13 +518,21 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Err= or **errp) g_free(ocm_name); } =20 - qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32= ); + qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", XLXN_ZYNQMP_GIC_NUM_S= PI_INTR + 32); qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus); qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secur= e); qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", s->virt); =20 + if (num_rpus > 0) { + qdev_prop_set_uint32(DEVICE(&s->rpu_gic), "num-irq", + XLXN_ZYNQMP_GIC_NUM_SPI_INTR + 32); + qdev_prop_set_uint32(DEVICE(&s->rpu_gic), "revision", 1); + qdev_prop_set_uint32(DEVICE(&s->rpu_gic), "num-cpu", num_rpus); + qdev_prop_set_uint32(DEVICE(&s->rpu_gic), "first-cpu-index", 4); + } + qdev_realize(DEVICE(&s->apu_cluster), NULL, &error_fatal); =20 /* Realize APUs before realizing the GIC. KVM requires this. */ @@ -608,13 +632,63 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Err= or **errp) return; } =20 + if (num_rpus > 0) { + if (!sysbus_realize(SYS_BUS_DEVICE(&s->rpu_gic), errp)) { + return; + } + + for (i =3D 0; i < num_rpus; i++) { + qemu_irq irq; + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->rpu_gic), i + 1, + GIC_BASE_ADDR + i * 0x1000); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rpu_gic), i, + qdev_get_gpio_in(DEVICE(&s->rpu_cpu[i]), + ARM_CPU_IRQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rpu_gic), i + num_rpus, + qdev_get_gpio_in(DEVICE(&s->rpu_cpu[i]), + ARM_CPU_FIQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rpu_gic), i + num_rpus *= 2, + qdev_get_gpio_in(DEVICE(&s->rpu_cpu[i]), + ARM_CPU_VIRQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rpu_gic), i + num_rpus *= 3, + qdev_get_gpio_in(DEVICE(&s->rpu_cpu[i]), + ARM_CPU_VFIQ)); + irq =3D qdev_get_gpio_in(DEVICE(&s->rpu_gic), + arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI= )); + qdev_connect_gpio_out(DEVICE(&s->rpu_cpu[i]), GTIMER_PHYS, irq= ); + irq =3D qdev_get_gpio_in(DEVICE(&s->rpu_gic), + arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI= )); + qdev_connect_gpio_out(DEVICE(&s->rpu_cpu[i]), GTIMER_VIRT, irq= ); + irq =3D qdev_get_gpio_in(DEVICE(&s->rpu_gic), + arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI)= ); + qdev_connect_gpio_out(DEVICE(&s->rpu_cpu[i]), GTIMER_HYP, irq); + irq =3D qdev_get_gpio_in(DEVICE(&s->rpu_gic), + arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI)= ); + qdev_connect_gpio_out(DEVICE(&s->rpu_cpu[i]), GTIMER_SEC, irq); + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->rpu_gic), 0, GIC_BASE_ADDR); + } + if (!s->boot_cpu_ptr) { error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu); return; } =20 - for (i =3D 0; i < GIC_NUM_SPI_INTR; i++) { - gic_spi[i] =3D qdev_get_gpio_in(DEVICE(&s->gic), i); + for (i =3D 0; i < XLXN_ZYNQMP_GIC_NUM_SPI_INTR; i++) { + splitter =3D DEVICE(&s->splitter[i]); + qdev_prop_set_uint16(splitter, "num-lines", 2); + qdev_realize(splitter, NULL, &error_abort); + if (num_rpus > 0) { + gic_spi[i] =3D qdev_get_gpio_in(splitter, 0); + qdev_connect_gpio_out(splitter, 0, + qdev_get_gpio_in(DEVICE(&s->gic), i)); + qdev_connect_gpio_out(splitter, 1, + qdev_get_gpio_in(DEVICE(&s->rpu_gic), i)= ); + } else { + gic_spi[i] =3D qdev_get_gpio_in(DEVICE(&s->gic), i); + } } =20 for (i =3D 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index c137ac59e8..a69953650d 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -42,6 +42,7 @@ #include "hw/misc/xlnx-zynqmp-crf.h" #include "hw/timer/cadence_ttc.h" #include "hw/usb/hcd-dwc3.h" +#include "hw/core/split-irq.h" =20 #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp" OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) @@ -87,12 +88,14 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE) =20 #define XLNX_ZYNQMP_NUM_TTC 4 +#define XLXN_ZYNQMP_GIC_NUM_SPI_INTR 160 =20 /* * Unimplemented mmio regions needed to boot some images. */ #define XLNX_ZYNQMP_NUM_UNIMP_AREAS 1 =20 + struct XlnxZynqMPState { /*< private >*/ DeviceState parent_obj; @@ -105,6 +108,9 @@ struct XlnxZynqMPState { GICState gic; MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES]; =20 + GICState rpu_gic; + SplitIRQ splitter[XLXN_ZYNQMP_GIC_NUM_SPI_INTR]; + MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS]; =20 MemoryRegion *ddr_ram; --=20 2.34.1 From nobody Sat Nov 15 19:06:03 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=adacore.com ARC-Seal: i=1; a=rsa-sha256; t=1748249813; cv=none; d=zohomail.com; s=zohoarc; b=GbaONsVVXS0z3iR4zcQ3aacyp/Peb7yevFo96u71LSrhhqGtbRJV4ajL0XWbXvUvKKHhbTW7MYOWkiwkSaAab5eWbLqHI/WVSaqxAVDkhB8xAxIYdsVNImWo+J5k4xnQqzE+jLdnVIBxXTKD5GdBeoOad+qWFaG13l9XvyUUmtg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1748249813; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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However, the ZynqMP board has two clusters, those being of two different architectures. Therefore, when gdb is connecting to the ZynqMP, it receives the target descriptor of the first CPU cluster. Up to now, it was always the APU cluster, which is AARCH64. When booting on a RPU, gdb will still connect to the APU. If gdb is supporting only ARM32, it will receive the APU target descriptor, resulting in: | (gdb) target remote :1234 | warning: while parsing target description (at line 1): Target | description specified unknown architecture "aarch64" Adjust the cluster-id based on the boot cpu will resolve the above issue; allowing a pure ARM32 toolchain to debug programs running on RPUs. Signed-off-by: Cl=C3=A9ment Chigot --- hw/arm/xlnx-zynqmp.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index be33669f87..f23ace6446 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -221,7 +221,13 @@ static void xlnx_zynqmp_create_rpu(MachineState *ms, X= lnxZynqMPState *s, =20 object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster, TYPE_CPU_CLUSTER); - qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1); + + /* In order to connect gdb to the boot cpu, adjust the cluster-id. */ + if (!strncmp(boot_cpu, "rpu-cpu", 7)) { + qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 0); + } else { + qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1); + } =20 for (i =3D 0; i < num_rpus; i++) { const char *name; @@ -380,7 +386,6 @@ static void xlnx_zynqmp_init(Object *obj) =20 object_initialize_child(obj, "apu-cluster", &s->apu_cluster, TYPE_CPU_CLUSTER); - qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0); =20 for (i =3D 0; i < num_apus; i++) { object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]", @@ -475,6 +480,13 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Erro= r **errp) =20 ram_size =3D memory_region_size(s->ddr_ram); =20 + /* In order to connect gdb to the boot cpu, adjust the cluster-id. */ + if (!strncmp(boot_cpu, "apu-cpu", 7)) { + qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0); + } else { + qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 1); + } + /* * Create the DDR Memory Regions. User friendly checks should happen at * the board level --=20 2.34.1