From nobody Sat Nov 15 19:23:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1748246856; cv=none; d=zohomail.com; s=zohoarc; b=UGQxULPQnYUzlLZhT3l9/LDqG7sN6qI5G6c7EyuWTB1R67+qD4Vjw9UjwKfQbQIXN9E984uQ6/t1KceOn6d5kZNH2D9gcH3AYJ+NaagQGA8slK6expkLXNJp6BDaScOqaAjrC4yni+wEfQNfxAw472yNUMl3/glGdUSa5+wmnE4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1748246856; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=cD9kW90sGkrW2nGYGqTYAf51SA64wzKUAEhh8PYOI50=; b=DvZlc1IDmof0V0VPzfe84HsgfBmj0GZrAm2XjZ2b4FqNVvYZLd/zJVWpkkw96Kw87Hbf3zZi4xlxzwl2TWZzfO+7MU81Q5eu9+vG7KfyDaKfxQTdItNyOwwpFAQWdv/TBE6zAjDrY1xEzLpdvRcmuUqUVgZHevjqMP4W9vM/ZTo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1748246856542796.3194896714175; Mon, 26 May 2025 01:07:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uJSql-0005AC-GK; Mon, 26 May 2025 04:06:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uJSqe-00050c-Gm for qemu-devel@nongnu.org; Mon, 26 May 2025 04:06:20 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uJSqc-0002LZ-0A for qemu-devel@nongnu.org; Mon, 26 May 2025 04:06:15 -0400 Received: from mx-prod-mc-04.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-269-5zGJA7lJMQez1RvjtwVpTw-1; Mon, 26 May 2025 04:05:38 -0400 Received: from mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.111]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-04.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 340E9195423F; Mon, 26 May 2025 08:05:37 +0000 (UTC) Received: from corto.redhat.com (unknown [10.45.224.49]) by mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 8E0FA18003FD; Mon, 26 May 2025 08:05:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1748246773; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=cD9kW90sGkrW2nGYGqTYAf51SA64wzKUAEhh8PYOI50=; b=cR+n12tyyQduPujR/mW6i+DsyyVQMqsYKtJ5n7ZudeA/1pHqbvIfExhOPbegtJkgGGgwjC enzBHULbbqEvKTS2KxZX7Zr4hjZbBe6Uf/CzungX4wDhnlL85U2+P3ev1mSX4NS4ZcfR+o NB0Y87LsrjR2bwUyJQonhzV+rDwEhj0= X-MC-Unique: 5zGJA7lJMQez1RvjtwVpTw-1 X-Mimecast-MFC-AGG-ID: 5zGJA7lJMQez1RvjtwVpTw_1748246737 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 05/39] hw/misc/aspeed_hace: Ensure HASH_IRQ is always set to prevent firmware hang Date: Mon, 26 May 2025 10:04:38 +0200 Message-ID: <20250526080512.1697528-6-clg@redhat.com> In-Reply-To: <20250526080512.1697528-1-clg@redhat.com> References: <20250526080512.1697528-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -59 X-Spam_score: -6.0 X-Spam_bar: ------ X-Spam_report: (-6.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.904, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1748246858535116600 From: Jamin Lin Currently, if the program encounters an unsupported algorithm, it does not = set the HASH_IRQ bit in the status register and send an interrupt to indicate command completion. As a result, the FW gets stuck waiting for a completion signal from the HACE module. Additionally, in do_hash_operation, if an error occurs within the condition= al statement, the HASH_IRQ bit is not set in the status register. This causes = the firmware to continuously send HASH commands, as it is unaware that the HACE model has completed processing the command. To fix this, the HASH_IRQ bit in the status register must always be set to ensure that the firmware receives an interrupt from the HACE module, preven= ting it from getting stuck or repeatedly sending HASH commands. Signed-off-by: Jamin Lin Fixes: c5475b3 ("hw: Model ASPEED's Hash and Crypto Engine") Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20250515081008.583578-4-jamin_lin@= aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- hw/misc/aspeed_hace.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index 6be94963bce7..1256926d2276 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -267,12 +267,6 @@ static void do_hash_operation(AspeedHACEState *s, int = algo, bool sg_mode, iov[iov_idx - 1].iov_len, false, iov[iov_idx - 1].iov_len); } - - /* - * Set status bits to indicate completion. Testing shows hardware sets - * these irrespective of HASH_IRQ_EN. - */ - s->regs[R_STATUS] |=3D HASH_IRQ; } =20 static uint64_t aspeed_hace_read(void *opaque, hwaddr addr, unsigned int s= ize) @@ -356,10 +350,16 @@ static void aspeed_hace_write(void *opaque, hwaddr ad= dr, uint64_t data, qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid hash algorithm selection 0x%"PRIx64"\= n", __func__, data & ahc->hash_mask); - break; + } else { + do_hash_operation(s, algo, data & HASH_SG_EN, + ((data & HASH_HMAC_MASK) =3D=3D HASH_DIGEST_ACCUM)); } - do_hash_operation(s, algo, data & HASH_SG_EN, - ((data & HASH_HMAC_MASK) =3D=3D HASH_DIGEST_ACCUM)); + + /* + * Set status bits to indicate completion. Testing shows hardware = sets + * these irrespective of HASH_IRQ_EN. + */ + s->regs[R_STATUS] |=3D HASH_IRQ; =20 if (data & HASH_IRQ_EN) { qemu_irq_raise(s->irq); --=20 2.49.0