From nobody Sat Nov 15 20:51:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747908899428318.87887118677384; Thu, 22 May 2025 03:14:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uI2w4-000774-Vk; Thu, 22 May 2025 06:14:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uI2vu-00075R-2I; Thu, 22 May 2025 06:13:50 -0400 Received: from smtp84.cstnet.cn ([159.226.251.84] helo=cstnet.cn) by eggs.gnu.org with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1uI2vo-0003fD-UZ; Thu, 22 May 2025 06:13:49 -0400 Received: from iscas.ac.cn (unknown [113.16.146.135]) by APP-05 (Coremail) with SMTP id zQCowAAnw8TF+C5opIQGAA--.2086S2; Thu, 22 May 2025 18:13:27 +0800 (CST) From: Meng Zhuo To: qemu-devel@nongnu.org Cc: Meng Zhuo , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs) Subject: [PATCH v4] target/riscv/kvm: add satp mode for host cpu Date: Thu, 22 May 2025 18:13:20 +0800 Message-Id: <20250522101320.96217-1-mengzhuo@iscas.ac.cn> X-Mailer: git-send-email 2.39.5 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: zQCowAAnw8TF+C5opIQGAA--.2086S2 X-Coremail-Antispam: 1UD129KBjvJXoWxZw15AF1DZF1rKF4UAF1UKFg_yoW5tFWUpF W5GrZ5CrW3tF9rJayxtrykXF45Jws5Kr42ka12vr1xXan8JrWUWF1kKa13CF98JF47AF13 A3WFkrW7CF40yFJanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUvK14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26F1j6w1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26F4j 6r4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oV Cq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0 I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r 4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY1x0262kKe7AKxVWU AVWUtwCY1x0264kExVAvwVAq07x20xyl42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7 v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF 1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIx AIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI 42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r1j6r4UYxBIdaVFxh VjvjDU0xZFpf9x0JUr5rcUUUUU= X-Originating-IP: [113.16.146.135] X-CM-SenderInfo: pphqw6xkxrqxpvfd2hldfou0/1tbiCRAKEmgu0b+yxAAAsf Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=159.226.251.84; envelope-from=mengzhuo@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1747908901471116600 Content-Type: text/plain; charset="utf-8" This patch adds host satp mode while kvm/host cpu satp mode is not set. This patch not change the output of errno nor errno strings pattern like other functions do. See [v3] for further information. Change in v4: - Adds changelog in commit message - Link to v3: https://lists.nongnu.org/archive/html/qemu-devel/2025-05/msg0= 4629.html Change in v3: - Rebase on https://github.com/alistair23/qemu/tree/riscv-to-apply.next as requested - Link to v2: https://lists.nongnu.org/archive/html/qemu-devel/2025-04/msg0= 5203.html Changes in v2: - use set_satp_mode_max_supported instead of hard code - Link to v1: https://lists.nongnu.org/archive/html/qemu-devel/2025-04/msg0= 5094.html Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2931 Signed-off-by: Meng Zhuo Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 3 +-- target/riscv/cpu.h | 1 + target/riscv/kvm/kvm-cpu.c | 20 +++++++++++++++++++- 3 files changed, 21 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d92874baa0..a84edd3a3b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -433,8 +433,7 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32= _bit) g_assert_not_reached(); } =20 -static void set_satp_mode_max_supported(RISCVCPU *cpu, - uint8_t satp_mode) +void set_satp_mode_max_supported(RISCVCPU *cpu, uint8_t satp_mode) { bool rv32 =3D riscv_cpu_mxl(&cpu->env) =3D=3D MXL_RV32; const bool *valid_vm =3D rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b56d3afa69..d7136f1d72 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -915,6 +915,7 @@ char *riscv_cpu_get_name(RISCVCPU *cpu); =20 void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp); void riscv_add_satp_mode_properties(Object *obj); +void set_satp_mode_max_supported(RISCVCPU *cpu, uint8_t satp_mode); bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu); =20 /* CSR function table */ diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 82f9728636..18fbca1a08 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -999,6 +999,23 @@ static void kvm_riscv_destroy_scratch_vcpu(KVMScratchC= PU *scratch) close(scratch->kvmfd); } =20 +static void kvm_riscv_init_satp_mode(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) +{ + CPURISCVState *env =3D &cpu->env; + struct kvm_one_reg reg; + int ret; + uint64_t val; + + reg.id =3D RISCV_CONFIG_REG(env, satp_mode); + reg.addr =3D (uint64_t)&val; + ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); + if (ret !=3D 0) { + error_report("Unable to retrieve satp from host, error %d", ret); + } + + set_satp_mode_max_supported(cpu, val); +} + static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcp= u) { struct kvm_one_reg reg; @@ -1302,6 +1319,7 @@ static void riscv_init_kvm_registers(Object *cpu_obj) kvm_riscv_init_machine_ids(cpu, &kvmcpu); kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); kvm_riscv_init_cfg(cpu, &kvmcpu); + kvm_riscv_init_satp_mode(cpu, &kvmcpu); =20 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); } @@ -1980,7 +1998,7 @@ static bool kvm_cpu_realize(CPUState *cs, Error **err= p) } } =20 - return true; + return true; } =20 void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp) --=20 2.39.5