From nobody Sat Nov 15 20:49:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1747901600; cv=none; d=zohomail.com; s=zohoarc; b=WjKwoDfoZaWVCtMBHvrK+WdW8N3+bdActgcF18MqICVAw/IOatS6692bnCgvRDnnd2e3IqgN8psbz0LGdubetC/OLMfAyILY6aTGcV++dukr6bRr9VjIWulbkoyOE/O5I03p2gCIlbmB7SVE6yl45jBaPIgU5pTEOHYdK+0YAuk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747901600; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=BeA9pPeZLVmg/ZpfFf5tDtTnRpdfSMVCAafGblAp4Rg=; b=dEukkvtLoijXhRyUVGNjjM3FvMh27HpLkNfw8xcvekkr4x7Hdv5rsoa9aET56ZKpTfby3UsE2Xc8ozMUjKFDaV0rlOr6y3UIV1gAWv/QgYznYpMtltbRnwUR5Wvz+pnoPvlf9r60nMqne+167lGxypXKhzqHrUrgNbg2DXXWVkc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747901600781287.4232888254869; Thu, 22 May 2025 01:13:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uI13B-0007Ud-Dh; Thu, 22 May 2025 04:13:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uI139-0007U8-CS for qemu-devel@nongnu.org; Thu, 22 May 2025 04:13:11 -0400 Received: from sea.source.kernel.org ([172.234.252.31]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uI137-0003No-OS for qemu-devel@nongnu.org; Thu, 22 May 2025 04:13:11 -0400 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id 04BFB44F40; Thu, 22 May 2025 08:13:07 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D3D06C4CEE4; Thu, 22 May 2025 08:13:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747901586; bh=3xq4wlfIvy9OM7kxdwoakK4Cms1/XS4ZMH0xxD790tQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Zro/PgbrhMzOxujAEbjrFQsyBAAew3CoA7aquy3EBkmkTS/v/4ls9ldkLf2xLriQq OSi/CWRQMDPFgHNACZywoaLDKDVguqTZ7RXMTmPKdB16ATAeEI6LXQManKNEY+n9MF PQPUciK0Nn8oTW7G6X3Wcn2pP7f2XKdtrnQaz8sjpuyqnHV9G1j1yNBvQDeJJ8McFX xhF9/DYNnCIahHMKsKdlq1jqfjARFpt1tD2wts2hyN0pfen5A4qAacAIOGmdvvZcQY ifCrHYket1WfTjxyNu/XfwwYc/+DPuzsYANOb0DitbOfTB0zZ4XDM4++3SZ6YaiH3/ 1iRvkxqRPtsCw== From: deller@kernel.org To: Stefan Hajnoczi , Richard Henderson , qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 1/3] target/hppa: Copy instruction code into fr1 on FPU assist fault Date: Thu, 22 May 2025 10:12:55 +0200 Message-ID: <20250522081257.3409-2-deller@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250522081257.3409-1-deller@kernel.org> References: <20250522081257.3409-1-deller@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=172.234.252.31; envelope-from=deller@kernel.org; helo=sea.source.kernel.org X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.184, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1747901602941116600 Content-Type: text/plain; charset="utf-8" From: Helge Deller The hardware stores the instruction code in the lower bits of the FP exception register #1 on FP assist traps. This fixes the FP exception handler on Linux, as the Linux kernel uses the value to decide on the correct signal which should be pushed into userspace (see decode_fpu() in Linux kernel). Signed-off-by: Helge Deller --- target/hppa/int_helper.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 7d48643bb6..191ae19404 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -177,6 +177,10 @@ void hppa_cpu_do_interrupt(CPUState *cs) } } env->cr[CR_IIR] =3D ldl_phys(cs->as, paddr); + if (i =3D=3D EXCP_ASSIST) { + /* stuff insn code into bits of FP exception register = #1 */ + env->fr[0] |=3D (env->cr[CR_IIR] & 0x03ffffff); + } } break; =20 --=20 2.47.0 From nobody Sat Nov 15 20:49:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1747901628; cv=none; d=zohomail.com; s=zohoarc; b=VS1KpZ4gR0jEWZ8UMkhU3V+/flOVJfbiyyedELyse/ovLcl/OU1vMzsYBWkc+bNhoAaaLvdFmOHGvrOXD2Gk2L3yLOxB1hsEr8wuFH51tbd+YhjoPUs+4O01ZRMB+9hMc/N/SSSC+p3IspWtD5f7OdapF4wCFS2wvBf0o4nV76I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747901628; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=C7mAlUGWD1imFksAuAzOntMacMpa31nId6s/lTOwUNg=; b=IgsX1huACh7VTCiUpztcw7eKqW1XSWnMnfVw67cXa3ExvNUpWMC9Xg9jxCbPx7mb+vh2iTFOrq/Hxw+5F8QcE5/YESLE7EVheeigtMuoUksY3ygb79qXaTy4H3SMm0wSSrUVpzUJ1Xu6xB0JowXT57SBuEaRO27V636J/XS5IiY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747901628725837.657859437412; Thu, 22 May 2025 01:13:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uI13F-0007Vx-6T; Thu, 22 May 2025 04:13:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uI13A-0007UY-Pq for qemu-devel@nongnu.org; Thu, 22 May 2025 04:13:12 -0400 Received: from nyc.source.kernel.org ([2604:1380:45d1:ec00::3]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uI138-0003Nu-Bw for qemu-devel@nongnu.org; Thu, 22 May 2025 04:13:12 -0400 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id A497EA4BDFE; Thu, 22 May 2025 08:13:08 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 50B13C4CEE4; Thu, 22 May 2025 08:13:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747901588; bh=mH6lWprZNCprzCYvb030arSxaYfC8yISrfaAKMY3jr8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=s5K1pbSKi6aRhlFXDxm6yvh3ExHVlD7+JLXo4kHbTcuc0BU51nPVHpsV4lXsD1hbM JFMVBFqD4T/YFgYkkke3XCs6nKdXP5XrpXSAn9BSi31nOGvin5leQRyRsNp8HHVXUY ljkF/zVda/yMozcdMS+NPMh3LERSG73XgMpfdixR803FV5lOXhdVFy7oUD4GL+Dx6W xrQqvnxxEOawJExAbXI5wdPStTMSQJ0CfxXGtmOEDw5h04KKXhs991AAJ7Z/mGfyhw gTjGm8pM3tgEoDQTi8w42b/p7aaH/hU8buUTlJLwyJZaKPa0V9zyc48bxU5TFy58bt MESdky+2KnQsA== From: deller@kernel.org To: Stefan Hajnoczi , Richard Henderson , qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 2/3] linux-user/hppa: Send proper si_code on SIGFPE exception Date: Thu, 22 May 2025 10:12:56 +0200 Message-ID: <20250522081257.3409-3-deller@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250522081257.3409-1-deller@kernel.org> References: <20250522081257.3409-1-deller@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2604:1380:45d1:ec00::3; envelope-from=deller@kernel.org; helo=nyc.source.kernel.org X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.184, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1747901629151116600 Content-Type: text/plain; charset="utf-8" From: Helge Deller Improve the linux-user emulation to send the correct si_code depending on overflow (TARGET_FPE_FLTOVF), underflow (TARGET_FPE_FLTUND), ... Note that the hardware stores the relevant flags in FP exception register #1, which is actually the lower 32-bits of the 64-bit fr[0] register in qemu. Signed-off-by: Helge Deller --- linux-user/hppa/cpu_loop.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index 890e758cd1..9abaad5ef8 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -112,7 +112,7 @@ static abi_ulong hppa_lws(CPUHPPAState *env) void cpu_loop(CPUHPPAState *env) { CPUState *cs =3D env_cpu(env); - abi_ulong ret; + abi_ulong ret, si_code =3D 0; int trapnr; =20 while (1) { @@ -169,7 +169,15 @@ void cpu_loop(CPUHPPAState *env) force_sig_fault(TARGET_SIGFPE, TARGET_FPE_CONDTRAP, env->iaoq_= f); break; case EXCP_ASSIST: - force_sig_fault(TARGET_SIGFPE, 0, env->iaoq_f); + #define set_si_code(mask, val) \ + if (env->fr[0] & mask) { si_code =3D val; } + set_si_code(R_FPSR_FLG_I_MASK, TARGET_FPE_FLTRES); + set_si_code(R_FPSR_FLG_U_MASK, TARGET_FPE_FLTUND); + set_si_code(R_FPSR_FLG_O_MASK, TARGET_FPE_FLTOVF); + set_si_code(R_FPSR_FLG_Z_MASK, TARGET_FPE_FLTDIV); + set_si_code(R_FPSR_FLG_V_MASK, TARGET_FPE_FLTINV); + #undef set_si_code + force_sig_fault(TARGET_SIGFPE, si_code, env->iaoq_f); break; case EXCP_BREAK: force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->iaoq_f= ); --=20 2.47.0 From nobody Sat Nov 15 20:49:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1747901641; cv=none; d=zohomail.com; s=zohoarc; b=Dd3P3uJFmXytpP6d817yw6BmNFpeSjdcO6VX2oWTjm2UL1KK4GesswtjfBlVh5AzkkGo1np8QDQR00fBUaFDUHpwYe6rqIyQziYOI+Q88/yTqpxcpA48UTJOTo7+oB01aqh6Nrc04okO3RMUYdnoClwI+AR01cze5XeSq+9Us78= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747901641; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=rOVBL8vWZMaQNsQZfeIhV1/w5+sz3I6qkq9mdTOZmjg=; b=B7061/lhsWxLJXYQB6UvFDRXcsfJTpBH7naOZSBRiUME5TPLhU6bI2r3xbsPnvg2nDdpKzJQMRpoUXp974SB4J+sBR+/RKKPyav6pZztdunRRwHTCN5IXJ/Ar/BhjwEcbPNdHHmCjjYXxszlx8qKgTpEDPytbXvRrhxjJq8EQF0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747901641503214.4106730642278; Thu, 22 May 2025 01:14:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uI13G-0007WS-3g; Thu, 22 May 2025 04:13:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uI13B-0007Uq-P6 for qemu-devel@nongnu.org; Thu, 22 May 2025 04:13:14 -0400 Received: from nyc.source.kernel.org ([2604:1380:45d1:ec00::3]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uI139-0003O7-9h for qemu-devel@nongnu.org; Thu, 22 May 2025 04:13:13 -0400 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id 212D1A4E306; Thu, 22 May 2025 08:13:10 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C1892C4CEEA; Thu, 22 May 2025 08:13:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747901589; bh=Q2Jud+Qo/Co5dwsffwNP+2WMO+4kLmz/GnQnSCCeKzM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lz6Ipi4ywX0MVtj9h3NvLvHXi+Z4O5dsIlyVa1cM8hCriuWQE+Ftc68DrKNavLTuf DgAeVPpyxAvabVw8DxZmMNDO/eU4cV+Ris2DYWXb8qeHSUPdc68CeW4gNd37sVqXtp 3lpZoNT5o/aW1TYwsxJRzTk5TzCJtGmGAJRgbxNKz0QzFK9E9iQXqurAkHSCl/FL6/ JY52GFR2Hj16QB1o+Y6H79Q/mQy2dKkwjHwMDb3WFg93bKH9rSnbK/z23+nt7WjW63 /Be61L1ykWoGiAofm5pvtdF4cxJBBFxiGn5ZhTdC8BAY/DSCDaXJIUfi5vniwkWrs8 3D9uOIFWrNhow== From: deller@kernel.org To: Stefan Hajnoczi , Richard Henderson , qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 3/3] target/hppa: Fix FPE exceptions Date: Thu, 22 May 2025 10:12:57 +0200 Message-ID: <20250522081257.3409-4-deller@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250522081257.3409-1-deller@kernel.org> References: <20250522081257.3409-1-deller@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2604:1380:45d1:ec00::3; envelope-from=deller@kernel.org; helo=nyc.source.kernel.org X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.184, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1747901643373116600 Content-Type: text/plain; charset="utf-8" From: Helge Deller Implement FP exception register #1 (lower 32-bits of 64-bit fr[0]). A proper implementation is necessary to allow the Linux kernel in system mode and the qemu linux-user to send proper si_code values on SIGFPE signal. Always set the T-bit on taken exception, and merge over- and underflow in system mode to just set overflow bit to mimic the behaviour I tested on a physical machine. The test program below can be used to verify correct behaviour. Note that behaviour on SIGFPE may vary on different platforms. The program should always detect the correct signal, but it may or may not be able to sucessfully continue afterwards. #define _GNU_SOURCE #include #include #include #include static void fpe_func(int sig, siginfo_t *i, void *v) { sigset_t set; sigemptyset(&set); sigaddset(&set, SIGFPE); sigprocmask(SIG_UNBLOCK, &set, NULL); printf("GOT signal %d with si_code %ld\n", sig, i->si_code); } int main(int argc, char *argv[]) { struct sigaction action =3D { .sa_sigaction =3D fpe_func, .sa_flags =3D SA_RESTART|SA_SIGINFO }; sigaction(SIGFPE, &action, 0); feenableexcept(FE_OVERFLOW | FE_UNDERFLOW); double x =3D DBL_MIN; return printf("%lf\n", argc > 1 ? 1.7976931348623158E308*1.7976931348623158E308 : x / 10); } Signed-off-by: Helge Deller --- target/hppa/fpu_helper.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c index a62d9d3083..294ce0a970 100644 --- a/target/hppa/fpu_helper.c +++ b/target/hppa/fpu_helper.c @@ -95,7 +95,8 @@ static void update_fr0_op(CPUHPPAState *env, uintptr_t ra) { uint32_t soft_exp =3D get_float_exception_flags(&env->fp_status); uint32_t hard_exp =3D 0; - uint32_t shadow =3D env->fr0_shadow; + uint32_t shadow =3D env->fr0_shadow & 0x3ffffff; + uint32_t fr1 =3D 0; =20 if (likely(soft_exp =3D=3D 0)) { env->fr[0] =3D (uint64_t)shadow << 32; @@ -108,9 +109,22 @@ static void update_fr0_op(CPUHPPAState *env, uintptr_t= ra) hard_exp |=3D CONVERT_BIT(soft_exp, float_flag_overflow, R_FPSR_ENA_O= _MASK); hard_exp |=3D CONVERT_BIT(soft_exp, float_flag_divbyzero, R_FPSR_ENA_Z= _MASK); hard_exp |=3D CONVERT_BIT(soft_exp, float_flag_invalid, R_FPSR_ENA_V= _MASK); - shadow |=3D hard_exp << (R_FPSR_FLAGS_SHIFT - R_FPSR_ENABLES_SHIFT); + if (hard_exp & shadow) { + shadow =3D FIELD_DP32(shadow, FPSR, T, 1); + /* fill exception register #1, which is lower 32-bits of fr[0] */ +#if !defined(CONFIG_USER_ONLY) + if (hard_exp & (R_FPSR_ENA_O_MASK | R_FPSR_ENA_U_MASK)) { + /* over- and underflow both set overflow flag only */ + fr1 =3D FIELD_DP32(fr1, FPSR, C, 1); + fr1 =3D FIELD_DP32(fr1, FPSR, FLG_O, 1); + } else +#endif + { + fr1 |=3D hard_exp << (R_FPSR_FLAGS_SHIFT - R_FPSR_ENABLES_SHIF= T); + } + } env->fr0_shadow =3D shadow; - env->fr[0] =3D (uint64_t)shadow << 32; + env->fr[0] =3D (uint64_t)shadow << 32 | fr1; =20 if (hard_exp & shadow) { hppa_dynamic_excp(env, EXCP_ASSIST, ra); --=20 2.47.0