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Thu, 22 May 2025 00:55:31 -0700 (PDT) From: Jay Chang To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Jay Chang , Frank Chang Subject: [PATCH v3 1/2] target/riscv: Extend PMP region up to 64 Date: Thu, 22 May 2025 15:55:19 +0800 Message-ID: <20250522075520.89527-2-jay.chang@sifive.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250522075520.89527-1-jay.chang@sifive.com> References: <20250522075520.89527-1-jay.chang@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=jay.chang@sifive.com; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1747900591266116600 According to the RISC-V Privileged Specification (version >1.12), RV32 supports 16 CSRs (pmpcfg0=E2=80=93pmpcfg15) to configure 64 PMP regions (pmpaddr0=E2=80=93pmpaddr63). Signed-off-by: Jay Chang Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu_bits.h | 60 +++++++++++++++++++ target/riscv/csr.c | 124 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 182 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index a30317c617..e6b3e28386 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -372,6 +372,18 @@ #define CSR_PMPCFG1 0x3a1 #define CSR_PMPCFG2 0x3a2 #define CSR_PMPCFG3 0x3a3 +#define CSR_PMPCFG4 0x3a4 +#define CSR_PMPCFG5 0x3a5 +#define CSR_PMPCFG6 0x3a6 +#define CSR_PMPCFG7 0x3a7 +#define CSR_PMPCFG8 0x3a8 +#define CSR_PMPCFG9 0x3a9 +#define CSR_PMPCFG10 0x3aa +#define CSR_PMPCFG11 0x3ab +#define CSR_PMPCFG12 0x3ac +#define CSR_PMPCFG13 0x3ad +#define CSR_PMPCFG14 0x3ae +#define CSR_PMPCFG15 0x3af #define CSR_PMPADDR0 0x3b0 #define CSR_PMPADDR1 0x3b1 #define CSR_PMPADDR2 0x3b2 @@ -388,6 +400,54 @@ #define CSR_PMPADDR13 0x3bd #define CSR_PMPADDR14 0x3be #define CSR_PMPADDR15 0x3bf +#define CSR_PMPADDR16 0x3c0 +#define CSR_PMPADDR17 0x3c1 +#define CSR_PMPADDR18 0x3c2 +#define CSR_PMPADDR19 0x3c3 +#define CSR_PMPADDR20 0x3c4 +#define CSR_PMPADDR21 0x3c5 +#define CSR_PMPADDR22 0x3c6 +#define CSR_PMPADDR23 0x3c7 +#define CSR_PMPADDR24 0x3c8 +#define CSR_PMPADDR25 0x3c9 +#define CSR_PMPADDR26 0x3ca +#define CSR_PMPADDR27 0x3cb +#define CSR_PMPADDR28 0x3cc +#define CSR_PMPADDR29 0x3cd +#define CSR_PMPADDR30 0x3ce +#define CSR_PMPADDR31 0x3cf +#define CSR_PMPADDR32 0x3d0 +#define CSR_PMPADDR33 0x3d1 +#define CSR_PMPADDR34 0x3d2 +#define CSR_PMPADDR35 0x3d3 +#define CSR_PMPADDR36 0x3d4 +#define CSR_PMPADDR37 0x3d5 +#define CSR_PMPADDR38 0x3d6 +#define CSR_PMPADDR39 0x3d7 +#define CSR_PMPADDR40 0x3d8 +#define CSR_PMPADDR41 0x3d9 +#define CSR_PMPADDR42 0x3da +#define CSR_PMPADDR43 0x3db +#define CSR_PMPADDR44 0x3dc +#define CSR_PMPADDR45 0x3dd +#define CSR_PMPADDR46 0x3de +#define CSR_PMPADDR47 0x3df +#define CSR_PMPADDR48 0x3e0 +#define CSR_PMPADDR49 0x3e1 +#define CSR_PMPADDR50 0x3e2 +#define CSR_PMPADDR51 0x3e3 +#define CSR_PMPADDR52 0x3e4 +#define CSR_PMPADDR53 0x3e5 +#define CSR_PMPADDR54 0x3e6 +#define CSR_PMPADDR55 0x3e7 +#define CSR_PMPADDR56 0x3e8 +#define CSR_PMPADDR57 0x3e9 +#define CSR_PMPADDR58 0x3ea +#define CSR_PMPADDR59 0x3eb +#define CSR_PMPADDR60 0x3ec +#define CSR_PMPADDR61 0x3ed +#define CSR_PMPADDR62 0x3ee +#define CSR_PMPADDR63 0x3ef =20 /* RNMI */ #define CSR_MNSCRATCH 0x740 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 1151ebb6ad..d6cd441133 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -6164,6 +6164,30 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_PMPCFG1] =3D { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPCFG2] =3D { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPCFG3] =3D { "pmpcfg3", pmp, read_pmpcfg, write_pmpcfg }, + [CSR_PMPCFG4] =3D { "pmpcfg4", pmp, read_pmpcfg, write_pmpcfg, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPCFG5] =3D { "pmpcfg5", pmp, read_pmpcfg, write_pmpcfg, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPCFG6] =3D { "pmpcfg6", pmp, read_pmpcfg, write_pmpcfg, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPCFG7] =3D { "pmpcfg7", pmp, read_pmpcfg, write_pmpcfg, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPCFG8] =3D { "pmpcfg8", pmp, read_pmpcfg, write_pmpcfg, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPCFG9] =3D { "pmpcfg9", pmp, read_pmpcfg, write_pmpcfg, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPCFG10] =3D { "pmpcfg10", pmp, read_pmpcfg, write_pmpcfg, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPCFG11] =3D { "pmpcfg11", pmp, read_pmpcfg, write_pmpcfg, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPCFG12] =3D { "pmpcfg12", pmp, read_pmpcfg, write_pmpcfg, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPCFG13] =3D { "pmpcfg13", pmp, read_pmpcfg, write_pmpcfg, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPCFG14] =3D { "pmpcfg14", pmp, read_pmpcfg, write_pmpcfg, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPCFG15] =3D { "pmpcfg15", pmp, read_pmpcfg, write_pmpcfg, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, [CSR_PMPADDR0] =3D { "pmpaddr0", pmp, read_pmpaddr, write_pmpaddr }, [CSR_PMPADDR1] =3D { "pmpaddr1", pmp, read_pmpaddr, write_pmpaddr }, [CSR_PMPADDR2] =3D { "pmpaddr2", pmp, read_pmpaddr, write_pmpaddr }, @@ -6178,8 +6202,104 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_PMPADDR11] =3D { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr }, [CSR_PMPADDR12] =3D { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr }, [CSR_PMPADDR13] =3D { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr }, - [CSR_PMPADDR14] =3D { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, - [CSR_PMPADDR15] =3D { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, + [CSR_PMPADDR14] =3D { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, + [CSR_PMPADDR15] =3D { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, + [CSR_PMPADDR16] =3D { "pmpaddr16", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR17] =3D { "pmpaddr17", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR18] =3D { "pmpaddr18", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR19] =3D { "pmpaddr19", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR20] =3D { "pmpaddr20", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR21] =3D { "pmpaddr21", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR22] =3D { "pmpaddr22", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR23] =3D { "pmpaddr23", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR24] =3D { "pmpaddr24", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR25] =3D { "pmpaddr25", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR26] =3D { "pmpaddr26", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR27] =3D { "pmpaddr27", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR28] =3D { "pmpaddr28", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR29] =3D { "pmpaddr29", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR30] =3D { "pmpaddr30", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR31] =3D { "pmpaddr31", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR32] =3D { "pmpaddr32", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR33] =3D { "pmpaddr33", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR34] =3D { "pmpaddr34", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR35] =3D { "pmpaddr35", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR36] =3D { "pmpaddr36", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR37] =3D { "pmpaddr37", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR38] =3D { "pmpaddr38", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR39] =3D { "pmpaddr39", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR40] =3D { "pmpaddr40", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR41] =3D { "pmpaddr41", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR42] =3D { "pmpaddr42", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR43] =3D { "pmpaddr43", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR44] =3D { "pmpaddr44", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR45] =3D { "pmpaddr45", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR46] =3D { "pmpaddr46", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR47] =3D { "pmpaddr47", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR48] =3D { "pmpaddr48", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR49] =3D { "pmpaddr49", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR50] =3D { "pmpaddr50", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR51] =3D { "pmpaddr51", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR52] =3D { "pmpaddr52", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR53] =3D { "pmpaddr53", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR54] =3D { "pmpaddr54", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR55] =3D { "pmpaddr55", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR56] =3D { "pmpaddr56", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR57] =3D { "pmpaddr57", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR58] =3D { "pmpaddr58", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR59] =3D { "pmpaddr59", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR60] =3D { "pmpaddr60", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR61] =3D { "pmpaddr61", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR62] =3D { "pmpaddr62", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR63] =3D { "pmpaddr63", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, =20 /* Debug CSRs */ [CSR_TSELECT] =3D { "tselect", debug, read_tselect, write_tselect= }, --=20 2.48.1 From nobody Sat Nov 15 20:52:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1747900606; cv=none; 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<20250522075520.89527-1-jay.chang@sifive.com> References: <20250522075520.89527-1-jay.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=jay.chang@sifive.com; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1747900608768116600 Content-Type: text/plain; charset="utf-8" Previously, the number of PMP regions was hardcoded to 16 in QEMU. This patch replaces the fixed value with a new `pmp_regions` field, allowing platforms to configure the number of PMP regions. If no specific value is provided, the default number of PMP regions remains 16 to preserve the existing behavior. A new CPU parameter num-pmp-regions has been introduced to the QEMU command line. For example: -cpu rv64, g=3Dtrue, c=3Dtrue, pmp=3Dtrue, num-pmp-regions=3D8 Signed-off-by: Jay Chang Reviewed-by: Frank Chang --- target/riscv/cpu.c | 54 +++++++++++++++++++++++++++++-- target/riscv/cpu.h | 3 +- target/riscv/cpu_cfg_fields.h.inc | 1 + target/riscv/csr.c | 5 ++- target/riscv/machine.c | 3 +- target/riscv/pmp.c | 28 ++++++++++------ 6 files changed, 80 insertions(+), 14 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 629ac37501..8e32252c11 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1117,6 +1117,7 @@ static void riscv_cpu_init(Object *obj) cpu->cfg.cbom_blocksize =3D 64; cpu->cfg.cbop_blocksize =3D 64; cpu->cfg.cboz_blocksize =3D 64; + cpu->cfg.pmp_regions =3D 16; cpu->env.vext_ver =3D VEXT_VERSION_1_00_0; cpu->cfg.max_satp_mode =3D -1; =20 @@ -1568,6 +1569,46 @@ static const PropertyInfo prop_pmp =3D { .set =3D prop_pmp_set, }; =20 +static void prop_num_pmp_regions_set(Object *obj, Visitor *v, const char *= name, + void *opaque, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint8_t value; + + visit_type_uint8(v, name, &value, errp); + + if (cpu->cfg.pmp_regions !=3D value && riscv_cpu_is_vendor(obj)) { + cpu_set_prop_err(cpu, name, errp); + return; + } + + if (cpu->env.priv_ver < PRIV_VERSION_1_12_0 && value > OLD_MAX_RISCV_P= MPS) { + error_setg(errp, "Number of PMP regions exceeds maximum available"= ); + return; + } else if (value > MAX_RISCV_PMPS) { + error_setg(errp, "Number of PMP regions exceeds maximum available"= ); + return; + } + + cpu_option_add_user_setting(name, value); + cpu->cfg.pmp_regions =3D value; +} + +static void prop_num_pmp_regions_get(Object *obj, Visitor *v, const char *= name, + void *opaque, Error **errp) +{ + uint8_t value =3D RISCV_CPU(obj)->cfg.pmp_regions; + + visit_type_uint8(v, name, &value, errp); +} + +static const PropertyInfo prop_num_pmp_regions =3D { + .type =3D "uint8", + .description =3D "num-pmp-regions", + .get =3D prop_num_pmp_regions_get, + .set =3D prop_num_pmp_regions_set, +}; + static int priv_spec_from_str(const char *priv_spec_str) { int priv_version =3D -1; @@ -2567,6 +2608,7 @@ static const Property riscv_cpu_properties[] =3D { =20 {.name =3D "mmu", .info =3D &prop_mmu}, {.name =3D "pmp", .info =3D &prop_pmp}, + {.name =3D "num-pmp-regions", .info =3D &prop_num_pmp_regions}, =20 {.name =3D "priv_spec", .info =3D &prop_priv_spec}, {.name =3D "vext_spec", .info =3D &prop_vext_spec}, @@ -2891,6 +2933,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_DYNAMIC_CPU, TYPE_RISCV_CPU, .cfg.mmu =3D true, .cfg.pmp =3D true, + .cfg.pmp_regions =3D 8, .priv_spec =3D PRIV_VERSION_LATEST, ), =20 @@ -2937,7 +2980,8 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .cfg.max_satp_mode =3D VM_1_10_MBARE, .cfg.ext_zifencei =3D true, .cfg.ext_zicsr =3D true, - .cfg.pmp =3D true + .cfg.pmp =3D true, + .cfg.pmp_regions =3D 8 ), =20 DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_U, TYPE_RISCV_VENDOR_C= PU, @@ -2948,7 +2992,8 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .cfg.ext_zifencei =3D true, .cfg.ext_zicsr =3D true, .cfg.mmu =3D true, - .cfg.pmp =3D true + .cfg.pmp =3D true, + .cfg.pmp_regions =3D 8 ), =20 #if defined(TARGET_RISCV32) || \ @@ -2966,6 +3011,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .cfg.ext_zifencei =3D true, .cfg.ext_zicsr =3D true, .cfg.pmp =3D true, + .cfg.pmp_regions =3D 8, .cfg.ext_smepmp =3D true, =20 .cfg.ext_zba =3D true, @@ -3040,6 +3086,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .cfg.ext_xtheadmempair =3D true, .cfg.ext_xtheadsync =3D true, .cfg.pmp =3D true, + .cfg.pmp_regions =3D 8, =20 .cfg.mvendorid =3D THEAD_VENDOR_ID, =20 @@ -3063,6 +3110,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .cfg.rvv_ta_all_1s =3D true, .cfg.misa_w =3D true, .cfg.pmp =3D true, + .cfg.pmp_regions =3D 8, .cfg.cbom_blocksize =3D 64, .cfg.cbop_blocksize =3D 64, .cfg.cboz_blocksize =3D 64, @@ -3119,6 +3167,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .cfg.ext_zifencei =3D true, .cfg.ext_zicsr =3D true, .cfg.pmp =3D true, + .cfg.pmp_regions =3D 8, .cfg.ext_zicbom =3D true, .cfg.cbom_blocksize =3D 64, .cfg.cboz_blocksize =3D 64, @@ -3163,6 +3212,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { =20 .cfg.mmu =3D true, .cfg.pmp =3D true, + .cfg.pmp_regions =3D 8, =20 .cfg.max_satp_mode =3D VM_1_10_SV39, ), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 229ade9ed9..67323a7d9d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -159,7 +159,8 @@ extern RISCVCPUImpliedExtsRule *riscv_multi_ext_implied= _rules[]; =20 #define MMU_USER_IDX 3 =20 -#define MAX_RISCV_PMPS (16) +#define MAX_RISCV_PMPS (64) +#define OLD_MAX_RISCV_PMPS (16) =20 #if !defined(CONFIG_USER_ONLY) #include "pmp.h" diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc index 59f134a419..33c4f9bac8 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -163,6 +163,7 @@ TYPED_FIELD(uint16_t, elen, 0) TYPED_FIELD(uint16_t, cbom_blocksize, 0) TYPED_FIELD(uint16_t, cbop_blocksize, 0) TYPED_FIELD(uint16_t, cboz_blocksize, 0) +TYPED_FIELD(uint8_t, pmp_regions, 0) =20 TYPED_FIELD(int8_t, max_satp_mode, -1) =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d6cd441133..44fb664636 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -738,7 +738,10 @@ static RISCVException dbltrp_hmode(CPURISCVState *env,= int csrno) static RISCVException pmp(CPURISCVState *env, int csrno) { if (riscv_cpu_cfg(env)->pmp) { - if (csrno <=3D CSR_PMPCFG3) { + uint8_t max_pmpcfg =3D (env->priv_ver >=3D PRIV_VERSION_1_12_0) ? ++ CSR_PMPCFG15 : CSR_PMPCFG3; + + if (csrno <=3D max_pmpcfg) { uint32_t reg_index =3D csrno - CSR_PMPCFG0; =20 /* TODO: RV128 restriction check */ diff --git a/target/riscv/machine.c b/target/riscv/machine.c index c97e9ce9df..1600ec44f0 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -36,8 +36,9 @@ static int pmp_post_load(void *opaque, int version_id) RISCVCPU *cpu =3D opaque; CPURISCVState *env =3D &cpu->env; int i; + uint8_t pmp_regions =3D riscv_cpu_cfg(env)->pmp_regions; =20 - for (i =3D 0; i < MAX_RISCV_PMPS; i++) { + for (i =3D 0; i < pmp_regions; i++) { pmp_update_rule_addr(env, i); } pmp_update_rule_nums(env); diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 5af295e410..3540327c9a 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -122,7 +122,9 @@ uint32_t pmp_get_num_rules(CPURISCVState *env) */ static inline uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t pmp_index) { - if (pmp_index < MAX_RISCV_PMPS) { + uint8_t pmp_regions =3D riscv_cpu_cfg(env)->pmp_regions; + + if (pmp_index < pmp_regions) { return env->pmp_state.pmp[pmp_index].cfg_reg; } =20 @@ -136,7 +138,9 @@ static inline uint8_t pmp_read_cfg(CPURISCVState *env, = uint32_t pmp_index) */ static bool pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t = val) { - if (pmp_index < MAX_RISCV_PMPS) { + uint8_t pmp_regions =3D riscv_cpu_cfg(env)->pmp_regions; + + if (pmp_index < pmp_regions) { if (env->pmp_state.pmp[pmp_index].cfg_reg =3D=3D val) { /* no change */ return false; @@ -236,9 +240,10 @@ void pmp_update_rule_addr(CPURISCVState *env, uint32_t= pmp_index) void pmp_update_rule_nums(CPURISCVState *env) { int i; + uint8_t pmp_regions =3D riscv_cpu_cfg(env)->pmp_regions; =20 env->pmp_state.num_rules =3D 0; - for (i =3D 0; i < MAX_RISCV_PMPS; i++) { + for (i =3D 0; i < pmp_regions; i++) { const uint8_t a_field =3D pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg); if (PMP_AMATCH_OFF !=3D a_field) { @@ -332,6 +337,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr, int pmp_size =3D 0; hwaddr s =3D 0; hwaddr e =3D 0; + uint8_t pmp_regions =3D riscv_cpu_cfg(env)->pmp_regions; =20 /* Short cut if no rules */ if (0 =3D=3D pmp_get_num_rules(env)) { @@ -356,7 +362,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr, * 1.10 draft priv spec states there is an implicit order * from low to high */ - for (i =3D 0; i < MAX_RISCV_PMPS; i++) { + for (i =3D 0; i < pmp_regions; i++) { s =3D pmp_is_in_range(env, i, addr); e =3D pmp_is_in_range(env, i, addr + pmp_size - 1); =20 @@ -527,8 +533,9 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t add= r_index, { trace_pmpaddr_csr_write(env->mhartid, addr_index, val); bool is_next_cfg_tor =3D false; + uint8_t pmp_regions =3D riscv_cpu_cfg(env)->pmp_regions; =20 - if (addr_index < MAX_RISCV_PMPS) { + if (addr_index < pmp_regions) { if (env->pmp_state.pmp[addr_index].addr_reg =3D=3D val) { /* no change */ return; @@ -538,7 +545,7 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t add= r_index, * In TOR mode, need to check the lock bit of the next pmp * (if there is a next). */ - if (addr_index + 1 < MAX_RISCV_PMPS) { + if (addr_index + 1 < pmp_regions) { uint8_t pmp_cfg =3D env->pmp_state.pmp[addr_index + 1].cfg_reg; is_next_cfg_tor =3D PMP_AMATCH_TOR =3D=3D pmp_get_a_field(pmp_= cfg); =20 @@ -573,8 +580,9 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t add= r_index, target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index) { target_ulong val =3D 0; + uint8_t pmp_regions =3D riscv_cpu_cfg(env)->pmp_regions; =20 - if (addr_index < MAX_RISCV_PMPS) { + if (addr_index < pmp_regions) { val =3D env->pmp_state.pmp[addr_index].addr_reg; trace_pmpaddr_csr_read(env->mhartid, addr_index, val); } else { @@ -592,6 +600,7 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong= val) { int i; uint64_t mask =3D MSECCFG_MMWP | MSECCFG_MML; + uint8_t pmp_regions =3D riscv_cpu_cfg(env)->pmp_regions; /* Update PMM field only if the value is valid according to Zjpm v1.0 = */ if (riscv_cpu_cfg(env)->ext_smmpm && riscv_cpu_mxl(env) =3D=3D MXL_RV64 && @@ -603,7 +612,7 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong= val) =20 /* RLB cannot be enabled if it's already 0 and if any regions are lock= ed */ if (!MSECCFG_RLB_ISSET(env)) { - for (i =3D 0; i < MAX_RISCV_PMPS; i++) { + for (i =3D 0; i < pmp_regions; i++) { if (pmp_is_locked(env, i)) { val &=3D ~MSECCFG_RLB; break; @@ -659,6 +668,7 @@ target_ulong pmp_get_tlb_size(CPURISCVState *env, hwadd= r addr) hwaddr tlb_sa =3D addr & ~(TARGET_PAGE_SIZE - 1); hwaddr tlb_ea =3D tlb_sa + TARGET_PAGE_SIZE - 1; int i; + uint8_t pmp_regions =3D riscv_cpu_cfg(env)->pmp_regions; =20 /* * If PMP is not supported or there are no PMP rules, the TLB page wil= l not @@ -669,7 +679,7 @@ target_ulong pmp_get_tlb_size(CPURISCVState *env, hwadd= r addr) return TARGET_PAGE_SIZE; } =20 - for (i =3D 0; i < MAX_RISCV_PMPS; i++) { + for (i =3D 0; i < pmp_regions; i++) { if (pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg) =3D=3D PMP_AMAT= CH_OFF) { continue; } --=20 2.48.1