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a="49895124" X-IronPort-AV: E=Sophos;i="6.15,303,1739865600"; d="scan'208";a="49895124" X-CSE-ConnectionGUID: iy4nvUElSLmhoQUyjlBBww== X-CSE-MsgGUID: 5Rj15SBeRQuIRLS0K7Ww0w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,303,1739865600"; d="scan'208";a="145158393" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PATCH rfcv3 16/21] intel_iommu: ERRATA_772415 workaround Date: Wed, 21 May 2025 19:14:46 +0800 Message-Id: <20250521111452.3316354-17-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250521111452.3316354-1-zhenzhong.duan@intel.com> References: <20250521111452.3316354-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.184, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1747826476060116600 Content-Type: text/plain; charset="utf-8" On a system influenced by ERRATA_772415, IOMMU_HW_INFO_VTD_ERRATA_772415_SP= R17 is repored by IOMMU_DEVICE_GET_HW_INFO. Due to this errata, even the readon= ly range mapped on stage-2 page table could still be written. Reference from 4th Gen Intel Xeon Processor Scalable Family Specification Update, Errata Details, SPR17. [0] https://edc.intel.com/content/www/us/en/design/products-and-solutions/p= rocessors-and-chipsets/eagle-stream/sapphire-rapids-specification-update We utilize the new added IOMMUFD container/ioas/hwpt management framework in VTD. Add a check to create new VTDIOASContainer to only hold RW mappings, then this VTDIOASContainer can be used as backend for device with ERRATA_772415. See below diagram for details: IntelIOMMUState | V .------------------. .------------------. .-------------------. | VTDIOASContainer |--->| VTDIOASContainer |--->| VTDIOASContainer |--= >... | (iommufd0,RW&RO) | | (iommufd1,RW&RO) | | (iommufd0,only RW)| .------------------. .------------------. .-------------------. | | | | .-->... | V V .-------------------. .-------------------. .------------= ---. | VTDS2Hwpt(CC) |--->| VTDS2Hwpt(non-CC) |-->... | VTDS2Hwpt(C= C) |-->... .-------------------. .-------------------. .------------= ---. | | | | | | | | .-----------. .-----------. .------------. .------------. | IOMMUFD | | IOMMUFD | | IOMMUFD | | IOMMUFD | | Device(CC)| | Device(CC)| | Device | | Device(CC) | | (iommufd0)| | (iommufd0)| | (non-CC) | | (errata) | | | | | | (iommufd0) | | (iommufd0) | .-----------. .-----------. .------------. .------------. Changed to pass VTDHostIOMMUDevice pointer to vtd_check_hdev() so errata could be saved. Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 1 + include/hw/i386/intel_iommu.h | 1 + hw/i386/intel_iommu.c | 25 +++++++++++++++++-------- 3 files changed, 19 insertions(+), 8 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index e76f43bb8f..75d840f9fe 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -654,5 +654,6 @@ typedef struct VTDHostIOMMUDevice { PCIBus *bus; uint8_t devfn; HostIOMMUDevice *hiod; + uint32_t errata; } VTDHostIOMMUDevice; #endif diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 594281c1d3..9b156dc32e 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -103,6 +103,7 @@ typedef struct VTDPASIDCacheEntry { typedef struct VTDIOASContainer { struct IOMMUFDBackend *iommufd; uint32_t ioas_id; + uint32_t errata; MemoryListener listener; QLIST_HEAD(, VTDS2Hwpt) s2_hwpt_list; QLIST_ENTRY(VTDIOASContainer) next; diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 3269a66ac7..9ffc2a8ffc 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2437,7 +2437,8 @@ static void vtd_context_global_invalidate(IntelIOMMUS= tate *s) } =20 #ifdef CONFIG_IOMMUFD -static bool iommufd_listener_skipped_section(MemoryRegionSection *section) +static bool iommufd_listener_skipped_section(VTDIOASContainer *container, + MemoryRegionSection *section) { return !memory_region_is_ram(section->mr) || memory_region_is_protected(section->mr) || @@ -2447,7 +2448,8 @@ static bool iommufd_listener_skipped_section(MemoryRe= gionSection *section) * are never accessed by the CPU and beyond the address width of * some IOMMU hardware. TODO: VFIO should tell us the IOMMU wi= dth. */ - section->offset_within_address_space & (1ULL << 63); + section->offset_within_address_space & (1ULL << 63) || + (container->errata && section->readonly); } =20 static void iommufd_listener_region_add_s2domain(MemoryListener *listener, @@ -2463,7 +2465,7 @@ static void iommufd_listener_region_add_s2domain(Memo= ryListener *listener, Error *err =3D NULL; int ret; =20 - if (iommufd_listener_skipped_section(section)) { + if (iommufd_listener_skipped_section(container, section)) { return; } iova =3D REAL_HOST_PAGE_ALIGN(section->offset_within_address_space); @@ -2514,7 +2516,7 @@ static void iommufd_listener_region_del_s2domain(Memo= ryListener *listener, Int128 llend, llsize; int ret; =20 - if (iommufd_listener_skipped_section(section)) { + if (iommufd_listener_skipped_section(container, section)) { return; } iova =3D REAL_HOST_PAGE_ALIGN(section->offset_within_address_space); @@ -2770,7 +2772,8 @@ static int vtd_device_attach_iommufd(VTDHostIOMMUDevi= ce *vtd_hiod, =20 /* try to attach to an existing container in this space */ QLIST_FOREACH(container, &s->containers, next) { - if (container->iommufd !=3D iommufd) { + if (container->iommufd !=3D iommufd || + container->errata !=3D vtd_hiod->errata) { continue; } =20 @@ -2797,6 +2800,7 @@ static int vtd_device_attach_iommufd(VTDHostIOMMUDevi= ce *vtd_hiod, container =3D g_malloc0(sizeof(*container)); container->iommufd =3D iommufd; container->ioas_id =3D ioas_id; + container->errata =3D vtd_hiod->errata; QLIST_INIT(&container->s2_hwpt_list); =20 if (vtd_device_attach_container(vtd_hiod, container, pasid, pe, hwpt, @@ -5355,9 +5359,10 @@ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s,= PCIBus *bus, return vtd_dev_as; } =20 -static bool vtd_check_hiod(IntelIOMMUState *s, HostIOMMUDevice *hiod, +static bool vtd_check_hiod(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hio= d, Error **errp) { + HostIOMMUDevice *hiod =3D vtd_hiod->hiod; HostIOMMUDeviceClass *hiodc =3D HOST_IOMMU_DEVICE_GET_CLASS(hiod); int ret; =20 @@ -5399,7 +5404,7 @@ static bool vtd_check_hiod(IntelIOMMUState *s, HostIO= MMUDevice *hiod, } =20 /* - * HOST_IOMMU_DEVICE_CAP_NESTING/FS1GP are VTD vendor specific + * HOST_IOMMU_DEVICE_CAP_NESTING/FS1GP/ERRATA are VTD vendor specific * capabilities, so get_cap() should never fail on them now that * HOST_IOMMU_DEVICE_IOMMU_HW_INFO_TYPE_INTEL_VTD type check passed * above. @@ -5416,6 +5421,9 @@ static bool vtd_check_hiod(IntelIOMMUState *s, HostIO= MMUDevice *hiod, return false; } =20 + ret =3D hiodc->get_cap(hiod, HOST_IOMMU_DEVICE_CAP_ERRATA, errp); + vtd_hiod->errata =3D ret; + error_setg(errp, "host device is uncompatible with stage-1 translation= "); return false; } @@ -5447,7 +5455,8 @@ static bool vtd_dev_set_iommu_device(PCIBus *bus, voi= d *opaque, int devfn, vtd_hiod->iommu_state =3D s; vtd_hiod->hiod =3D hiod; =20 - if (!vtd_check_hiod(s, hiod, errp)) { + if (!vtd_check_hiod(s, vtd_hiod, errp)) { + g_free(vtd_hiod); vtd_iommu_unlock(s); return false; } --=20 2.34.1