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Wed, 21 May 2025 07:18:49 -0400 Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2025 04:18:43 -0700 Received: from spr-s2600bt.bj.intel.com ([10.240.192.127]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2025 04:18:38 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1747826327; x=1779362327; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YZB35DqJoOlf0GURKOFT9vGqd0Aim1q03SvKO/Negkk=; b=iZQOtZvHRipgJFAv3cPQCHhkiwlN+/wwycwfx5o8OESLW+hOQNW+UZHO KdDv1x7f6KnA6VPdPHnP9KjA+3jC5h7Uh7qNeJg3LZV1RAiKoMil3fCQ5 3ebSMa4a4Vy+w6YXHMPiE/MdTAZXfTf3IFbO3MmB5ttPappiicDNCP188 hP/awM/kPVaIxt/c96nhQ4xxXc4nW5M6uFdYSOgl69PMJAJ1WzFd08grP IHMUV8uuCRYxepdLRGF7PdKOj6ngdXsws78P+9e1mYqP5KcdVlTxdEL4p postZkwRJJwoneVg9hp4i7kCXR1Wy0erPR3D7y40yWaOGO2eFyYPT53TC w==; X-CSE-ConnectionGUID: s8k9xk7lS7OA9MXcGteGmw== X-CSE-MsgGUID: KhQiyyGMSSOhZp6uC0aYKQ== X-IronPort-AV: E=McAfee;i="6700,10204,11439"; a="49894860" X-IronPort-AV: E=Sophos;i="6.15,303,1739865600"; d="scan'208";a="49894860" X-CSE-ConnectionGUID: aUSk5PxhSyGrEEThOjTjfg== X-CSE-MsgGUID: q9iaI9KSRP+o9t5zc8VA+Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,303,1739865600"; d="scan'208";a="145158304" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH rfcv3 01/21] backends/iommufd: Add a helper to invalidate user-managed HWPT Date: Wed, 21 May 2025 19:14:31 +0800 Message-Id: <20250521111452.3316354-2-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250521111452.3316354-1-zhenzhong.duan@intel.com> References: <20250521111452.3316354-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.184, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1747826443497116600 Content-Type: text/plain; charset="utf-8" This helper passes cache invalidation request from guest to invalidate stage-1 page table cache in host hardware. Signed-off-by: Nicolin Chen Signed-off-by: Zhenzhong Duan --- include/system/iommufd.h | 4 ++++ backends/iommufd.c | 33 +++++++++++++++++++++++++++++++++ backends/trace-events | 1 + 3 files changed, 38 insertions(+) diff --git a/include/system/iommufd.h b/include/system/iommufd.h index cbab75bfbf..5399519626 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -61,6 +61,10 @@ bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend *be= , uint32_t hwpt_id, uint64_t iova, ram_addr_t size, uint64_t page_size, uint64_t *data, Error **errp); +bool iommufd_backend_invalidate_cache(IOMMUFDBackend *be, uint32_t id, + uint32_t data_type, uint32_t entry_l= en, + uint32_t *entry_num, void *data_ptr, + Error **errp); =20 #define TYPE_HOST_IOMMU_DEVICE_IOMMUFD TYPE_HOST_IOMMU_DEVICE "-iommufd" #endif diff --git a/backends/iommufd.c b/backends/iommufd.c index b73f75cd0b..c8788a6438 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -311,6 +311,39 @@ bool iommufd_backend_get_device_info(IOMMUFDBackend *b= e, uint32_t devid, return true; } =20 +bool iommufd_backend_invalidate_cache(IOMMUFDBackend *be, uint32_t id, + uint32_t data_type, uint32_t entry_l= en, + uint32_t *entry_num, void *data_ptr, + Error **errp) +{ + int ret, fd =3D be->fd; + uint32_t total_entries =3D *entry_num; + struct iommu_hwpt_invalidate cache =3D { + .size =3D sizeof(cache), + .hwpt_id =3D id, + .data_type =3D data_type, + .entry_len =3D entry_len, + .entry_num =3D total_entries, + .data_uptr =3D (uintptr_t)data_ptr, + }; + + ret =3D ioctl(fd, IOMMU_HWPT_INVALIDATE, &cache); + trace_iommufd_backend_invalidate_cache(fd, id, data_type, entry_len, + total_entries, cache.entry_num, + (uintptr_t)data_ptr, + ret ? errno : 0); + if (ret) { + *entry_num =3D cache.entry_num; + error_setg_errno(errp, errno, "IOMMU_HWPT_INVALIDATE failed:" + " totally %d entries, processed %d entries", + total_entries, cache.entry_num); + } else { + g_assert(total_entries =3D=3D cache.entry_num); + } + + return !ret; +} + static int hiod_iommufd_get_cap(HostIOMMUDevice *hiod, int cap, Error **er= rp) { HostIOMMUDeviceCaps *caps =3D &hiod->caps; diff --git a/backends/trace-events b/backends/trace-events index 40811a3162..7278214ea5 100644 --- a/backends/trace-events +++ b/backends/trace-events @@ -18,3 +18,4 @@ iommufd_backend_alloc_hwpt(int iommufd, uint32_t dev_id, = uint32_t pt_id, uint32_ iommufd_backend_free_id(int iommufd, uint32_t id, int ret) " iommufd=3D%d = id=3D%d (%d)" iommufd_backend_set_dirty(int iommufd, uint32_t hwpt_id, bool start, int r= et) " iommufd=3D%d hwpt=3D%u enable=3D%d (%d)" iommufd_backend_get_dirty_bitmap(int iommufd, uint32_t hwpt_id, uint64_t i= ova, uint64_t size, uint64_t page_size, int ret) " iommufd=3D%d hwpt=3D%u i= ova=3D0x%"PRIx64" size=3D0x%"PRIx64" page_size=3D0x%"PRIx64" (%d)" +iommufd_backend_invalidate_cache(int iommufd, uint32_t id, uint32_t data_t= ype, uint32_t entry_len, uint32_t entry_num, uint32_t done_num, uint64_t da= ta_ptr, int ret) " iommufd=3D%d id=3D%u data_type=3D%u entry_len=3D%u entry= _num=3D%u done_num=3D%u data_ptr=3D0x%"PRIx64" (%d)" --=20 2.34.1 From nobody Sat Nov 15 20:49:57 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="49894872" X-IronPort-AV: E=Sophos;i="6.15,303,1739865600"; d="scan'208";a="49894872" X-CSE-ConnectionGUID: nEWXbSUcS7OZw1upa5dm2g== X-CSE-MsgGUID: WapkNoOBSOql+56Z28Gz3Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,303,1739865600"; d="scan'208";a="145158308" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH rfcv3 02/21] vfio/iommufd: Add properties and handlers to TYPE_HOST_IOMMU_DEVICE_IOMMUFD Date: Wed, 21 May 2025 19:14:32 +0800 Message-Id: <20250521111452.3316354-3-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250521111452.3316354-1-zhenzhong.duan@intel.com> References: <20250521111452.3316354-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.184, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1747826399445116600 Content-Type: text/plain; charset="utf-8" Enhance HostIOMMUDeviceIOMMUFD object with 3 new members, specific to the iommufd BE + 2 new class functions. IOMMUFD BE includes IOMMUFD handle, devid and hwpt_id. IOMMUFD handle and devid are used to allocate/free ioas and hwpt. hwpt_id is used to re-attach IOMMUFD backed device to its default VFIO sub-system created hwpt, i.e., when vIOMMU is disabled by guest. These properties will be initialized after attachment. 2 new class functions are [at|de]tach_hwpt(). They are used to attach/detach hwpt. VFIO and VDPA can have different implementions, so implementation will be in sub-class instead of HostIOMMUDeviceIOMMUFD, e.g., in HostIOMMUDeviceIOMMUFDVFIO. Add two wrappers host_iommu_device_iommufd_[at|de]tach_hwpt to wrap the two functions. Signed-off-by: Zhenzhong Duan --- include/system/iommufd.h | 50 ++++++++++++++++++++++++++++++++++++++++ backends/iommufd.c | 22 ++++++++++++++++++ 2 files changed, 72 insertions(+) diff --git a/include/system/iommufd.h b/include/system/iommufd.h index 5399519626..a704575662 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -67,4 +67,54 @@ bool iommufd_backend_invalidate_cache(IOMMUFDBackend *be= , uint32_t id, Error **errp); =20 #define TYPE_HOST_IOMMU_DEVICE_IOMMUFD TYPE_HOST_IOMMU_DEVICE "-iommufd" +OBJECT_DECLARE_TYPE(HostIOMMUDeviceIOMMUFD, HostIOMMUDeviceIOMMUFDClass, + HOST_IOMMU_DEVICE_IOMMUFD) + +/* Overload of the host IOMMU device for the iommufd backend */ +struct HostIOMMUDeviceIOMMUFD { + HostIOMMUDevice parent_obj; + + IOMMUFDBackend *iommufd; + uint32_t devid; + uint32_t hwpt_id; +}; + +struct HostIOMMUDeviceIOMMUFDClass { + HostIOMMUDeviceClass parent_class; + + /** + * @attach_hwpt: attach host IOMMU device to IOMMUFD hardware page tab= le. + * VFIO and VDPA device can have different implementation. + * + * Mandatory callback. + * + * @idev: host IOMMU device backed by IOMMUFD backend. + * + * @hwpt_id: ID of IOMMUFD hardware page table. + * + * @errp: pass an Error out when attachment fails. + * + * Returns: true on success, false on failure. + */ + bool (*attach_hwpt)(HostIOMMUDeviceIOMMUFD *idev, uint32_t hwpt_id, + Error **errp); + /** + * @detach_hwpt: detach host IOMMU device from IOMMUFD hardware page t= able. + * VFIO and VDPA device can have different implementation. + * + * Mandatory callback. + * + * @idev: host IOMMU device backed by IOMMUFD backend. + * + * @errp: pass an Error out when attachment fails. + * + * Returns: true on success, false on failure. + */ + bool (*detach_hwpt)(HostIOMMUDeviceIOMMUFD *idev, Error **errp); +}; + +bool host_iommu_device_iommufd_attach_hwpt(HostIOMMUDeviceIOMMUFD *idev, + uint32_t hwpt_id, Error **errp); +bool host_iommu_device_iommufd_detach_hwpt(HostIOMMUDeviceIOMMUFD *idev, + Error **errp); #endif diff --git a/backends/iommufd.c b/backends/iommufd.c index c8788a6438..b114fb08e7 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -344,6 +344,26 @@ bool iommufd_backend_invalidate_cache(IOMMUFDBackend *= be, uint32_t id, return !ret; } =20 +bool host_iommu_device_iommufd_attach_hwpt(HostIOMMUDeviceIOMMUFD *idev, + uint32_t hwpt_id, Error **errp) +{ + HostIOMMUDeviceIOMMUFDClass *idevc =3D + HOST_IOMMU_DEVICE_IOMMUFD_GET_CLASS(idev); + + g_assert(idevc->attach_hwpt); + return idevc->attach_hwpt(idev, hwpt_id, errp); +} + +bool host_iommu_device_iommufd_detach_hwpt(HostIOMMUDeviceIOMMUFD *idev, + Error **errp) +{ + HostIOMMUDeviceIOMMUFDClass *idevc =3D + HOST_IOMMU_DEVICE_IOMMUFD_GET_CLASS(idev); + + g_assert(idevc->detach_hwpt); + return idevc->detach_hwpt(idev, errp); +} + static int hiod_iommufd_get_cap(HostIOMMUDevice *hiod, int cap, Error **er= rp) { HostIOMMUDeviceCaps *caps =3D &hiod->caps; @@ -382,6 +402,8 @@ static const TypeInfo types[] =3D { }, { .name =3D TYPE_HOST_IOMMU_DEVICE_IOMMUFD, .parent =3D TYPE_HOST_IOMMU_DEVICE, + .instance_size =3D sizeof(HostIOMMUDeviceIOMMUFD), + .class_size =3D sizeof(HostIOMMUDeviceIOMMUFDClass), .class_init =3D hiod_iommufd_class_init, .abstract =3D true, } --=20 2.34.1 From nobody Sat Nov 15 20:49:57 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="145158312" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH rfcv3 03/21] vfio/iommufd: Initialize iommufd specific members in HostIOMMUDeviceIOMMUFD Date: Wed, 21 May 2025 19:14:33 +0800 Message-Id: <20250521111452.3316354-4-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250521111452.3316354-1-zhenzhong.duan@intel.com> References: <20250521111452.3316354-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.184, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1747826435895116600 Content-Type: text/plain; charset="utf-8" There are three iommufd specific members in HostIOMMUDeviceIOMMUFD that need to be initialized after attachment, they will all be used by vIOMMU. Signed-off-by: Zhenzhong Duan --- hw/vfio/iommufd.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c index af1c7ab10a..5fde2b633a 100644 --- a/hw/vfio/iommufd.c +++ b/hw/vfio/iommufd.c @@ -814,6 +814,7 @@ static bool hiod_iommufd_vfio_realize(HostIOMMUDevice *= hiod, void *opaque, Error **errp) { VFIODevice *vdev =3D opaque; + HostIOMMUDeviceIOMMUFD *idev; HostIOMMUDeviceCaps *caps =3D &hiod->caps; enum iommu_hw_info_type type; union { @@ -833,6 +834,11 @@ static bool hiod_iommufd_vfio_realize(HostIOMMUDevice = *hiod, void *opaque, caps->type =3D type; caps->hw_caps =3D hw_caps; =20 + idev =3D HOST_IOMMU_DEVICE_IOMMUFD(hiod); + idev->iommufd =3D vdev->iommufd; + idev->devid =3D vdev->devid; + idev->hwpt_id =3D vdev->hwpt->hwpt_id; + return true; } =20 --=20 2.34.1 From nobody Sat Nov 15 20:49:57 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="145158317" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH rfcv3 04/21] vfio/iommufd: Implement [at|de]tach_hwpt handlers Date: Wed, 21 May 2025 19:14:34 +0800 Message-Id: <20250521111452.3316354-5-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250521111452.3316354-1-zhenzhong.duan@intel.com> References: <20250521111452.3316354-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.184, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1747826400959116600 Content-Type: text/plain; charset="utf-8" Implement [at|de]tach_hwpt handlers in VFIO subsystem. vIOMMU utilizes them to attach to or detach from hwpt on host side. Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Duan --- hw/vfio/iommufd.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c index 5fde2b633a..d661737c17 100644 --- a/hw/vfio/iommufd.c +++ b/hw/vfio/iommufd.c @@ -810,6 +810,24 @@ static void vfio_iommu_iommufd_class_init(ObjectClass = *klass, const void *data) vioc->query_dirty_bitmap =3D iommufd_query_dirty_bitmap; }; =20 +static bool +host_iommu_device_iommufd_vfio_attach_hwpt(HostIOMMUDeviceIOMMUFD *idev, + uint32_t hwpt_id, Error **errp) +{ + VFIODevice *vbasedev =3D HOST_IOMMU_DEVICE(idev)->agent; + + return !iommufd_cdev_attach_ioas_hwpt(vbasedev, hwpt_id, errp); +} + +static bool +host_iommu_device_iommufd_vfio_detach_hwpt(HostIOMMUDeviceIOMMUFD *idev, + Error **errp) +{ + VFIODevice *vbasedev =3D HOST_IOMMU_DEVICE(idev)->agent; + + return iommufd_cdev_detach_ioas_hwpt(vbasedev, errp); +} + static bool hiod_iommufd_vfio_realize(HostIOMMUDevice *hiod, void *opaque, Error **errp) { @@ -864,10 +882,14 @@ hiod_iommufd_vfio_get_page_size_mask(HostIOMMUDevice = *hiod) static void hiod_iommufd_vfio_class_init(ObjectClass *oc, const void *data) { HostIOMMUDeviceClass *hiodc =3D HOST_IOMMU_DEVICE_CLASS(oc); + HostIOMMUDeviceIOMMUFDClass *idevc =3D HOST_IOMMU_DEVICE_IOMMUFD_CLASS= (oc); =20 hiodc->realize =3D hiod_iommufd_vfio_realize; hiodc->get_iova_ranges =3D hiod_iommufd_vfio_get_iova_ranges; hiodc->get_page_size_mask =3D hiod_iommufd_vfio_get_page_size_mask; + + idevc->attach_hwpt =3D host_iommu_device_iommufd_vfio_attach_hwpt; + idevc->detach_hwpt =3D host_iommu_device_iommufd_vfio_detach_hwpt; }; =20 static const TypeInfo types[] =3D { --=20 2.34.1 From nobody Sat Nov 15 20:49:57 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1747826522; cv=none; d=zohomail.com; s=zohoarc; b=GyHfXC7CEWZqlY0hOjvf4FCwJo9Ge9dwyXp5D4VlgfcHPR5Ok6K46+eqYsrXRbrYlpdim3lnvsrQZOgugbwc4M4sRh+TCdPOGzU2zUBldv3a5W1tUTM9j85MM4/VVMWmD5q/rrjpIRR1X1r8A2ia8JAX1A9v/f91DPgdAZq8Vto= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.184, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1747826524518116600 Content-Type: text/plain; charset="utf-8" Some device information returned by ioctl(IOMMU_GET_HW_INFO) are vendor specific. Save them all in a new defined structure mirroring that vendor IOMMU's structure, then get_cap() can query those information for capability. We can't use the vendor IOMMU's structure directly because they are in linux/iommufd.h which breaks build on windows. Suggested-by: Eric Auger Suggested-by: Nicolin Chen Signed-off-by: Zhenzhong Duan --- include/system/host_iommu_device.h | 12 ++++++++++++ hw/vfio/iommufd.c | 12 ++++++++++++ 2 files changed, 24 insertions(+) diff --git a/include/system/host_iommu_device.h b/include/system/host_iommu= _device.h index 809cced4ba..908bfe32c7 100644 --- a/include/system/host_iommu_device.h +++ b/include/system/host_iommu_device.h @@ -15,6 +15,17 @@ #include "qom/object.h" #include "qapi/error.h" =20 +/* This is mirror of struct iommu_hw_info_vtd */ +typedef struct Vtd_Caps { + uint32_t flags; + uint64_t cap_reg; + uint64_t ecap_reg; +} Vtd_Caps; + +typedef union VendorCaps { + Vtd_Caps vtd; +} VendorCaps; + /** * struct HostIOMMUDeviceCaps - Define host IOMMU device capabilities. * @@ -26,6 +37,7 @@ typedef struct HostIOMMUDeviceCaps { uint32_t type; uint64_t hw_caps; + VendorCaps vendor_caps; } HostIOMMUDeviceCaps; =20 #define TYPE_HOST_IOMMU_DEVICE "host-iommu-device" diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c index d661737c17..5c740222e5 100644 --- a/hw/vfio/iommufd.c +++ b/hw/vfio/iommufd.c @@ -834,6 +834,7 @@ static bool hiod_iommufd_vfio_realize(HostIOMMUDevice *= hiod, void *opaque, VFIODevice *vdev =3D opaque; HostIOMMUDeviceIOMMUFD *idev; HostIOMMUDeviceCaps *caps =3D &hiod->caps; + VendorCaps *vendor_caps =3D &caps->vendor_caps; enum iommu_hw_info_type type; union { struct iommu_hw_info_vtd vtd; @@ -852,6 +853,17 @@ static bool hiod_iommufd_vfio_realize(HostIOMMUDevice = *hiod, void *opaque, caps->type =3D type; caps->hw_caps =3D hw_caps; =20 + switch (type) { + case IOMMU_HW_INFO_TYPE_INTEL_VTD: + vendor_caps->vtd.flags =3D data.vtd.flags; + vendor_caps->vtd.cap_reg =3D data.vtd.cap_reg; + vendor_caps->vtd.ecap_reg =3D data.vtd.ecap_reg; + break; + case IOMMU_HW_INFO_TYPE_ARM_SMMUV3: + case IOMMU_HW_INFO_TYPE_NONE: + break; + } + idev =3D HOST_IOMMU_DEVICE_IOMMUFD(hiod); idev->iommufd =3D vdev->iommufd; idev->devid =3D vdev->devid; --=20 2.34.1 From nobody Sat Nov 15 20:49:57 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="145158327" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH rfcv3 06/21] iommufd: Implement query of host VTD IOMMU's capability Date: Wed, 21 May 2025 19:14:36 +0800 Message-Id: <20250521111452.3316354-7-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250521111452.3316354-1-zhenzhong.duan@intel.com> References: <20250521111452.3316354-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.184, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1747826401240116600 Content-Type: text/plain; charset="utf-8" Implement query of HOST_IOMMU_DEVICE_CAP_[NESTING|FS1GP|ERRATA] for IOMMUFD backed host VTD IOMMU device. Query on these capabilities is not supported for legacy backend because the= re is no plan to support nesting with legacy backend backed host device. Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 1 + include/system/host_iommu_device.h | 7 ++++++ backends/iommufd.c | 39 ++++++++++++++++++++++++++++-- 3 files changed, 45 insertions(+), 2 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index e8b211e8b0..2cda744786 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -191,6 +191,7 @@ #define VTD_ECAP_PT (1ULL << 6) #define VTD_ECAP_SC (1ULL << 7) #define VTD_ECAP_MHMV (15ULL << 20) +#define VTD_ECAP_NEST (1ULL << 26) #define VTD_ECAP_SRS (1ULL << 31) #define VTD_ECAP_PASID (1ULL << 40) #define VTD_ECAP_SMTS (1ULL << 43) diff --git a/include/system/host_iommu_device.h b/include/system/host_iommu= _device.h index 908bfe32c7..30da88789d 100644 --- a/include/system/host_iommu_device.h +++ b/include/system/host_iommu_device.h @@ -33,6 +33,10 @@ typedef union VendorCaps { * * @hw_caps: host platform IOMMU capabilities (e.g. on IOMMUFD this repres= ents * the @out_capabilities value returned from IOMMU_GET_HW_INFO i= octl) + * + * @vendor_caps: host platform IOMMU vendor specific capabilities (e.g. on + * IOMMUFD this represents extracted content from data_uptr + * buffer returned from IOMMU_GET_HW_INFO ioctl) */ typedef struct HostIOMMUDeviceCaps { uint32_t type; @@ -117,6 +121,9 @@ struct HostIOMMUDeviceClass { */ #define HOST_IOMMU_DEVICE_CAP_IOMMU_TYPE 0 #define HOST_IOMMU_DEVICE_CAP_AW_BITS 1 +#define HOST_IOMMU_DEVICE_CAP_NESTING 2 +#define HOST_IOMMU_DEVICE_CAP_FS1GP 3 +#define HOST_IOMMU_DEVICE_CAP_ERRATA 4 =20 #define HOST_IOMMU_DEVICE_CAP_AW_BITS_MAX 64 #endif diff --git a/backends/iommufd.c b/backends/iommufd.c index b114fb08e7..d91c1eb8b8 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -21,6 +21,7 @@ #include "hw/vfio/vfio-device.h" #include #include +#include "hw/i386/intel_iommu_internal.h" =20 static void iommufd_backend_init(Object *obj) { @@ -364,6 +365,41 @@ bool host_iommu_device_iommufd_detach_hwpt(HostIOMMUDe= viceIOMMUFD *idev, return idevc->detach_hwpt(idev, errp); } =20 +static int hiod_iommufd_get_vtd_cap(HostIOMMUDevice *hiod, int cap, + Error **errp) +{ + Vtd_Caps *caps =3D &hiod->caps.vendor_caps.vtd; + + switch (cap) { + case HOST_IOMMU_DEVICE_CAP_NESTING: + return !!(caps->ecap_reg & VTD_ECAP_NEST); + case HOST_IOMMU_DEVICE_CAP_FS1GP: + return !!(caps->cap_reg & VTD_CAP_FS1GP); + case HOST_IOMMU_DEVICE_CAP_ERRATA: + return caps->flags & IOMMU_HW_INFO_VTD_ERRATA_772415_SPR17; + default: + error_setg(errp, "%s: unsupported capability %x", hiod->name, cap); + return -EINVAL; + } +} + +static int hiod_iommufd_get_vendor_cap(HostIOMMUDevice *hiod, int cap, + Error **errp) +{ + enum iommu_hw_info_type type =3D hiod->caps.type; + + switch (type) { + case IOMMU_HW_INFO_TYPE_INTEL_VTD: + return hiod_iommufd_get_vtd_cap(hiod, cap, errp); + case IOMMU_HW_INFO_TYPE_ARM_SMMUV3: + case IOMMU_HW_INFO_TYPE_NONE: + break; + } + + error_setg(errp, "%s: unsupported capability type %x", hiod->name, typ= e); + return -EINVAL; +} + static int hiod_iommufd_get_cap(HostIOMMUDevice *hiod, int cap, Error **er= rp) { HostIOMMUDeviceCaps *caps =3D &hiod->caps; @@ -374,8 +410,7 @@ static int hiod_iommufd_get_cap(HostIOMMUDevice *hiod, = int cap, Error **errp) case HOST_IOMMU_DEVICE_CAP_AW_BITS: return vfio_device_get_aw_bits(hiod->agent); default: - error_setg(errp, "%s: unsupported capability %x", hiod->name, cap); - return -EINVAL; + return hiod_iommufd_get_vendor_cap(hiod, cap, errp); } } =20 --=20 2.34.1 From nobody Sat Nov 15 20:49:57 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1747826542; cv=none; d=zohomail.com; s=zohoarc; b=PPOf6jHUpArNFF6onrJBw9F94IX/1Emg65MSFb1lwxABTwl7SOoaHo00P6ZKPCoRPl/i4VeHqyuYPZnSZ4Q67WPXywrmN/UzMKTbI2bTc4ur62YcSiPfLCZ6s68Kr9Yj+XbD+m8uLF8W5ijknw9uxlhb++PYosk2GY8iHxZyxVw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747826542; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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X-CSE-ConnectionGUID: +9QlBSPtRumecxbF3rHiSA== X-CSE-MsgGUID: 3zneiYofRj+NE8tYZB20Og== X-IronPort-AV: E=McAfee;i="6700,10204,11439"; a="49894975" X-IronPort-AV: E=Sophos;i="6.15,303,1739865600"; d="scan'208";a="49894975" X-CSE-ConnectionGUID: 7OYsvwEuRkiu2vswt7fbkA== X-CSE-MsgGUID: /DJKiclfRy20apYHfweaug== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,303,1739865600"; d="scan'208";a="145158331" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH rfcv3 07/21] intel_iommu: Rename vtd_ce_get_rid2pasid_entry to vtd_ce_get_pasid_entry Date: Wed, 21 May 2025 19:14:37 +0800 Message-Id: <20250521111452.3316354-8-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250521111452.3316354-1-zhenzhong.duan@intel.com> References: <20250521111452.3316354-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.184, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1747826544827116600 In early days vtd_ce_get_rid2pasid_entry() was used to get pasid entry of rid2pasid, then it was extended to get any pasid entry. So a new name vtd_ce_get_pasid_entry is better to match what it actually does. No functional change intended. Signed-off-by: Zhenzhong Duan Reviewed-by: Cl=C3=A9ment Mathieu--Drif --- hw/i386/intel_iommu.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 69d72ad35c..f0b1f90eff 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -944,7 +944,7 @@ static int vtd_get_pe_from_pasid_table(IntelIOMMUState = *s, return 0; } =20 -static int vtd_ce_get_rid2pasid_entry(IntelIOMMUState *s, +static int vtd_ce_get_pasid_entry(IntelIOMMUState *s, VTDContextEntry *ce, VTDPASIDEntry *pe, uint32_t pasid) @@ -1025,7 +1025,7 @@ static uint32_t vtd_get_iova_level(IntelIOMMUState *s, VTDPASIDEntry pe; =20 if (s->root_scalable) { - vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); + vtd_ce_get_pasid_entry(s, ce, &pe, pasid); if (s->flts) { return VTD_PE_GET_FL_LEVEL(&pe); } else { @@ -1048,7 +1048,7 @@ static uint32_t vtd_get_iova_agaw(IntelIOMMUState *s, VTDPASIDEntry pe; =20 if (s->root_scalable) { - vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); + vtd_ce_get_pasid_entry(s, ce, &pe, pasid); return 30 + ((pe.val[0] >> 2) & VTD_SM_PASID_ENTRY_AW) * 9; } =20 @@ -1116,7 +1116,7 @@ static dma_addr_t vtd_get_iova_pgtbl_base(IntelIOMMUS= tate *s, VTDPASIDEntry pe; =20 if (s->root_scalable) { - vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); + vtd_ce_get_pasid_entry(s, ce, &pe, pasid); if (s->flts) { return pe.val[2] & VTD_SM_PASID_ENTRY_FLPTPTR; } else { @@ -1522,7 +1522,7 @@ static int vtd_ce_rid2pasid_check(IntelIOMMUState *s, * has valid rid2pasid setting, which includes valid * rid2pasid field and corresponding pasid entry setting */ - return vtd_ce_get_rid2pasid_entry(s, ce, &pe, PCI_NO_PASID); + return vtd_ce_get_pasid_entry(s, ce, &pe, PCI_NO_PASID); } =20 /* Map a device to its corresponding domain (context-entry) */ @@ -1611,7 +1611,7 @@ static uint16_t vtd_get_domain_id(IntelIOMMUState *s, VTDPASIDEntry pe; =20 if (s->root_scalable) { - vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); + vtd_ce_get_pasid_entry(s, ce, &pe, pasid); return VTD_SM_PASID_ENTRY_DID(pe.val[1]); } =20 @@ -1687,7 +1687,7 @@ static bool vtd_dev_pt_enabled(IntelIOMMUState *s, VT= DContextEntry *ce, int ret; =20 if (s->root_scalable) { - ret =3D vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); + ret =3D vtd_ce_get_pasid_entry(s, ce, &pe, pasid); if (ret) { /* * This error is guest triggerable. We should assumt PT --=20 2.34.1 From nobody Sat Nov 15 20:49:57 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1747826556; cv=none; d=zohomail.com; s=zohoarc; b=nkDG/xiWL88LOjj0Kc47Lwh1Z2vc95dyoD8fKe3q1DhZ3lCidU9Zr30qYe3HVqtXoyeuJypqmCto0GsZnFxBV5mYGrUidNOu1/PuBYP27dyF0+R7LgGwSw96yaHDLRCgkgyTAdZVZze3SpN3tSslZPYsQ5VivyK1Oc8fi+ManT8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747826556; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=kq23I6OO6Qr3dZ9pgyWgD0+oiHDLRnTY62eB56/T9rw=; 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Wed, 21 May 2025 07:19:18 -0400 Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2025 04:19:15 -0700 Received: from spr-s2600bt.bj.intel.com ([10.240.192.127]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2025 04:19:10 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1747826356; x=1779362356; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KLjRZ+Hv72Y3pA0KOcUTZCjBQvdG45vZ8JtjLhnvJ+A=; b=SL3G64zuqtyDxtF7QWYY9hhSmYK+HEQAAbduTbVhSUFCMyS0WK9+pcEf PXr8bc+Er8X2uA6to/mHC2HwkYY5VV4kmIX4GZMamIAvI1RTMoDsMQEEu eroGUuOg8Rl+khNErHs4lr3MArZdMn9FpXM7AYk/mEmi51Eb9EQ6doWzw 6KaHhQjr2BWMtK+gFd5DbnV0mpXl6XV4KEWzRBWyi+/GYcuwoIqNx7Num 5nuT/jjYAsNBJ8r22H2EcEcVkhNLnzwoBBoikIUaaOBl6NVj8VhSL7Udj 6WkPq0Rs9bzaGIgljdN4gXzasx3tkootpWfr0YeZJNtzU6oosYHXL/9Nf g==; X-CSE-ConnectionGUID: B+cjEv68RF+NB+I0c1gecw== X-CSE-MsgGUID: JFRHimOYRqawviazBIrk6w== X-IronPort-AV: E=McAfee;i="6700,10204,11439"; a="49894991" X-IronPort-AV: E=Sophos;i="6.15,303,1739865600"; d="scan'208";a="49894991" X-CSE-ConnectionGUID: xYBNWGo1SZOU1uNKeJCF7Q== X-CSE-MsgGUID: 5oi/zXR/SDCKo/LYSEVakw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,303,1739865600"; d="scan'208";a="145158336" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PATCH rfcv3 08/21] intel_iommu: Optimize context entry cache utilization Date: Wed, 21 May 2025 19:14:38 +0800 Message-Id: <20250521111452.3316354-9-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250521111452.3316354-1-zhenzhong.duan@intel.com> References: <20250521111452.3316354-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.184, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1747826557161116600 Content-Type: text/plain; charset="utf-8" There are many call sites referencing context entry by calling vtd_dev_to_context_entry() which will traverse the DMAR table. In most cases we can use cached context entry in vtd_as->context_cache_entry except when its entry is stale. Currently only global and domain context invalidation stale it. So introduce a helper function vtd_as_to_context_entry() to fetch from cache before trying with vtd_dev_to_context_entry(). Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 36 +++++++++++++++++++++++------------- 1 file changed, 23 insertions(+), 13 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index f0b1f90eff..a2f3250724 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -1597,6 +1597,22 @@ static int vtd_dev_to_context_entry(IntelIOMMUState = *s, uint8_t bus_num, return 0; } =20 +static int vtd_as_to_context_entry(VTDAddressSpace *vtd_as, VTDContextEntr= y *ce) +{ + IntelIOMMUState *s =3D vtd_as->iommu_state; + uint8_t bus_num =3D pci_bus_num(vtd_as->bus); + uint8_t devfn =3D vtd_as->devfn; + VTDContextCacheEntry *cc_entry =3D &vtd_as->context_cache_entry; + + /* Try to fetch context-entry from cache first */ + if (cc_entry->context_cache_gen =3D=3D s->context_cache_gen) { + *ce =3D cc_entry->context_entry; + return 0; + } else { + return vtd_dev_to_context_entry(s, bus_num, devfn, ce); + } +} + static int vtd_sync_shadow_page_hook(const IOMMUTLBEvent *event, void *private) { @@ -1649,9 +1665,7 @@ static int vtd_address_space_sync(VTDAddressSpace *vt= d_as) return 0; } =20 - ret =3D vtd_dev_to_context_entry(vtd_as->iommu_state, - pci_bus_num(vtd_as->bus), - vtd_as->devfn, &ce); + ret =3D vtd_as_to_context_entry(vtd_as, &ce); if (ret) { if (ret =3D=3D -VTD_FR_CONTEXT_ENTRY_P) { /* @@ -1710,8 +1724,7 @@ static bool vtd_as_pt_enabled(VTDAddressSpace *as) assert(as); =20 s =3D as->iommu_state; - if (vtd_dev_to_context_entry(s, pci_bus_num(as->bus), as->devfn, - &ce)) { + if (vtd_as_to_context_entry(as, &ce)) { /* * Possibly failed to parse the context entry for some reason * (e.g., during init, or any guest configuration errors on @@ -2435,8 +2448,7 @@ static void vtd_iotlb_domain_invalidate(IntelIOMMUSta= te *s, uint16_t domain_id) vtd_iommu_unlock(s); =20 QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) { - if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus), - vtd_as->devfn, &ce) && + if (!vtd_as_to_context_entry(vtd_as, &ce) && domain_id =3D=3D vtd_get_domain_id(s, &ce, vtd_as->pasid)) { vtd_address_space_sync(vtd_as); } @@ -2458,8 +2470,7 @@ static void vtd_iotlb_page_invalidate_notify(IntelIOM= MUState *s, hwaddr size =3D (1 << am) * VTD_PAGE_SIZE; =20 QLIST_FOREACH(vtd_as, &(s->vtd_as_with_notifiers), next) { - ret =3D vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus), - vtd_as->devfn, &ce); + ret =3D vtd_as_to_context_entry(vtd_as, &ce); if (!ret && domain_id =3D=3D vtd_get_domain_id(s, &ce, vtd_as->pas= id)) { uint32_t rid2pasid =3D PCI_NO_PASID; =20 @@ -2966,8 +2977,7 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUSta= te *s, vtd_iommu_unlock(s); =20 QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) { - if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus), - vtd_as->devfn, &ce) && + if (!vtd_as_to_context_entry(vtd_as, &ce) && domain_id =3D=3D vtd_get_domain_id(s, &ce, vtd_as->pasid)) { uint32_t rid2pasid =3D VTD_CE_GET_RID2PASID(&ce); =20 @@ -4146,7 +4156,7 @@ static void vtd_report_ir_illegal_access(VTDAddressSp= ace *vtd_as, assert(vtd_as->pasid !=3D PCI_NO_PASID); =20 /* Try out best to fetch FPD, we can't do anything more */ - if (vtd_dev_to_context_entry(s, bus_n, vtd_as->devfn, &ce) =3D=3D 0) { + if (vtd_as_to_context_entry(vtd_as, &ce) =3D=3D 0) { is_fpd_set =3D ce.lo & VTD_CONTEXT_ENTRY_FPD; if (!is_fpd_set && s->root_scalable) { vtd_ce_get_pasid_fpd(s, &ce, &is_fpd_set, vtd_as->pasid); @@ -4506,7 +4516,7 @@ static void vtd_iommu_replay(IOMMUMemoryRegion *iommu= _mr, IOMMUNotifier *n) /* replay is protected by BQL, page walk will re-setup it safely */ iova_tree_remove(vtd_as->iova_tree, map); =20 - if (vtd_dev_to_context_entry(s, bus_n, vtd_as->devfn, &ce) =3D=3D 0) { + if (vtd_as_to_context_entry(vtd_as, &ce) =3D=3D 0) { trace_vtd_replay_ce_valid(s->root_scalable ? "scalable mode" : "legacy mode", bus_n, PCI_SLOT(vtd_as->devfn), --=20 2.34.1 From nobody Sat Nov 15 20:49:57 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1747826443; cv=none; d=zohomail.com; s=zohoarc; b=Avevsota2b8DNzyD2OMCcuGIrQ8FSErMzZorfgNdGWEDtdoK+KeLPZdeCOyxOkgQ9PjxqiFEeza6X4zPdk0taCIRrzRcE/BhPhGRw6H5XG7qc55KVdri3vaor6whPGKMI/mQoUUMql57JvjLZELgJZAf+ff1fewfQnTWRAa7jqg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747826443; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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X-CSE-ConnectionGUID: ONYMm9qCT1mMbjQ0hUN4qA== X-CSE-MsgGUID: 7Qm/aAMdRoyl2oSn6L5AUg== X-IronPort-AV: E=McAfee;i="6700,10204,11439"; a="49895006" X-IronPort-AV: E=Sophos;i="6.15,303,1739865600"; d="scan'208";a="49895006" X-CSE-ConnectionGUID: V/nx36OaSd+4dGB1vpHAXQ== X-CSE-MsgGUID: muY/OyvSQyq0ZQeII2sSXQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,303,1739865600"; d="scan'208";a="145158339" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PATCH rfcv3 09/21] intel_iommu: Check for compatibility with IOMMUFD backed device when x-flts=on Date: Wed, 21 May 2025 19:14:39 +0800 Message-Id: <20250521111452.3316354-10-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250521111452.3316354-1-zhenzhong.duan@intel.com> References: <20250521111452.3316354-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.184, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1747826446013116600 Content-Type: text/plain; charset="utf-8" When vIOMMU is configured x-flts=3Don in scalable mode, stage-1 page table is passed to host to construct nested page table. We need to check compatibility of some critical IOMMU capabilities between vIOMMU and host IOMMU to ensure guest stage-1 page table could be used by host. For instance, vIOMMU supports stage-1 1GB huge page mapping, but host does not, then this IOMMUFD backed device should be failed. Declare an enum type host_iommu_device_iommu_hw_info_type aliased to iommu_hw_info_type which comes from iommufd header file. This can avoid build failure on windows which doesn't support iommufd. Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Duan --- include/system/host_iommu_device.h | 13 +++++++++++ hw/i386/intel_iommu.c | 36 ++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) diff --git a/include/system/host_iommu_device.h b/include/system/host_iommu= _device.h index 30da88789d..38070aff09 100644 --- a/include/system/host_iommu_device.h +++ b/include/system/host_iommu_device.h @@ -125,5 +125,18 @@ struct HostIOMMUDeviceClass { #define HOST_IOMMU_DEVICE_CAP_FS1GP 3 #define HOST_IOMMU_DEVICE_CAP_ERRATA 4 =20 +/** + * enum host_iommu_device_iommu_hw_info_type - IOMMU Hardware Info Types + * @HOST_IOMMU_DEVICE_IOMMU_HW_INFO_TYPE_NONE: Used by the drivers that do= not + * report hardware info + * @HOST_IOMMU_DEVICE_IOMMU_HW_INFO_TYPE_INTEL_VTD: Intel VT-d iommu info = type + * + * This is alias to enum iommu_hw_info_type but for general purpose. + */ +enum host_iommu_device_iommu_hw_info_type { + HOST_IOMMU_DEVICE_IOMMU_HW_INFO_TYPE_NONE, + HOST_IOMMU_DEVICE_IOMMU_HW_INFO_TYPE_INTEL_VTD, +}; + #define HOST_IOMMU_DEVICE_CAP_AW_BITS_MAX 64 #endif diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index a2f3250724..dc839037cf 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -39,6 +39,7 @@ #include "kvm/kvm_i386.h" #include "migration/vmstate.h" #include "trace.h" +#include "system/iommufd.h" =20 /* context entry operations */ #define VTD_CE_GET_RID2PASID(ce) \ @@ -4361,6 +4362,41 @@ static bool vtd_check_hiod(IntelIOMMUState *s, HostI= OMMUDevice *hiod, return true; } =20 + /* Remaining checks are all stage-1 translation specific */ + if (!object_dynamic_cast(OBJECT(hiod), TYPE_HOST_IOMMU_DEVICE_IOMMUFD)= ) { + error_setg(errp, "Need IOMMUFD backend when x-flts=3Don"); + return false; + } + + /* + * HOST_IOMMU_DEVICE_CAP_IOMMU_TYPE should be supported by different + * backend devices, either VFIO or VDPA. + */ + ret =3D hiodc->get_cap(hiod, HOST_IOMMU_DEVICE_CAP_IOMMU_TYPE, errp); + assert(ret >=3D 0); + if (ret !=3D HOST_IOMMU_DEVICE_IOMMU_HW_INFO_TYPE_INTEL_VTD) { + error_setg(errp, "Incompatible host platform IOMMU type %d", ret); + return false; + } + + /* + * HOST_IOMMU_DEVICE_CAP_NESTING/FS1GP are VTD vendor specific + * capabilities, so get_cap() should never fail on them now that + * HOST_IOMMU_DEVICE_IOMMU_HW_INFO_TYPE_INTEL_VTD type check passed + * above. + */ + ret =3D hiodc->get_cap(hiod, HOST_IOMMU_DEVICE_CAP_NESTING, errp); + if (ret !=3D 1) { + error_setg(errp, "Host IOMMU doesn't support nested translation"); + return false; + } + + ret =3D hiodc->get_cap(hiod, HOST_IOMMU_DEVICE_CAP_FS1GP, errp); + if (s->fs1gp && ret !=3D 1) { + error_setg(errp, "Stage-1 1GB huge page is unsupported by host IOM= MU"); + return false; + } + error_setg(errp, "host device is uncompatible with stage-1 translation= "); return false; } --=20 2.34.1 From nobody Sat Nov 15 20:49:57 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="145158342" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PATCH rfcv3 10/21] intel_iommu: Introduce a new structure VTDHostIOMMUDevice Date: Wed, 21 May 2025 19:14:40 +0800 Message-Id: <20250521111452.3316354-11-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250521111452.3316354-1-zhenzhong.duan@intel.com> References: <20250521111452.3316354-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.184, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1747826589324116600 Content-Type: text/plain; charset="utf-8" Introduce a new structure VTDHostIOMMUDevice which replaces HostIOMMUDevice to be stored in hash table. It includes a reference to HostIOMMUDevice and IntelIOMMUState, also includes BDF information which will be used in future patches. Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 7 +++++++ include/hw/i386/intel_iommu.h | 2 +- hw/i386/intel_iommu.c | 14 ++++++++++++-- 3 files changed, 20 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 2cda744786..18bc22fc72 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -28,6 +28,7 @@ #ifndef HW_I386_INTEL_IOMMU_INTERNAL_H #define HW_I386_INTEL_IOMMU_INTERNAL_H #include "hw/i386/intel_iommu.h" +#include "system/host_iommu_device.h" =20 /* * Intel IOMMU register specification @@ -608,4 +609,10 @@ typedef struct VTDRootEntry VTDRootEntry; /* Bits to decide the offset for each level */ #define VTD_LEVEL_BITS 9 =20 +typedef struct VTDHostIOMMUDevice { + IntelIOMMUState *iommu_state; + PCIBus *bus; + uint8_t devfn; + HostIOMMUDevice *hiod; +} VTDHostIOMMUDevice; #endif diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index e95477e855..50f9b27a45 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -295,7 +295,7 @@ struct IntelIOMMUState { /* list of registered notifiers */ QLIST_HEAD(, VTDAddressSpace) vtd_as_with_notifiers; =20 - GHashTable *vtd_host_iommu_dev; /* HostIOMMUDevice */ + GHashTable *vtd_host_iommu_dev; /* VTDHostIOMMUDevice */ =20 /* interrupt remapping */ bool intr_enabled; /* Whether guest enabled IR */ diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index dc839037cf..b2ea109c7c 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -281,7 +281,10 @@ static gboolean vtd_hiod_equal(gconstpointer v1, gcons= tpointer v2) =20 static void vtd_hiod_destroy(gpointer v) { - object_unref(v); + VTDHostIOMMUDevice *vtd_hiod =3D v; + + object_unref(vtd_hiod->hiod); + g_free(vtd_hiod); } =20 static gboolean vtd_hash_remove_by_domain(gpointer key, gpointer value, @@ -4405,6 +4408,7 @@ static bool vtd_dev_set_iommu_device(PCIBus *bus, voi= d *opaque, int devfn, HostIOMMUDevice *hiod, Error **errp) { IntelIOMMUState *s =3D opaque; + VTDHostIOMMUDevice *vtd_hiod; struct vtd_as_key key =3D { .bus =3D bus, .devfn =3D devfn, @@ -4421,6 +4425,12 @@ static bool vtd_dev_set_iommu_device(PCIBus *bus, vo= id *opaque, int devfn, return false; } =20 + vtd_hiod =3D g_malloc0(sizeof(VTDHostIOMMUDevice)); + vtd_hiod->bus =3D bus; + vtd_hiod->devfn =3D (uint8_t)devfn; + vtd_hiod->iommu_state =3D s; + vtd_hiod->hiod =3D hiod; + if (!vtd_check_hiod(s, hiod, errp)) { vtd_iommu_unlock(s); return false; @@ -4431,7 +4441,7 @@ static bool vtd_dev_set_iommu_device(PCIBus *bus, voi= d *opaque, int devfn, new_key->devfn =3D devfn; =20 object_ref(hiod); - g_hash_table_insert(s->vtd_host_iommu_dev, new_key, hiod); + g_hash_table_insert(s->vtd_host_iommu_dev, new_key, vtd_hiod); =20 vtd_iommu_unlock(s); =20 --=20 2.34.1 From nobody Sat Nov 15 20:49:57 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1747826566; cv=none; d=zohomail.com; s=zohoarc; b=mI49lc4Xgl5TgMwK/PMicLs3xhqyu7yNL710poCkBfmj4wvnwBeCPZp3571VGc7mnQhy6vcLU+I32qMbMTb+cA6jTwDTc3DSG02NQ+Pcc3aJLEtXkn+4+U54ymYS9cvPDnMtXloeDvfuv5oBkjBYEiVZUCJQju7wnk8FRUxeZ00= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.184, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1747826569050116600 Content-Type: text/plain; charset="utf-8" We already have vtd_find_add_as() to find an AS from BDF+pasid, but this pasid is passed from PCI subsystem. PCI device supports two request types, Requests-without-PASID and Requests-with-PASID. Requests-without-PASID doesn't include a PASID TLP prefix, IOMMU fetches rid_pasid from context entry and use it as IOMMU's pasid to index pasid table. So we need to translate between PCI's pasid and IOMMU's pasid specially for Requests-without-PASID, e.g., PCI_NO_PASID(-1) <-> rid_pasid. For Requests-with-PASID, PCI's pasid and IOMMU's pasid are same value. vtd_as_from_iommu_pasid_locked() translates from BDF+iommu_pasid to vtd_as which contains PCI's pasid vtd_as->pasid. vtd_as_to_iommu_pasid_locked() translates from BDF+vtd_as->pasid to iommu_p= asid. Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 50 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index b2ea109c7c..a9c0bd5021 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -1617,6 +1617,56 @@ static int vtd_as_to_context_entry(VTDAddressSpace *= vtd_as, VTDContextEntry *ce) } } =20 +static inline int vtd_as_to_iommu_pasid_locked(VTDAddressSpace *vtd_as, + uint32_t *pasid) +{ + VTDContextEntry ce; + int ret; + + ret =3D vtd_as_to_context_entry(vtd_as, &ce); + if (ret) { + return ret; + } + + /* Translate to iommu pasid if PCI_NO_PASID */ + if (vtd_as->pasid =3D=3D PCI_NO_PASID) { + *pasid =3D VTD_CE_GET_RID2PASID(&ce); + } else { + *pasid =3D vtd_as->pasid; + } + + return 0; +} + +static gboolean vtd_find_as_by_sid_and_iommu_pasid(gpointer key, gpointer = value, + gpointer user_data) +{ + VTDAddressSpace *vtd_as =3D (VTDAddressSpace *)value; + struct vtd_as_raw_key *target =3D (struct vtd_as_raw_key *)user_data; + uint16_t sid =3D PCI_BUILD_BDF(pci_bus_num(vtd_as->bus), vtd_as->devfn= ); + uint32_t pasid; + + if (vtd_as_to_iommu_pasid_locked(vtd_as, &pasid)) { + return false; + } + + return (pasid =3D=3D target->pasid) && (sid =3D=3D target->sid); +} + +/* Translate iommu pasid to vtd_as */ +static inline +VTDAddressSpace *vtd_as_from_iommu_pasid_locked(IntelIOMMUState *s, + uint16_t sid, uint32_t pas= id) +{ + struct vtd_as_raw_key key =3D { + .sid =3D sid, + .pasid =3D pasid + }; + + return g_hash_table_find(s->vtd_address_spaces, + vtd_find_as_by_sid_and_iommu_pasid, &key); +} + static int vtd_sync_shadow_page_hook(const IOMMUTLBEvent *event, void *private) { --=20 2.34.1 From nobody Sat Nov 15 20:49:57 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; 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d="scan'208";a="145158351" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Yi Sun , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH rfcv3 12/21] intel_iommu: Handle PASID entry removing and updating Date: Wed, 21 May 2025 19:14:42 +0800 Message-Id: <20250521111452.3316354-13-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250521111452.3316354-1-zhenzhong.duan@intel.com> References: <20250521111452.3316354-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.184, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1747826427929116600 Content-Type: text/plain; charset="utf-8" This adds an new entry VTDPASIDCacheEntry in VTDAddressSpace to cache the pasid entry and track PASID usage and future PASID tagged DMA address translation support in vIOMMU. VTDAddressSpace of PCI_NO_PASID is allocated when device is plugged and never freed. For other pasid, VTDAddressSpace instance is created/destroyed per the guest pasid entry set up/destroy for passthrough devices. While for emulated devices, VTDAddressSpace instance is created in the PASID tagged D= MA translation and be destroyed per guest PASID cache invalidation. This focus= es on the PASID cache management for passthrough devices as there is no PASID capable emulated devices yet. When guest modifies a PASID entry, QEMU will capture the guest pasid select= ive pasid cache invalidation, allocate or remove a VTDAddressSpace instance per= the invalidation reasons: a) a present pasid entry moved to non-present b) a present pasid entry to be a present entry c) a non-present pasid entry moved to present This handles a) and b), following patch will handle c). vIOMMU emulator could figure out the reason by fetching latest guest pasid = entry and compare it with the PASID cache. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 26 ++++ include/hw/i386/intel_iommu.h | 6 + hw/i386/intel_iommu.c | 252 +++++++++++++++++++++++++++++++-- hw/i386/trace-events | 3 + 4 files changed, 277 insertions(+), 10 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 18bc22fc72..82b84db80f 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -315,6 +315,7 @@ typedef enum VTDFaultReason { * request while disabled */ VTD_FR_IR_SID_ERR =3D 0x26, /* Invalid Source-ID */ =20 + VTD_FR_RTADDR_INV_TTM =3D 0x31, /* Invalid TTM in RTADDR */ /* PASID directory entry access failure */ VTD_FR_PASID_DIR_ACCESS_ERR =3D 0x50, /* The Present(P) field of pasid directory entry is 0 */ @@ -492,6 +493,15 @@ typedef union VTDInvDesc VTDInvDesc; #define VTD_INV_DESC_PIOTLB_RSVD_VAL0 0xfff000000000f1c0ULL #define VTD_INV_DESC_PIOTLB_RSVD_VAL1 0xf80ULL =20 +#define VTD_INV_DESC_PASIDC_G (3ULL << 4) +#define VTD_INV_DESC_PASIDC_PASID(val) (((val) >> 32) & 0xfffffULL) +#define VTD_INV_DESC_PASIDC_DID(val) (((val) >> 16) & VTD_DOMAIN_ID_MASK) +#define VTD_INV_DESC_PASIDC_RSVD_VAL0 0xfff000000000f1c0ULL + +#define VTD_INV_DESC_PASIDC_DSI (0ULL << 4) +#define VTD_INV_DESC_PASIDC_PASID_SI (1ULL << 4) +#define VTD_INV_DESC_PASIDC_GLOBAL (3ULL << 4) + /* Information about page-selective IOTLB invalidate */ struct VTDIOTLBPageInvInfo { uint16_t domain_id; @@ -552,6 +562,21 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(aw) (0x1e0ULL | ~VTD_HAW_MASK(aw)) #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 0xffffffffffe00000ULL =20 +typedef enum VTDPCInvType { + /* pasid cache invalidation rely on guest PASID entry */ + VTD_PASID_CACHE_GLOBAL_INV, /* pasid cache global invalidation */ + VTD_PASID_CACHE_DOMSI, /* pasid cache domain selective invalidati= on */ + VTD_PASID_CACHE_PASIDSI, /* pasid cache pasid selective invalidatio= n */ +} VTDPCInvType; + +typedef struct VTDPASIDCacheInfo { + VTDPCInvType type; + uint16_t domain_id; + uint32_t pasid; + PCIBus *bus; + uint16_t devfn; +} VTDPASIDCacheInfo; + /* PASID Table Related Definitions */ #define VTD_PASID_DIR_BASE_ADDR_MASK (~0xfffULL) #define VTD_PASID_TABLE_BASE_ADDR_MASK (~0xfffULL) @@ -563,6 +588,7 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_PASID_TABLE_BITS_MASK (0x3fULL) #define VTD_PASID_TABLE_INDEX(pasid) ((pasid) & VTD_PASID_TABLE_BITS_MASK) #define VTD_PASID_ENTRY_FPD (1ULL << 1) /* Fault Processing Disa= ble */ +#define VTD_PASID_TBL_ENTRY_NUM (1ULL << 6) =20 /* PASID Granular Translation Type Mask */ #define VTD_PASID_ENTRY_P 1ULL diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 50f9b27a45..fbc9da903a 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -95,6 +95,11 @@ struct VTDPASIDEntry { uint64_t val[8]; }; =20 +typedef struct VTDPASIDCacheEntry { + struct VTDPASIDEntry pasid_entry; + bool cache_filled; +} VTDPASIDCacheEntry; + struct VTDAddressSpace { PCIBus *bus; uint8_t devfn; @@ -107,6 +112,7 @@ struct VTDAddressSpace { MemoryRegion iommu_ir_fault; /* Interrupt region for catching fault */ IntelIOMMUState *iommu_state; VTDContextCacheEntry context_cache_entry; + VTDPASIDCacheEntry pasid_cache_entry; QLIST_ENTRY(VTDAddressSpace) next; /* Superset of notifier flags that this address space has */ IOMMUNotifierFlag notifier_flags; diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index a9c0bd5021..0c6587735e 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -825,6 +825,11 @@ static inline bool vtd_pe_type_check(IntelIOMMUState *= s, VTDPASIDEntry *pe) } } =20 +static inline uint16_t vtd_pe_get_did(VTDPASIDEntry *pe) +{ + return VTD_SM_PASID_ENTRY_DID((pe)->val[1]); +} + static inline bool vtd_pdire_present(VTDPASIDDirEntry *pdire) { return pdire->val & 1; @@ -3104,6 +3109,236 @@ static bool vtd_process_piotlb_desc(IntelIOMMUState= *s, return true; } =20 +static inline int vtd_dev_get_pe_from_pasid(VTDAddressSpace *vtd_as, + uint32_t pasid, VTDPASIDEntry = *pe) +{ + IntelIOMMUState *s =3D vtd_as->iommu_state; + VTDContextEntry ce; + int ret; + + if (!s->root_scalable) { + return -VTD_FR_RTADDR_INV_TTM; + } + + ret =3D vtd_as_to_context_entry(vtd_as, &ce); + if (ret) { + return ret; + } + + return vtd_ce_get_pasid_entry(s, &ce, pe, pasid); +} + +static bool vtd_pasid_entry_compare(VTDPASIDEntry *p1, VTDPASIDEntry *p2) +{ + return !memcmp(p1, p2, sizeof(*p1)); +} + +/* + * This function fills in the pasid entry in &vtd_as. Caller + * of this function should hold iommu_lock. + */ +static void vtd_fill_pe_in_cache(IntelIOMMUState *s, VTDAddressSpace *vtd_= as, + VTDPASIDEntry *pe) +{ + VTDPASIDCacheEntry *pc_entry =3D &vtd_as->pasid_cache_entry; + + if (vtd_pasid_entry_compare(pe, &pc_entry->pasid_entry)) { + /* No need to go further as cached pasid entry is latest */ + return; + } + + pc_entry->pasid_entry =3D *pe; + pc_entry->cache_filled =3D true; + /* + * TODO: send pasid bind to host for passthru devices + */ +} + +/* + * This function is used to clear cached pasid entry in vtd_as + * instances. Caller of this function should hold iommu_lock. + */ +static gboolean vtd_flush_pasid(gpointer key, gpointer value, + gpointer user_data) +{ + VTDPASIDCacheInfo *pc_info =3D user_data; + VTDAddressSpace *vtd_as =3D value; + IntelIOMMUState *s =3D vtd_as->iommu_state; + VTDPASIDCacheEntry *pc_entry =3D &vtd_as->pasid_cache_entry; + VTDPASIDEntry pe; + uint16_t did; + uint32_t pasid; + int ret; + + /* Replay only filled pasid entry cache for passthrough device */ + if (!pc_entry->cache_filled) { + return false; + } + did =3D vtd_pe_get_did(&pc_entry->pasid_entry); + + if (vtd_as_to_iommu_pasid_locked(vtd_as, &pasid)) { + goto remove; + } + + switch (pc_info->type) { + case VTD_PASID_CACHE_PASIDSI: + if (pc_info->pasid !=3D pasid) { + return false; + } + /* Fall through */ + case VTD_PASID_CACHE_DOMSI: + if (pc_info->domain_id !=3D did) { + return false; + } + /* Fall through */ + case VTD_PASID_CACHE_GLOBAL_INV: + break; + default: + error_report("invalid pc_info->type"); + abort(); + } + + /* + * pasid cache invalidation may indicate a present pasid + * entry to present pasid entry modification. To cover such + * case, vIOMMU emulator needs to fetch latest guest pasid + * entry and check cached pasid entry, then update pasid + * cache and send pasid bind/unbind to host properly. + */ + ret =3D vtd_dev_get_pe_from_pasid(vtd_as, pasid, &pe); + if (ret) { + /* + * No valid pasid entry in guest memory. e.g. pasid entry + * was modified to be either all-zero or non-present. Either + * case means existing pasid cache should be removed. + */ + goto remove; + } + + vtd_fill_pe_in_cache(s, vtd_as, &pe); + return false; + +remove: + /* + * TODO: send pasid unbind to host for passthru devices + */ + pc_entry->cache_filled =3D false; + + /* + * Don't remove address space of PCI_NO_PASID which is created by PCI + * sub-system. + */ + if (vtd_as->pasid =3D=3D PCI_NO_PASID) { + return false; + } + return true; +} + +/* + * This function syncs the pasid bindings between guest and host. + * It includes updating the pasid cache in vIOMMU and updating the + * pasid bindings per guest's latest pasid entry presence. + */ +static void vtd_pasid_cache_sync(IntelIOMMUState *s, + VTDPASIDCacheInfo *pc_info) +{ + if (!s->flts || !s->root_scalable || !s->dmar_enabled) { + return; + } + + /* + * Regards to a pasid cache invalidation, e.g. a PSI. + * it could be either cases of below: + * a) a present pasid entry moved to non-present + * b) a present pasid entry to be a present entry + * c) a non-present pasid entry moved to present + * + * Different invalidation granularity may affect different device + * scope and pasid scope. But for each invalidation granularity, + * it needs to do two steps to sync host and guest pasid binding. + * + * Here is the handling of a PSI: + * 1) loop all the existing vtd_as instances to update them + * according to the latest guest pasid entry in pasid table. + * this will make sure affected existing vtd_as instances + * cached the latest pasid entries. Also, during the loop, the + * host should be notified if needed. e.g. pasid unbind or pasid + * update. Should be able to cover case a) and case b). + * + * 2) loop all devices to cover case c) + * - For devices which are backed by HostIOMMUDeviceIOMMUFD instanc= es, + * we loop them and check if guest pasid entry exists. If yes, + * it is case c), we update the pasid cache and also notify + * host. + * - For devices which are not backed by HostIOMMUDeviceIOMMUFD, + * it is not necessary to create pasid cache at this phase since + * it could be created when vIOMMU does DMA address translation. + * This is not yet implemented since there is no emulated + * pasid-capable devices today. If we have such devices in + * future, the pasid cache shall be created there. + * Other granularity follow the same steps, just with different scope + * + */ + + vtd_iommu_lock(s); + /* + * Step 1: loop all the existing vtd_as instances for pasid unbind and + * update. + */ + g_hash_table_foreach_remove(s->vtd_address_spaces, vtd_flush_pasid, + pc_info); + vtd_iommu_unlock(s); + + /* TODO: Step 2: loop all the existing vtd_hiod instances for pasid bi= nd. */ +} + +static bool vtd_process_pasid_desc(IntelIOMMUState *s, + VTDInvDesc *inv_desc) +{ + uint16_t domain_id; + uint32_t pasid; + VTDPASIDCacheInfo pc_info; + uint64_t mask[4] =3D {VTD_INV_DESC_PASIDC_RSVD_VAL0, VTD_INV_DESC_ALL_= ONE, + VTD_INV_DESC_ALL_ONE, VTD_INV_DESC_ALL_ONE}; + + if (!vtd_inv_desc_reserved_check(s, inv_desc, mask, true, + __func__, "pasid cache inv")) { + return false; + } + + domain_id =3D VTD_INV_DESC_PASIDC_DID(inv_desc->val[0]); + pasid =3D VTD_INV_DESC_PASIDC_PASID(inv_desc->val[0]); + + switch (inv_desc->val[0] & VTD_INV_DESC_PASIDC_G) { + case VTD_INV_DESC_PASIDC_DSI: + trace_vtd_pasid_cache_dsi(domain_id); + pc_info.type =3D VTD_PASID_CACHE_DOMSI; + pc_info.domain_id =3D domain_id; + break; + + case VTD_INV_DESC_PASIDC_PASID_SI: + /* PASID selective implies a DID selective */ + trace_vtd_pasid_cache_psi(domain_id, pasid); + pc_info.type =3D VTD_PASID_CACHE_PASIDSI; + pc_info.domain_id =3D domain_id; + pc_info.pasid =3D pasid; + break; + + case VTD_INV_DESC_PASIDC_GLOBAL: + trace_vtd_pasid_cache_gsi(); + pc_info.type =3D VTD_PASID_CACHE_GLOBAL_INV; + break; + + default: + error_report_once("invalid-inv-granu-in-pc_inv_desc hi: 0x%" PRIx64 + " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]); + return false; + } + + vtd_pasid_cache_sync(s, &pc_info); + return true; +} + static bool vtd_process_inv_iec_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) { @@ -3265,6 +3500,13 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s) } break; =20 + case VTD_INV_DESC_PC: + trace_vtd_inv_desc("pasid-cache", inv_desc.val[1], inv_desc.val[0]= ); + if (!vtd_process_pasid_desc(s, &inv_desc)) { + return false; + } + break; + case VTD_INV_DESC_PIOTLB: trace_vtd_inv_desc("p-iotlb", inv_desc.val[1], inv_desc.val[0]); if (!vtd_process_piotlb_desc(s, &inv_desc)) { @@ -3300,16 +3542,6 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s) } break; =20 - /* - * TODO: the entity of below two cases will be implemented in future s= eries. - * To make guest (which integrates scalable mode support patch set in - * iommu driver) work, just return true is enough so far. - */ - case VTD_INV_DESC_PC: - if (s->scalable_mode) { - break; - } - /* fallthrough */ default: error_report_once("%s: invalid inv desc: hi=3D%"PRIx64", lo=3D%"PR= Ix64 " (unknown type)", __func__, inv_desc.hi, diff --git a/hw/i386/trace-events b/hw/i386/trace-events index ac9e1a10aa..ae5bbfcdc0 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -24,6 +24,9 @@ vtd_inv_qi_head(uint16_t head) "read head %d" vtd_inv_qi_tail(uint16_t head) "write tail %d" vtd_inv_qi_fetch(void) "" vtd_context_cache_reset(void) "" +vtd_pasid_cache_gsi(void) "" +vtd_pasid_cache_dsi(uint16_t domain) "Domain selective PC invalidation dom= ain 0x%"PRIx16 +vtd_pasid_cache_psi(uint16_t domain, uint32_t pasid) "PASID selective PC i= nvalidation domain 0x%"PRIx16" pasid 0x%"PRIx32 vtd_re_not_present(uint8_t bus) "Root entry bus %"PRIu8" not present" vtd_ce_not_present(uint8_t bus, uint8_t devfn) "Context entry bus %"PRIu8"= devfn %"PRIu8" not present" vtd_iotlb_page_hit(uint16_t sid, uint64_t addr, uint64_t slpte, uint16_t d= omain) "IOTLB page hit sid 0x%"PRIx16" iova 0x%"PRIx64" slpte 0x%"PRIx64" d= omain 0x%"PRIx16 --=20 2.34.1 From nobody Sat Nov 15 20:49:57 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 21 May 2025 07:19:46 -0400 Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2025 04:19:41 -0700 Received: from spr-s2600bt.bj.intel.com ([10.240.192.127]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2025 04:19:36 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1747826382; x=1779362382; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7C/02Y0xWg8u+erfG+hwC1Iyf+JbU13z43k3tWBekp8=; b=EANShPWXVGtQLwd7m79Y5nKk26FGt2bg64gZaOqO39iUm+ldPbppi09n xtFO1YsOwUj3TVlDhXml5TJCvDbjYjPE18of/NCR+66NL55FqBi14qhK8 zzNiFnN3hbpUHwcNy0aDrXa/MB2gwtBtO/Oioy8fSIbicCoKy63PX1r8C AgDq452lBRncEOZ92V0NSbgSNbXwp+RHxSL59Gu/3gGN/KL0levws9bMZ 2gkKw7PmHazR8uOhzrSscEwJxeJAr+oAPSwpmrtwqhaq9wymPwo/ywDIN RA9jJ81syz4qaae9Hh2i6VmkRB7mU6F32P2qbWpYZ+QVlFSAQw7ZeyTUf Q==; X-CSE-ConnectionGUID: gxkPe4ZSQrectE4al/Wn0A== X-CSE-MsgGUID: q3UE8WP5S0KtYDCPJ9TN3Q== X-IronPort-AV: E=McAfee;i="6700,10204,11439"; a="49895080" X-IronPort-AV: E=Sophos;i="6.15,303,1739865600"; d="scan'208";a="49895080" X-CSE-ConnectionGUID: h53k/JypSzyZdMEC3FpD3Q== X-CSE-MsgGUID: 9wkPi6KmRWCZh2t2lw2WMg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,303,1739865600"; d="scan'208";a="145158362" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Yi Sun , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PATCH rfcv3 13/21] intel_iommu: Handle PASID entry adding Date: Wed, 21 May 2025 19:14:43 +0800 Message-Id: <20250521111452.3316354-14-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250521111452.3316354-1-zhenzhong.duan@intel.com> References: <20250521111452.3316354-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.184, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1747826488322116600 Content-Type: text/plain; charset="utf-8" When guest modifies a PASID entry, QEMU will capture the guest pasid select= ive pasid cache invalidation, allocate or remove a VTDAddressSpace instance per= the invalidation reasons: a) a present pasid entry moved to non-present b) a present pasid entry to be a present entry c) a non-present pasid entry moved to present This handles c). Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 1 + hw/i386/intel_iommu.c | 167 ++++++++++++++++++++++++++++++++- 2 files changed, 167 insertions(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 82b84db80f..4f6d9e9036 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -558,6 +558,7 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_CTX_ENTRY_LEGACY_SIZE 16 #define VTD_CTX_ENTRY_SCALABLE_SIZE 32 =20 +#define VTD_SM_CONTEXT_ENTRY_PDTS(val) (((val) >> 9) & 0x7) #define VTD_SM_CONTEXT_ENTRY_RID2PASID_MASK 0xfffff #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(aw) (0x1e0ULL | ~VTD_HAW_MASK(aw)) #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 0xffffffffffe00000ULL diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 0c6587735e..8d9076216c 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -825,6 +825,11 @@ static inline bool vtd_pe_type_check(IntelIOMMUState *= s, VTDPASIDEntry *pe) } } =20 +static inline uint32_t vtd_sm_ce_get_pdt_entry_num(VTDContextEntry *ce) +{ + return 1U << (VTD_SM_CONTEXT_ENTRY_PDTS(ce->val[0]) + 7); +} + static inline uint16_t vtd_pe_get_did(VTDPASIDEntry *pe) { return VTD_SM_PASID_ENTRY_DID((pe)->val[1]); @@ -3234,6 +3239,157 @@ remove: return true; } =20 +static void vtd_sm_pasid_table_walk_one(IntelIOMMUState *s, + dma_addr_t pt_base, + int start, + int end, + VTDPASIDCacheInfo *info) +{ + VTDPASIDEntry pe; + int pasid =3D start; + int pasid_next; + + while (pasid < end) { + pasid_next =3D pasid + 1; + + if (!vtd_get_pe_in_pasid_leaf_table(s, pasid, pt_base, &pe) + && vtd_pe_present(&pe)) { + int bus_n =3D pci_bus_num(info->bus), devfn =3D info->devfn; + uint16_t sid =3D PCI_BUILD_BDF(bus_n, devfn); + VTDAddressSpace *vtd_as; + + vtd_iommu_lock(s); + /* + * When indexed by rid2pasid, vtd_as should have been created, + * e.g., by PCI subsystem. For other iommu pasid, we need to + * create vtd_as dynamically. The other iommu pasid is same as + * PCI's pasid, so it's used as input of vtd_find_add_as(). + */ + vtd_as =3D vtd_as_from_iommu_pasid_locked(s, sid, pasid); + if (!vtd_as) { + vtd_iommu_unlock(s); + vtd_as =3D vtd_find_add_as(s, info->bus, devfn, pasid); + } + vtd_iommu_unlock(s); + + if ((info->type =3D=3D VTD_PASID_CACHE_DOMSI || + info->type =3D=3D VTD_PASID_CACHE_PASIDSI) && + !(info->domain_id =3D=3D vtd_pe_get_did(&pe))) { + /* + * VTD_PASID_CACHE_DOMSI and VTD_PASID_CACHE_PASIDSI + * requires domain ID check. If domain Id check fail, + * go to next pasid. + */ + pasid =3D pasid_next; + continue; + } + vtd_fill_pe_in_cache(s, vtd_as, &pe); + } + pasid =3D pasid_next; + } +} + +/* + * Currently, VT-d scalable mode pasid table is a two level table, + * this function aims to loop a range of PASIDs in a given pasid + * table to identify the pasid config in guest. + */ +static void vtd_sm_pasid_table_walk(IntelIOMMUState *s, + dma_addr_t pdt_base, + int start, + int end, + VTDPASIDCacheInfo *info) +{ + VTDPASIDDirEntry pdire; + int pasid =3D start; + int pasid_next; + dma_addr_t pt_base; + + while (pasid < end) { + pasid_next =3D ((end - pasid) > VTD_PASID_TBL_ENTRY_NUM) ? + (pasid + VTD_PASID_TBL_ENTRY_NUM) : end; + if (!vtd_get_pdire_from_pdir_table(pdt_base, pasid, &pdire) + && vtd_pdire_present(&pdire)) { + pt_base =3D pdire.val & VTD_PASID_TABLE_BASE_ADDR_MASK; + vtd_sm_pasid_table_walk_one(s, pt_base, pasid, pasid_next, inf= o); + } + pasid =3D pasid_next; + } +} + +static void vtd_replay_pasid_bind_for_dev(IntelIOMMUState *s, + int start, int end, + VTDPASIDCacheInfo *info) +{ + VTDContextEntry ce; + VTDAddressSpace *vtd_as; + + vtd_as =3D vtd_find_add_as(s, info->bus, info->devfn, PCI_NO_PASID); + + if (!vtd_as_to_context_entry(vtd_as, &ce)) { + uint32_t max_pasid; + + max_pasid =3D vtd_sm_ce_get_pdt_entry_num(&ce) * VTD_PASID_TBL_ENT= RY_NUM; + if (end > max_pasid) { + end =3D max_pasid; + } + vtd_sm_pasid_table_walk(s, + VTD_CE_GET_PASID_DIR_TABLE(&ce), + start, + end, + info); + } +} + +/* + * This function replay the guest pasid bindings to hosts by + * walking the guest PASID table. This ensures host will have + * latest guest pasid bindings. + */ +static void vtd_replay_guest_pasid_bindings(IntelIOMMUState *s, + VTDPASIDCacheInfo *pc_info) +{ + VTDHostIOMMUDevice *vtd_hiod; + int start =3D 0, end =3D 1; /* only rid2pasid is supported */ + VTDPASIDCacheInfo walk_info; + GHashTableIter as_it; + + switch (pc_info->type) { + case VTD_PASID_CACHE_PASIDSI: + start =3D pc_info->pasid; + end =3D pc_info->pasid + 1; + /* + * PASID selective invalidation is within domain, + * thus fall through. + */ + case VTD_PASID_CACHE_DOMSI: + case VTD_PASID_CACHE_GLOBAL_INV: + /* loop all assigned devices */ + break; + default: + error_report("invalid pc_info->type for replay"); + abort(); + } + + /* + * In this replay, only needs to care about the devices which + * are backed by host IOMMU. For such devices, their vtd_hiod + * instances are in the s->vtd_host_iommu_dev. For devices which + * are not backed by host IOMMU, it is not necessary to replay + * the bindings since their cache could be re-created in the future + * DMA address translation. Access to vtd_host_iommu_dev is already + * protected by BQL, so no iommu lock needed here. + */ + walk_info =3D *pc_info; + g_hash_table_iter_init(&as_it, s->vtd_host_iommu_dev); + while (g_hash_table_iter_next(&as_it, NULL, (void **)&vtd_hiod)) { + /* bus|devfn fields are not identical with pc_info */ + walk_info.bus =3D vtd_hiod->bus; + walk_info.devfn =3D vtd_hiod->devfn; + vtd_replay_pasid_bind_for_dev(s, start, end, &walk_info); + } +} + /* * This function syncs the pasid bindings between guest and host. * It includes updating the pasid cache in vIOMMU and updating the @@ -3289,7 +3445,16 @@ static void vtd_pasid_cache_sync(IntelIOMMUState *s, pc_info); vtd_iommu_unlock(s); =20 - /* TODO: Step 2: loop all the existing vtd_hiod instances for pasid bi= nd. */ + /* + * Step 2: loop all the existing vtd_hiod instances for pasid bind. + * Ideally, needs to loop all devices to find if there is any new + * PASID binding regards to the PASID cache invalidation request. + * But it is enough to loop the devices which are backed by host + * IOMMU. For devices backed by vIOMMU (a.k.a emulated devices), + * if new PASID happened on them, their vtd_as instance could + * be created during future vIOMMU DMA translation. + */ + vtd_replay_guest_pasid_bindings(s, pc_info); } =20 static bool vtd_process_pasid_desc(IntelIOMMUState *s, --=20 2.34.1 From nobody Sat Nov 15 20:49:57 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1747826443; cv=none; d=zohomail.com; s=zohoarc; b=j8q+Y0C7KGhoCTdy56AEEg7iDQWDWhhClpd3+PJ9BwcmuOFe8EKt2FXR7rVYv5nR3iOyuo22PZSO6yArpmVYpIX731/bhbmY8FQsQbk3qR8KIeUZbAnydC+MgwVzvh/DrCjh5v11NNNr+5QVYJM1GaoIcsHX8a6fhWIOMgNlfeg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747826443; 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bh=3K50eCvsdiQRtVIiYWqzkx8n0RxYaguzz/yR54JEsYE=; b=LBUh7RTm6pB4i7DMpXW+/ZYTPUmnM9GlrSRfcXiCfkiXxj5Wj7CLg9CH aqERSKoqlDH//B/9jUS64MTLnvixjShmfi2xgnLGzaK0SrBRrKHBy1qQY PJZi3EPO7xaThdnHXDWH59Wf5GlPCfHIwhfonhj+XCDcB7D5OhboBcg5T J9c8Y/ggA4QrEXue3wUSa84m6ERFu+tkqZm86z5fgGQ+iny9H04l8rMMG AJ+Im37bCIt51BcVXNnpxyi6MQIYSSGC2lsfm44lydSx6pCzF07cH6pz8 t689lqkSo2J4Lg5cNjTUiSl84dkhZdgylJIr9PyT78CflNSzN8+UV9aZE Q==; X-CSE-ConnectionGUID: OVIXqqlnTryBAWe6H6INzw== X-CSE-MsgGUID: dwShg3QJT9ahlIF3ynHR1g== X-IronPort-AV: E=McAfee;i="6700,10204,11439"; a="49895101" X-IronPort-AV: E=Sophos;i="6.15,303,1739865600"; d="scan'208";a="49895101" X-CSE-ConnectionGUID: T9mGUAHnQfeNSirbFbvS9Q== X-CSE-MsgGUID: p4S455VQQcmL/VIsYmiRmQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,303,1739865600"; d="scan'208";a="145158373" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PATCH rfcv3 14/21] intel_iommu: Introduce a new pasid cache invalidation type FORCE_RESET Date: Wed, 21 May 2025 19:14:44 +0800 Message-Id: <20250521111452.3316354-15-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250521111452.3316354-1-zhenzhong.duan@intel.com> References: <20250521111452.3316354-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.184, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1747826446039116600 Content-Type: text/plain; charset="utf-8" FORCE_RESET is different from GLOBAL_INV which updates pasid cache if underlying pasid entry is still valid, it drops all the pasid caches. FORCE_RESET isn't a VTD spec defined invalidation type for pasid cache, only used internally in system level reset. Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 2 ++ hw/i386/intel_iommu.c | 28 ++++++++++++++++++++++++++++ hw/i386/trace-events | 1 + 3 files changed, 31 insertions(+) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 4f6d9e9036..5e5583d94a 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -564,6 +564,8 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 0xffffffffffe00000ULL =20 typedef enum VTDPCInvType { + /* Force reset all */ + VTD_PASID_CACHE_FORCE_RESET =3D 0, /* pasid cache invalidation rely on guest PASID entry */ VTD_PASID_CACHE_GLOBAL_INV, /* pasid cache global invalidation */ VTD_PASID_CACHE_DOMSI, /* pasid cache domain selective invalidati= on */ diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 8d9076216c..050b0d3ca2 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -86,6 +86,8 @@ struct vtd_iotlb_key { static void vtd_address_space_refresh_all(IntelIOMMUState *s); static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n); =20 +static void vtd_pasid_cache_reset_locked(IntelIOMMUState *s); + static void vtd_panic_require_caching_mode(void) { error_report("We need to set caching-mode=3Don for intel-iommu to enab= le " @@ -390,6 +392,7 @@ static void vtd_reset_caches(IntelIOMMUState *s) vtd_iommu_lock(s); vtd_reset_iotlb_locked(s); vtd_reset_context_cache_locked(s); + vtd_pasid_cache_reset_locked(s); vtd_iommu_unlock(s); } =20 @@ -3186,6 +3189,8 @@ static gboolean vtd_flush_pasid(gpointer key, gpointe= r value, } =20 switch (pc_info->type) { + case VTD_PASID_CACHE_FORCE_RESET: + goto remove; case VTD_PASID_CACHE_PASIDSI: if (pc_info->pasid !=3D pasid) { return false; @@ -3239,6 +3244,26 @@ remove: return true; } =20 +/* Caller of this function should hold iommu_lock */ +static void vtd_pasid_cache_reset_locked(IntelIOMMUState *s) +{ + VTDPASIDCacheInfo pc_info; + + trace_vtd_pasid_cache_reset(); + + pc_info.type =3D VTD_PASID_CACHE_FORCE_RESET; + + /* + * Reset pasid cache is a big hammer, so use g_hash_table_foreach_remo= ve + * which will free the vtd_as instances. Also, as a big hammer, use + * VTD_PASID_CACHE_FORCE_RESET to ensure all the vtd_as instances are + * dropped, meanwhile the change will be passed to host if + * HostIOMMUDeviceIOMMUFD is available. + */ + g_hash_table_foreach_remove(s->vtd_address_spaces, + vtd_flush_pasid, &pc_info); +} + static void vtd_sm_pasid_table_walk_one(IntelIOMMUState *s, dma_addr_t pt_base, int start, @@ -3366,6 +3391,9 @@ static void vtd_replay_guest_pasid_bindings(IntelIOMM= UState *s, case VTD_PASID_CACHE_GLOBAL_INV: /* loop all assigned devices */ break; + case VTD_PASID_CACHE_FORCE_RESET: + /* For force reset, no need to go further replay */ + return; default: error_report("invalid pc_info->type for replay"); abort(); diff --git a/hw/i386/trace-events b/hw/i386/trace-events index ae5bbfcdc0..c8a936eb46 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -24,6 +24,7 @@ vtd_inv_qi_head(uint16_t head) "read head %d" vtd_inv_qi_tail(uint16_t head) "write tail %d" vtd_inv_qi_fetch(void) "" vtd_context_cache_reset(void) "" +vtd_pasid_cache_reset(void) "" vtd_pasid_cache_gsi(void) "" vtd_pasid_cache_dsi(uint16_t domain) "Domain selective PC invalidation dom= ain 0x%"PRIx16 vtd_pasid_cache_psi(uint16_t domain, uint32_t pasid) "PASID selective PC i= nvalidation domain 0x%"PRIx16" pasid 0x%"PRIx32 --=20 2.34.1 From nobody Sat Nov 15 20:49:57 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 21 May 2025 07:19:57 -0400 Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2025 04:19:51 -0700 Received: from spr-s2600bt.bj.intel.com ([10.240.192.127]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2025 04:19:46 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1747826393; x=1779362393; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sXZ6OEWV04h2UJjK9eSsqUQ5F7LVbkWCqsynpoB7PSg=; b=GSytVbaGBPAldNQMYgq5uq0SjKMFjrvJsrwuDArDi15CTyGWHzLnnnIv 1F6UxxiJNK7h0qrlxyKBZEHjaSiBeX8vgHOwKl3XrJPwZPvt/ev14yYd5 X9gNC9t61JHmePYUJkuAnmKlWECpXkrMkKbItkJJ5V6HtQsuq0Eb5e+CC HU1VledHPDDk6rRua9JRs7xaB4Og+SMtVzkwTfWDsTM5x19Z4AxezRFC/ Q+m8WBwolZdd1MaouXSC98rDMlVLreZmDS5yh5zy09dk7Rk44Ig7a1WYv 1M3GU5R6ZqoaBHNJRfQCaNs5SluC5YB3wxunPSJQSdzwT6j6g+Xh8s34F A==; X-CSE-ConnectionGUID: Rk9ld50USySF4ONharZe6Q== X-CSE-MsgGUID: una9/+GgRVyLYJ91F+ih2Q== X-IronPort-AV: E=McAfee;i="6700,10204,11439"; a="49895113" X-IronPort-AV: E=Sophos;i="6.15,303,1739865600"; d="scan'208";a="49895113" X-CSE-ConnectionGUID: BK/3hzV7QKuqgcm9FlhsAQ== X-CSE-MsgGUID: OtNAd79NQrKYx7prPxR8ww== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,303,1739865600"; d="scan'208";a="145158382" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Yi Sun , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PATCH rfcv3 15/21] intel_iommu: Bind/unbind guest page table to host Date: Wed, 21 May 2025 19:14:45 +0800 Message-Id: <20250521111452.3316354-16-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250521111452.3316354-1-zhenzhong.duan@intel.com> References: <20250521111452.3316354-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.184, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1747826512710116600 Content-Type: text/plain; charset="utf-8" This captures the guest PASID table entry modifications and propagates the changes to host to attach a hwpt with type determined per guest PGTT configuration. When PGTT is Pass-through(100b), the hwpt on host side is a stage-2 page table(GPA->HPA). When PGTT is First-stage Translation only(001b), the hwpt on host side is a nested page table. The guest page table is configured as stage-1 page table (gIOVA->GPA) whose translation result would further go through host VT-d stage-2 page table(GPA->HPA) under nested translation mode. This is the key to support gIOVA over stage-1 page table for Intel VT-d in virtualization environment. Stage-2 page table could be shared by different devices if there is no conflict and devices link to same iommufd object, i.e. devices under same host IOMMU can share same stage-2 page table. If there is conflict, i.e. there is one device under non cache coherency mode which is different from others, it requires a separate stage-2 page table in non-CC mode. See below example diagram: IntelIOMMUState | V .------------------. .------------------. | VTDIOASContainer |--->| VTDIOASContainer |--->... | (iommufd0) | | (iommufd1) | .------------------. .------------------. | | | .-->... V .-------------------. .-------------------. | VTDS2Hwpt(CC) |--->| VTDS2Hwpt(non-CC) |-->... .-------------------. .-------------------. | | | | | | .-----------. .-----------. .------------. | IOMMUFD | | IOMMUFD | | IOMMUFD | | Device(CC)| | Device(CC)| | Device | | (iommufd0)| | (iommufd0)| | (non-CC) | | | | | | (iommufd0) | .-----------. .-----------. .------------. Co-Authored-by: Yi Liu Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 11 + include/hw/i386/intel_iommu.h | 24 ++ hw/i386/intel_iommu.c | 581 +++++++++++++++++++++++++++++++-- hw/i386/trace-events | 8 + 4 files changed, 604 insertions(+), 20 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 5e5583d94a..e76f43bb8f 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -563,6 +563,13 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(aw) (0x1e0ULL | ~VTD_HAW_MASK(aw)) #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 0xffffffffffe00000ULL =20 +typedef enum VTDPASIDOp { + VTD_PASID_BIND, + VTD_PASID_UPDATE, + VTD_PASID_UNBIND, + VTD_OP_NUM +} VTDPASIDOp; + typedef enum VTDPCInvType { /* Force reset all */ VTD_PASID_CACHE_FORCE_RESET =3D 0, @@ -578,6 +585,7 @@ typedef struct VTDPASIDCacheInfo { uint32_t pasid; PCIBus *bus; uint16_t devfn; + bool error_happened; } VTDPASIDCacheInfo; =20 /* PASID Table Related Definitions */ @@ -606,6 +614,9 @@ typedef struct VTDPASIDCacheInfo { =20 #define VTD_SM_PASID_ENTRY_FLPM 3ULL #define VTD_SM_PASID_ENTRY_FLPTPTR (~0xfffULL) +#define VTD_SM_PASID_ENTRY_SRE_BIT(val) (!!((val) & 1ULL)) +#define VTD_SM_PASID_ENTRY_WPE_BIT(val) (!!(((val) >> 4) & 1ULL)) +#define VTD_SM_PASID_ENTRY_EAFE_BIT(val) (!!(((val) >> 7) & 1ULL)) =20 /* First Level Paging Structure */ /* Masks for First Level Paging Entry */ diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index fbc9da903a..594281c1d3 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -100,10 +100,32 @@ typedef struct VTDPASIDCacheEntry { bool cache_filled; } VTDPASIDCacheEntry; =20 +typedef struct VTDIOASContainer { + struct IOMMUFDBackend *iommufd; + uint32_t ioas_id; + MemoryListener listener; + QLIST_HEAD(, VTDS2Hwpt) s2_hwpt_list; + QLIST_ENTRY(VTDIOASContainer) next; + Error *error; +} VTDIOASContainer; + +typedef struct VTDS2Hwpt { + uint32_t users; + uint32_t hwpt_id; + VTDIOASContainer *container; + QLIST_ENTRY(VTDS2Hwpt) next; +} VTDS2Hwpt; + +typedef struct VTDHwpt { + uint32_t hwpt_id; + VTDS2Hwpt *s2_hwpt; +} VTDHwpt; + struct VTDAddressSpace { PCIBus *bus; uint8_t devfn; uint32_t pasid; + VTDHwpt hwpt; AddressSpace as; IOMMUMemoryRegion iommu; MemoryRegion root; /* The root container of the device */ @@ -303,6 +325,8 @@ struct IntelIOMMUState { =20 GHashTable *vtd_host_iommu_dev; /* VTDHostIOMMUDevice */ =20 + QLIST_HEAD(, VTDIOASContainer) containers; + /* interrupt remapping */ bool intr_enabled; /* Whether guest enabled IR */ dma_addr_t intr_root; /* Interrupt remapping table pointer */ diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 050b0d3ca2..3269a66ac7 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -20,6 +20,7 @@ */ =20 #include "qemu/osdep.h" +#include CONFIG_DEVICES /* CONFIG_IOMMUFD */ #include "qemu/error-report.h" #include "qemu/main-loop.h" #include "qapi/error.h" @@ -40,6 +41,9 @@ #include "migration/vmstate.h" #include "trace.h" #include "system/iommufd.h" +#ifdef CONFIG_IOMMUFD +#include +#endif =20 /* context entry operations */ #define VTD_CE_GET_RID2PASID(ce) \ @@ -838,11 +842,40 @@ static inline uint16_t vtd_pe_get_did(VTDPASIDEntry *= pe) return VTD_SM_PASID_ENTRY_DID((pe)->val[1]); } =20 +static inline dma_addr_t vtd_pe_get_flpt_base(VTDPASIDEntry *pe) +{ + return pe->val[2] & VTD_SM_PASID_ENTRY_FLPTPTR; +} + +static inline uint32_t vtd_pe_get_fl_aw(VTDPASIDEntry *pe) +{ + return 48 + ((pe->val[2] >> 2) & VTD_SM_PASID_ENTRY_FLPM) * 9; +} + +static inline bool vtd_pe_pgtt_is_pt(VTDPASIDEntry *pe) +{ + return (VTD_PE_GET_TYPE(pe) =3D=3D VTD_SM_PASID_ENTRY_PT); +} + +/* check if pgtt is first stage translation */ +static inline bool vtd_pe_pgtt_is_flt(VTDPASIDEntry *pe) +{ + return (VTD_PE_GET_TYPE(pe) =3D=3D VTD_SM_PASID_ENTRY_FLT); +} + static inline bool vtd_pdire_present(VTDPASIDDirEntry *pdire) { return pdire->val & 1; } =20 +static inline void pasid_cache_info_set_error(VTDPASIDCacheInfo *pc_info) +{ + if (pc_info->error_happened) { + return; + } + pc_info->error_happened =3D true; +} + /** * Caller of this function should check present bit if wants * to use pdir entry for further usage except for fpd bit check. @@ -1776,7 +1809,7 @@ static bool vtd_dev_pt_enabled(IntelIOMMUState *s, VT= DContextEntry *ce, */ return false; } - return (VTD_PE_GET_TYPE(&pe) =3D=3D VTD_SM_PASID_ENTRY_PT); + return vtd_pe_pgtt_is_pt(&pe); } =20 return (vtd_ce_get_type(ce) =3D=3D VTD_CONTEXT_TT_PASS_THROUGH); @@ -2403,6 +2436,497 @@ static void vtd_context_global_invalidate(IntelIOMM= UState *s) vtd_iommu_replay_all(s); } =20 +#ifdef CONFIG_IOMMUFD +static bool iommufd_listener_skipped_section(MemoryRegionSection *section) +{ + return !memory_region_is_ram(section->mr) || + memory_region_is_protected(section->mr) || + /* + * Sizing an enabled 64-bit BAR can cause spurious mappings to + * addresses in the upper part of the 64-bit address space. Th= ese + * are never accessed by the CPU and beyond the address width of + * some IOMMU hardware. TODO: VFIO should tell us the IOMMU wi= dth. + */ + section->offset_within_address_space & (1ULL << 63); +} + +static void iommufd_listener_region_add_s2domain(MemoryListener *listener, + MemoryRegionSection *sect= ion) +{ + VTDIOASContainer *container =3D container_of(listener, + VTDIOASContainer, listener); + IOMMUFDBackend *iommufd =3D container->iommufd; + uint32_t ioas_id =3D container->ioas_id; + hwaddr iova; + Int128 llend, llsize; + void *vaddr; + Error *err =3D NULL; + int ret; + + if (iommufd_listener_skipped_section(section)) { + return; + } + iova =3D REAL_HOST_PAGE_ALIGN(section->offset_within_address_space); + llend =3D int128_make64(section->offset_within_address_space); + llend =3D int128_add(llend, section->size); + llend =3D int128_and(llend, int128_exts64(qemu_real_host_page_mask())); + llsize =3D int128_sub(llend, int128_make64(iova)); + vaddr =3D memory_region_get_ram_ptr(section->mr) + + section->offset_within_region + + (iova - section->offset_within_address_space); + + memory_region_ref(section->mr); + + ret =3D iommufd_backend_map_dma(iommufd, ioas_id, iova, int128_get64(l= lsize), + vaddr, section->readonly); + if (!ret) { + return; + } + + error_setg(&err, + "iommufd_listener_region_add_s2domain(%p, 0x%"HWADDR_PRIx",= " + "0x%"HWADDR_PRIx", %p) =3D %d (%s)", + container, iova, int128_get64(llsize), vaddr, ret, + strerror(-ret)); + + if (memory_region_is_ram_device(section->mr)) { + /* Allow unexpected mappings not to be fatal for RAM devices */ + error_report_err(err); + return; + } + + if (!container->error) { + error_propagate_prepend(&container->error, err, "Region %s: ", + memory_region_name(section->mr)); + } else { + error_free(err); + } +} + +static void iommufd_listener_region_del_s2domain(MemoryListener *listener, + MemoryRegionSection *sect= ion) +{ + VTDIOASContainer *container =3D container_of(listener, + VTDIOASContainer, listener); + IOMMUFDBackend *iommufd =3D container->iommufd; + uint32_t ioas_id =3D container->ioas_id; + hwaddr iova; + Int128 llend, llsize; + int ret; + + if (iommufd_listener_skipped_section(section)) { + return; + } + iova =3D REAL_HOST_PAGE_ALIGN(section->offset_within_address_space); + llend =3D int128_make64(section->offset_within_address_space); + llend =3D int128_add(llend, section->size); + llend =3D int128_and(llend, int128_exts64(qemu_real_host_page_mask())); + llsize =3D int128_sub(llend, int128_make64(iova)); + + ret =3D iommufd_backend_unmap_dma(iommufd, ioas_id, + iova, int128_get64(llsize)); + if (ret) { + error_report("iommufd_listener_region_del_s2domain(%p, " + "0x%"HWADDR_PRIx", 0x%"HWADDR_PRIx") =3D %d (%s)", + container, iova, int128_get64(llsize), ret, + strerror(-ret)); + } + + memory_region_unref(section->mr); +} + +static const MemoryListener iommufd_s2domain_memory_listener =3D { + .name =3D "iommufd_s2domain", + .priority =3D 1000, + .region_add =3D iommufd_listener_region_add_s2domain, + .region_del =3D iommufd_listener_region_del_s2domain, +}; + +static void vtd_init_s1_hwpt_data(struct iommu_hwpt_vtd_s1 *vtd, + VTDPASIDEntry *pe) +{ + memset(vtd, 0, sizeof(*vtd)); + + vtd->flags =3D (VTD_SM_PASID_ENTRY_SRE_BIT(pe->val[2]) ? + IOMMU_VTD_S1_SRE : 0) | + (VTD_SM_PASID_ENTRY_WPE_BIT(pe->val[2]) ? + IOMMU_VTD_S1_WPE : 0) | + (VTD_SM_PASID_ENTRY_EAFE_BIT(pe->val[2]) ? + IOMMU_VTD_S1_EAFE : 0); + vtd->addr_width =3D vtd_pe_get_fl_aw(pe); + vtd->pgtbl_addr =3D (uint64_t)vtd_pe_get_flpt_base(pe); +} + +static int vtd_create_s1_hwpt(HostIOMMUDeviceIOMMUFD *idev, + VTDS2Hwpt *s2_hwpt, VTDHwpt *hwpt, + VTDPASIDEntry *pe, Error **errp) +{ + struct iommu_hwpt_vtd_s1 vtd; + uint32_t hwpt_id, s2_hwpt_id =3D s2_hwpt->hwpt_id; + + vtd_init_s1_hwpt_data(&vtd, pe); + + if (!iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, + s2_hwpt_id, 0, IOMMU_HWPT_DATA_VTD_S1, + sizeof(vtd), &vtd, &hwpt_id, errp)) { + return -EINVAL; + } + + hwpt->hwpt_id =3D hwpt_id; + + return 0; +} + +static void vtd_destroy_s1_hwpt(HostIOMMUDeviceIOMMUFD *idev, VTDHwpt *hwp= t) +{ + iommufd_backend_free_id(idev->iommufd, hwpt->hwpt_id); +} + +static VTDS2Hwpt *vtd_ioas_container_get_s2_hwpt(VTDIOASContainer *contain= er, + uint32_t hwpt_id) +{ + VTDS2Hwpt *s2_hwpt; + + QLIST_FOREACH(s2_hwpt, &container->s2_hwpt_list, next) { + if (s2_hwpt->hwpt_id =3D=3D hwpt_id) { + return s2_hwpt; + } + } + + s2_hwpt =3D g_malloc0(sizeof(*s2_hwpt)); + + s2_hwpt->hwpt_id =3D hwpt_id; + s2_hwpt->container =3D container; + QLIST_INSERT_HEAD(&container->s2_hwpt_list, s2_hwpt, next); + + return s2_hwpt; +} + +static void vtd_ioas_container_put_s2_hwpt(VTDS2Hwpt *s2_hwpt) +{ + VTDIOASContainer *container =3D s2_hwpt->container; + + if (s2_hwpt->users) { + return; + } + + QLIST_REMOVE(s2_hwpt, next); + iommufd_backend_free_id(container->iommufd, s2_hwpt->hwpt_id); + g_free(s2_hwpt); +} + +static void vtd_ioas_container_destroy(VTDIOASContainer *container) +{ + if (!QLIST_EMPTY(&container->s2_hwpt_list)) { + return; + } + + QLIST_REMOVE(container, next); + memory_listener_unregister(&container->listener); + iommufd_backend_free_id(container->iommufd, container->ioas_id); + g_free(container); +} + +static int vtd_device_attach_hwpt(VTDHostIOMMUDevice *vtd_hiod, + uint32_t pasid, VTDPASIDEntry *pe, + VTDS2Hwpt *s2_hwpt, VTDHwpt *hwpt, + Error **errp) +{ + HostIOMMUDeviceIOMMUFD *idev =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->h= iod); + int ret; + + if (vtd_pe_pgtt_is_flt(pe)) { + ret =3D vtd_create_s1_hwpt(idev, s2_hwpt, hwpt, pe, errp); + if (ret) { + return ret; + } + } else { + hwpt->hwpt_id =3D s2_hwpt->hwpt_id; + } + + ret =3D !host_iommu_device_iommufd_attach_hwpt(idev, hwpt->hwpt_id, er= rp); + trace_vtd_device_attach_hwpt(idev->devid, pasid, hwpt->hwpt_id, ret); + if (ret) { + if (vtd_pe_pgtt_is_flt(pe)) { + vtd_destroy_s1_hwpt(idev, hwpt); + } + hwpt->hwpt_id =3D 0; + error_report("devid %d pasid %d failed to attach hwpt %d", + idev->devid, pasid, hwpt->hwpt_id); + return ret; + } + + s2_hwpt->users++; + hwpt->s2_hwpt =3D s2_hwpt; + + return 0; +} + +static void vtd_device_detach_hwpt(VTDHostIOMMUDevice *vtd_hiod, + uint32_t pasid, VTDPASIDEntry *pe, + VTDHwpt *hwpt, Error **errp) +{ + HostIOMMUDeviceIOMMUFD *idev =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->h= iod); + int ret; + + if (vtd_hiod->iommu_state->dmar_enabled) { + ret =3D !host_iommu_device_iommufd_detach_hwpt(idev, errp); + trace_vtd_device_detach_hwpt(idev->devid, pasid, ret); + } else { + ret =3D !host_iommu_device_iommufd_attach_hwpt(idev, idev->hwpt_id= , errp); + trace_vtd_device_reattach_def_hwpt(idev->devid, pasid, idev->hwpt_= id, + ret); + } + + if (ret) { + error_report("devid %d pasid %d failed to attach hwpt %d", + idev->devid, pasid, hwpt->hwpt_id); + } + + if (vtd_pe_pgtt_is_flt(pe)) { + vtd_destroy_s1_hwpt(idev, hwpt); + } + + hwpt->s2_hwpt->users--; + hwpt->s2_hwpt =3D NULL; + hwpt->hwpt_id =3D 0; +} + +static int vtd_device_attach_container(VTDHostIOMMUDevice *vtd_hiod, + VTDIOASContainer *container, + uint32_t pasid, VTDPASIDEntry *pe, + VTDHwpt *hwpt, Error **errp) +{ + HostIOMMUDeviceIOMMUFD *idev =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->h= iod); + IOMMUFDBackend *iommufd =3D idev->iommufd; + VTDS2Hwpt *s2_hwpt; + uint32_t s2_hwpt_id; + Error *err =3D NULL; + int ret; + + /* try to attach to an existing hwpt in this container */ + QLIST_FOREACH(s2_hwpt, &container->s2_hwpt_list, next) { + ret =3D vtd_device_attach_hwpt(vtd_hiod, pasid, pe, s2_hwpt, hwpt,= &err); + if (ret) { + const char *msg =3D error_get_pretty(err); + + trace_vtd_device_fail_attach_existing_hwpt(msg); + error_free(err); + err =3D NULL; + } else { + goto found_hwpt; + } + } + + if (!iommufd_backend_alloc_hwpt(iommufd, idev->devid, container->ioas_= id, + IOMMU_HWPT_ALLOC_NEST_PARENT, + IOMMU_HWPT_DATA_NONE, 0, NULL, + &s2_hwpt_id, errp)) { + return -EINVAL; + } + + s2_hwpt =3D vtd_ioas_container_get_s2_hwpt(container, s2_hwpt_id); + + /* Attach vtd device to a new allocated hwpt within iommufd */ + ret =3D vtd_device_attach_hwpt(vtd_hiod, pasid, pe, s2_hwpt, hwpt, err= p); + if (ret) { + goto err_attach_hwpt; + } + +found_hwpt: + trace_vtd_device_attach_container(iommufd->fd, idev->devid, pasid, + container->ioas_id, hwpt->hwpt_id); + return 0; + +err_attach_hwpt: + vtd_ioas_container_put_s2_hwpt(s2_hwpt); + return ret; +} + +static void vtd_device_detach_container(VTDHostIOMMUDevice *vtd_hiod, + uint32_t pasid, VTDPASIDEntry *pe, + VTDHwpt *hwpt, Error **errp) +{ + HostIOMMUDeviceIOMMUFD *idev =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->h= iod); + IOMMUFDBackend *iommufd =3D idev->iommufd; + VTDS2Hwpt *s2_hwpt =3D hwpt->s2_hwpt; + + trace_vtd_device_detach_container(iommufd->fd, idev->devid, pasid); + vtd_device_detach_hwpt(vtd_hiod, pasid, pe, hwpt, errp); + vtd_ioas_container_put_s2_hwpt(s2_hwpt); +} + +static int vtd_device_attach_iommufd(VTDHostIOMMUDevice *vtd_hiod, + uint32_t pasid, VTDPASIDEntry *pe, + VTDHwpt *hwpt, Error **errp) +{ + HostIOMMUDeviceIOMMUFD *idev =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->h= iod); + IOMMUFDBackend *iommufd =3D idev->iommufd; + IntelIOMMUState *s =3D vtd_hiod->iommu_state; + VTDIOASContainer *container; + Error *err =3D NULL; + uint32_t ioas_id; + int ret; + + /* try to attach to an existing container in this space */ + QLIST_FOREACH(container, &s->containers, next) { + if (container->iommufd !=3D iommufd) { + continue; + } + + if (vtd_device_attach_container(vtd_hiod, container, pasid, pe, hw= pt, + &err)) { + const char *msg =3D error_get_pretty(err); + + trace_vtd_device_fail_attach_existing_container(msg); + error_free(err); + err =3D NULL; + } else { + return 0; + } + } + + /* Need to allocate a new dedicated container */ + ret =3D iommufd_backend_alloc_ioas(iommufd, &ioas_id, errp); + if (ret < 0) { + return ret; + } + + trace_vtd_device_alloc_ioas(iommufd->fd, ioas_id); + + container =3D g_malloc0(sizeof(*container)); + container->iommufd =3D iommufd; + container->ioas_id =3D ioas_id; + QLIST_INIT(&container->s2_hwpt_list); + + if (vtd_device_attach_container(vtd_hiod, container, pasid, pe, hwpt, + errp)) { + goto err_attach_container; + } + + container->listener =3D iommufd_s2domain_memory_listener; + memory_listener_register(&container->listener, &address_space_memory); + + if (container->error) { + ret =3D -1; + error_propagate_prepend(errp, container->error, + "memory listener initialization failed: "); + goto err_listener_register; + } + + QLIST_INSERT_HEAD(&s->containers, container, next); + + return 0; + +err_listener_register: + vtd_device_detach_container(vtd_hiod, pasid, pe, hwpt, errp); +err_attach_container: + iommufd_backend_free_id(iommufd, container->ioas_id); + g_free(container); + return ret; +} + +static void vtd_device_detach_iommufd(VTDHostIOMMUDevice *vtd_hiod, + uint32_t pasid, VTDPASIDEntry *pe, + VTDHwpt *hwpt, Error **errp) +{ + VTDIOASContainer *container =3D hwpt->s2_hwpt->container; + + vtd_device_detach_container(vtd_hiod, pasid, pe, hwpt, errp); + vtd_ioas_container_destroy(container); +} + +static int vtd_device_attach_pgtbl(VTDHostIOMMUDevice *vtd_hiod, + VTDAddressSpace *vtd_as, VTDPASIDEntry = *pe) +{ + /* + * If pe->gptt !=3D FLT, should be go ahead to do bind as host only + * accepts guest FLT under nesting. If pe->pgtt=3D=3DPT, should setup + * the pasid with GPA page table. Otherwise should return failure. + */ + if (!vtd_pe_pgtt_is_flt(pe) && !vtd_pe_pgtt_is_pt(pe)) { + return -EINVAL; + } + + /* Should fail if the FLPT base is 0 */ + if (vtd_pe_pgtt_is_flt(pe) && !vtd_pe_get_flpt_base(pe)) { + return -EINVAL; + } + + return vtd_device_attach_iommufd(vtd_hiod, vtd_as->pasid, pe, + &vtd_as->hwpt, &error_abort); +} + +static int vtd_device_detach_pgtbl(VTDHostIOMMUDevice *vtd_hiod, + VTDAddressSpace *vtd_as) +{ + VTDPASIDEntry *cached_pe =3D vtd_as->pasid_cache_entry.cache_filled ? + &vtd_as->pasid_cache_entry.pasid_entry : NULL; + + if (!cached_pe || + (!vtd_pe_pgtt_is_flt(cached_pe) && !vtd_pe_pgtt_is_pt(cached_pe)))= { + return 0; + } + + vtd_device_detach_iommufd(vtd_hiod, vtd_as->pasid, cached_pe, + &vtd_as->hwpt, &error_abort); + + return 0; +} + +/** + * Caller should hold iommu_lock. + */ +static int vtd_bind_guest_pasid(VTDAddressSpace *vtd_as, + VTDPASIDEntry *pe, VTDPASIDOp op) +{ + IntelIOMMUState *s =3D vtd_as->iommu_state; + VTDHostIOMMUDevice *vtd_hiod; + int devfn =3D vtd_as->devfn; + int ret =3D -EINVAL; + struct vtd_as_key key =3D { + .bus =3D vtd_as->bus, + .devfn =3D devfn, + }; + + vtd_hiod =3D g_hash_table_lookup(s->vtd_host_iommu_dev, &key); + if (!vtd_hiod || !vtd_hiod->hiod) { + /* means no need to go further, e.g. for emulated devices */ + return 0; + } + + if (vtd_as->pasid !=3D PCI_NO_PASID) { + error_report("Non-rid_pasid %d not supported yet", vtd_as->pasid); + return ret; + } + + switch (op) { + case VTD_PASID_UPDATE: + case VTD_PASID_BIND: + { + ret =3D vtd_device_attach_pgtbl(vtd_hiod, vtd_as, pe); + break; + } + case VTD_PASID_UNBIND: + { + ret =3D vtd_device_detach_pgtbl(vtd_hiod, vtd_as); + break; + } + default: + error_report_once("Unknown VTDPASIDOp!!!\n"); + break; + } + + return ret; +} +#else +static int vtd_bind_guest_pasid(VTDAddressSpace *vtd_as, + VTDPASIDEntry *pe, VTDPASIDOp op) +{ + return 0; +} +#endif + /* Do a context-cache device-selective invalidation. * @func_mask: FM field after shifting */ @@ -3145,21 +3669,27 @@ static bool vtd_pasid_entry_compare(VTDPASIDEntry *= p1, VTDPASIDEntry *p2) * This function fills in the pasid entry in &vtd_as. Caller * of this function should hold iommu_lock. */ -static void vtd_fill_pe_in_cache(IntelIOMMUState *s, VTDAddressSpace *vtd_= as, - VTDPASIDEntry *pe) +static int vtd_fill_pe_in_cache(IntelIOMMUState *s, VTDAddressSpace *vtd_a= s, + VTDPASIDEntry *pe) { VTDPASIDCacheEntry *pc_entry =3D &vtd_as->pasid_cache_entry; + int ret; =20 - if (vtd_pasid_entry_compare(pe, &pc_entry->pasid_entry)) { - /* No need to go further as cached pasid entry is latest */ - return; + if (pc_entry->cache_filled) { + if (vtd_pasid_entry_compare(pe, &pc_entry->pasid_entry)) { + /* No need to go further as cached pasid entry is latest */ + return 0; + } + ret =3D vtd_bind_guest_pasid(vtd_as, pe, VTD_PASID_UPDATE); + } else { + ret =3D vtd_bind_guest_pasid(vtd_as, pe, VTD_PASID_BIND); } =20 - pc_entry->pasid_entry =3D *pe; - pc_entry->cache_filled =3D true; - /* - * TODO: send pasid bind to host for passthru devices - */ + if (!ret) { + pc_entry->pasid_entry =3D *pe; + pc_entry->cache_filled =3D true; + } + return ret; } =20 /* @@ -3225,14 +3755,20 @@ static gboolean vtd_flush_pasid(gpointer key, gpoin= ter value, goto remove; } =20 - vtd_fill_pe_in_cache(s, vtd_as, &pe); + if (vtd_fill_pe_in_cache(s, vtd_as, &pe)) { + pasid_cache_info_set_error(pc_info); + } return false; =20 remove: - /* - * TODO: send pasid unbind to host for passthru devices - */ - pc_entry->cache_filled =3D false; + if (pc_entry->cache_filled) { + if (vtd_bind_guest_pasid(vtd_as, NULL, VTD_PASID_UNBIND)) { + pasid_cache_info_set_error(pc_info); + return false; + } else { + pc_entry->cache_filled =3D false; + } + } =20 /* * Don't remove address space of PCI_NO_PASID which is created by PCI @@ -3247,7 +3783,7 @@ remove: /* Caller of this function should hold iommu_lock */ static void vtd_pasid_cache_reset_locked(IntelIOMMUState *s) { - VTDPASIDCacheInfo pc_info; + VTDPASIDCacheInfo pc_info =3D { .error_happened =3D false, }; =20 trace_vtd_pasid_cache_reset(); =20 @@ -3308,7 +3844,9 @@ static void vtd_sm_pasid_table_walk_one(IntelIOMMUSta= te *s, pasid =3D pasid_next; continue; } - vtd_fill_pe_in_cache(s, vtd_as, &pe); + if (vtd_fill_pe_in_cache(s, vtd_as, &pe)) { + pasid_cache_info_set_error(info); + } } pasid =3D pasid_next; } @@ -3416,6 +3954,9 @@ static void vtd_replay_guest_pasid_bindings(IntelIOMM= UState *s, walk_info.devfn =3D vtd_hiod->devfn; vtd_replay_pasid_bind_for_dev(s, start, end, &walk_info); } + if (walk_info.error_happened) { + pasid_cache_info_set_error(pc_info); + } } =20 /* @@ -3488,9 +4029,9 @@ static void vtd_pasid_cache_sync(IntelIOMMUState *s, static bool vtd_process_pasid_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) { + VTDPASIDCacheInfo pc_info =3D { .error_happened =3D false, }; uint16_t domain_id; uint32_t pasid; - VTDPASIDCacheInfo pc_info; uint64_t mask[4] =3D {VTD_INV_DESC_PASIDC_RSVD_VAL0, VTD_INV_DESC_ALL_= ONE, VTD_INV_DESC_ALL_ONE, VTD_INV_DESC_ALL_ONE}; =20 @@ -3529,7 +4070,7 @@ static bool vtd_process_pasid_desc(IntelIOMMUState *s, } =20 vtd_pasid_cache_sync(s, &pc_info); - return true; + return !pc_info.error_happened ? true : false; } =20 static bool vtd_process_inv_iec_desc(IntelIOMMUState *s, diff --git a/hw/i386/trace-events b/hw/i386/trace-events index c8a936eb46..de903a0033 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -73,6 +73,14 @@ vtd_warn_invalid_qi_tail(uint16_t tail) "tail 0x%"PRIx16 vtd_warn_ir_vector(uint16_t sid, int index, int vec, int target) "sid 0x%"= PRIx16" index %d vec %d (should be: %d)" vtd_warn_ir_trigger(uint16_t sid, int index, int trig, int target) "sid 0x= %"PRIx16" index %d trigger %d (should be: %d)" vtd_reset_exit(void) "" +vtd_device_attach_hwpt(uint32_t dev_id, uint32_t pasid, uint32_t hwpt_id, = int ret) "dev_id %d pasid %d hwpt_id %d, ret: %d" +vtd_device_detach_hwpt(uint32_t dev_id, uint32_t pasid, int ret) "dev_id %= d pasid %d ret: %d" +vtd_device_reattach_def_hwpt(uint32_t dev_id, uint32_t pasid, uint32_t hwp= t_id, int ret) "dev_id %d pasid %d hwpt_id %d, ret: %d" +vtd_device_fail_attach_existing_hwpt(const char *msg) " %s" +vtd_device_attach_container(int fd, uint32_t dev_id, uint32_t pasid, uint3= 2_t ioas_id, uint32_t hwpt_id) "iommufd %d dev_id %d pasid %d ioas_id %d hw= pt_id %d" +vtd_device_detach_container(int fd, uint32_t dev_id, uint32_t pasid) "iomm= ufd %d dev_id %d pasid %d" +vtd_device_fail_attach_existing_container(const char *msg) " %s" +vtd_device_alloc_ioas(int fd, uint32_t ioas_id) "iommufd %d ioas_id %d" =20 # amd_iommu.c amdvi_evntlog_fail(uint64_t addr, uint32_t head) "error: fail to write at = addr 0x%"PRIx64" + offset 0x%"PRIx32 --=20 2.34.1 From nobody Sat Nov 15 20:49:57 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="49895124" X-IronPort-AV: E=Sophos;i="6.15,303,1739865600"; d="scan'208";a="49895124" X-CSE-ConnectionGUID: iy4nvUElSLmhoQUyjlBBww== X-CSE-MsgGUID: 5Rj15SBeRQuIRLS0K7Ww0w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,303,1739865600"; d="scan'208";a="145158393" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PATCH rfcv3 16/21] intel_iommu: ERRATA_772415 workaround Date: Wed, 21 May 2025 19:14:46 +0800 Message-Id: <20250521111452.3316354-17-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250521111452.3316354-1-zhenzhong.duan@intel.com> References: <20250521111452.3316354-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.184, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1747826476060116600 Content-Type: text/plain; charset="utf-8" On a system influenced by ERRATA_772415, IOMMU_HW_INFO_VTD_ERRATA_772415_SP= R17 is repored by IOMMU_DEVICE_GET_HW_INFO. Due to this errata, even the readon= ly range mapped on stage-2 page table could still be written. Reference from 4th Gen Intel Xeon Processor Scalable Family Specification Update, Errata Details, SPR17. [0] https://edc.intel.com/content/www/us/en/design/products-and-solutions/p= rocessors-and-chipsets/eagle-stream/sapphire-rapids-specification-update We utilize the new added IOMMUFD container/ioas/hwpt management framework in VTD. Add a check to create new VTDIOASContainer to only hold RW mappings, then this VTDIOASContainer can be used as backend for device with ERRATA_772415. See below diagram for details: IntelIOMMUState | V .------------------. .------------------. .-------------------. | VTDIOASContainer |--->| VTDIOASContainer |--->| VTDIOASContainer |--= >... | (iommufd0,RW&RO) | | (iommufd1,RW&RO) | | (iommufd0,only RW)| .------------------. .------------------. .-------------------. | | | | .-->... | V V .-------------------. .-------------------. .------------= ---. | VTDS2Hwpt(CC) |--->| VTDS2Hwpt(non-CC) |-->... | VTDS2Hwpt(C= C) |-->... .-------------------. .-------------------. .------------= ---. | | | | | | | | .-----------. .-----------. .------------. .------------. | IOMMUFD | | IOMMUFD | | IOMMUFD | | IOMMUFD | | Device(CC)| | Device(CC)| | Device | | Device(CC) | | (iommufd0)| | (iommufd0)| | (non-CC) | | (errata) | | | | | | (iommufd0) | | (iommufd0) | .-----------. .-----------. .------------. .------------. Changed to pass VTDHostIOMMUDevice pointer to vtd_check_hdev() so errata could be saved. Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 1 + include/hw/i386/intel_iommu.h | 1 + hw/i386/intel_iommu.c | 25 +++++++++++++++++-------- 3 files changed, 19 insertions(+), 8 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index e76f43bb8f..75d840f9fe 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -654,5 +654,6 @@ typedef struct VTDHostIOMMUDevice { PCIBus *bus; uint8_t devfn; HostIOMMUDevice *hiod; + uint32_t errata; } VTDHostIOMMUDevice; #endif diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 594281c1d3..9b156dc32e 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -103,6 +103,7 @@ typedef struct VTDPASIDCacheEntry { typedef struct VTDIOASContainer { struct IOMMUFDBackend *iommufd; uint32_t ioas_id; + uint32_t errata; MemoryListener listener; QLIST_HEAD(, VTDS2Hwpt) s2_hwpt_list; QLIST_ENTRY(VTDIOASContainer) next; diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 3269a66ac7..9ffc2a8ffc 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2437,7 +2437,8 @@ static void vtd_context_global_invalidate(IntelIOMMUS= tate *s) } =20 #ifdef CONFIG_IOMMUFD -static bool iommufd_listener_skipped_section(MemoryRegionSection *section) +static bool iommufd_listener_skipped_section(VTDIOASContainer *container, + MemoryRegionSection *section) { return !memory_region_is_ram(section->mr) || memory_region_is_protected(section->mr) || @@ -2447,7 +2448,8 @@ static bool iommufd_listener_skipped_section(MemoryRe= gionSection *section) * are never accessed by the CPU and beyond the address width of * some IOMMU hardware. TODO: VFIO should tell us the IOMMU wi= dth. */ - section->offset_within_address_space & (1ULL << 63); + section->offset_within_address_space & (1ULL << 63) || + (container->errata && section->readonly); } =20 static void iommufd_listener_region_add_s2domain(MemoryListener *listener, @@ -2463,7 +2465,7 @@ static void iommufd_listener_region_add_s2domain(Memo= ryListener *listener, Error *err =3D NULL; int ret; =20 - if (iommufd_listener_skipped_section(section)) { + if (iommufd_listener_skipped_section(container, section)) { return; } iova =3D REAL_HOST_PAGE_ALIGN(section->offset_within_address_space); @@ -2514,7 +2516,7 @@ static void iommufd_listener_region_del_s2domain(Memo= ryListener *listener, Int128 llend, llsize; int ret; =20 - if (iommufd_listener_skipped_section(section)) { + if (iommufd_listener_skipped_section(container, section)) { return; } iova =3D REAL_HOST_PAGE_ALIGN(section->offset_within_address_space); @@ -2770,7 +2772,8 @@ static int vtd_device_attach_iommufd(VTDHostIOMMUDevi= ce *vtd_hiod, =20 /* try to attach to an existing container in this space */ QLIST_FOREACH(container, &s->containers, next) { - if (container->iommufd !=3D iommufd) { + if (container->iommufd !=3D iommufd || + container->errata !=3D vtd_hiod->errata) { continue; } =20 @@ -2797,6 +2800,7 @@ static int vtd_device_attach_iommufd(VTDHostIOMMUDevi= ce *vtd_hiod, container =3D g_malloc0(sizeof(*container)); container->iommufd =3D iommufd; container->ioas_id =3D ioas_id; + container->errata =3D vtd_hiod->errata; QLIST_INIT(&container->s2_hwpt_list); =20 if (vtd_device_attach_container(vtd_hiod, container, pasid, pe, hwpt, @@ -5355,9 +5359,10 @@ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s,= PCIBus *bus, return vtd_dev_as; } =20 -static bool vtd_check_hiod(IntelIOMMUState *s, HostIOMMUDevice *hiod, +static bool vtd_check_hiod(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hio= d, Error **errp) { + HostIOMMUDevice *hiod =3D vtd_hiod->hiod; HostIOMMUDeviceClass *hiodc =3D HOST_IOMMU_DEVICE_GET_CLASS(hiod); int ret; =20 @@ -5399,7 +5404,7 @@ static bool vtd_check_hiod(IntelIOMMUState *s, HostIO= MMUDevice *hiod, } =20 /* - * HOST_IOMMU_DEVICE_CAP_NESTING/FS1GP are VTD vendor specific + * HOST_IOMMU_DEVICE_CAP_NESTING/FS1GP/ERRATA are VTD vendor specific * capabilities, so get_cap() should never fail on them now that * HOST_IOMMU_DEVICE_IOMMU_HW_INFO_TYPE_INTEL_VTD type check passed * above. @@ -5416,6 +5421,9 @@ static bool vtd_check_hiod(IntelIOMMUState *s, HostIO= MMUDevice *hiod, return false; } =20 + ret =3D hiodc->get_cap(hiod, HOST_IOMMU_DEVICE_CAP_ERRATA, errp); + vtd_hiod->errata =3D ret; + error_setg(errp, "host device is uncompatible with stage-1 translation= "); return false; } @@ -5447,7 +5455,8 @@ static bool vtd_dev_set_iommu_device(PCIBus *bus, voi= d *opaque, int devfn, vtd_hiod->iommu_state =3D s; vtd_hiod->hiod =3D hiod; =20 - if (!vtd_check_hiod(s, hiod, errp)) { + if (!vtd_check_hiod(s, vtd_hiod, errp)) { + g_free(vtd_hiod); vtd_iommu_unlock(s); return false; } --=20 2.34.1 From nobody Sat Nov 15 20:49:57 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1747826447; cv=none; d=zohomail.com; s=zohoarc; b=cvYNzPN1z6t/nhZkuvdoBzBl0EZomtFZn5fxL3stsM1o6rtYAy8+W8sRKH5C6osU/C1mFIbA3UH3YAtRqldKpm19g6LDezBtuS3zOCynZaewTTRgR5c1Uzcrq7fz3XCx4CQrbFRpq4kzU0ncv7FGQbN/VNJa/RZOdefFesME0io= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.184, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1747826447853116600 Content-Type: text/plain; charset="utf-8" From: Yi Liu This replays guest pasid attachments after context cache invalidation. This is a behavior to ensure safety. Actually, programmer should issue pasid cache invalidation with proper granularity after issuing a context cache invalidation. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 1 + hw/i386/intel_iommu.c | 51 ++++++++++++++++++++++++++++++++-- hw/i386/trace-events | 1 + 3 files changed, 51 insertions(+), 2 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 75d840f9fe..198726b48f 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -575,6 +575,7 @@ typedef enum VTDPCInvType { VTD_PASID_CACHE_FORCE_RESET =3D 0, /* pasid cache invalidation rely on guest PASID entry */ VTD_PASID_CACHE_GLOBAL_INV, /* pasid cache global invalidation */ + VTD_PASID_CACHE_DEVSI, /* pasid cache device selective invalidati= on */ VTD_PASID_CACHE_DOMSI, /* pasid cache domain selective invalidati= on */ VTD_PASID_CACHE_PASIDSI, /* pasid cache pasid selective invalidatio= n */ } VTDPCInvType; diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 9ffc2a8ffc..d686d0ee1a 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -91,6 +91,10 @@ static void vtd_address_space_refresh_all(IntelIOMMUStat= e *s); static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n); =20 static void vtd_pasid_cache_reset_locked(IntelIOMMUState *s); +static void vtd_pasid_cache_sync(IntelIOMMUState *s, + VTDPASIDCacheInfo *pc_info); +static void vtd_pasid_cache_devsi(IntelIOMMUState *s, + PCIBus *bus, uint16_t devfn); =20 static void vtd_panic_require_caching_mode(void) { @@ -2417,6 +2421,8 @@ static void vtd_iommu_replay_all(IntelIOMMUState *s) =20 static void vtd_context_global_invalidate(IntelIOMMUState *s) { + VTDPASIDCacheInfo pc_info =3D { .error_happened =3D false, }; + trace_vtd_inv_desc_cc_global(); /* Protects context cache */ vtd_iommu_lock(s); @@ -2434,6 +2440,9 @@ static void vtd_context_global_invalidate(IntelIOMMUS= tate *s) * VT-d emulation codes. */ vtd_iommu_replay_all(s); + + pc_info.type =3D VTD_PASID_CACHE_GLOBAL_INV; + vtd_pasid_cache_sync(s, &pc_info); } =20 #ifdef CONFIG_IOMMUFD @@ -2989,6 +2998,21 @@ static void vtd_context_device_invalidate(IntelIOMMU= State *s, * happened. */ vtd_address_space_sync(vtd_as); + /* + * Per spec, context flush should also followed with PASID + * cache and iotlb flush. Regards to a device selective + * context cache invalidation: + * if (emaulted_device) + * invalidate pasid cache and pasid-based iotlb + * else if (assigned_device) + * check if the device has been bound to any pasid + * invoke pasid_unbind regards to each bound pasid + * Here, we have vtd_pasid_cache_devsi() to invalidate pasid + * caches, while for piotlb in QEMU, we don't have it yet, so + * no handling. For assigned device, host iommu driver would + * flush piotlb when a pasid unbind is pass down to it. + */ + vtd_pasid_cache_devsi(s, vtd_as->bus, devfn); } } } @@ -3737,6 +3761,11 @@ static gboolean vtd_flush_pasid(gpointer key, gpoint= er value, /* Fall through */ case VTD_PASID_CACHE_GLOBAL_INV: break; + case VTD_PASID_CACHE_DEVSI: + if (pc_info->bus !=3D vtd_as->bus || pc_info->devfn !=3D vtd_as->d= evfn) { + return false; + } + break; default: error_report("invalid pc_info->type"); abort(); @@ -3933,6 +3962,11 @@ static void vtd_replay_guest_pasid_bindings(IntelIOM= MUState *s, case VTD_PASID_CACHE_GLOBAL_INV: /* loop all assigned devices */ break; + case VTD_PASID_CACHE_DEVSI: + walk_info.bus =3D pc_info->bus; + walk_info.devfn =3D pc_info->devfn; + vtd_replay_pasid_bind_for_dev(s, start, end, &walk_info); + return; case VTD_PASID_CACHE_FORCE_RESET: /* For force reset, no need to go further replay */ return; @@ -3968,8 +4002,7 @@ static void vtd_replay_guest_pasid_bindings(IntelIOMM= UState *s, * It includes updating the pasid cache in vIOMMU and updating the * pasid bindings per guest's latest pasid entry presence. */ -static void vtd_pasid_cache_sync(IntelIOMMUState *s, - VTDPASIDCacheInfo *pc_info) +static void vtd_pasid_cache_sync(IntelIOMMUState *s, VTDPASIDCacheInfo *pc= _info) { if (!s->flts || !s->root_scalable || !s->dmar_enabled) { return; @@ -4030,6 +4063,20 @@ static void vtd_pasid_cache_sync(IntelIOMMUState *s, vtd_replay_guest_pasid_bindings(s, pc_info); } =20 +static void vtd_pasid_cache_devsi(IntelIOMMUState *s, + PCIBus *bus, uint16_t devfn) +{ + VTDPASIDCacheInfo pc_info =3D { .error_happened =3D false, }; + + trace_vtd_pasid_cache_devsi(devfn); + + pc_info.type =3D VTD_PASID_CACHE_DEVSI; + pc_info.bus =3D bus; + pc_info.devfn =3D devfn; + + vtd_pasid_cache_sync(s, &pc_info); +} + static bool vtd_process_pasid_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) { diff --git a/hw/i386/trace-events b/hw/i386/trace-events index de903a0033..f001b820d9 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -28,6 +28,7 @@ vtd_pasid_cache_reset(void) "" vtd_pasid_cache_gsi(void) "" vtd_pasid_cache_dsi(uint16_t domain) "Domain selective PC invalidation dom= ain 0x%"PRIx16 vtd_pasid_cache_psi(uint16_t domain, uint32_t pasid) "PASID selective PC i= nvalidation domain 0x%"PRIx16" pasid 0x%"PRIx32 +vtd_pasid_cache_devsi(uint16_t devfn) "Dev selective PC invalidation dev: = 0x%"PRIx16 vtd_re_not_present(uint8_t bus) "Root entry bus %"PRIu8" not present" vtd_ce_not_present(uint8_t bus, uint8_t devfn) "Context entry bus %"PRIu8"= devfn %"PRIu8" not present" vtd_iotlb_page_hit(uint16_t sid, uint64_t addr, uint64_t slpte, uint16_t d= omain) "IOTLB page hit sid 0x%"PRIx16" iova 0x%"PRIx64" slpte 0x%"PRIx64" d= omain 0x%"PRIx16 --=20 2.34.1 From nobody Sat Nov 15 20:49:57 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="49895155" X-IronPort-AV: E=Sophos;i="6.15,303,1739865600"; d="scan'208";a="49895155" X-CSE-ConnectionGUID: bIrvWRhbSICpjhLKmg53zQ== X-CSE-MsgGUID: nrWvXHGySz2SNLOnrNquaA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,303,1739865600"; d="scan'208";a="145158460" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Yi Sun , Zhenzhong Duan , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PATCH rfcv3 18/21] intel_iommu: Propagate PASID-based iotlb invalidation to host Date: Wed, 21 May 2025 19:14:48 +0800 Message-Id: <20250521111452.3316354-19-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250521111452.3316354-1-zhenzhong.duan@intel.com> References: <20250521111452.3316354-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.184, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1747826553234116600 Content-Type: text/plain; charset="utf-8" From: Yi Liu This traps the guest PASID-based iotlb invalidation request and propagate it to host. Intel VT-d 3.0 supports nested translation in PASID granular. Guest SVA sup= port could be implemented by configuring nested translation on specific PASID. T= his is also known as dual stage DMA translation. Under such configuration, guest owns the GVA->GPA translation which is configured as stage-1 page table in host side for a specific pasid, and host owns GPA->HPA translation. As guest owns stage-1 translation table, piotlb invalidation should be propagated to host since host IOMMU will cache first level page table related mappings during DMA address translation. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 6 ++ hw/i386/intel_iommu.c | 118 ++++++++++++++++++++++++++++++++- 2 files changed, 122 insertions(+), 2 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 198726b48f..e4552ff9bd 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -589,6 +589,12 @@ typedef struct VTDPASIDCacheInfo { bool error_happened; } VTDPASIDCacheInfo; =20 +typedef struct VTDPIOTLBInvInfo { + uint16_t domain_id; + uint32_t pasid; + struct iommu_hwpt_vtd_s1_invalidate *inv_data; +} VTDPIOTLBInvInfo; + /* PASID Table Related Definitions */ #define VTD_PASID_DIR_BASE_ADDR_MASK (~0xfffULL) #define VTD_PASID_TABLE_BASE_ADDR_MASK (~0xfffULL) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index d686d0ee1a..bb21060d7e 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2932,12 +2932,110 @@ static int vtd_bind_guest_pasid(VTDAddressSpace *v= td_as, =20 return ret; } + +/* + * Caller of this function should hold iommu_lock. + */ +static void vtd_invalidate_piotlb(VTDAddressSpace *vtd_as, + struct iommu_hwpt_vtd_s1_invalidate *cac= he) +{ + VTDHostIOMMUDevice *vtd_hiod; + HostIOMMUDeviceIOMMUFD *idev; + VTDHwpt *hwpt =3D &vtd_as->hwpt; + int devfn =3D vtd_as->devfn; + struct vtd_as_key key =3D { + .bus =3D vtd_as->bus, + .devfn =3D devfn, + }; + IntelIOMMUState *s =3D vtd_as->iommu_state; + uint32_t entry_num =3D 1; /* Only implement one request for simplicity= */ + Error *err; + + if (!hwpt) { + return; + } + + vtd_hiod =3D g_hash_table_lookup(s->vtd_host_iommu_dev, &key); + if (!vtd_hiod || !vtd_hiod->hiod) { + return; + } + idev =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->hiod); + + if (!iommufd_backend_invalidate_cache(idev->iommufd, hwpt->hwpt_id, + IOMMU_HWPT_INVALIDATE_DATA_VTD_S= 1, + sizeof(*cache), &entry_num, cach= e, + &err)) { + error_report_err(err); + } +} + +/* + * This function is a loop function for the s->vtd_address_spaces + * list with VTDPIOTLBInvInfo as execution filter. It propagates + * the piotlb invalidation to host. Caller of this function + * should hold iommu_lock. + */ +static void vtd_flush_pasid_iotlb(gpointer key, gpointer value, + gpointer user_data) +{ + VTDPIOTLBInvInfo *piotlb_info =3D user_data; + VTDAddressSpace *vtd_as =3D value; + VTDPASIDCacheEntry *pc_entry =3D &vtd_as->pasid_cache_entry; + uint32_t pasid; + uint16_t did; + + /* Replay only fill pasid entry cache for passthrough device */ + if (!pc_entry->cache_filled || + !vtd_pe_pgtt_is_flt(&pc_entry->pasid_entry)) { + return; + } + + if (vtd_as_to_iommu_pasid_locked(vtd_as, &pasid)) { + return; + } + + did =3D vtd_pe_get_did(&pc_entry->pasid_entry); + + if (piotlb_info->domain_id =3D=3D did && piotlb_info->pasid =3D=3D pas= id) { + vtd_invalidate_piotlb(vtd_as, piotlb_info->inv_data); + } +} + +static void vtd_flush_pasid_iotlb_all(IntelIOMMUState *s, + uint16_t domain_id, uint32_t pasid, + hwaddr addr, uint64_t npages, bool i= h) +{ + struct iommu_hwpt_vtd_s1_invalidate cache_info =3D { 0 }; + VTDPIOTLBInvInfo piotlb_info; + + cache_info.addr =3D addr; + cache_info.npages =3D npages; + cache_info.flags =3D ih ? IOMMU_VTD_INV_FLAGS_LEAF : 0; + + piotlb_info.domain_id =3D domain_id; + piotlb_info.pasid =3D pasid; + piotlb_info.inv_data =3D &cache_info; + + /* + * Here loops all the vtd_as instances in s->vtd_address_spaces + * to find out the affected devices since piotlb invalidation + * should check pasid cache per architecture point of view. + */ + g_hash_table_foreach(s->vtd_address_spaces, + vtd_flush_pasid_iotlb, &piotlb_info); +} #else static int vtd_bind_guest_pasid(VTDAddressSpace *vtd_as, VTDPASIDEntry *pe, VTDPASIDOp op) { return 0; } + +static void vtd_flush_pasid_iotlb_all(IntelIOMMUState *s, + uint16_t domain_id, uint32_t pasid, + hwaddr addr, uint64_t npages, bool i= h) +{ +} #endif =20 /* Do a context-cache device-selective invalidation. @@ -3591,6 +3689,13 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUSt= ate *s, info.pasid =3D pasid; =20 vtd_iommu_lock(s); + /* + * Here loops all the vtd_as instances in s->vtd_as + * to find out the affected devices since piotlb invalidation + * should check pasid cache per architecture point of view. + */ + vtd_flush_pasid_iotlb_all(s, domain_id, pasid, 0, (uint64_t)-1, 0); + g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_pasid, &info); vtd_iommu_unlock(s); @@ -3613,7 +3718,8 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUSta= te *s, } =20 static void vtd_piotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain= _id, - uint32_t pasid, hwaddr addr, uint8_= t am) + uint32_t pasid, hwaddr addr, uint8_= t am, + bool ih) { VTDIOTLBPageInvInfo info; =20 @@ -3623,6 +3729,13 @@ static void vtd_piotlb_page_invalidate(IntelIOMMUSta= te *s, uint16_t domain_id, info.mask =3D ~((1 << am) - 1); =20 vtd_iommu_lock(s); + /* + * Here loops all the vtd_as instances in s->vtd_as + * to find out the affected devices since piotlb invalidation + * should check pasid cache per architecture point of view. + */ + vtd_flush_pasid_iotlb_all(s, domain_id, pasid, addr, 1 << am, ih); + g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_page_piotlb, &info); vtd_iommu_unlock(s); @@ -3656,7 +3769,8 @@ static bool vtd_process_piotlb_desc(IntelIOMMUState *= s, case VTD_INV_DESC_PIOTLB_PSI_IN_PASID: am =3D VTD_INV_DESC_PIOTLB_AM(inv_desc->val[1]); addr =3D (hwaddr) VTD_INV_DESC_PIOTLB_ADDR(inv_desc->val[1]); - vtd_piotlb_page_invalidate(s, domain_id, pasid, addr, am); + vtd_piotlb_page_invalidate(s, domain_id, pasid, addr, am, + VTD_INV_DESC_PIOTLB_IH(inv_desc->val[1]= )); break; =20 default: --=20 2.34.1 From nobody Sat Nov 15 20:49:57 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1747826458; cv=none; d=zohomail.com; s=zohoarc; b=Xbzi1IJ1qki4Yr80MO7IFXJnATqY5csbI27EJCknIdNkYY5/GGYDEyR0JG474oxj5g0DoK/vkzuk8lRe9QiOfjFISdBdbyeBS/pyXWBuIC1vA5ef5LCauHNjvanxhRUgqhLaZTwTpC+atAPAnfTiuE3k2JOyEVkivrtY9pR0NiQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747826458; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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X-CSE-ConnectionGUID: eZo20kAlRU6U389+lTg1WQ== X-CSE-MsgGUID: 2kZD3j+qR4Cyh70sRkY/fA== X-IronPort-AV: E=McAfee;i="6700,10204,11439"; a="49895175" X-IronPort-AV: E=Sophos;i="6.15,303,1739865600"; d="scan'208";a="49895175" X-CSE-ConnectionGUID: VdAQK/qJQt6eG+5sb+49/Q== X-CSE-MsgGUID: q/60nqvvSVycJXzm5Fz3FQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,303,1739865600"; d="scan'208";a="145158488" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PATCH rfcv3 19/21] intel_iommu: Refresh pasid bind when either SRTP or TE bit is changed Date: Wed, 21 May 2025 19:14:49 +0800 Message-Id: <20250521111452.3316354-20-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250521111452.3316354-1-zhenzhong.duan@intel.com> References: <20250521111452.3316354-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.184, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1747826460092116600 Content-Type: text/plain; charset="utf-8" From: Yi Liu When either 'Set Root Table Pointer' or 'Translation Enable' bit is changed, the pasid bindings on host side become stale and need to be updated. Introduce a helper function vtd_refresh_pasid_bind() for that purpose. Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index bb21060d7e..b8f3b8effa 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -89,6 +89,7 @@ struct vtd_iotlb_key { =20 static void vtd_address_space_refresh_all(IntelIOMMUState *s); static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n); +static void vtd_refresh_pasid_bind(IntelIOMMUState *s); =20 static void vtd_pasid_cache_reset_locked(IntelIOMMUState *s); static void vtd_pasid_cache_sync(IntelIOMMUState *s, @@ -3362,6 +3363,7 @@ static void vtd_handle_gcmd_srtp(IntelIOMMUState *s) vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_RTPS); vtd_reset_caches(s); vtd_address_space_refresh_all(s); + vtd_refresh_pasid_bind(s); } =20 /* Set Interrupt Remap Table Pointer */ @@ -3396,6 +3398,7 @@ static void vtd_handle_gcmd_te(IntelIOMMUState *s, bo= ol en) =20 vtd_reset_caches(s); vtd_address_space_refresh_all(s); + vtd_refresh_pasid_bind(s); } =20 /* Handle Interrupt Remap Enable/Disable */ @@ -4111,6 +4114,26 @@ static void vtd_replay_guest_pasid_bindings(IntelIOM= MUState *s, } } =20 +static void vtd_refresh_pasid_bind(IntelIOMMUState *s) +{ + VTDPASIDCacheInfo pc_info =3D { .error_happened =3D false, + .type =3D VTD_PASID_CACHE_GLOBAL_INV }; + + /* + * Only when dmar is enabled, should pasid bindings replayed, + * otherwise no need to replay. + */ + if (!s->dmar_enabled) { + return; + } + + if (!s->flts || !s->root_scalable) { + return; + } + + vtd_replay_guest_pasid_bindings(s, &pc_info); +} + /* * This function syncs the pasid bindings between guest and host. * It includes updating the pasid cache in vIOMMU and updating the --=20 2.34.1 From nobody Sat Nov 15 20:49:57 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="145158496" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PATCH rfcv3 20/21] intel_iommu: Bypass replay in stage-1 page table mode Date: Wed, 21 May 2025 19:14:50 +0800 Message-Id: <20250521111452.3316354-21-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250521111452.3316354-1-zhenzhong.duan@intel.com> References: <20250521111452.3316354-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.184, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1747826553025116600 Content-Type: text/plain; charset="utf-8" VFIO utilizes replay to setup initial shadow iommu mappings. But when stage-1 page table is configured, it is passed to host to construct nested page table, there is no replay needed. Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index b8f3b8effa..e7c662f609 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -5768,6 +5768,14 @@ static void vtd_iommu_replay(IOMMUMemoryRegion *iomm= u_mr, IOMMUNotifier *n) VTDContextEntry ce; DMAMap map =3D { .iova =3D 0, .size =3D HWADDR_MAX }; =20 + /* + * Replay on stage-1 page table is meaningless as stage-1 page table + * is passthroughed to host to construct nested page table + */ + if (s->flts && s->root_scalable) { + return; + } + /* replay is protected by BQL, page walk will re-setup it safely */ iova_tree_remove(vtd_as->iova_tree, map); =20 --=20 2.34.1 From nobody Sat Nov 15 20:49:57 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="145158532" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH rfcv3 21/21] intel_iommu: Enable host device when x-flts=on in scalable mode Date: Wed, 21 May 2025 19:14:51 +0800 Message-Id: <20250521111452.3316354-22-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250521111452.3316354-1-zhenzhong.duan@intel.com> References: <20250521111452.3316354-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.184, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1747826463799116600 Content-Type: text/plain; charset="utf-8" Now that all infrastructures of supporting passthrough device running with stage-1 translation are there, enable it now. Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index e7c662f609..c64bd9506e 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -5608,8 +5608,7 @@ static bool vtd_check_hiod(IntelIOMMUState *s, VTDHos= tIOMMUDevice *vtd_hiod, ret =3D hiodc->get_cap(hiod, HOST_IOMMU_DEVICE_CAP_ERRATA, errp); vtd_hiod->errata =3D ret; =20 - error_setg(errp, "host device is uncompatible with stage-1 translation= "); - return false; + return true; } =20 static bool vtd_dev_set_iommu_device(PCIBus *bus, void *opaque, int devfn, --=20 2.34.1