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d="scan'208";a="144461846" From: Zhao Liu To: Paolo Bonzini Cc: qemu-devel@nongnu.org, qemu-rust@nongnu.org, Dapeng Mi , Zhao Liu Subject: [PATCH 1/5] hw/timer/hpet: Reorganize register decoding Date: Tue, 20 May 2025 23:27:46 +0800 Message-Id: <20250520152750.2542612-2-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250520152750.2542612-1-zhao1.liu@intel.com> References: <20250520152750.2542612-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.11; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -48 X-Spam_score: -4.9 X-Spam_bar: ---- X-Spam_report: (-4.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.487, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1747753797286116600 Content-Type: text/plain; charset="utf-8" For Rust HPET, since the commit 519088b7cf6d ("rust: hpet: decode HPET registers into enums"), it decodes register address by checking if the register belongs to global register space. And for C HPET, it checks timer register space first. While both approaches are fine, it's best to be as consistent as possible. Synchronize changes from the rust side to C side. Signed-off-by: Zhao Liu --- Picked from <20250218073702.3299300-1-zhao1.liu@intel.com>. But because of Rust code base change, it's enough to just sync the changes. --- hw/timer/hpet.c | 166 ++++++++++++++++++++++++------------------------ 1 file changed, 84 insertions(+), 82 deletions(-) diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c index d1b7bc52b7be..0fd1337a1564 100644 --- a/hw/timer/hpet.c +++ b/hw/timer/hpet.c @@ -426,30 +426,11 @@ static uint64_t hpet_ram_read(void *opaque, hwaddr ad= dr, uint64_t cur_tick; =20 trace_hpet_ram_read(addr); + addr &=3D ~4; =20 - /*address range of all TN regs*/ - if (addr >=3D 0x100 && addr <=3D 0x3ff) { - uint8_t timer_id =3D (addr - 0x100) / 0x20; - HPETTimer *timer =3D &s->timer[timer_id]; - - if (timer_id > s->num_timers) { - trace_hpet_timer_id_out_of_range(timer_id); - return 0; - } - - switch (addr & 0x18) { - case HPET_TN_CFG: // including interrupt capabilities - return timer->config >> shift; - case HPET_TN_CMP: // comparator register - return timer->cmp >> shift; - case HPET_TN_ROUTE: - return timer->fsb >> shift; - default: - trace_hpet_ram_read_invalid(); - break; - } - } else { - switch (addr & ~4) { + /*address range of all global regs*/ + if (addr <=3D 0xff) { + switch (addr) { case HPET_ID: // including HPET_PERIOD return s->capability >> shift; case HPET_CFG: @@ -468,6 +449,26 @@ static uint64_t hpet_ram_read(void *opaque, hwaddr add= r, trace_hpet_ram_read_invalid(); break; } + } else { + uint8_t timer_id =3D (addr - 0x100) / 0x20; + HPETTimer *timer =3D &s->timer[timer_id]; + + if (timer_id > s->num_timers) { + trace_hpet_timer_id_out_of_range(timer_id); + return 0; + } + + switch (addr & 0x1f) { + case HPET_TN_CFG: // including interrupt capabilities + return timer->config >> shift; + case HPET_TN_CMP: // comparator register + return timer->cmp >> shift; + case HPET_TN_ROUTE: + return timer->fsb >> shift; + default: + trace_hpet_ram_read_invalid(); + break; + } } return 0; } @@ -482,9 +483,67 @@ static void hpet_ram_write(void *opaque, hwaddr addr, uint64_t old_val, new_val, cleared; =20 trace_hpet_ram_write(addr, value); + addr &=3D ~4; =20 - /*address range of all TN regs*/ - if (addr >=3D 0x100 && addr <=3D 0x3ff) { + /*address range of all global regs*/ + if (addr <=3D 0xff) { + switch (addr) { + case HPET_ID: + return; + case HPET_CFG: + old_val =3D s->config; + new_val =3D deposit64(old_val, shift, len, value); + new_val =3D hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MA= SK); + s->config =3D new_val; + if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) { + /* Enable main counter and interrupt generation. */ + s->hpet_offset =3D + ticks_to_ns(s->hpet_counter) - qemu_clock_get_ns(QEMU_= CLOCK_VIRTUAL); + for (i =3D 0; i < s->num_timers; i++) { + if (timer_enabled(&s->timer[i]) && (s->isr & (1 << i))= ) { + update_irq(&s->timer[i], 1); + } + hpet_set_timer(&s->timer[i]); + } + } else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)= ) { + /* Halt main counter and disable interrupt generation. */ + s->hpet_counter =3D hpet_get_ticks(s); + for (i =3D 0; i < s->num_timers; i++) { + hpet_del_timer(&s->timer[i]); + } + } + /* i8254 and RTC output pins are disabled + * when HPET is in legacy mode */ + if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) { + qemu_set_irq(s->pit_enabled, 0); + qemu_irq_lower(s->irqs[0]); + qemu_irq_lower(s->irqs[RTC_ISA_IRQ]); + } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)= ) { + qemu_irq_lower(s->irqs[0]); + qemu_set_irq(s->pit_enabled, 1); + qemu_set_irq(s->irqs[RTC_ISA_IRQ], s->rtc_irq_level); + } + break; + case HPET_STATUS: + new_val =3D value << shift; + cleared =3D new_val & s->isr; + for (i =3D 0; i < s->num_timers; i++) { + if (cleared & (1 << i)) { + update_irq(&s->timer[i], 0); + } + } + break; + case HPET_COUNTER: + if (hpet_enabled(s)) { + trace_hpet_ram_write_counter_write_while_enabled(); + } + s->hpet_counter =3D deposit64(s->hpet_counter, shift, len, val= ue); + break; + default: + trace_hpet_ram_write_invalid(); + break; + } + } else { uint8_t timer_id =3D (addr - 0x100) / 0x20; HPETTimer *timer =3D &s->timer[timer_id]; =20 @@ -550,63 +609,6 @@ static void hpet_ram_write(void *opaque, hwaddr addr, break; } return; - } else { - switch (addr & ~4) { - case HPET_ID: - return; - case HPET_CFG: - old_val =3D s->config; - new_val =3D deposit64(old_val, shift, len, value); - new_val =3D hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MA= SK); - s->config =3D new_val; - if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) { - /* Enable main counter and interrupt generation. */ - s->hpet_offset =3D - ticks_to_ns(s->hpet_counter) - qemu_clock_get_ns(QEMU_= CLOCK_VIRTUAL); - for (i =3D 0; i < s->num_timers; i++) { - if (timer_enabled(&s->timer[i]) && (s->isr & (1 << i))= ) { - update_irq(&s->timer[i], 1); - } - hpet_set_timer(&s->timer[i]); - } - } else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)= ) { - /* Halt main counter and disable interrupt generation. */ - s->hpet_counter =3D hpet_get_ticks(s); - for (i =3D 0; i < s->num_timers; i++) { - hpet_del_timer(&s->timer[i]); - } - } - /* i8254 and RTC output pins are disabled - * when HPET is in legacy mode */ - if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) { - qemu_set_irq(s->pit_enabled, 0); - qemu_irq_lower(s->irqs[0]); - qemu_irq_lower(s->irqs[RTC_ISA_IRQ]); - } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)= ) { - qemu_irq_lower(s->irqs[0]); - qemu_set_irq(s->pit_enabled, 1); - qemu_set_irq(s->irqs[RTC_ISA_IRQ], s->rtc_irq_level); - } - break; - case HPET_STATUS: - new_val =3D value << shift; - cleared =3D new_val & s->isr; - for (i =3D 0; i < s->num_timers; i++) { - if (cleared & (1 << i)) { - update_irq(&s->timer[i], 0); - } - } - break; - case HPET_COUNTER: - if (hpet_enabled(s)) { - trace_hpet_ram_write_counter_write_while_enabled(); - } - s->hpet_counter =3D deposit64(s->hpet_counter, shift, len, val= ue); - break; - default: - trace_hpet_ram_write_invalid(); - break; - } } } =20 --=20 2.34.1 From nobody Sat Nov 15 20:49:57 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="144461860" From: Zhao Liu To: Paolo Bonzini Cc: qemu-devel@nongnu.org, qemu-rust@nongnu.org, Dapeng Mi , Zhao Liu Subject: [PATCH 2/5] hw/timer/hpet: Adjust num_timers in hpet_init() Date: Tue, 20 May 2025 23:27:47 +0800 Message-Id: <20250520152750.2542612-3-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250520152750.2542612-1-zhao1.liu@intel.com> References: <20250520152750.2542612-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.11; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -48 X-Spam_score: -4.9 X-Spam_bar: ---- X-Spam_report: (-4.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.487, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1747753931030116600 Content-Type: text/plain; charset="utf-8" Currently, HPET adjusts num_timers in hpet_realize(), and doesn't change it in any other place. And this field is initialized as a property. Therefore, it's possible to move such adjustments to hept_init(), so that Rust side can synchronize this change. Adjust num_timers in hpet_init(). Signed-off-by: Zhao Liu --- hw/timer/hpet.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c index 0fd1337a1564..48b1a9289f83 100644 --- a/hw/timer/hpet.c +++ b/hw/timer/hpet.c @@ -682,6 +682,12 @@ static void hpet_init(Object *obj) /* HPET Area */ memory_region_init_io(&s->iomem, obj, &hpet_ram_ops, s, "hpet", HPET_L= EN); sysbus_init_mmio(sbd, &s->iomem); + + if (s->num_timers < HPET_MIN_TIMERS) { + s->num_timers =3D HPET_MIN_TIMERS; + } else if (s->num_timers > HPET_MAX_TIMERS) { + s->num_timers =3D HPET_MAX_TIMERS; + } } =20 static void hpet_realize(DeviceState *dev, Error **errp) @@ -710,11 +716,6 @@ static void hpet_realize(DeviceState *dev, Error **err= p) sysbus_init_irq(sbd, &s->irqs[i]); } =20 - if (s->num_timers < HPET_MIN_TIMERS) { - s->num_timers =3D HPET_MIN_TIMERS; - } else if (s->num_timers > HPET_MAX_TIMERS) { - s->num_timers =3D HPET_MAX_TIMERS; - } for (i =3D 0; i < HPET_MAX_TIMERS; i++) { timer =3D &s->timer[i]; timer->qemu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, hpet_timer,= timer); --=20 2.34.1 From nobody Sat Nov 15 20:49:57 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1747753703; cv=none; d=zohomail.com; s=zohoarc; b=ge/5umd/ebNZXt96zNLhmBSjouMl8Eo2hlFzphE6hH9NtZfMSn/0riulvFwCX5LmP958ZfSfYHVYHweuHVEHQQpl1s5EVX3Ayk5xCzxiCgbfyZjgaXAbWPyMln6JoLE5rSN3fOkYQRcXL7frwCgSuvmajC5zQSbkvq5T6ZK+Jpo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747753703; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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X-CSE-ConnectionGUID: yV2/xn3+S36xX7ewTJ63qg== X-CSE-MsgGUID: pjuQnyayTXetRBmOd7oIQw== X-IronPort-AV: E=McAfee;i="6700,10204,11439"; a="59922537" X-IronPort-AV: E=Sophos;i="6.15,302,1739865600"; d="scan'208";a="59922537" X-CSE-ConnectionGUID: X7YEE3/ATi+In5SuXPV4kg== X-CSE-MsgGUID: +q1xE8LBQ6ehbwEon2jClg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,302,1739865600"; d="scan'208";a="144461880" From: Zhao Liu To: Paolo Bonzini Cc: qemu-devel@nongnu.org, qemu-rust@nongnu.org, Dapeng Mi , Zhao Liu Subject: [PATCH 3/5] rust/hpet: Drop BalCell wrapper for num_timers Date: Tue, 20 May 2025 23:27:48 +0800 Message-Id: <20250520152750.2542612-4-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250520152750.2542612-1-zhao1.liu@intel.com> References: <20250520152750.2542612-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.11; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -48 X-Spam_score: -4.9 X-Spam_bar: ---- X-Spam_report: (-4.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.487, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1747753705788116600 Content-Type: text/plain; charset="utf-8" Currently, HPET adjusts num_timers in HPETState::realize(), and doesn't change it in any other method. And this field is initialized as a property. Meanwhile, please note that as a property, someone may change its default value in the future using qdev_prop_set_uint8() binding on either the C side or Rust side after HPET object creation. However, since this depends on QOM core code (on the C side) and all subsequent processes occur on the C side, there's no need for additional safety considerations as it doesn't cross FFI boundaries. Therefore, this field could be immutable after init() so as not to be necessary to have a BqlCell wrapper. Adjust num_timers in HPETState::init() and drop the BqlCell wrapper. Note, when num_timers came out of BqlCell, the capability field doesn't need BqlCell as well since it's read-only. But from the view of readability, it's best to keep consistent with the other registers. Signed-off-by: Zhao Liu --- rust/hw/timer/hpet/src/hpet.rs | 37 +++++++++++++++------------------- 1 file changed, 16 insertions(+), 21 deletions(-) diff --git a/rust/hw/timer/hpet/src/hpet.rs b/rust/hw/timer/hpet/src/hpet.rs index 779681d65099..6cc6fa0aeda0 100644 --- a/rust/hw/timer/hpet/src/hpet.rs +++ b/rust/hw/timer/hpet/src/hpet.rs @@ -562,7 +562,7 @@ pub struct HPETState { /// HPET timer array managed by this timer block. #[doc(alias =3D "timer")] timers: [BqlRefCell; HPET_MAX_TIMERS as usize], - num_timers: BqlCell, + num_timers: u8, num_timers_save: BqlCell, =20 /// Instance id (HPET timer block ID). @@ -570,11 +570,6 @@ pub struct HPETState { } =20 impl HPETState { - // Get num_timers with `usize` type, which is useful to play with arra= y index. - fn get_num_timers(&self) -> usize { - self.num_timers.get().into() - } - const fn has_msi_flag(&self) -> bool { self.flags & (1 << HPET_FLAG_MSI_SUPPORT_SHIFT) !=3D 0 } @@ -636,7 +631,7 @@ fn set_cfg_reg(&self, shift: u32, len: u32, val: u64) { self.hpet_offset .set(ticks_to_ns(self.counter.get()) - CLOCK_VIRTUAL.get_n= s()); =20 - for timer in self.timers.iter().take(self.get_num_timers()) { + for timer in self.timers.iter().take(self.num_timers.into()) { let mut t =3D timer.borrow_mut(); =20 if t.is_int_enabled() && t.is_int_active() { @@ -648,7 +643,7 @@ fn set_cfg_reg(&self, shift: u32, len: u32, val: u64) { // Halt main counter and disable interrupt generation. self.counter.set(self.get_ticks()); =20 - for timer in self.timers.iter().take(self.get_num_timers()) { + for timer in self.timers.iter().take(self.num_timers.into()) { timer.borrow_mut().del_timer(); } } @@ -671,7 +666,7 @@ fn set_int_status_reg(&self, shift: u32, _len: u32, val= : u64) { let new_val =3D val << shift; let cleared =3D new_val & self.int_status.get(); =20 - for (index, timer) in self.timers.iter().take(self.get_num_timers(= )).enumerate() { + for (index, timer) in self.timers.iter().take(self.num_timers.into= ()).enumerate() { if cleared & (1 << index) !=3D 0 { timer.borrow_mut().update_irq(false); } @@ -715,6 +710,12 @@ unsafe fn init(&mut self) { "hpet", HPET_REG_SPACE_LEN, ); + + if self.num_timers < HPET_MIN_TIMERS { + self.num_timers =3D HPET_MIN_TIMERS; + } else if self.num_timers > HPET_MAX_TIMERS { + self.num_timers =3D HPET_MAX_TIMERS; + } } =20 fn post_init(&self) { @@ -732,12 +733,6 @@ fn realize(&self) { =20 self.hpet_id.set(HPETFwConfig::assign_hpet_id()); =20 - if self.num_timers.get() < HPET_MIN_TIMERS { - self.num_timers.set(HPET_MIN_TIMERS); - } else if self.num_timers.get() > HPET_MAX_TIMERS { - self.num_timers.set(HPET_MAX_TIMERS); - } - self.init_timer(); // 64-bit General Capabilities and ID Register; LegacyReplacementR= oute. self.capability.set( @@ -745,7 +740,7 @@ fn realize(&self) { 1 << HPET_CAP_COUNT_SIZE_CAP_SHIFT | 1 << HPET_CAP_LEG_RT_CAP_SHIFT | HPET_CAP_VENDER_ID_VALUE << HPET_CAP_VENDER_ID_SHIFT | - ((self.get_num_timers() - 1) as u64) << HPET_CAP_NUM_TIM_SHIFT= | // indicate the last timer + ((self.num_timers - 1) as u64) << HPET_CAP_NUM_TIM_SHIFT | // = indicate the last timer (HPET_CLK_PERIOD * FS_PER_NS) << HPET_CAP_CNT_CLK_PERIOD_SHIFT= , // 10 ns ); =20 @@ -754,7 +749,7 @@ fn realize(&self) { } =20 fn reset_hold(&self, _type: ResetType) { - for timer in self.timers.iter().take(self.get_num_timers()) { + for timer in self.timers.iter().take(self.num_timers.into()) { timer.borrow_mut().reset(); } =20 @@ -782,7 +777,7 @@ fn decode(&self, mut addr: hwaddr, size: u32) -> HPETAd= drDecode { GlobalRegister::try_from(addr).map(HPETRegister::Global) } else { let timer_id: usize =3D ((addr - 0x100) / 0x20) as usize; - if timer_id <=3D self.get_num_timers() { + if timer_id <=3D self.num_timers.into() { // TODO: Add trace point - trace_hpet_ram_[read|write]_tim= er_id(timer_id) TimerRegister::try_from(addr & 0x18) .map(|reg| HPETRegister::Timer(&self.timers[timer_id],= reg)) @@ -853,12 +848,12 @@ fn pre_save(&self) -> i32 { * also added to the migration stream. Check that it matches the = value * that was configured. */ - self.num_timers_save.set(self.num_timers.get()); + self.num_timers_save.set(self.num_timers); 0 } =20 fn post_load(&self, _version_id: u8) -> i32 { - for timer in self.timers.iter().take(self.get_num_timers()) { + for timer in self.timers.iter().take(self.num_timers.into()) { let mut t =3D timer.borrow_mut(); =20 t.cmp64 =3D t.calculate_cmp64(t.get_state().counter.get(), t.c= mp); @@ -883,7 +878,7 @@ fn is_offset_needed(&self) -> bool { } =20 fn validate_num_timers(&self, _version_id: u8) -> bool { - self.num_timers.get() =3D=3D self.num_timers_save.get() + self.num_timers =3D=3D self.num_timers_save.get() } } =20 --=20 2.34.1 From nobody Sat Nov 15 20:49:57 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; 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d="scan'208";a="144461890" From: Zhao Liu To: Paolo Bonzini Cc: qemu-devel@nongnu.org, qemu-rust@nongnu.org, Dapeng Mi , Zhao Liu Subject: [PATCH 4/5] rust: Fix Zhao's email address Date: Tue, 20 May 2025 23:27:49 +0800 Message-Id: <20250520152750.2542612-5-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250520152750.2542612-1-zhao1.liu@intel.com> References: <20250520152750.2542612-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.11; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -48 X-Spam_score: -4.9 X-Spam_bar: ---- X-Spam_report: (-4.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.487, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1747753780888116600 Content-Type: text/plain; charset="utf-8" No one could find Zhao Liu via zhai1.liu@intel.com. Signed-off-by: Zhao Liu Reviewed-by: Peter Maydell --- rust/hw/timer/hpet/src/fw_cfg.rs | 2 +- rust/hw/timer/hpet/src/hpet.rs | 2 +- rust/hw/timer/hpet/src/lib.rs | 2 +- rust/qemu-api/src/bitops.rs | 2 +- rust/qemu-api/src/timer.rs | 2 +- rust/qemu-api/tests/vmstate_tests.rs | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/rust/hw/timer/hpet/src/fw_cfg.rs b/rust/hw/timer/hpet/src/fw_c= fg.rs index aa08d2835194..6c10316104ce 100644 --- a/rust/hw/timer/hpet/src/fw_cfg.rs +++ b/rust/hw/timer/hpet/src/fw_cfg.rs @@ -1,5 +1,5 @@ // Copyright (C) 2024 Intel Corporation. -// Author(s): Zhao Liu +// Author(s): Zhao Liu // SPDX-License-Identifier: GPL-2.0-or-later =20 use std::ptr::addr_of_mut; diff --git a/rust/hw/timer/hpet/src/hpet.rs b/rust/hw/timer/hpet/src/hpet.rs index 6cc6fa0aeda0..8f68372dee52 100644 --- a/rust/hw/timer/hpet/src/hpet.rs +++ b/rust/hw/timer/hpet/src/hpet.rs @@ -1,5 +1,5 @@ // Copyright (C) 2024 Intel Corporation. -// Author(s): Zhao Liu +// Author(s): Zhao Liu // SPDX-License-Identifier: GPL-2.0-or-later =20 use std::{ diff --git a/rust/hw/timer/hpet/src/lib.rs b/rust/hw/timer/hpet/src/lib.rs index 1954584a87e9..141aae229d4d 100644 --- a/rust/hw/timer/hpet/src/lib.rs +++ b/rust/hw/timer/hpet/src/lib.rs @@ -1,5 +1,5 @@ // Copyright (C) 2024 Intel Corporation. -// Author(s): Zhao Liu +// Author(s): Zhao Liu // SPDX-License-Identifier: GPL-2.0-or-later =20 //! # HPET QEMU Device Model diff --git a/rust/qemu-api/src/bitops.rs b/rust/qemu-api/src/bitops.rs index 023ec1a99831..b1e3a530ab54 100644 --- a/rust/qemu-api/src/bitops.rs +++ b/rust/qemu-api/src/bitops.rs @@ -1,5 +1,5 @@ // Copyright (C) 2024 Intel Corporation. -// Author(s): Zhao Liu +// Author(s): Zhao Liu // SPDX-License-Identifier: GPL-2.0-or-later =20 //! This module provides bit operation extensions to integer types. diff --git a/rust/qemu-api/src/timer.rs b/rust/qemu-api/src/timer.rs index 868bd88575f2..0a2d111d4909 100644 --- a/rust/qemu-api/src/timer.rs +++ b/rust/qemu-api/src/timer.rs @@ -1,5 +1,5 @@ // Copyright (C) 2024 Intel Corporation. -// Author(s): Zhao Liu +// Author(s): Zhao Liu // SPDX-License-Identifier: GPL-2.0-or-later =20 use std::{ diff --git a/rust/qemu-api/tests/vmstate_tests.rs b/rust/qemu-api/tests/vms= tate_tests.rs index ad0fc5cd5dd0..bded836eb608 100644 --- a/rust/qemu-api/tests/vmstate_tests.rs +++ b/rust/qemu-api/tests/vmstate_tests.rs @@ -1,5 +1,5 @@ // Copyright (C) 2025 Intel Corporation. -// Author(s): Zhao Liu +// Author(s): Zhao Liu // SPDX-License-Identifier: GPL-2.0-or-later =20 use std::{ --=20 2.34.1 From nobody Sat Nov 15 20:49:57 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="144461908" From: Zhao Liu To: Paolo Bonzini Cc: qemu-devel@nongnu.org, qemu-rust@nongnu.org, Dapeng Mi , Zhao Liu Subject: [PATCH 5/5] rust: Fix the typos in doc Date: Tue, 20 May 2025 23:27:50 +0800 Message-Id: <20250520152750.2542612-6-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250520152750.2542612-1-zhao1.liu@intel.com> References: <20250520152750.2542612-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.11; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -48 X-Spam_score: -4.9 X-Spam_bar: ---- X-Spam_report: (-4.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.487, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1747753673220116600 Content-Type: text/plain; charset="utf-8" These typos are found by "cargo spellcheck". Though it outputs a lot of noise and false positives, there still are some real typos. Signed-off-by: Zhao Liu Reviewed-by: Peter Maydell --- Note: But I have to admit, cargo spellcheck isn't a great tool. Picked from <20250218092108.3347963-1-zhao1.liu@intel.com> with checking again. --- rust/hw/char/pl011/src/device.rs | 4 ++-- rust/qemu-api/src/qom.rs | 4 ++-- rust/qemu-api/src/vmstate.rs | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi= ce.rs index bde3be65c5b0..bd5cee046473 100644 --- a/rust/hw/char/pl011/src/device.rs +++ b/rust/hw/char/pl011/src/device.rs @@ -480,13 +480,13 @@ pub fn post_load(&mut self) -> Result<(), ()> { } =20 impl PL011State { - /// Initializes a pre-allocated, unitialized instance of `PL011State`. + /// Initializes a pre-allocated, uninitialized instance of `PL011State= `. /// /// # Safety /// /// `self` must point to a correctly sized and aligned location for the /// `PL011State` type. It must not be called more than once on the same - /// location/instance. All its fields are expected to hold unitialized + /// location/instance. All its fields are expected to hold uninitializ= ed /// values with the sole exception of `parent_obj`. unsafe fn init(&mut self) { static PL011_OPS: MemoryRegionOps =3D MemoryRegionOpsB= uilder::::new() diff --git a/rust/qemu-api/src/qom.rs b/rust/qemu-api/src/qom.rs index 41e5a5e29a82..14f98fee60ab 100644 --- a/rust/qemu-api/src/qom.rs +++ b/rust/qemu-api/src/qom.rs @@ -291,7 +291,7 @@ fn as_object(&self) -> &Object { } =20 /// Return the receiver as a const raw pointer to Object. - /// This is preferrable to `as_object_mut_ptr()` if a C + /// This is preferable to `as_object_mut_ptr()` if a C /// function only needs a `const Object *`. fn as_object_ptr(&self) -> *const bindings::Object { self.as_object().as_ptr() @@ -485,7 +485,7 @@ pub trait ObjectImpl: ObjectType + IsA { /// `INSTANCE_INIT` functions have been called. const INSTANCE_POST_INIT: Option =3D None; =20 - /// Called on descendent classes after all parent class initialization + /// Called on descendant classes after all parent class initialization /// has occurred, but before the class itself is initialized. This /// is only useful if a class is not a leaf, and can be used to undo /// the effects of copying the contents of the parent's class struct diff --git a/rust/qemu-api/src/vmstate.rs b/rust/qemu-api/src/vmstate.rs index 9c8b2398e9d4..812f390d7802 100644 --- a/rust/qemu-api/src/vmstate.rs +++ b/rust/qemu-api/src/vmstate.rs @@ -9,7 +9,7 @@ //! * [`vmstate_unused!`](crate::vmstate_unused) and //! [`vmstate_of!`](crate::vmstate_of), which are used to express the //! migration format for a struct. This is based on the [`VMState`] tra= it, -//! which is defined by all migrateable types. +//! which is defined by all migratable types. //! //! * [`impl_vmstate_forward`](crate::impl_vmstate_forward) and //! [`impl_vmstate_bitsized`](crate::impl_vmstate_bitsized), which help = with --=20 2.34.1