From nobody Sat Nov 15 22:35:30 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1747740883; cv=none; d=zohomail.com; s=zohoarc; b=mGDKCCEJHYkDlQpXJKJyChA0sluFhtduzUrekPXwd0zvxsxTDmMrGozcX1KSiiP1BS558jy/qZgG5LCkYHfs14Gm1ab6XqE6mlKwGOr7VFxGguBz6d31g8VfTKTlEFkZjuK2vMrXzm0YRDxzi1/nI03hFocH+2y2E/zB1P/C0fo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747740883; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=15HkIZ5W3yN8OHci0OT9HsUs7MUfJ+rWI7POCkk5xRs=; b=D3j7ZSuTi9BTI7MIfbk4OsC+luI0NYh9Yp0/smCttGg/4APTetbFlOW9MjsF3L7TpwZBvIAluYxC5RAEa5zKg96Yilkb84r07I9Zb1l+3OwKqxw7gEkuJlSLBBywFm2Ieohj/YA9ahmdb92aEWaBu1WOOgd4Q8C4MgRQps73Xoc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174774088396867.69986678048542; Tue, 20 May 2025 04:34:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uHLCv-0000mb-PR; Tue, 20 May 2025 07:32:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uHLCt-0000iW-I2 for qemu-devel@nongnu.org; Tue, 20 May 2025 07:32:27 -0400 Received: from linux.microsoft.com ([13.77.154.182]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uHLCr-0001Nm-6Y for qemu-devel@nongnu.org; Tue, 20 May 2025 07:32:27 -0400 Received: from DESKTOP-TUU1E5L.fritz.box (unknown [172.201.77.43]) by linux.microsoft.com (Postfix) with ESMTPSA id 203832068328; Tue, 20 May 2025 04:32:10 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 203832068328 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1747740734; bh=15HkIZ5W3yN8OHci0OT9HsUs7MUfJ+rWI7POCkk5xRs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=saYq3XiH75PbXDEL3oNzUwz4AahKp17a26FlmyJt97v5GOX46jlzYtUDS4aHc5LOf 1FpEyHPTgBGZ2IskQeoD904v4gpfbOErFKeBndIl8u6Hx+MbVoGjnxFch3AeuYHRIW MX1gKMmmWyREYkgxsoZfoQcSgoI5F2Gy8W9DU0HY= From: Magnus Kulke To: magnuskulke@microsoft.com, qemu-devel@nongnu.org, liuwe@microsoft.com Cc: Paolo Bonzini , "Michael S. Tsirkin" , Wei Liu , Phil Dennis-Jordan , Roman Bolshakov , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Zhao Liu , Richard Henderson , Cameron Esfahani , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= Subject: [RFC PATCH 19/25] target/i386/mshv: Set local interrupt controller state Date: Tue, 20 May 2025 13:30:12 +0200 Message-Id: <20250520113018.49569-20-magnuskulke@linux.microsoft.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250520113018.49569-1-magnuskulke@linux.microsoft.com> References: <20250520113018.49569-1-magnuskulke@linux.microsoft.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=magnuskulke@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1747740886094116600 Content-Type: text/plain; charset="utf-8" To set the local interrupt controller state, perform hv calls retrieving partition state from the hypervisor. Signed-off-by: Magnus Kulke --- target/i386/mshv/mshv-cpu.c | 120 ++++++++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c index ad42a09b99..dd856a2242 100644 --- a/target/i386/mshv/mshv-cpu.c +++ b/target/i386/mshv/mshv-cpu.c @@ -17,6 +17,7 @@ #include "qemu/atomic.h" #include "qemu/lockable.h" #include "qemu/error-report.h" +#include "qemu/memalign.h" #include "qemu/typedefs.h" =20 #include "system/mshv.h" @@ -108,6 +109,10 @@ static enum hv_register_name FPU_REGISTER_NAMES[26] = =3D { HV_X64_REGISTER_XMM_CONTROL_STATUS, }; =20 +/* Defines poached from apicdef.h kernel header. */ +static u_int32_t APIC_MODE_NMI =3D 0x4; +static u_int32_t APIC_MODE_EXTINT =3D 0x7; + static void add_cpu_guard(int cpu_fd) { QemuMutex *guard; @@ -545,6 +550,114 @@ static int set_cpu_state(const CPUState *cpu, const M= shvFPU *fpu_regs, return 0; } =20 +static int get_vp_state(int cpu_fd, mshv_get_set_vp_state *state) +{ + int ret; + + ret =3D ioctl(cpu_fd, MSHV_GET_VP_STATE, state); + if (ret < 0) { + error_report("failed to get partition state: %s", strerror(errno)); + return -1; + } + + return 0; +} + +static int get_lapic(int cpu_fd, + struct hv_local_interrupt_controller_state *state) +{ + int ret; + size_t size =3D 4096; + /* buffer aligned to 4k, as *state requires that */ + void *buffer =3D qemu_memalign(size, size); + struct mshv_get_set_vp_state mshv_state =3D { 0 }; + + mshv_state.buf_ptr =3D (uint64_t) buffer; + mshv_state.buf_sz =3D size; + mshv_state.type =3D MSHV_VP_STATE_LAPIC; + + ret =3D get_vp_state(cpu_fd, &mshv_state); + if (ret =3D=3D 0) { + memcpy(state, buffer, sizeof(*state)); + } + qemu_vfree(buffer); + if (ret < 0) { + error_report("failed to get lapic"); + return -1; + } + + return 0; +} + +static uint32_t set_apic_delivery_mode(uint32_t reg, uint32_t mode) +{ + return ((reg) & ~0x700) | ((mode) << 8); +} + +static int set_vp_state(int cpu_fd, const mshv_get_set_vp_state *state) +{ + int ret; + + ret =3D ioctl(cpu_fd, MSHV_SET_VP_STATE, state); + if (ret < 0) { + error_report("failed to set partition state: %s", strerror(errno)); + return -1; + } + + return 0; +} + +static int set_lapic(int cpu_fd, + const struct hv_local_interrupt_controller_state *sta= te) +{ + int ret; + size_t size =3D 4096; + /* buffer aligned to 4k, as *state requires that */ + void *buffer =3D qemu_memalign(size, size); + struct mshv_get_set_vp_state mshv_state =3D { 0 }; + + if (!state) { + error_report("lapic state is NULL"); + return -1; + } + memcpy(buffer, state, sizeof(*state)); + + mshv_state.buf_ptr =3D (uint64_t) buffer; + mshv_state.buf_sz =3D size; + mshv_state.type =3D MSHV_VP_STATE_LAPIC; + + ret =3D set_vp_state(cpu_fd, &mshv_state); + qemu_vfree(buffer); + if (ret < 0) { + error_report("failed to set lapic: %s", strerror(errno)); + return -1; + } + + return 0; +} + +static int set_lint(int cpu_fd) +{ + int ret; + uint32_t *lvt_lint0, *lvt_lint1; + + struct hv_local_interrupt_controller_state lapic_state =3D { 0 }; + ret =3D get_lapic(cpu_fd, &lapic_state); + if (ret < 0) { + return ret; + } + + lvt_lint0 =3D &lapic_state.apic_lvt_lint0; + *lvt_lint0 =3D set_apic_delivery_mode(*lvt_lint0, APIC_MODE_EXTINT); + + lvt_lint1 =3D &lapic_state.apic_lvt_lint1; + *lvt_lint1 =3D set_apic_delivery_mode(*lvt_lint1, APIC_MODE_NMI); + + /* TODO: should we skip setting lapic if the values are the same? */ + + return set_lapic(cpu_fd, &lapic_state); +} + /* * TODO: populate topology info: * @@ -556,6 +669,7 @@ int mshv_configure_vcpu(const CPUState *cpu, const stru= ct MshvFPU *fpu, uint64_t xcr0) { int ret; + int cpu_fd =3D mshv_vcpufd(cpu); =20 ret =3D set_cpu_state(cpu, fpu, xcr0); if (ret < 0) { @@ -563,6 +677,12 @@ int mshv_configure_vcpu(const CPUState *cpu, const str= uct MshvFPU *fpu, return -1; } =20 + ret =3D set_lint(cpu_fd); + if (ret < 0) { + error_report("failed to set lpic int"); + return -1; + } + return 0; } =20 --=20 2.34.1