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Tue, 20 May 2025 04:05:37 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFUw2cXljvCSutROYFW3Mdqws4CmPEUGC/f872J0I+xkvn4QpQTlEgMWW50kLldGYlDmSMGiQ== X-Received: by 2002:a17:907:94d0:b0:ad2:2949:bdfc with SMTP id a640c23a62f3a-ad536b7ca51mr1548030466b.3.1747739137256; Tue, 20 May 2025 04:05:37 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Rakesh Jeyasingh , Thomas Huth Subject: [PULL 03/35] hw/pci-host/gt64120: Fix endianness handling Date: Tue, 20 May 2025 13:04:58 +0200 Message-ID: <20250520110530.366202-4-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250520110530.366202-1-pbonzini@redhat.com> References: <20250520110530.366202-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.487, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1747739162149116600 Content-Type: text/plain; charset="utf-8" From: Rakesh Jeyasingh The GT-64120 PCI controller requires special handling where: 1. Host bridge(bus 0 ,device 0) must never be byte-swapped 2. Other devices follow MByteSwap bit in GT_PCI0_CMD The previous implementation incorrectly swapped all accesses, breaking host bridge detection (lspci -d 11ab:4620). Changes made: 1. Removed gt64120_update_pci_cfgdata_mapping() and moved data_mem initiali= zation to gt64120_realize() for cleaner setup 2. Implemented custom read/write handlers that: - Preserve host bridge accesses (extract32(config_reg,11,13)=3D=3D0) - apply swapping only for non-bridge devices in big-endian mode Fixes: 145e2198 ("hw/mips/gt64xxx_pci: Endian-swap using PCI_HOST_BRIDGE Me= moryRegionOps") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2826 Signed-off-by: Rakesh Jeyasingh Tested-by: Thomas Huth Link: https://lore.kernel.org/r/20250429170354.150581-2-rakeshjb010@gmail.c= om Signed-off-by: Paolo Bonzini --- hw/pci-host/gt64120.c | 82 +++++++++++++++++++++++++------------------ 1 file changed, 48 insertions(+), 34 deletions(-) diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c index 56a6ef93b7a..b12a25696c4 100644 --- a/hw/pci-host/gt64120.c +++ b/hw/pci-host/gt64120.c @@ -320,38 +320,6 @@ static void gt64120_isd_mapping(GT64120State *s) memory_region_transaction_commit(); } =20 -static void gt64120_update_pci_cfgdata_mapping(GT64120State *s) -{ - /* Indexed on MByteSwap bit, see Table 158: PCI_0 Command, Offset: 0xc= 00 */ - static const MemoryRegionOps *pci_host_data_ops[] =3D { - &pci_host_data_be_ops, &pci_host_data_le_ops - }; - PCIHostState *phb =3D PCI_HOST_BRIDGE(s); - - memory_region_transaction_begin(); - - /* - * The setting of the MByteSwap bit and MWordSwap bit in the PCI Inter= nal - * Command Register determines how data transactions from the CPU to/f= rom - * PCI are handled along with the setting of the Endianness bit in the= CPU - * Configuration Register. See: - * - Table 16: 32-bit PCI Transaction Endianness - * - Table 158: PCI_0 Command, Offset: 0xc00 - */ - - if (memory_region_is_mapped(&phb->data_mem)) { - memory_region_del_subregion(&s->ISD_mem, &phb->data_mem); - object_unparent(OBJECT(&phb->data_mem)); - } - memory_region_init_io(&phb->data_mem, OBJECT(phb), - pci_host_data_ops[s->regs[GT_PCI0_CMD] & 1], - s, "pci-conf-data", 4); - memory_region_add_subregion_overlap(&s->ISD_mem, GT_PCI0_CFGDATA << 2, - &phb->data_mem, 1); - - memory_region_transaction_commit(); -} - static void gt64120_pci_mapping(GT64120State *s) { memory_region_transaction_begin(); @@ -645,7 +613,6 @@ static void gt64120_writel(void *opaque, hwaddr addr, case GT_PCI0_CMD: case GT_PCI1_CMD: s->regs[saddr] =3D val & 0x0401fc0f; - gt64120_update_pci_cfgdata_mapping(s); break; case GT_PCI0_TOR: case GT_PCI0_BS_SCS10: @@ -1024,6 +991,48 @@ static const MemoryRegionOps isd_mem_ops =3D { }, }; =20 +static bool bswap(const GT64120State *s)=20 +{ + PCIHostState *phb =3D PCI_HOST_BRIDGE(s); + /*check for bus =3D=3D 0 && device =3D=3D 0, Bits 11:15 =3D Device , B= its 16:23 =3D Bus*/ + bool is_phb_dev0 =3D extract32(phb->config_reg, 11, 13) =3D=3D 0; + bool le_mode =3D FIELD_EX32(s->regs[GT_PCI0_CMD], GT_PCI0_CMD, MByteSw= ap); + /* Only swap for non-bridge devices in big-endian mode */ + return !le_mode && !is_phb_dev0; +} + +static uint64_t gt64120_pci_data_read(void *opaque, hwaddr addr, unsigned = size) +{ + GT64120State *s =3D opaque; + uint32_t val =3D pci_host_data_le_ops.read(opaque, addr, size); + + if (bswap(s)) { + val =3D bswap32(val); + } + return val; +} + +static void gt64120_pci_data_write(void *opaque, hwaddr addr,=20 + uint64_t val, unsigned size) +{ + GT64120State *s =3D opaque; + + if (bswap(s)) { + val =3D bswap32(val);=20 + } + pci_host_data_le_ops.write(opaque, addr, val, size); =20 +} + +static const MemoryRegionOps gt64120_pci_data_ops =3D { + .read =3D gt64120_pci_data_read, + .write =3D gt64120_pci_data_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + static void gt64120_reset(DeviceState *dev) { GT64120State *s =3D GT64120_PCI_HOST_BRIDGE(dev); @@ -1178,7 +1187,6 @@ static void gt64120_reset(DeviceState *dev) =20 gt64120_isd_mapping(s); gt64120_pci_mapping(s); - gt64120_update_pci_cfgdata_mapping(s); } =20 static void gt64120_realize(DeviceState *dev, Error **errp) @@ -1202,6 +1210,12 @@ static void gt64120_realize(DeviceState *dev, Error = **errp) memory_region_add_subregion_overlap(&s->ISD_mem, GT_PCI0_CFGADDR << 2, &phb->conf_mem, 1); =20 + memory_region_init_io(&phb->data_mem, OBJECT(phb), + >64120_pci_data_ops, + s, "pci-conf-data", 4); + memory_region_add_subregion_overlap(&s->ISD_mem, GT_PCI0_CFGDATA << 2, + &phb->data_mem, 1); + =20 /* * The whole address space decoded by the GT-64120A doesn't generate --=20 2.49.0