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envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.487, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1747739362987116600 Content-Type: text/plain; charset="utf-8" Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 113 +++++++++++++-------------------------------- 1 file changed, 31 insertions(+), 82 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8b82a1b7b33..2b26f23bd0a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -485,38 +485,7 @@ static void set_satp_mode_default_map(RISCVCPU *cpu) } #endif =20 -static void riscv_max_cpu_init(Object *obj) -{ - RISCVCPU *cpu =3D RISCV_CPU(obj); - CPURISCVState *env =3D &cpu->env; - - cpu->cfg.mmu =3D true; - cpu->cfg.pmp =3D true; - - env->priv_ver =3D PRIV_VERSION_LATEST; -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(RISCV_CPU(obj), - riscv_cpu_mxl(&RISCV_CPU(obj)->env) =3D=3D MXL_RV32 ? - VM_1_10_SV32 : VM_1_10_SV57); -#endif -} - #if defined(TARGET_RISCV64) -static void rv64_base_cpu_init(Object *obj) -{ - RISCVCPU *cpu =3D RISCV_CPU(obj); - CPURISCVState *env =3D &cpu->env; - - cpu->cfg.mmu =3D true; - cpu->cfg.pmp =3D true; - - /* Set latest version of privileged specification */ - env->priv_ver =3D PRIV_VERSION_LATEST; -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); -#endif -} - static void rv64_sifive_u_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); @@ -717,41 +686,11 @@ static void rv64_xiangshan_nanhu_cpu_init(Object *obj) #endif } =20 -#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) -static void rv128_base_cpu_init(Object *obj) -{ - RISCVCPU *cpu =3D RISCV_CPU(obj); - CPURISCVState *env =3D &cpu->env; - - cpu->cfg.mmu =3D true; - cpu->cfg.pmp =3D true; - - /* Set latest version of privileged specification */ - env->priv_ver =3D PRIV_VERSION_LATEST; - set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); -} -#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ - #endif /* !TARGET_RISCV64 */ =20 #if defined(TARGET_RISCV32) || \ (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY)) =20 -static void rv32_base_cpu_init(Object *obj) -{ - RISCVCPU *cpu =3D RISCV_CPU(obj); - CPURISCVState *env =3D &cpu->env; - - cpu->cfg.mmu =3D true; - cpu->cfg.pmp =3D true; - - /* Set latest version of privileged specification */ - env->priv_ver =3D PRIV_VERSION_LATEST; -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); -#endif -} - static void rv32_sifive_u_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); @@ -3166,19 +3105,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, c= har *nodename) } #endif =20 -#define DEFINE_DYNAMIC_CPU(type_name, misa_mxl_max_, initfn) \ - { \ - .name =3D (type_name), \ - .parent =3D TYPE_RISCV_DYNAMIC_CPU, \ - .instance_init =3D (initfn), \ - .class_data =3D &(const RISCVCPUDef) { \ - .misa_mxl_max =3D (misa_mxl_max_), \ - .priv_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ - .vext_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ - .cfg.max_satp_mode =3D -1, \ - }, \ - } - #define DEFINE_VENDOR_CPU(type_name, misa_mxl_max_, initfn) \ { \ .name =3D (type_name), \ @@ -3235,7 +3161,12 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .class_base_init =3D riscv_cpu_class_base_init, }, =20 - DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_DYNAMIC_CPU, TYPE_RISCV_CPU), + DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_DYNAMIC_CPU, TYPE_RISCV_CPU, + .cfg.mmu =3D true, + .cfg.pmp =3D true, + .priv_spec =3D PRIV_VERSION_LATEST, + ), + DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_VENDOR_CPU, TYPE_RISCV_CPU), DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_BARE_CPU, TYPE_RISCV_CPU, /* @@ -3263,15 +3194,23 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { #endif ), =20 + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_MAX, TYPE_RISCV_DYNAMIC_CPU, #if defined(TARGET_RISCV32) - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV32, riscv_max_cpu_= init), + .misa_mxl_max =3D MXL_RV32, + .cfg.max_satp_mode =3D VM_1_10_SV32, #elif defined(TARGET_RISCV64) - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV64, riscv_max_cpu_= init), + .misa_mxl_max =3D MXL_RV64, + .cfg.max_satp_mode =3D VM_1_10_SV57, #endif + ), =20 #if defined(TARGET_RISCV32) || \ (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY)) - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, MXL_RV32, rv32_base_cpu_= init), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE32, TYPE_RISCV_DYNAMIC_CPU, + .cfg.max_satp_mode =3D VM_1_10_SV32, + .misa_mxl_max =3D MXL_RV32, + ), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, MXL_RV32, rv32_ibex_cpu_= init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, MXL_RV32, rv32_sifive_e_= cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, MXL_RV32, rv32_imafcu_no= mmu_cpu_init), @@ -3288,11 +3227,18 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { #endif =20 #if (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY)) - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX32, MXL_RV32, riscv_max_cpu_= init), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_MAX32, TYPE_RISCV_DYNAMIC_CPU, + .cfg.max_satp_mode =3D VM_1_10_SV32, + .misa_mxl_max =3D MXL_RV32, + ), #endif =20 #if defined(TARGET_RISCV64) - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, MXL_RV64, rv64_base_cpu_= init), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE64, TYPE_RISCV_DYNAMIC_CPU, + .cfg.max_satp_mode =3D VM_1_10_SV57, + .misa_mxl_max =3D MXL_RV64, + ), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64, rv64_sifive_e_= cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64, rv64_sifive_u_= cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64, rv64_sifive_u_= cpu_init), @@ -3302,8 +3248,11 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU, MXL_RV64, rv64_xiangshan_= nanhu_cpu_init), #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu= _init), -#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU, + .cfg.max_satp_mode =3D VM_1_10_SV57, + .misa_mxl_max =3D MXL_RV128, + ), +#endif /* CONFIG_TCG */ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV64I, TYPE_RISCV_BARE_CPU, .misa_mxl_max =3D MXL_RV64, .misa_ext =3D RVI --=20 2.49.0