From nobody Sat Nov 15 22:24:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1747726620; cv=none; d=zohomail.com; s=zohoarc; b=gspc9LfsOc1317zOwsX3Lg3Uwwq+Mf/p9ZGHFwam8UULzCy3Ia9qL1Ae7FNox1VPItvDAy88RQFKpf4brWhnzKiJxdYiZSYpruCkX3pP/aV/X8YokXFLqsSRrIn/HL1t+cC/2EYmC3RX7JRR4aTJxbfn4LfajU27HjqS8eZZZ1A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747726620; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=vlBSIVHkFH978bCqALFckfDd+uWXf0feBWEpApKTbe4=; b=R7Q97PDC9aW4ydg0U7vpVZE6R153ABk9nqZx+/5wKt/RqLe3gxZSdzEj/T/BEZUxCmuX42PPtMrbHJ3khpfH/9n1dW9TOCuUglPg/5OunAhs5DjK8yIGUxsXOvZm5vHSetNXccU45GJO+gBvujw2WID/LPIBGAWsIrDFlgo/7kw= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747726620590445.15889984223895; Tue, 20 May 2025 00:37:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uHHWD-0002jP-1c; Tue, 20 May 2025 03:36:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uHHW7-0002TN-GU; Tue, 20 May 2025 03:36:03 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uHHW5-0003tR-AA; Tue, 20 May 2025 03:36:02 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 20 May 2025 15:35:41 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 20 May 2025 15:35:41 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 3/3] hw/arm/aspeed_ast27x0: Fix RAM size detection failure on BE hosts Date: Tue, 20 May 2025 15:35:39 +0800 Message-ID: <20250520073540.2014240-4-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250520073540.2014240-1-jamin_lin@aspeedtech.com> References: <20250520073540.2014240-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1747726621331116600 Content-Type: text/plain; charset="utf-8" On big-endian hosts, the aspeed_ram_capacity_write() function previously pa= ssed the address of a 64-bit "data" variable directly to address_space_write(), assuming host and guest endianness matched. However, the data is expected to be written in little-endian format to DRAM. On big-endian hosts, this led to incorrect data being written into DRAM, which caused the guest firmware to misdetect the DRAM size. As a result, U-Boot fails to boot and hangs. - Explicitly converting the 32-bit portion of "data" to little-endian format using cpu_to_le32(), storing it in a temporary "uint32_t le_data". - Updating the MemoryRegionOps to restrict access to exactly 4 bytes using .valid.{min,max}_access_size =3D 4 and .impl.min_access_size =3D 4. Signed-off-by: Jamin Lin Fixes: 7436db1 ("aspeed/soc: fix incorrect dram size for AST2700") --- hw/arm/aspeed_ast27x0.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 1974a25766..7ed0919b3f 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -335,24 +335,34 @@ static void aspeed_ram_capacity_write(void *opaque, h= waddr addr, uint64_t data, AspeedSoCState *s =3D ASPEED_SOC(opaque); ram_addr_t ram_size; MemTxResult result; + uint32_t le_data; =20 ram_size =3D object_property_get_uint(OBJECT(&s->sdmc), "ram-size", &error_abort); =20 assert(ram_size > 0); =20 + if (size !=3D 4) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Unsupported write size: %d (only 4-byte allowed= )\n", + __func__, size); + return; + } + + le_data =3D cpu_to_le32((uint32_t)data); + /* * Emulate ddr capacity hardware behavior. * If writes the data to the address which is beyond the ram size, * it would write the data to the "address % ram_size". */ result =3D address_space_write(&s->dram_as, addr % ram_size, - MEMTXATTRS_UNSPECIFIED, &data, 4); + MEMTXATTRS_UNSPECIFIED, &le_data, 4); if (result !=3D MEMTX_OK) { qemu_log_mask(LOG_GUEST_ERROR, "%s: DRAM write failed, addr:0x%" HWADDR_PRIx - ", data :0x%" PRIx64 "\n", - __func__, addr % ram_size, data); + ", data :0x%x\n", + __func__, addr % ram_size, le_data); } } =20 @@ -360,9 +370,10 @@ static const MemoryRegionOps aspeed_ram_capacity_ops = =3D { .read =3D aspeed_ram_capacity_read, .write =3D aspeed_ram_capacity_write, .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl.min_access_size =3D 4, .valid =3D { - .min_access_size =3D 1, - .max_access_size =3D 8, + .min_access_size =3D 4, + .max_access_size =3D 4, }, }; =20 --=20 2.43.0