From nobody Mon Sep 8 21:24:26 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747666330; cv=none; d=zohomail.com; s=zohoarc; b=BhlMImnpxtSTOa1SZfj6pNCQJEVIS+iTjyYKICMuN1rNKNoW6tIePd/KUeDGosPW3xvfugcs1SSw3wEhcJchPD9KNfKzSvUTw4kFEZw7ZA8wgUheugNX+ER5ZlppQ8DuFU+z4kX1AEzDdKWg+njkYHBneDzOCBqJccsDdlMeiHc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747666330; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=rLeYSMExit9M+e09aBWpDZdYMYM/Zp11cwRyipN7UwE=; b=j51KxpJVj/GmSgE2idQybrHX9jwAi4Q/JhGat9jEyzPaVoWRdu7tO6dyDyFYR9Ufi2vsItYlDXkwIfkPx2EjAlmr0dUL18ephC0H4W9MomNIQujoHL7uzI4fFL6F+KBJ3uapaNBhRcMdal7IPG1e7liFvGZ0SZIjA3gETw/qqho= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747666330188843.2858582050947; Mon, 19 May 2025 07:52:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uH1pv-0000Q8-5n; Mon, 19 May 2025 10:51:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uH1pt-0000PW-G6 for qemu-devel@nongnu.org; Mon, 19 May 2025 10:51:25 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uH1pq-000126-OZ for qemu-devel@nongnu.org; Mon, 19 May 2025 10:51:25 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-43edecbfb94so48589505e9.1 for ; Mon, 19 May 2025 07:51:19 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442fd50b9b2sm145672035e9.12.2025.05.19.07.51.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 May 2025 07:51:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747666278; x=1748271078; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rLeYSMExit9M+e09aBWpDZdYMYM/Zp11cwRyipN7UwE=; b=wKtJneHTpyLwrZBJTH5+ZXz80iwBpTjEsZUYyRziJEMFfve8d+LhemRsV8DTWxXMH2 rzDviQ54feealtr+cndcQYbkXWWse7p+RMgUopT9ng/N7P/Px5mRvUJMAIxFWZ9v5NP8 rcImycuW1usLWYRlYec2Q3YRwCX4HbgaqhXlFx1aEcQrzuXWcOHqfC1C55hQjoqkwJGu xD0bo71jl5WBAHbgXLJei3+04dAIdIKOI2Q8MAYyJje2gEe5sDhIOP3Dba8gJR8P32pL k8t5nmrQKfdoY9u2Pxzdvkheez4Ywcf8f7G5X1lizUPNFAsFwoyDyt1betaZa/flaN9Z TqQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747666278; x=1748271078; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rLeYSMExit9M+e09aBWpDZdYMYM/Zp11cwRyipN7UwE=; b=I8YaB5eTGSg2zee5+MCeVizmE6UoGZ4yOAEpEx3fwtWKwDvb/KHxxuY/aZgei4KzoO wsHOob1ce5c3Ft5eukhQKOuMZB2jIp4mP0pjahm3ZIX5JKes9psWQR62PMotmi1d++U2 4m/zpcPMKHsYqFkkBncZeu36UMkVSDFqqm0D5WXtJPboVGEIzxgqguT3ZA9rhkimrNrp GIUoA4ZtbYIfNK190O61NBPniH/ES4/I/jg48UWL8+wdK44C1Aw9rEm59SNanJBDWjHD SnwSjKFdt/WMw85z6eKvfGpXv9TpSUbhDxEssAAytBtFnXMaLyninXJIjyTEpTbVwLMd wB8A== X-Gm-Message-State: AOJu0YxqNjuSpDE19RD079Fv+te5mKixypILYihgl+Ww3yv34rR0xw72 8R2ARedSKRJuFtLYiv3n2XfkbmR6r0vV8uH0kJyU6XRS0BvkuO3khvsJg/M0uGppOWOsul8C8Kr /ZA+T X-Gm-Gg: ASbGncv06U9NfX5tzdKQjBeFApmIZG5xemLlMkjsuIadOnpjSWaVHZZjSrv4D5NZ5Yh zWjA6llNojo/zGofA5gxWKMWDsLT9hrCgn4cohtY6/cwQZV/JTIr7fL+gUMcYdfqHO5pi9a7/Yv gKK4q5bRDF5pbQw0OS4A+uOVUp6uYSnYIvbhfyhErFxgASoclpS2BF3PKlSfYaOX6sRmxN3IhZO tsaaKSegb508+MJa7CMkW42INjoZMrwUnS2PJ41Rmn3is1WYvwF3k6AzHoF8FrtMb1L7rkeGkWw HIhBag52XiawfR7O9tchM9nZ455Z2h5EekdorHHI2Yfp8xBaKQBXdNhuug== X-Google-Smtp-Source: AGHT+IHtYZK6pZLdZE0fhDdTE44bP59UvutwMINzbtlcp7w4Twgt5lSdGxc1HMg7MONOOY4kKl1eaQ== X-Received: by 2002:a05:600c:a012:b0:43c:e70d:44f0 with SMTP id 5b1f17b1804b1-442fd63bfa4mr115504035e9.19.1747666277757; Mon, 19 May 2025 07:51:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Richard Henderson , Zhao Liu , Paolo Bonzini , Eduardo Habkost Subject: [PATCH v2 1/4] target/i386: Detect flush-to-zero after rounding Date: Mon, 19 May 2025 15:51:11 +0100 Message-ID: <20250519145114.2786534-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250519145114.2786534-1-peter.maydell@linaro.org> References: <20250519145114.2786534-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747666331388116600 Content-Type: text/plain; charset="utf-8" The Intel SDM section 10.2.3.3 on the MXCSR.FTZ bit says that we flush outputs to zero when we detect underflow, which is after rounding. Set the detect_ftz flag accordingly. This allows us to enable the test in fma.c which checks this behaviour. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Zhao Liu --- target/i386/tcg/fpu_helper.c | 8 ++++---- tests/tcg/x86_64/fma.c | 5 ----- 2 files changed, 4 insertions(+), 9 deletions(-) diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 1cbadb14533..9ea67ea76c8 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -189,13 +189,13 @@ void cpu_init_fp_statuses(CPUX86State *env) set_float_default_nan_pattern(0b11000000, &env->mmx_status); set_float_default_nan_pattern(0b11000000, &env->sse_status); /* - * TODO: x86 does flush-to-zero detection after rounding (the SDM + * x86 does flush-to-zero detection after rounding (the SDM * section 10.2.3.3 on the FTZ bit of MXCSR says that we flush * when we detect underflow, which x86 does after rounding). */ - set_float_ftz_detection(float_ftz_before_rounding, &env->fp_status); - set_float_ftz_detection(float_ftz_before_rounding, &env->mmx_status); - set_float_ftz_detection(float_ftz_before_rounding, &env->sse_status); + set_float_ftz_detection(float_ftz_after_rounding, &env->fp_status); + set_float_ftz_detection(float_ftz_after_rounding, &env->mmx_status); + set_float_ftz_detection(float_ftz_after_rounding, &env->sse_status); } =20 static inline uint8_t save_exception_flags(CPUX86State *env) diff --git a/tests/tcg/x86_64/fma.c b/tests/tcg/x86_64/fma.c index 09c622ebc00..46f863005ed 100644 --- a/tests/tcg/x86_64/fma.c +++ b/tests/tcg/x86_64/fma.c @@ -79,14 +79,9 @@ static testdata tests[] =3D { /* * Flushing of denormal outputs to zero should also happen after * rounding, so setting FTZ should not affect the result or the flags. - * QEMU currently does not emulate this correctly because we do the - * flush-to-zero check before rounding, so we incorrectly produce a - * zero result and set Underflow as well as Precision. */ -#ifdef ENABLE_FAILING_TESTS { 0x3fdfffffffffffff, 0x001fffffffffffff, 0x801fffffffffffff, true, 0x8010000000000000, 0x20 }, /* Enabling FTZ shouldn't change flags */ -#endif }; =20 int main(void) --=20 2.43.0 From nobody Mon Sep 8 21:24:26 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747666326; cv=none; d=zohomail.com; s=zohoarc; b=OU1Z1QAp7v4H4NBRd0hJ8ZvayvZvSDTHXFBuCEesyz/qkUaZQ15hTXJl+pAyCu6TOEmj6/sjYskSVikw/saeNFAHUbgHOwJxKclvLghcvs4Mq0TBtF9aamIUhiO+cnNajkysgg674SXPaBiyEE5IoHija/fYpIHlIb9zHTOHzgU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747666326; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=7ucPDBJC4UWinthzj8Yzwx+/14dHP1IlAgfkUOwkWu8=; b=MYXi7kjhuYJoZYGYyr0ElDURfhwbJDHII2sw+6QCcqL1no20k0nO+xcvovi0zc7hRbpBW1HXYcNoQuOo0g3K9tqzmI6mwbQJapvkQ89pk/k/E0Du7ceyrbmZnKcKoaiKuAOaVuzPo+jRONxb90WyixyNSNMgu3Umt05GkdyymoE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747666326121101.22605192892263; Mon, 19 May 2025 07:52:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uH1pw-0000RF-9v; Mon, 19 May 2025 10:51:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uH1pt-0000PS-Da for qemu-devel@nongnu.org; Mon, 19 May 2025 10:51:25 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uH1pp-00012E-K8 for qemu-devel@nongnu.org; Mon, 19 May 2025 10:51:24 -0400 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-3a376da332aso330064f8f.3 for ; Mon, 19 May 2025 07:51:20 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442fd50b9b2sm145672035e9.12.2025.05.19.07.51.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 May 2025 07:51:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747666279; x=1748271079; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7ucPDBJC4UWinthzj8Yzwx+/14dHP1IlAgfkUOwkWu8=; b=V+wxPywy5kbPeC2B2SPN05oi+yOfHSK3QM8pPzgue4DCdS5j3cabNvEQEcyBSXKw8A 9YFe3o091kAGWDgcy9y0TkAMMVbaAKXp4US5EWfwBz+W2mPK3jDkH/lN97eeto5TId8I vzpUH/GWVw1AXOcbdI+qGWFNQA+DAXBoccBo1x4QiMV67p+Aawv4T0Olt0DiXMPLWfbi iGfe9jRRrP2GEOzn9E7c5lUuxlCyWBuWioC4p8K+1CFVdUnOa4v2diEWGj+Ehbk+fi/F bUKwEgitzY6eM3Dzg/xIAyZWIqn+XZyM6SG2dJ4q0BUUCU5+rgXEwH6LbSSxq+32AyHe a7Xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747666279; x=1748271079; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7ucPDBJC4UWinthzj8Yzwx+/14dHP1IlAgfkUOwkWu8=; b=vwM4wk0P+l3FwqNaborMGfC7Y3CMZRGdspa80AN7ktdFh3/F17N0dZcsUElY5l0kVv oNCrSUhblbMfaoNxqlMj2wx88DFH3GuhtxCVKwkJ7B340Wh67/DZlpy2ZmpTEqgM5gmO DmghUxAlsSl1aYognWgmt94mByWShvxaF8VhDQMIlI3lzgPfIAbRngTzmfM7rnp/iuU+ NYCIpiagNiBmkDcqxOLAozsRYJcqzmAmQxJ3NOqppfQUJ3Qcq2L9F5vGAPkCO7wMOPfO WV7TenRD+WnVlZMRM20JIsgNhy6BJBjsG8s7ld/+LUpgbNknCU1P6OsCm4HE+Xj5OtWV bY5Q== X-Gm-Message-State: AOJu0Yxtd5aAOBa15n3kBIyxXeeZLW9G4NqtIYc35jQeaicdj4EDjBCN uYA4r2nNzvP1SqwYVKJE0Pkks1hXzZUn7F0XKruGYAtllyg9ejSHj4VyU0nd2tiOOJuPFhMXve+ Cx8vB X-Gm-Gg: ASbGncthNzGj8kLtRMAM3cnD9xA451rRHM9828iiERVIvbZ7FY4oHk2GBjrrC29syAj sjnhkEvSyS9dzwHR2+qIEpLnovpxGalFMp9ke+smXoSG3mxiDg615/UmztA2f30OwDoC3g1kXK0 OD6EZ9Z0CNI02Z7+NgKsoZJxH93ULGKWzeNl0msFt14g3bIdu8bSu6nD5CQ8ki98faCaKL3Zik+ +S2HrUTDCXh7Q24ywoYuQTfvAME54SjTLV99uqRb3/mOSrvM8VCvdq/a6/JwYyvmmvDe+QjeSTh GcVyLtmwYYsjwaDzjr2QlRKHZtUp/I8UoBQW/Dary7/P5MRTBdR8K8CnjQ== X-Google-Smtp-Source: AGHT+IF0LlXlu3PVCDS7v97e5pvMY0ApReIEh1kVKhNmpyPfko31/B6N+Wq1P/JJR5mWux9vFY0+Sg== X-Received: by 2002:a05:6000:1862:b0:3a1:f69f:3341 with SMTP id ffacd0b85a97d-3a35fe929c0mr9808921f8f.26.1747666278797; Mon, 19 May 2025 07:51:18 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Richard Henderson , Zhao Liu , Paolo Bonzini , Eduardo Habkost Subject: [PATCH v2 2/4] target/i386: Use correct type for get_float_exception_flags() values Date: Mon, 19 May 2025 15:51:12 +0100 Message-ID: <20250519145114.2786534-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250519145114.2786534-1-peter.maydell@linaro.org> References: <20250519145114.2786534-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747666333414116600 The softfloat get_float_exception_flags() function returns 'int', but in various places in target/i386 we incorrectly store the returned value into a uint8_t. This currently has no ill effects because i386 doesn't care about any of the float_flag enum values above 0x40. However, we want to start using float_flag_input_denormal_used, which is 0x4000. Switch to using 'int' so that we can handle all the possible valid float_flag_* values. This includes changing the return type of save_exception_flags() and the argument to merge_exception_flags(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Zhao Liu --- target/i386/ops_sse.h | 16 +++---- target/i386/tcg/fpu_helper.c | 82 ++++++++++++++++++------------------ 2 files changed, 49 insertions(+), 49 deletions(-) diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h index f0aa1894aa2..a2e4d480399 100644 --- a/target/i386/ops_sse.h +++ b/target/i386/ops_sse.h @@ -842,7 +842,7 @@ int64_t helper_cvttsd2sq(CPUX86State *env, ZMMReg *s) =20 void glue(helper_rsqrtps, SUFFIX)(CPUX86State *env, ZMMReg *d, ZMMReg *s) { - uint8_t old_flags =3D get_float_exception_flags(&env->sse_status); + int old_flags =3D get_float_exception_flags(&env->sse_status); int i; for (i =3D 0; i < 2 << SHIFT; i++) { d->ZMM_S(i) =3D float32_div(float32_one, @@ -855,7 +855,7 @@ void glue(helper_rsqrtps, SUFFIX)(CPUX86State *env, ZMM= Reg *d, ZMMReg *s) #if SHIFT =3D=3D 1 void helper_rsqrtss(CPUX86State *env, ZMMReg *d, ZMMReg *v, ZMMReg *s) { - uint8_t old_flags =3D get_float_exception_flags(&env->sse_status); + int old_flags =3D get_float_exception_flags(&env->sse_status); int i; d->ZMM_S(0) =3D float32_div(float32_one, float32_sqrt(s->ZMM_S(0), &env->sse_status), @@ -869,7 +869,7 @@ void helper_rsqrtss(CPUX86State *env, ZMMReg *d, ZMMReg= *v, ZMMReg *s) =20 void glue(helper_rcpps, SUFFIX)(CPUX86State *env, ZMMReg *d, ZMMReg *s) { - uint8_t old_flags =3D get_float_exception_flags(&env->sse_status); + int old_flags =3D get_float_exception_flags(&env->sse_status); int i; for (i =3D 0; i < 2 << SHIFT; i++) { d->ZMM_S(i) =3D float32_div(float32_one, s->ZMM_S(i), &env->sse_st= atus); @@ -880,7 +880,7 @@ void glue(helper_rcpps, SUFFIX)(CPUX86State *env, ZMMRe= g *d, ZMMReg *s) #if SHIFT =3D=3D 1 void helper_rcpss(CPUX86State *env, ZMMReg *d, ZMMReg *v, ZMMReg *s) { - uint8_t old_flags =3D get_float_exception_flags(&env->sse_status); + int old_flags =3D get_float_exception_flags(&env->sse_status); int i; d->ZMM_S(0) =3D float32_div(float32_one, s->ZMM_S(0), &env->sse_status= ); for (i =3D 1; i < 2 << SHIFT; i++) { @@ -1714,7 +1714,7 @@ void glue(helper_phminposuw, SUFFIX)(CPUX86State *env= , Reg *d, Reg *s) void glue(helper_roundps, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, uint32_t mode) { - uint8_t old_flags =3D get_float_exception_flags(&env->sse_status); + int old_flags =3D get_float_exception_flags(&env->sse_status); signed char prev_rounding_mode; int i; =20 @@ -1738,7 +1738,7 @@ void glue(helper_roundps, SUFFIX)(CPUX86State *env, R= eg *d, Reg *s, void glue(helper_roundpd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, uint32_t mode) { - uint8_t old_flags =3D get_float_exception_flags(&env->sse_status); + int old_flags =3D get_float_exception_flags(&env->sse_status); signed char prev_rounding_mode; int i; =20 @@ -1763,7 +1763,7 @@ void glue(helper_roundpd, SUFFIX)(CPUX86State *env, R= eg *d, Reg *s, void glue(helper_roundss, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s, uint32_t mode) { - uint8_t old_flags =3D get_float_exception_flags(&env->sse_status); + int old_flags =3D get_float_exception_flags(&env->sse_status); signed char prev_rounding_mode; int i; =20 @@ -1788,7 +1788,7 @@ void glue(helper_roundss, SUFFIX)(CPUX86State *env, R= eg *d, Reg *v, Reg *s, void glue(helper_roundsd, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s, uint32_t mode) { - uint8_t old_flags =3D get_float_exception_flags(&env->sse_status); + int old_flags =3D get_float_exception_flags(&env->sse_status); signed char prev_rounding_mode; int i; =20 diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 9ea67ea76c8..4732b718129 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -198,16 +198,16 @@ void cpu_init_fp_statuses(CPUX86State *env) set_float_ftz_detection(float_ftz_after_rounding, &env->sse_status); } =20 -static inline uint8_t save_exception_flags(CPUX86State *env) +static inline int save_exception_flags(CPUX86State *env) { - uint8_t old_flags =3D get_float_exception_flags(&env->fp_status); + int old_flags =3D get_float_exception_flags(&env->fp_status); set_float_exception_flags(0, &env->fp_status); return old_flags; } =20 -static void merge_exception_flags(CPUX86State *env, uint8_t old_flags) +static void merge_exception_flags(CPUX86State *env, int old_flags) { - uint8_t new_flags =3D get_float_exception_flags(&env->fp_status); + int new_flags =3D get_float_exception_flags(&env->fp_status); float_raise(old_flags, &env->fp_status); fpu_set_exception(env, ((new_flags & float_flag_invalid ? FPUS_IE : 0) | @@ -220,7 +220,7 @@ static void merge_exception_flags(CPUX86State *env, uin= t8_t old_flags) =20 static inline floatx80 helper_fdiv(CPUX86State *env, floatx80 a, floatx80 = b) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); floatx80 ret =3D floatx80_div(a, b, &env->fp_status); merge_exception_flags(env, old_flags); return ret; @@ -240,7 +240,7 @@ static void fpu_raise_exception(CPUX86State *env, uintp= tr_t retaddr) =20 void helper_flds_FT0(CPUX86State *env, uint32_t val) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); union { float32 f; uint32_t i; @@ -253,7 +253,7 @@ void helper_flds_FT0(CPUX86State *env, uint32_t val) =20 void helper_fldl_FT0(CPUX86State *env, uint64_t val) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); union { float64 f; uint64_t i; @@ -271,7 +271,7 @@ void helper_fildl_FT0(CPUX86State *env, int32_t val) =20 void helper_flds_ST0(CPUX86State *env, uint32_t val) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); int new_fpstt; union { float32 f; @@ -288,7 +288,7 @@ void helper_flds_ST0(CPUX86State *env, uint32_t val) =20 void helper_fldl_ST0(CPUX86State *env, uint64_t val) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); int new_fpstt; union { float64 f; @@ -338,7 +338,7 @@ void helper_fildll_ST0(CPUX86State *env, int64_t val) =20 uint32_t helper_fsts_ST0(CPUX86State *env) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); union { float32 f; uint32_t i; @@ -351,7 +351,7 @@ uint32_t helper_fsts_ST0(CPUX86State *env) =20 uint64_t helper_fstl_ST0(CPUX86State *env) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); union { float64 f; uint64_t i; @@ -364,7 +364,7 @@ uint64_t helper_fstl_ST0(CPUX86State *env) =20 int32_t helper_fist_ST0(CPUX86State *env) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); int32_t val; =20 val =3D floatx80_to_int32(ST0, &env->fp_status); @@ -378,7 +378,7 @@ int32_t helper_fist_ST0(CPUX86State *env) =20 int32_t helper_fistl_ST0(CPUX86State *env) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); int32_t val; =20 val =3D floatx80_to_int32(ST0, &env->fp_status); @@ -391,7 +391,7 @@ int32_t helper_fistl_ST0(CPUX86State *env) =20 int64_t helper_fistll_ST0(CPUX86State *env) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); int64_t val; =20 val =3D floatx80_to_int64(ST0, &env->fp_status); @@ -404,7 +404,7 @@ int64_t helper_fistll_ST0(CPUX86State *env) =20 int32_t helper_fistt_ST0(CPUX86State *env) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); int32_t val; =20 val =3D floatx80_to_int32_round_to_zero(ST0, &env->fp_status); @@ -418,7 +418,7 @@ int32_t helper_fistt_ST0(CPUX86State *env) =20 int32_t helper_fisttl_ST0(CPUX86State *env) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); int32_t val; =20 val =3D floatx80_to_int32_round_to_zero(ST0, &env->fp_status); @@ -431,7 +431,7 @@ int32_t helper_fisttl_ST0(CPUX86State *env) =20 int64_t helper_fisttll_ST0(CPUX86State *env) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); int64_t val; =20 val =3D floatx80_to_int64_round_to_zero(ST0, &env->fp_status); @@ -527,7 +527,7 @@ static const int fcom_ccval[4] =3D {0x0100, 0x4000, 0x0= 000, 0x4500}; =20 void helper_fcom_ST0_FT0(CPUX86State *env) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); FloatRelation ret; =20 ret =3D floatx80_compare(ST0, FT0, &env->fp_status); @@ -537,7 +537,7 @@ void helper_fcom_ST0_FT0(CPUX86State *env) =20 void helper_fucom_ST0_FT0(CPUX86State *env) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); FloatRelation ret; =20 ret =3D floatx80_compare_quiet(ST0, FT0, &env->fp_status); @@ -549,7 +549,7 @@ static const int fcomi_ccval[4] =3D {CC_C, CC_Z, 0, CC_= Z | CC_P | CC_C}; =20 void helper_fcomi_ST0_FT0(CPUX86State *env) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); int eflags; FloatRelation ret; =20 @@ -562,7 +562,7 @@ void helper_fcomi_ST0_FT0(CPUX86State *env) =20 void helper_fucomi_ST0_FT0(CPUX86State *env) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); int eflags; FloatRelation ret; =20 @@ -575,28 +575,28 @@ void helper_fucomi_ST0_FT0(CPUX86State *env) =20 void helper_fadd_ST0_FT0(CPUX86State *env) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); ST0 =3D floatx80_add(ST0, FT0, &env->fp_status); merge_exception_flags(env, old_flags); } =20 void helper_fmul_ST0_FT0(CPUX86State *env) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); ST0 =3D floatx80_mul(ST0, FT0, &env->fp_status); merge_exception_flags(env, old_flags); } =20 void helper_fsub_ST0_FT0(CPUX86State *env) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); ST0 =3D floatx80_sub(ST0, FT0, &env->fp_status); merge_exception_flags(env, old_flags); } =20 void helper_fsubr_ST0_FT0(CPUX86State *env) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); ST0 =3D floatx80_sub(FT0, ST0, &env->fp_status); merge_exception_flags(env, old_flags); } @@ -615,28 +615,28 @@ void helper_fdivr_ST0_FT0(CPUX86State *env) =20 void helper_fadd_STN_ST0(CPUX86State *env, int st_index) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); ST(st_index) =3D floatx80_add(ST(st_index), ST0, &env->fp_status); merge_exception_flags(env, old_flags); } =20 void helper_fmul_STN_ST0(CPUX86State *env, int st_index) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); ST(st_index) =3D floatx80_mul(ST(st_index), ST0, &env->fp_status); merge_exception_flags(env, old_flags); } =20 void helper_fsub_STN_ST0(CPUX86State *env, int st_index) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); ST(st_index) =3D floatx80_sub(ST(st_index), ST0, &env->fp_status); merge_exception_flags(env, old_flags); } =20 void helper_fsubr_STN_ST0(CPUX86State *env, int st_index) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); ST(st_index) =3D floatx80_sub(ST0, ST(st_index), &env->fp_status); merge_exception_flags(env, old_flags); } @@ -861,7 +861,7 @@ void helper_fbld_ST0(CPUX86State *env, target_ulong ptr) =20 void helper_fbst_ST0(CPUX86State *env, target_ulong ptr) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); int v; target_ulong mem_ref, mem_end; int64_t val; @@ -1136,7 +1136,7 @@ static const struct f2xm1_data f2xm1_table[65] =3D { =20 void helper_f2xm1(CPUX86State *env) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); uint64_t sig =3D extractFloatx80Frac(ST0); int32_t exp =3D extractFloatx80Exp(ST0); bool sign =3D extractFloatx80Sign(ST0); @@ -1369,7 +1369,7 @@ static const struct fpatan_data fpatan_table[9] =3D { =20 void helper_fpatan(CPUX86State *env) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); uint64_t arg0_sig =3D extractFloatx80Frac(ST0); int32_t arg0_exp =3D extractFloatx80Exp(ST0); bool arg0_sign =3D extractFloatx80Sign(ST0); @@ -1808,7 +1808,7 @@ void helper_fpatan(CPUX86State *env) =20 void helper_fxtract(CPUX86State *env) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); CPU_LDoubleU temp; =20 temp.d =3D ST0; @@ -1857,7 +1857,7 @@ void helper_fxtract(CPUX86State *env) =20 static void helper_fprem_common(CPUX86State *env, bool mod) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); uint64_t quotient; CPU_LDoubleU temp0, temp1; int exp0, exp1, expdiff; @@ -2053,7 +2053,7 @@ static void helper_fyl2x_common(CPUX86State *env, flo= atx80 arg, int32_t *exp, =20 void helper_fyl2xp1(CPUX86State *env) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); uint64_t arg0_sig =3D extractFloatx80Frac(ST0); int32_t arg0_exp =3D extractFloatx80Exp(ST0); bool arg0_sign =3D extractFloatx80Sign(ST0); @@ -2151,7 +2151,7 @@ void helper_fyl2xp1(CPUX86State *env) =20 void helper_fyl2x(CPUX86State *env) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); uint64_t arg0_sig =3D extractFloatx80Frac(ST0); int32_t arg0_exp =3D extractFloatx80Exp(ST0); bool arg0_sign =3D extractFloatx80Sign(ST0); @@ -2298,7 +2298,7 @@ void helper_fyl2x(CPUX86State *env) =20 void helper_fsqrt(CPUX86State *env) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); if (floatx80_is_neg(ST0)) { env->fpus &=3D ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */ env->fpus |=3D 0x400; @@ -2324,14 +2324,14 @@ void helper_fsincos(CPUX86State *env) =20 void helper_frndint(CPUX86State *env) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); ST0 =3D floatx80_round_to_int(ST0, &env->fp_status); merge_exception_flags(env, old_flags); } =20 void helper_fscale(CPUX86State *env) { - uint8_t old_flags =3D save_exception_flags(env); + int old_flags =3D save_exception_flags(env); if (floatx80_invalid_encoding(ST1, &env->fp_status) || floatx80_invalid_encoding(ST0, &env->fp_status)) { float_raise(float_flag_invalid, &env->fp_status); @@ -2369,7 +2369,7 @@ void helper_fscale(CPUX86State *env) } else { int n; FloatX80RoundPrec save =3D env->fp_status.floatx80_rounding_precis= ion; - uint8_t save_flags =3D get_float_exception_flags(&env->fp_status); + int save_flags =3D get_float_exception_flags(&env->fp_status); set_float_exception_flags(0, &env->fp_status); n =3D floatx80_to_int32_round_to_zero(ST1, &env->fp_status); set_float_exception_flags(save_flags, &env->fp_status); @@ -3269,7 +3269,7 @@ void update_mxcsr_status(CPUX86State *env) =20 void update_mxcsr_from_sse_status(CPUX86State *env) { - uint8_t flags =3D get_float_exception_flags(&env->sse_status); + int flags =3D get_float_exception_flags(&env->sse_status); /* * The MXCSR denormal flag has opposite semantics to * float_flag_input_denormal_flushed (the softfloat code sets that flag --=20 2.43.0 From nobody Mon Sep 8 21:24:26 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747666339; cv=none; d=zohomail.com; s=zohoarc; b=OgHfVv5x+U17RlnvGKEUOawWCDegD8q5DkXH2UqRVwMagqSUvU+Joq/c8Tg8hgxVcxXuYxLD5QXks218zRidos0Z4ogSUjT71XWiP07I7tQUaKDTGnS7lhQEwwgklpAVc4g13VfyOYdD/sVO+2w4mGmtd1gDifp7rmkncZxgEDg= ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442fd50b9b2sm145672035e9.12.2025.05.19.07.51.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 May 2025 07:51:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747666280; x=1748271080; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BygWdv7/tDO5ALXb8h6QMuJ2wk4/0l16+7gCvaB1RJ0=; b=foX1zpYb7JmLIustiVUDnnEEzJWAJb4n8bVqVnLlguNnOfO5ewx0WslKt521In+l/b 6TK/j3DrI2t2RNDwWd4YQrRw+RFsyK2kSxXwoUJgqtPZHh1J//imsa0iN9Nbq1BV5oPv tZ6l3WIUdMrggSwXPUuvc8pRG1hiRZ8r/NZ8hDJ3IzNcy01n3jOpO5I+OyvGAM1ac4/N YFXWsduU1gz6VwfrSTtilbrU8lXJw1RRb99QSeTeWF5onyH8LQlzXup+rdxMyJNmJU9p WTusoCl+w/prJDkO+qRQlwRzyJ3zdeJQ7YYVHf1mBz3oiwvQvDoF0VO8lw5MEbLoZuYu 5TAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747666280; x=1748271080; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BygWdv7/tDO5ALXb8h6QMuJ2wk4/0l16+7gCvaB1RJ0=; b=pjgeIPsmFO4WtDNozq+GjqBqJGNZveF/MlqfVjuK78jR4wbMGpXPLBaK6cGoEkXU+S rNFuHny3d4e0fA8AtGYFA/TSR609VndMDkyqrIdo4fO5e4Hsj2WLKa6w8UKhadPTp1+2 +ck7D6D86mXSuOD4jQNhylMzkNNtXR4W9jGemfBVqn+aUAAQtGs6rI1oh5nxr/02J1xK Adisf2pijd8f/Txq4MfnJmCK6YgILDftwYajY6SNn0V6URZTrXHp95yPkUm+hq5cbYcA 8VEGtOdUOakXnVt1Jl5+sWJMbp2r5Qva230fctDYzkDXyyiTKSzUKp6i+ZgcbKKe8Xuc 9X6Q== X-Gm-Message-State: AOJu0Yw5ZZFukmduMt96z/MMFYK7+76SrxMo+8xPEHABvifPizf5U6Gl 9JtpHYVz/cd+pI174Cm9tT8ddlKe9yYPa9X3QrDaLw1WZsy+YvDlnSThpfN734cDZ8VwKOJHIfz lY+y6 X-Gm-Gg: ASbGncvFHiT5nte9ip/cn+5cWhuI3px3VIIfWAfOR+1S83JPiK9D9Sodb4JMwGiOeSD rOJybmgQQ9e/hPP4AHnJI/JafAi8bW259i51MaubiKFehF5DLe26FkY4L1SphTDI4UNaLHx3xsk 20BAtgMLb3xySwd7NtCPs11UG9S6cltBcq/2d5evf+BHPCXGFdtYLQ37niJrpWNrwqNVJE7T9h3 rjAKTtpCpnxVzkK5WwrnHBMYOEPaAW62s+Rq0cEJqtKt/nbPs105ZI0Uz7sgBDqBwBbezn+26b6 nbE4h31IZtbvBpT5wP4Lo1Er+Rda9SlG2phgpTdkDoW+XEi+ZCQKmcljDw== X-Google-Smtp-Source: AGHT+IEPHbFdWY2MqGCilpqVun03+uRqCtsMlt3RbVkuFn0b1G4O/dFiaZh9aJhQ0wLhnNessbm+ug== X-Received: by 2002:a05:600c:a42:b0:43b:cc42:c54f with SMTP id 5b1f17b1804b1-442fd6276f7mr120108075e9.14.1747666279767; Mon, 19 May 2025 07:51:19 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Richard Henderson , Zhao Liu , Paolo Bonzini , Eduardo Habkost Subject: [PATCH v2 3/4] target/i386: Wire up MXCSR.DE and FPUS.DE correctly Date: Mon, 19 May 2025 15:51:13 +0100 Message-ID: <20250519145114.2786534-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250519145114.2786534-1-peter.maydell@linaro.org> References: <20250519145114.2786534-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747666341470116600 Content-Type: text/plain; charset="utf-8" The x86 DE bit in the FPU and MXCSR status is supposed to be set when an input denormal is consumed. We didn't previously report this from softfloat, so the x86 code either simply didn't set the DE bit or else incorrectly wired it up to denormal_flushed, depending on which register you looked at. Now we have input_denormal_used we can wire up these DE bits with the semantics they are supposed to have. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/i386/tcg/fpu_helper.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 4732b718129..b3b23823fda 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -215,7 +215,7 @@ static void merge_exception_flags(CPUX86State *env, int= old_flags) (new_flags & float_flag_overflow ? FPUS_OE : 0) | (new_flags & float_flag_underflow ? FPUS_UE : 0) | (new_flags & float_flag_inexact ? FPUS_PE : 0) | - (new_flags & float_flag_input_denormal_flushed ? FP= US_DE : 0))); + (new_flags & float_flag_input_denormal_used ? FPUS_= DE : 0))); } =20 static inline floatx80 helper_fdiv(CPUX86State *env, floatx80 a, floatx80 = b) @@ -3254,6 +3254,7 @@ void update_mxcsr_status(CPUX86State *env) =20 /* Set exception flags. */ set_float_exception_flags((mxcsr & FPUS_IE ? float_flag_invalid : 0) | + (mxcsr & FPUS_DE ? float_flag_input_denormal= _used : 0) | (mxcsr & FPUS_ZE ? float_flag_divbyzero : 0)= | (mxcsr & FPUS_OE ? float_flag_overflow : 0) | (mxcsr & FPUS_UE ? float_flag_underflow : 0)= | @@ -3270,14 +3271,8 @@ void update_mxcsr_status(CPUX86State *env) void update_mxcsr_from_sse_status(CPUX86State *env) { int flags =3D get_float_exception_flags(&env->sse_status); - /* - * The MXCSR denormal flag has opposite semantics to - * float_flag_input_denormal_flushed (the softfloat code sets that flag - * only when flushing input denormals to zero, but SSE sets it - * only when not flushing them to zero), so is not converted - * here. - */ env->mxcsr |=3D ((flags & float_flag_invalid ? FPUS_IE : 0) | + (flags & float_flag_input_denormal_used ? FPUS_DE : 0) | (flags & float_flag_divbyzero ? FPUS_ZE : 0) | (flags & float_flag_overflow ? FPUS_OE : 0) | (flags & float_flag_underflow ? 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442fd50b9b2sm145672035e9.12.2025.05.19.07.51.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 May 2025 07:51:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747666281; x=1748271081; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Sv1uIzRpfIE5FbpULnDuS+CVfaDrnJOSP2gIW1vzay4=; b=qoRBavxqolwLArY0YFOLfHaVxKyebWMDogUALxNWl75i9tpMG/iNwpZ74KF8tLom4W RATfMcRoc07tawKWYiHsUU/0TEiutS/4+N0Nd99HdjRCUjmhpNDreMbTv4yLuOD9tVs+ K5GeUFvkV+C0XsWYK1NxAOKqhUImt9XJmJl0RrWPHVV3h2fAO3CvNqbBFBkiwzbdtia+ wTnOZb1rzX+b0C7O/XYczSyQ7eIDAEAdKt6bxV5N21+h+db67w+g+pEuqQH+9s2Q29ng hkEdaBm5Fw4INboI5JAyFqr2ruJ/JMDbXmcuyE2XAXGQbQMNKv+h19q4/XOo9jnbYkGd pIvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747666281; x=1748271081; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Sv1uIzRpfIE5FbpULnDuS+CVfaDrnJOSP2gIW1vzay4=; b=hLyEiQzsLZQsvn6VTKpbFlL/om5bAKA+SILtqjdRuqaEY4ebKr9xyDe6coFJ/AqxtA DHSy9VV1vibLFZoioLd/c5Z9PgXvS6oLN1lBSSNlOmqt23GrXVcUJsuAhxotRiY7wDf7 Wjy7UYdQ9fA+nmzDb0QbdUwMA0bfaEJLAA4GrhJ46h/CmXj1LxOjuKP5NfPx7/XbH1RQ xK8ayXKKmN8PGfpIIDJ2KeS7yA1DvfBpwiA2rRguUkaf4/5p+jtYAFJcchfgnwYjEETX sRTE21ytuoNH5HFPNiyx4qdwm9c9pcItEsGpwccG7xxjAsuZZpsBtn5Xa4V9/u4pZkyk HDzA== X-Gm-Message-State: AOJu0YxJgygvNy6vic4R6vaz3/M1QwSemMYLlzQGAwrNUKzPbpFCyedu g3eavceXLVO/UU7uXHc3a6WsmSneEKOpOT503awS0HzkPCihZfuifFY90/9Kn7uSCKF/NO6MDQu Cth58 X-Gm-Gg: ASbGncvLGOzTOVcMg63EPCwrFUO8RNz487jSob2WJ7kRjAL2HErSI/7LRuU8N8USa6e UdPKDmFYu3BHjpIyHyHU/Q+Ne0nAzIc0u/7RU+c/7xVZwuxAb2e6p2eZFaIn/6g8bv4hRAOuYyF GL2LYnw6h8UDFM2KKGjoiCUbmyXoT5wFy8xTjk7JAlt7N3gvX2nl3+cmpHeixHzaoGWhUHmRGDw CVuxBdCN95nrA/jJsoPGXVe1lixrUbKMUg3/bvP3XiQxOKxONa3nnu+d2GLnI6uwUuQLo9kxZHU v6qtm3H8Ayr3c01/XT61tECM8In+eBVFQeHgr9iG3HBSnWgK9vB6qAVI8Q== X-Google-Smtp-Source: AGHT+IGbUy3Gf11AY0KmYIbqQhhoeQ0sl38zQp0VYqeEUuEjiIDvegiODVDeVq9mwflmKG/RRJG/Uw== X-Received: by 2002:a05:600c:4e0f:b0:43d:649:4e50 with SMTP id 5b1f17b1804b1-442feff05c2mr117749165e9.13.1747666281344; Mon, 19 May 2025 07:51:21 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Richard Henderson , Zhao Liu , Paolo Bonzini , Eduardo Habkost Subject: [PATCH v2 4/4] tests/tcg/x86_64/fma: add test for exact-denormal output Date: Mon, 19 May 2025 15:51:14 +0100 Message-ID: <20250519145114.2786534-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250519145114.2786534-1-peter.maydell@linaro.org> References: <20250519145114.2786534-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747666351602116600 Content-Type: text/plain; charset="utf-8" Add some fma test cases that check for correct handling of FTZ and for the flag that indicates that the input denormal was consumed. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Zhao Liu --- tests/tcg/x86_64/fma.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/tests/tcg/x86_64/fma.c b/tests/tcg/x86_64/fma.c index 46f863005ed..34219614c0a 100644 --- a/tests/tcg/x86_64/fma.c +++ b/tests/tcg/x86_64/fma.c @@ -82,6 +82,18 @@ static testdata tests[] =3D { */ { 0x3fdfffffffffffff, 0x001fffffffffffff, 0x801fffffffffffff, true, 0x8010000000000000, 0x20 }, /* Enabling FTZ shouldn't change flags */ + /* + * normal * 0 + a denormal. With FTZ disabled this gives an exact + * result (equal to the input denormal) that has consumed the denormal. + */ + { 0x3cc8000000000000, 0x0000000000000000, 0x8008000000000000, false, + 0x8008000000000000, 0x2 }, /* Denormal */ + /* + * With FTZ enabled, this consumes the denormal, returns zero (because + * flushed) and indicates also Underflow and Precision. + */ + { 0x3cc8000000000000, 0x0000000000000000, 0x8008000000000000, true, + 0x8000000000000000, 0x32 }, /* Precision, Underflow, Denormal */ }; =20 int main(void) --=20 2.43.0