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The vs1 EEW of vrgatherei16.vv is 16. Co-authored-by: Anton Blanchard Reviewed-by: Daniel Henrique Barboza Signed-off-by: Max Chou Message-ID: <20250408103938.3623486-4-max.chou@sifive.com> Signed-off-by: Alistair Francis Cc: qemu-stable@nongnu.org --- target/riscv/insn_trans/trans_rvv.c.inc | 32 +++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index d8333d8311..04367e1bec 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -379,6 +379,35 @@ static bool vext_check_ld_index(DisasContext *s, int v= d, int vs2, return ret; } =20 +/* + * Check whether a vector register is used to provide source operands with + * more than one EEW for the vector instruction. + * Returns true if the instruction has valid encoding + * Returns false if encoding violates the mismatched input EEWs constraint + */ +static bool vext_check_input_eew(DisasContext *s, int vs1, uint8_t eew_vs1, + int vs2, uint8_t eew_vs2, int vm) +{ + bool is_valid =3D true; + int8_t emul_vs1 =3D eew_vs1 - s->sew + s->lmul; + int8_t emul_vs2 =3D eew_vs2 - s->sew + s->lmul; + + /* When vm is 0, vs1 & vs2(EEW!=3D1) group can't overlap v0 (EEW=3D1) = */ + if ((vs1 !=3D -1 && !require_vm(vm, vs1)) || + (vs2 !=3D -1 && !require_vm(vm, vs2))) { + is_valid =3D false; + } + + /* When eew_vs1 !=3D eew_vs2, check whether vs1 and vs2 are overlapped= */ + if ((vs1 !=3D -1 && vs2 !=3D -1) && (eew_vs1 !=3D eew_vs2) && + is_overlapped(vs1, 1 << MAX(emul_vs1, 0), + vs2, 1 << MAX(emul_vs2, 0))) { + is_valid =3D false; + } + + return is_valid; +} + static bool vext_check_ss(DisasContext *s, int vd, int vs, int vm) { return require_vm(vm, vd) && @@ -3733,6 +3762,7 @@ static bool vrgather_vv_check(DisasContext *s, arg_rm= rr *a) { return require_rvv(s) && vext_check_isa_ill(s) && + vext_check_input_eew(s, a->rs1, s->sew, a->rs2, s->sew, a->vm) = && require_align(a->rd, s->lmul) && require_align(a->rs1, s->lmul) && require_align(a->rs2, s->lmul) && @@ -3745,6 +3775,7 @@ static bool vrgatherei16_vv_check(DisasContext *s, ar= g_rmrr *a) int8_t emul =3D MO_16 - s->sew + s->lmul; return require_rvv(s) && vext_check_isa_ill(s) && + vext_check_input_eew(s, a->rs1, MO_16, a->rs2, s->sew, a->vm) && (emul >=3D -3 && emul <=3D 3) && require_align(a->rd, s->lmul) && require_align(a->rs1, emul) && @@ -3764,6 +3795,7 @@ static bool vrgather_vx_check(DisasContext *s, arg_rm= rr *a) { return require_rvv(s) && vext_check_isa_ill(s) && + vext_check_input_eew(s, -1, MO_64, a->rs2, s->sew, a->vm) && require_align(a->rd, s->lmul) && require_align(a->rs2, s->lmul) && (a->rd !=3D a->rs2) && --=20 2.49.0