From nobody Wed Dec 17 07:25:48 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1747483336; cv=none; d=zohomail.com; s=zohoarc; b=YrptgOmNfM8tSmwGNOSSnZtqHCYLl4Tfuj8OBaOzmT4G872uKeKpYBZkmRm5kowcwW6cMReTvB/cdv+RG8GoXLs6AIFmJNBnMies2dvQovilmCoud+JbUHfiNYpAPvuG50tsBp+ZtN11uahvww/2LofUdiXjbUVDDczrnbBu6tc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747483336; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=BeA9pPeZLVmg/ZpfFf5tDtTnRpdfSMVCAafGblAp4Rg=; b=NS+AvFlB1oaNanRaCUx3qSQPRnw8UU0efGw3MX40KCBsy0gXnru9e1gwGM3bSVmXWdaymSnXTy2uLJp2beORAjRn4tMaFjkVqVcnXmsXFWp2sHHvR/YVW7sgm2bmKlbVmhvscASzjW+24SIT7lClWl8+IxLo/KxZyu6rr5tyhAw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747483336165188.91981286547752; Sat, 17 May 2025 05:02:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uGGEW-0000ej-2x; Sat, 17 May 2025 08:01:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uGGE4-000057-Ac for qemu-devel@nongnu.org; Sat, 17 May 2025 08:01:13 -0400 Received: from tor.source.kernel.org ([172.105.4.254]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uGGDz-0002iA-31 for qemu-devel@nongnu.org; Sat, 17 May 2025 08:01:11 -0400 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id C2F6B6116F; Sat, 17 May 2025 12:00:57 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9EF25C4CEE9; Sat, 17 May 2025 12:00:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747483257; bh=3xq4wlfIvy9OM7kxdwoakK4Cms1/XS4ZMH0xxD790tQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pp1/+rB+7vHYVClSufoSG5C8YJVJZBiWkaQYFOzAh8tciR+vYewYjsJOVA32dwjQj sGD6/cCMD6osUCfYJ5PHjKgIBiCsqf9l+O46ihclS3WhJXGZPrzI0G8H2jrLG/NokL A0ikJW6nlrUkGKFrBCZfo9slo0K36eZkXrskay6a+k4omFJJ84mQpmhjxH7okrk747 qMh6pI0LtmvvNqaJ+VKED7OcjFQ9O+00GofFDId8wbFKk1KrDRuyFTZCqeA62a3zrv wSXEvMibbJtrBhl1DWPiw41GqMKHZBsiPjsmyZJw0CKWRouD+CvCDFUwXYnogZbR87 fGe70CckcjNTw== From: deller@kernel.org To: Richard Henderson , qemu-devel@nongnu.org Cc: Helge Deller Subject: [PATCH 1/3] target/hppa: Copy instruction code into fr1 on FPU assist fault Date: Sat, 17 May 2025 14:00:51 +0200 Message-ID: <20250517120053.18231-2-deller@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250517120053.18231-1-deller@kernel.org> References: <20250517120053.18231-1-deller@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=172.105.4.254; envelope-from=deller@kernel.org; helo=tor.source.kernel.org X-Spam_score_int: -36 X-Spam_score: -3.7 X-Spam_bar: --- X-Spam_report: (-3.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.616, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1747483338505116600 Content-Type: text/plain; charset="utf-8" From: Helge Deller The hardware stores the instruction code in the lower bits of the FP exception register #1 on FP assist traps. This fixes the FP exception handler on Linux, as the Linux kernel uses the value to decide on the correct signal which should be pushed into userspace (see decode_fpu() in Linux kernel). Signed-off-by: Helge Deller --- target/hppa/int_helper.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 7d48643bb6..191ae19404 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -177,6 +177,10 @@ void hppa_cpu_do_interrupt(CPUState *cs) } } env->cr[CR_IIR] =3D ldl_phys(cs->as, paddr); + if (i =3D=3D EXCP_ASSIST) { + /* stuff insn code into bits of FP exception register = #1 */ + env->fr[0] |=3D (env->cr[CR_IIR] & 0x03ffffff); + } } break; =20 --=20 2.47.0 From nobody Wed Dec 17 07:25:48 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1747483363; cv=none; d=zohomail.com; s=zohoarc; b=ZF8WD18qkAOJ+3wZayd67csjQRTe99+wnDHDR5zQDe+m2R/ITXOwlm8qCgAVWfNu0QPozQcdCEhQzYEVIGvUnUaZ8doOhCJB5fodm4TCjrTEBl8PEBndMB62IV1HLVzx4KJMn1Pr4pwoOqJQ8sJdaGoMbcEly/LXQMXGjcwo1Nw= ARC-Message-Signature: i=1; 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Sat, 17 May 2025 08:01:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uGGE4-000055-AV for qemu-devel@nongnu.org; Sat, 17 May 2025 08:01:13 -0400 Received: from nyc.source.kernel.org ([2604:1380:45d1:ec00::3]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uGGE0-0002iY-Sg for qemu-devel@nongnu.org; Sat, 17 May 2025 08:01:12 -0400 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id 7151CA4E40A; Sat, 17 May 2025 12:00:59 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E3596C4CEE3; Sat, 17 May 2025 12:00:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747483258; bh=mH6lWprZNCprzCYvb030arSxaYfC8yISrfaAKMY3jr8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=h7UxJ0EYXOrd7kG/WkGf5py6AGc3RVGqiiT0U0M6uJEShaxDXWNlhdXCql9+ANM1h 0aspvERN7zbUzwaJWCw/FIHDwPYfr9ePuxSvgQ3NGWcfQ/pgqkEwJ+qcPKY74A2QCP cGHmqYfrKZXSYo7q7vbIL28SDu+n0Kx8NEfMpI0yA8EsfyyYRIEfjE9ktbt2wPwLkO 6HRwJ9yooFsRsIehnamwg04EvFtgKGTfZStDdgNSW/nGyxO9w0Ee7KJyxoWS/LMCrr rDzq+z8aZtcLbDMEKi6j+ZbRrxYqDBdgOSC+1UcYlNBhPmiwrP4+FMNAz56Mhs5DQo gujPbA1/YnUhA== From: deller@kernel.org To: Richard Henderson , qemu-devel@nongnu.org Cc: Helge Deller Subject: [PATCH 2/3] linux-user/hppa: Send proper si_code on SIGFPE exception Date: Sat, 17 May 2025 14:00:52 +0200 Message-ID: <20250517120053.18231-3-deller@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250517120053.18231-1-deller@kernel.org> References: <20250517120053.18231-1-deller@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2604:1380:45d1:ec00::3; envelope-from=deller@kernel.org; helo=nyc.source.kernel.org X-Spam_score_int: -36 X-Spam_score: -3.7 X-Spam_bar: --- X-Spam_report: (-3.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.616, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1747483364632116600 Content-Type: text/plain; charset="utf-8" From: Helge Deller Improve the linux-user emulation to send the correct si_code depending on overflow (TARGET_FPE_FLTOVF), underflow (TARGET_FPE_FLTUND), ... Note that the hardware stores the relevant flags in FP exception register #1, which is actually the lower 32-bits of the 64-bit fr[0] register in qemu. Signed-off-by: Helge Deller --- linux-user/hppa/cpu_loop.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index 890e758cd1..9abaad5ef8 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -112,7 +112,7 @@ static abi_ulong hppa_lws(CPUHPPAState *env) void cpu_loop(CPUHPPAState *env) { CPUState *cs =3D env_cpu(env); - abi_ulong ret; + abi_ulong ret, si_code =3D 0; int trapnr; =20 while (1) { @@ -169,7 +169,15 @@ void cpu_loop(CPUHPPAState *env) force_sig_fault(TARGET_SIGFPE, TARGET_FPE_CONDTRAP, env->iaoq_= f); break; case EXCP_ASSIST: - force_sig_fault(TARGET_SIGFPE, 0, env->iaoq_f); + #define set_si_code(mask, val) \ + if (env->fr[0] & mask) { si_code =3D val; } + set_si_code(R_FPSR_FLG_I_MASK, TARGET_FPE_FLTRES); + set_si_code(R_FPSR_FLG_U_MASK, TARGET_FPE_FLTUND); + set_si_code(R_FPSR_FLG_O_MASK, TARGET_FPE_FLTOVF); + set_si_code(R_FPSR_FLG_Z_MASK, TARGET_FPE_FLTDIV); + set_si_code(R_FPSR_FLG_V_MASK, TARGET_FPE_FLTINV); + #undef set_si_code + force_sig_fault(TARGET_SIGFPE, si_code, env->iaoq_f); break; case EXCP_BREAK: force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->iaoq_f= ); --=20 2.47.0 From nobody Wed Dec 17 07:25:48 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1747483335; cv=none; d=zohomail.com; s=zohoarc; b=AOYmuJvySYUNU3BAJ6SkRyN9Q3C8Id/RlBvWvCsuYw9wUI8/O3WYA41+GnyPSu/5ymnx5oBjsMAnteQ5vnxoRiIEqq2AbtVh4/WYoXzz0QZHndbZkZvuu9U2Yx3oQG9pXlwAtvrUrq5bxp40YZrCoN3VcBbo6qWMwjCYlDSX9do= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747483335; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Sat, 17 May 2025 08:01:13 -0400 Received: from dfw.source.kernel.org ([139.178.84.217]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uGGE1-0002iv-FE for qemu-devel@nongnu.org; Sat, 17 May 2025 08:01:12 -0400 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 1A1865C1A3D; Sat, 17 May 2025 11:58:43 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 34447C4CEED; Sat, 17 May 2025 12:00:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747483260; bh=Q2Jud+Qo/Co5dwsffwNP+2WMO+4kLmz/GnQnSCCeKzM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=P3T9RLeD+TPePsDbgUB5jANcJ+LtehgEUMSTkErE+VVTwDLNtp1gVZ4dB2/QDysYL HbnHD1L9sIaiRtu5dNvgsV3epu0TfhcDke+m41nYQH2OOnk2awVbNMtocGUwGPCQ2t 8Nc5NtHlPu/om/XP50c3p0xL/c6Rk/qXYsnDLFp2YnTbxuT06Hsarvw3EaQ6MHMKEX bBNThXBHZhf1sa+RswIDHlQKfVRST3I0SsF5NQYYMFhRH8doh+prSsQmHFXh5Y6oEH kP0BtnDiCBF87M0hrv40TTWEqtLwRTHFYGSSmU/lY4AxFzuPl90LrHOvMR+65hq8o9 kNTdsXuzQh70w== From: deller@kernel.org To: Richard Henderson , qemu-devel@nongnu.org Cc: Helge Deller Subject: [PATCH 3/3] target/hppa: Fix FPE exceptions Date: Sat, 17 May 2025 14:00:53 +0200 Message-ID: <20250517120053.18231-4-deller@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250517120053.18231-1-deller@kernel.org> References: <20250517120053.18231-1-deller@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=139.178.84.217; envelope-from=deller@kernel.org; helo=dfw.source.kernel.org X-Spam_score_int: -86 X-Spam_score: -8.7 X-Spam_bar: -------- X-Spam_report: (-8.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.616, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1747483338552116600 Content-Type: text/plain; charset="utf-8" From: Helge Deller Implement FP exception register #1 (lower 32-bits of 64-bit fr[0]). A proper implementation is necessary to allow the Linux kernel in system mode and the qemu linux-user to send proper si_code values on SIGFPE signal. Always set the T-bit on taken exception, and merge over- and underflow in system mode to just set overflow bit to mimic the behaviour I tested on a physical machine. The test program below can be used to verify correct behaviour. Note that behaviour on SIGFPE may vary on different platforms. The program should always detect the correct signal, but it may or may not be able to sucessfully continue afterwards. #define _GNU_SOURCE #include #include #include #include static void fpe_func(int sig, siginfo_t *i, void *v) { sigset_t set; sigemptyset(&set); sigaddset(&set, SIGFPE); sigprocmask(SIG_UNBLOCK, &set, NULL); printf("GOT signal %d with si_code %ld\n", sig, i->si_code); } int main(int argc, char *argv[]) { struct sigaction action =3D { .sa_sigaction =3D fpe_func, .sa_flags =3D SA_RESTART|SA_SIGINFO }; sigaction(SIGFPE, &action, 0); feenableexcept(FE_OVERFLOW | FE_UNDERFLOW); double x =3D DBL_MIN; return printf("%lf\n", argc > 1 ? 1.7976931348623158E308*1.7976931348623158E308 : x / 10); } Signed-off-by: Helge Deller --- target/hppa/fpu_helper.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c index a62d9d3083..294ce0a970 100644 --- a/target/hppa/fpu_helper.c +++ b/target/hppa/fpu_helper.c @@ -95,7 +95,8 @@ static void update_fr0_op(CPUHPPAState *env, uintptr_t ra) { uint32_t soft_exp =3D get_float_exception_flags(&env->fp_status); uint32_t hard_exp =3D 0; - uint32_t shadow =3D env->fr0_shadow; + uint32_t shadow =3D env->fr0_shadow & 0x3ffffff; + uint32_t fr1 =3D 0; =20 if (likely(soft_exp =3D=3D 0)) { env->fr[0] =3D (uint64_t)shadow << 32; @@ -108,9 +109,22 @@ static void update_fr0_op(CPUHPPAState *env, uintptr_t= ra) hard_exp |=3D CONVERT_BIT(soft_exp, float_flag_overflow, R_FPSR_ENA_O= _MASK); hard_exp |=3D CONVERT_BIT(soft_exp, float_flag_divbyzero, R_FPSR_ENA_Z= _MASK); hard_exp |=3D CONVERT_BIT(soft_exp, float_flag_invalid, R_FPSR_ENA_V= _MASK); - shadow |=3D hard_exp << (R_FPSR_FLAGS_SHIFT - R_FPSR_ENABLES_SHIFT); + if (hard_exp & shadow) { + shadow =3D FIELD_DP32(shadow, FPSR, T, 1); + /* fill exception register #1, which is lower 32-bits of fr[0] */ +#if !defined(CONFIG_USER_ONLY) + if (hard_exp & (R_FPSR_ENA_O_MASK | R_FPSR_ENA_U_MASK)) { + /* over- and underflow both set overflow flag only */ + fr1 =3D FIELD_DP32(fr1, FPSR, C, 1); + fr1 =3D FIELD_DP32(fr1, FPSR, FLG_O, 1); + } else +#endif + { + fr1 |=3D hard_exp << (R_FPSR_FLAGS_SHIFT - R_FPSR_ENABLES_SHIF= T); + } + } env->fr0_shadow =3D shadow; - env->fr[0] =3D (uint64_t)shadow << 32; + env->fr[0] =3D (uint64_t)shadow << 32 | fr1; =20 if (hard_exp & shadow) { hppa_dynamic_excp(env, EXCP_ASSIST, ra); --=20 2.47.0