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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442f396c3a4sm65657855e9.26.2025.05.15.03.25.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 03:25:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747304757; x=1747909557; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=V44BClu19+jvYPw+zjT/7PfwtqiqasGrnUcfMcg673Q=; b=CZS+esSn4X67hdD7niZJW2zNGW1xSZjmt9Vp6kQXA/irzEdJfQCJO9peJ7JSaaaI8W YgHcF8wzJ4ITbP5/Nf9yHxmFzneuQpaGw3tMDlx3T1tmLNtb3zxWysOrP169Cc2UFKqY sOF3so3IYCIhQ9G0bjhfmyWUetoH6tqFNjPLeJcmskXmcoxotE8TpynPMvLz0bgaCbSm ZGkIa+IQmAav/CFdKVEvWt2VYwbChGSIbM+wbBK+XeWUooP4NAcj7t9YqoxvfyT/16Qs qqL4MiTygxm/9JkA9XSL8ozoKY1ZYFcNxG5veQKHrh4esa7PCKD6luQKf5Lj/CJudCFK 3RgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747304757; x=1747909557; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=V44BClu19+jvYPw+zjT/7PfwtqiqasGrnUcfMcg673Q=; b=k12AB/syNHqeXeJ0ZAv3WKeSmnVmXOxHpuDJT1QItSIwloeTAzQIl6OT5cURWW4DCa yYa1Tq03KFnTAi1e6RdKPGAvCJSfqQaPfxV4jUbzY+clcytwt3hxywttCVQh7MYRvFiE rEM6hm71RPU4swr0segb/Kg6LzzmBynBGU/nARJxHA5ln4/aR6IBejRE1xeGRm4jI8I5 7bto8FeCDpol1kiM8mABTFEl6JJKPp9DOxbCkKIJ50OnVJdBhluaAuweQRDULg/moEmZ s9xIGkvv3qVPWYb3TeMsLKFWxe24wNhZeXVyio9iWBem96XRXFeW5MjCz0BLNTwy+5cx AEKA== X-Gm-Message-State: AOJu0YxJYEBIEDhsjsSccZMUEn8p/hzfCKp5+j6XRdccytJBJyJMgzYX eesJ8nSKX2/J/HpwttfQf6txsDsZp0jK29v3wUi+zQsjm/z7k2+XS0s0gn82K8XW/mrTVCjtcoB aMaw= X-Gm-Gg: ASbGncvrDcKvHahGWhib8nivoBSfWkSJ8kFw6ARdgrJDbyHphQFwWCoJkaE8EEpYY0g jMIdPdW+3xi7xomQLzluJMzSUWUuQ7IdT6frik+KRK2NtwErlkoVj1UJF11UMvMJzYCEhJ9q2r2 NLXu4/ULm8EcC0IyUcaBKHYeAoNH4TsUeCQjjiWiEaVJ1CcbPRR7SBljM2ySOIG/04XfUbuVRfg 2L+jmDCP9EhULv1NCUCxfh26gyQ7pnurYAa5Voo5lGFLE1PgIRhLzW3rSBABXwnhCUNBjS6LIC4 MJ7+1+LGeB116N3d2jXFvZSoRaNld5JNLMSRXSNi6leo1mkCO/05FmHBgyCjseEvju/y X-Google-Smtp-Source: AGHT+IF2c+SWv/P9+Tpn2LV7RD4SHoKn+nx5riGwMirs1xFP5ntFGsPXnbFQ/pWSdohybR1ZJfxUGg== X-Received: by 2002:a05:600c:c09:b0:43d:82c:2b23 with SMTP id 5b1f17b1804b1-442f2168c29mr54196595e9.23.1747304756870; Thu, 15 May 2025 03:25:56 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/58] target/arm: Move aarch64 CPU property code to TYPE_ARM_CPU Date: Thu, 15 May 2025 11:24:53 +0100 Message-ID: <20250515102546.2149601-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305577964116600 The only thing we have left in the TYPE_AARCH64_CPU class that makes it different to TYPE_ARM_CPU is that we register the handling of the "aarch64" property there. Move the handling of this property to the base class, where we make it a property of the object rather than of the class, and add it to the CPU if it has the ARM_FEATURE_AARCH64 property present at init. This is in line with how we handle other Arm CPU properties, and should not change which CPUs it's visible for. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20250429132200.605611-6-peter.maydell@linaro.org --- target/arm/cpu.c | 36 ++++++++++++++++++++++++++++++++++++ target/arm/cpu64.c | 33 --------------------------------- 2 files changed, 36 insertions(+), 33 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 45cb6fd7eed..603f08d05a0 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1609,6 +1609,35 @@ static void arm_set_pmu(Object *obj, bool value, Err= or **errp) cpu->has_pmu =3D value; } =20 +static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); +} + +static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + /* + * At this time, this property is only allowed if KVM is enabled. This + * restriction allows us to avoid fixing up functionality that assumes= a + * uniform execution state like do_interrupt. + */ + if (value =3D=3D false) { + if (!kvm_enabled() || !kvm_arm_aarch32_supported()) { + error_setg(errp, "'aarch64' feature cannot be disabled " + "unless KVM is enabled and 32-bit EL1 " + "is supported"); + return; + } + unset_feature(&cpu->env, ARM_FEATURE_AARCH64); + } else { + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + } +} + unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) { /* @@ -1736,6 +1765,13 @@ void arm_cpu_post_init(Object *obj) */ arm_cpu_propagate_feature_implications(cpu); =20 + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64, + aarch64_cpu_set_aarch64); + object_property_set_description(obj, "aarch64", + "Set on/off to enable/disable aarc= h64 " + "execution state "); + } if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property= ); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 00629a5d1d1..e527465a3ca 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -781,45 +781,12 @@ static const ARMCPUInfo aarch64_cpus[] =3D { #endif }; =20 -static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); -} - -static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - /* At this time, this property is only allowed if KVM is enabled. This - * restriction allows us to avoid fixing up functionality that assumes= a - * uniform execution state like do_interrupt. - */ - if (value =3D=3D false) { - if (!kvm_enabled() || !kvm_arm_aarch32_supported()) { - error_setg(errp, "'aarch64' feature cannot be disabled " - "unless KVM is enabled and 32-bit EL1 " - "is supported"); - return; - } - unset_feature(&cpu->env, ARM_FEATURE_AARCH64); - } else { - set_feature(&cpu->env, ARM_FEATURE_AARCH64); - } -} - static void aarch64_cpu_finalizefn(Object *obj) { } =20 static void aarch64_cpu_class_init(ObjectClass *oc, const void *data) { - object_class_property_add_bool(oc, "aarch64", aarch64_cpu_get_aarch64, - aarch64_cpu_set_aarch64); - object_class_property_set_description(oc, "aarch64", - "Set on/off to enable/disable aa= rch64 " - "execution state "); } =20 static void aarch64_cpu_instance_init(Object *obj) --=20 2.43.0