From nobody Fri Dec 19 17:37:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747305346; cv=none; d=zohomail.com; s=zohoarc; b=jk5G63rJhnXCic1I2XuDavndatcSgKlDwUQFcaHBQpNbzFgappu2rPSWfCP/I1hgItsrhiBJYHXB/90veZe3XF1CvtjAgtac/cUj3FnhZWVta7GRsX/Hb+Di5rXQvAsPPW4jrHvgDYW+s/dHlDG3VHOvExiONN+RQjbBRLVP+Z4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747305346; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=DRuZri4+JHhBySzNzcQhM79/aaMB+kacQBfm+tsx07Y=; b=ZkQNgheduA54d/PESFIwKuKJHu+qB7+AuFaHbTek1SsRf5J6ff5LnkjYYsqmchW1rmazAme/Nxjde2OXWbRLqQDfUyyQOnQWXk+YtsyX51evp4kVxbOQyf6F2XJHTw/K+p7bYsLOtJqQ1cFBodTZk7lmevhKn6bTjHRCCJ7kgnE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747305346884241.91225599980635; Thu, 15 May 2025 03:35:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uFVmn-0004FJ-IB; Thu, 15 May 2025 06:25:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uFVmm-0004D2-4T for qemu-devel@nongnu.org; Thu, 15 May 2025 06:25:56 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uFVmi-000864-UY for qemu-devel@nongnu.org; Thu, 15 May 2025 06:25:55 -0400 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-3a1f5d2d91eso426734f8f.1 for ; Thu, 15 May 2025 03:25:52 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442f396c3a4sm65657855e9.26.2025.05.15.03.25.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 03:25:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747304751; x=1747909551; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=DRuZri4+JHhBySzNzcQhM79/aaMB+kacQBfm+tsx07Y=; b=R0UL/O4MqkhIDNdOvIXJ1L0UBLFTOp2HCljZRbM+i/3y/SwF+z+4iqIKv1rN8YdChz v/4dq5+LkpSmJc5I1aGTQGG7SPPacsCoYyqLDW+L6oykgqvZjNTlw2bMvIDaC5B689M3 4L/r45MqyqL+W1UWy0JQU5F9xI96KfTMTHgNx6ggF/KAYBwYe2pi59orH9mW4zTEFwbU UqbRjoY8hrqyTreAAU4ZwAGL/bOJ8s+fKteXfx4ZP+QvxK57mpoLxeYZW3RA21FqVA8Q ha6yE1hI+zqgSuTZM3y4FWa2Yk+f1LFdKvlW+pcbMlFC8wh9mOiLlioiZV+lxygaJ9Wo FKUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747304751; x=1747909551; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DRuZri4+JHhBySzNzcQhM79/aaMB+kacQBfm+tsx07Y=; b=iFYX9T+xI40slRpDBRXNMhmol0yfr8ReZa+Y2rWvxyFfgoKxTeq1VGP4h4cIl3+Fdm DkFtJFTILOoK05Mi1zGJ1ABtdWkPXbsXrx4e7JD3bUyZkWQQ8gNhTMBL/euJRfjTy1JW wB+ujqLxWTDo/A6zuTNEb4BMywptfYpjk7FknVbAZagmnA5ApWBorB/NcD1tllqj94W5 wOqK2QjmjEEwbNgDeignpDoZd7iES4hc4J/+jLymC5HDyUJ65BqPtwfmzmwz54HS1oh4 MHUGce2ND7OpfPj1d8aZJgzz9XCZ57lDAaCa2FtCc19sLGrd9vVceDNGCZ/48MtxU0uQ kBIw== X-Gm-Message-State: AOJu0Yzxi71JMgG6Fj7Fo9oOFI3XPa+iTB7XzWhFataaRrsQvIsQKcpN W56bu0aGKeWZqfCPrL74K01Hq9UNkHk9mCpxku4qkTFebnS16Fu44w7O+IS7xMdGwgJDZ/F4gdf 3PwY= X-Gm-Gg: ASbGncthLdcVAVbbAkjDqMcpnq6+t02mL25Ban6UHg75h6zDMzXLROwiYQtzMLNeP3i fqSCtKgBY7q9A5MYRpsn5DY65vhZ5sdXQ3lWZRnOtN4el83On986YJd9fx1fBN3kbYqAy6kB9VT m/kcLjWORh78Au+tUCrgKd76v/843QlI3Z91TThpB4sf8HNaBqk4ApeLMSdZV/5voniEImkGkkD NEFBWuH3qMLiXGKfH4CcFXTOsWGjvLkRfLxD8+Dlt6kGthnFR/cbo9GzZEyksSsucv/1DbEvqYm ViRZukQSCAWMFVKCajdF3x7aZbLz8gmcU3B1BplOU5NwJGGoiVQR6qxBkA== X-Google-Smtp-Source: AGHT+IH/aW/fMj81E/Si0c0zIuju5J38nYPJuAEahfIqnVXjqdx4C6suTJJUh+UC+x8v/8UFsNP3xg== X-Received: by 2002:a05:6000:2dc7:b0:39a:c9c1:5453 with SMTP id ffacd0b85a97d-3a34994d408mr5882258f8f.49.1747304751287; Thu, 15 May 2025 03:25:51 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/58] target/microblaze: Use 'obj' in DEVICE() casts in mb_cpu_initfn() Date: Thu, 15 May 2025 11:24:49 +0100 Message-ID: <20250515102546.2149601-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305347906116600 We're about to make a change that removes the only other use of the 'cpu' local variable in mb_cpu_initfn(); since the DEVICE() casts work fine with the Object*, use that instead, so that we can remove the local variable when we make the following change. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Edgar E. Iglesias Reviewed-by: Richard Henderson Message-id: 20250429132200.605611-2-peter.maydell@linaro.org --- target/microblaze/cpu.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index d069e40e70c..d895d683956 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -344,11 +344,11 @@ static void mb_cpu_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY /* Inbound IRQ and FIR lines */ - qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2); - qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dp, "ns_axi_dp", 1); - qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ip, "ns_axi_ip", 1); - qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dc, "ns_axi_dc", 1); - qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ic, "ns_axi_ic", 1); + qdev_init_gpio_in(DEVICE(obj), microblaze_cpu_set_irq, 2); + qdev_init_gpio_in_named(DEVICE(obj), mb_cpu_ns_axi_dp, "ns_axi_dp", 1); + qdev_init_gpio_in_named(DEVICE(obj), mb_cpu_ns_axi_ip, "ns_axi_ip", 1); + qdev_init_gpio_in_named(DEVICE(obj), mb_cpu_ns_axi_dc, "ns_axi_dc", 1); + qdev_init_gpio_in_named(DEVICE(obj), mb_cpu_ns_axi_ic, "ns_axi_ic", 1); #endif =20 /* Restricted 'endianness' property is equivalent of 'little-endian' */ --=20 2.43.0 From nobody Fri Dec 19 17:37:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747305376; cv=none; d=zohomail.com; s=zohoarc; b=fBK7uMD0JOt4b/GvRyEM7MuRJ6/CXu/L1lsncvbuynetzT5muAPcGFilg7zbxJvm+BxDL/Og0NyCfJgXqr4SXzHSFYEMMSWOJv3J7G/lh1BQjaWtTIICAAauIoTe/e/nIfuN3JZ1j1rF+lkrP23kl4ThawkFPOAXO0tcqpGD1Es= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747305376; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=jUxbkP+HhDnHsdXnm5ZqQIvQggnNxrTAh7W07VaYQEE=; b=jVxrxEE2mXbVHoO0btBH8R0c5a4hCkkxfsIs5hGdzCDkPYGbDXKgUvbviubT4Av3o/I+19+5oqk+MVH6ScPknb7t8Xhgt7l+wH9FqekRRMNfIsAEcnMCpGV1/PLeni8lCvk3ASx/cr59NJschjIFRBxVwCmKR/Y7155bQeSovTM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747305376395495.45693070159564; Thu, 15 May 2025 03:36:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uFVmp-0004GH-1W; Thu, 15 May 2025 06:25:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uFVmm-0004D7-6M for qemu-devel@nongnu.org; Thu, 15 May 2025 06:25:56 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uFVmk-00086D-6n for qemu-devel@nongnu.org; Thu, 15 May 2025 06:25:55 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-440685d6afcso8439845e9.0 for ; Thu, 15 May 2025 03:25:53 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442f396c3a4sm65657855e9.26.2025.05.15.03.25.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 03:25:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747304752; x=1747909552; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=jUxbkP+HhDnHsdXnm5ZqQIvQggnNxrTAh7W07VaYQEE=; b=WPeadnobR0g7cdFCbpy1In3VyqJkhtWgTcYbTMR88FS28lljQ6poq2AaKsMqgrxjHH HHMDWmzM1a3cFrynAdq+CRzbLo5ovKc9mo16QnTafXcMWNNZxYZtMDJKBGY0DD1uVP8Q KH7zeMm83xvNAmcJQAfMHsgYeATHXZF0nBg6iRmzAOh5y3mvxRg+zrzTdusrnoe+4sd1 bp9jG4Nl85vXVSKCxfukhm91hNOJ2GzCfpP6qPd/9uFNi3kHemuuX83KLZPpNWHQwMsU NQVu9Z3hy90B6k8K3op15gNRV/KXzzZTtNS7jLBWJSPZK8t4odW/VKl9bcuA3vbldtRT S1gQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747304752; x=1747909552; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jUxbkP+HhDnHsdXnm5ZqQIvQggnNxrTAh7W07VaYQEE=; b=B4nqZzokAqgQZyjmx3aR0AZM547AOlmbi9Rbquddg3sVlhdbpQXfI7FK+ZZ457yqcC m6sAXfmYB/IOtG8xkVkuzXGtpqqDmxuoNvVcKExwrI+vi3H4TnpaAN8mG6OSEGxoiYso iqhp0jecAvzgf2PO+gEw08pWcjwdm0yhVpziz4JLSaG5Ha4aXKD4SKdK4ym6nzI6hiUa fpa1rPAz0koJGTfzQuXpuOLW21crGycQkTpihbjZO8/VpUl0AAIIPH75lTUO402pQxxi G1H7j4+NKQ2DVdfhFXyhb1EaGQMRX0CVsR+NKZdWj5xOKAYvQxOhXwIh/6rYAAYTYSjK SyQQ== X-Gm-Message-State: AOJu0YwE0+GDQcBXEBHjAMm20F6Tc5Q9bHhcpqSJPsJD8kQoRS/Oayg/ xfoN9oavvAF2a22fLKOGOLjZm8SFJzfRtbFQrpLZAUFdqZBchrLiL4eVkYJApkNRTU7GlDVCmHS 7wuk= X-Gm-Gg: ASbGncuClHjdLhAWppGuLcM1xauXsTxk2NYSzHfEmmmhI6ISIO1lI+FnEMHW8kv7j4V LoOpOGRZFLPil3yAMEY7brPEmIEC6jCd9naGIpKnCf1qN4TpJa+rW5d4zjS8pJZzmCAaApb6HVF 9y7zLibODjqhFRXZVKz0k3W5hzbqyfGx0gwmp21047mqEZlMK1erstmNNkjXiwJDc84lD4gBgJ2 RueDySqvlq7+zFKdzSry91L4DmabhBrzIavdM0e2ZD71EEwUYKzNlTqiZmyvx8P4W3PJnKZxSEM oNCquuwUo54K0hDVSPsq9uh+9ZQ7c52fBwUeVxNkExVq0oDjj2dgK2xzYw== X-Google-Smtp-Source: AGHT+IGPdoxmrU9I5FL1bOyJAYbU7BuFnYDbMQ5zgXX9LWBMcy0Q+VTNN8Ycwe1izP38euQppcu3Jg== X-Received: by 2002:a05:600c:1e02:b0:43c:ea36:9840 with SMTP id 5b1f17b1804b1-442f970a8dcmr15025815e9.22.1747304752462; Thu, 15 May 2025 03:25:52 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/58] target/microblaze: Delay gdb_register_coprocessor() to realize Date: Thu, 15 May 2025 11:24:50 +0100 Message-ID: <20250515102546.2149601-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305378393116600 Currently the microblaze code calls gdb_register_coprocessor() in its initfn. This works, but we would like to delay setting up GDB registers until realize. All other target architectures only call gdb_register_coprocessor() in realize, after the call to cpu_exec_realizefn(). Move the microblaze gdb_register_coprocessor() use, bringing it in line with other targets. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20250429132200.605611-3-peter.maydell@linaro.org --- target/microblaze/cpu.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index d895d683956..615a9592005 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -263,6 +263,11 @@ static void mb_cpu_realizefn(DeviceState *dev, Error *= *errp) return; } =20 + gdb_register_coprocessor(cs, mb_cpu_gdb_read_stack_protect, + mb_cpu_gdb_write_stack_protect, + gdb_find_static_feature("microblaze-stack-pro= tect.xml"), + 0); + qemu_init_vcpu(cs); =20 version =3D cpu->cfg.version ? cpu->cfg.version : DEFAULT_CPU_VERSION; @@ -335,13 +340,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error *= *errp) =20 static void mb_cpu_initfn(Object *obj) { - MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(obj); - - gdb_register_coprocessor(CPU(cpu), mb_cpu_gdb_read_stack_protect, - mb_cpu_gdb_write_stack_protect, - gdb_find_static_feature("microblaze-stack-pro= tect.xml"), - 0); - #ifndef CONFIG_USER_ONLY /* Inbound IRQ and FIR lines */ qdev_init_gpio_in(DEVICE(obj), microblaze_cpu_set_irq, 2); --=20 2.43.0 From nobody Fri Dec 19 17:37:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747304876; cv=none; d=zohomail.com; s=zohoarc; b=PoIuMXlbVHfP2sd6+rOg0+8oWU1E3g/z2Jwk8urJB88QW/J3L8AiH3n+teNP8CTCDOl/3Z7jWdMsJOv2z3qZBbEqM1iBQczZrqnbvXFiwo6CuXnqk2labYMG0ZbXN8vIsQX6WsQ6ul4E1zp9WdQ4WPee+kBlnz+wJyQ04XxgJeo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747304876; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=7QtsMbWF7VE6Px6bLjp5onVkzczQnDLHxWTCi6gF8ps=; b=RTqT2WJYs9Eu5eG4RMFqiRKsEG3f3D9BNQhXPolhNJhgugN/UlnQwoekzM6xQ7OJuKOpteSahZO61Wi5rbkvX9rFb9o9cypl0BZfsGSCongzIZk0olWkIYb9TklwBaCQ9K9l/AN3z3h9RYbLahgJi9l3sr7UWButaluWZFC5iSQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747304876088581.1729307905686; Thu, 15 May 2025 03:27:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uFVmr-0004Jk-Rn; Thu, 15 May 2025 06:26:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uFVmo-0004GI-3j for qemu-devel@nongnu.org; Thu, 15 May 2025 06:25:58 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uFVmm-00086Y-4s for qemu-devel@nongnu.org; Thu, 15 May 2025 06:25:57 -0400 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-43cfba466b2so8367505e9.3 for ; Thu, 15 May 2025 03:25:55 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442f396c3a4sm65657855e9.26.2025.05.15.03.25.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 03:25:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747304754; x=1747909554; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=7QtsMbWF7VE6Px6bLjp5onVkzczQnDLHxWTCi6gF8ps=; b=vL7bC4/5r4i4GuqhwXZAXFaO8mc4/35wlFZbZmipaYUfnxSsRePslhPubL8L/wUmG3 mMJBlu8qF5B9K+t7YZlJArdH/z3CiGUoeWVpIpfASOOsnffVrlK+yKmJBsJKMdZrA7cM J8JOCTi1XUTDqZMq1RCHzul6DCrN7mVJZrZVvuGdsWU30cr0e8YiUqSE3dEoPIP8t8PG RlI7+n9yy4munKFjcyr9fmOvALOHG752xKShBg2eer5pW//2Gv4wRUJbJXtAMLwj7Uvk 7bdPhcQfmG4RY/uNB5sqWu0fL54idCtS4DqKi4egkgslKG/xWEZGWk8ItPn4WvqRYjAL +Bpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747304754; x=1747909554; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7QtsMbWF7VE6Px6bLjp5onVkzczQnDLHxWTCi6gF8ps=; b=xPLS48LPGzn3Or7SGSnSZVjBu7imMkk0xOu2vh15adqecLdZc8b5z7EXsT9weCeGzF vV7bUlZmmPuyVOi0YGcGtchhp4uCRVbJ6Je0JajKSf9J/dzA8N1VMuWsmkAtog0v1NAD wBD3izE4ZA1OOfneWkgH6wq6FvFJb1ukfOgiR4c3RbNVIFhBxGAKyrdA33jT7UN6sAJY nmkhZ1t1ZOp/b/S6ZyX9GILkRpMl0954a2RfKlz4uB5Jql98/0+BNhfvToQu9sGOKb3H ihACtk4e//GHJKlG9gfn1tMu66zbeNp2hwZ3FRG1peAAMcjzkmQ+GoWYQbrzouXqVScE maZQ== X-Gm-Message-State: AOJu0YxMiaRyxd1I9qNSSfSOI3cBKo1ee0hgENqxMrngFbeRtL9FqmQs hLX8dCygNcnl/PB3WTxifpy8VMAYCiN74TcmW7GtKsgi9ynedF62FpuNO4fHKiUIpQXhDr2SWsN +iMQ= X-Gm-Gg: ASbGncskAT4iqAbY0wXxF8zH5I2CbD2ozhQKjQbSLacT/S5Aa73N2y6b2hUqFilg8pE 5LU3RJQWczEk1hOQ3Bsz/zI/vv1In7zEtoTK3klE9EaA+9tDYQisTy8QiQ0B2v2bmYxziwU2Lc+ 7v/KtVRn/9vnQ/Y6qWr2FAVG8rfpUTYan4ReRvcnOzWCXOf0gIyGXoMMqVY/V6AVKikQftYT4XE 0WpBrWPF12L+cZuDfCVgL+ooazExywrn/sHDmceubwcI558joaraR2kSzwdQW0H2uSUif7TwSWC m9kHQu3YhehgBKjw6uuCAZe+doD/uNs93zJ1vD0vyZiKWRBJtr/JTVSzcg== X-Google-Smtp-Source: AGHT+IHlFbT0p+7Se7sYBLG2Ww4KJIDgkIg1oh/aojKGaXwTeHLZ0RPSWnuba1h4Zylawr2K8dIRqw== X-Received: by 2002:a05:600c:83c8:b0:442:f485:6fa4 with SMTP id 5b1f17b1804b1-442f971924amr21742645e9.31.1747304754143; Thu, 15 May 2025 03:25:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/58] hw/core/cpu-common: Don't init gdbstub until cpu_exec_realizefn() Date: Thu, 15 May 2025 11:24:51 +0100 Message-ID: <20250515102546.2149601-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747304877748116600 Currently we call gdb_init_cpu() in cpu_common_initfn(), which is very early in the CPU object's init->realize creation sequence. In particular this happens before the architecture-specific subclass's init fn has even run. This means that gdb_init_cpu() can only do things that depend strictly on the class, not on the object, because the CPUState* that it is passed is currently half-initialized. In commit a1f728ecc90cf6c6 we accidentally broke this rule, by adding a call to the gdb_get_core_xml_file method which takes the CPUState. At the moment we get away with this because the only implementation doesn't actually look at the pointer it is passed. However the whole reason we created that method was so that we could make the "which XML file?" decision based on a property of the CPU object, and we currently can't change the Arm implementation of the method to do what we want without causing wrong behaviour or a crash. The ordering restrictions here are: * we must call gdb_init_cpu before: - any call to gdb_register_coprocessor() - any use of the gdb_num_regs field (this is only used in code that's about to call gdb_register_coprocessor() and wants to know the first register number of the set of registers it's about to add) * we must call gdb_init_cpu after CPU properties have been set, which is to say somewhere in realize The function cpu_exec_realizefn() meets both of these requirements, as it is called by the architecture-specific CPU realize function early in realize, before any calls ot gdb_register_coprocessor(). Move the gdb_init_cpu() call to there. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20250429132200.605611-4-peter.maydell@linaro.org --- hw/core/cpu-common.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index 92c40b6bf83..39e674aca21 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -234,6 +234,8 @@ bool cpu_exec_realizefn(CPUState *cpu, Error **errp) return false; } =20 + gdb_init_cpu(cpu); + /* Wait until cpu initialization complete before exposing cpu. */ cpu_list_add(cpu); =20 @@ -304,7 +306,6 @@ static void cpu_common_initfn(Object *obj) /* cache the cpu class for the hotpath */ cpu->cc =3D CPU_GET_CLASS(cpu); =20 - gdb_init_cpu(cpu); cpu->cpu_index =3D UNASSIGNED_CPU_INDEX; cpu->cluster_index =3D UNASSIGNED_CLUSTER_INDEX; cpu->as =3D NULL; --=20 2.43.0 From nobody Fri Dec 19 17:37:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747304922; cv=none; d=zohomail.com; s=zohoarc; b=ZANR3lfkBpEXmxrkc4PGDDX28OnNiST/5vLbUJBmhmL6rGV6rdzqy7TVQdSB6ni1KEUKgnYRRV6ijOjz7mHu4Z7uXdDV2IrVokQKfycRxjxqPj2PFAiGrYjxGFLI5fCN2JVaaFsXVWlHJ030W4ozH56IJ/6JJHmNjgj6O20I7mA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747304922; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=bObN/GZFYIPXswmzQmBrFY+KFYsdoS+icAznneCd2Ck=; b=lxyMRoGEDppCruszgFy2NRaYOy1TYcAHoDoBMdDsp5xKBxtHrUUx213D7H1lfxZavhTjaDM9ewOJ+xLLpN8HpMRvt0hNBRD+a8G+vD4XOBZElUI6YJUI1LyYvResp19xNPf7HnQwFcipmkGpl32gzjbhAEIt87BkGFBUOKURrak= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747304922505185.90743307939704; Thu, 15 May 2025 03:28:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uFVmr-0004Ja-Ql; Thu, 15 May 2025 06:26:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uFVmp-0004HJ-9w for qemu-devel@nongnu.org; Thu, 15 May 2025 06:25:59 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uFVmn-000872-Jv for qemu-devel@nongnu.org; Thu, 15 May 2025 06:25:59 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-43cfba466b2so8367755e9.3 for ; Thu, 15 May 2025 03:25:57 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442f396c3a4sm65657855e9.26.2025.05.15.03.25.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 03:25:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747304756; x=1747909556; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=bObN/GZFYIPXswmzQmBrFY+KFYsdoS+icAznneCd2Ck=; b=XK+ppCmRVs3Q+RVjZ7bil6PE3H2GC1u6wK3pfVA4qak0y6KX74s99DEnjEohuul1wi +l8oJs2tSC80sfMfrFs+sKL3VPj1rudrTIEuamrldFxaLMjk8406/hfIfArkQfMqcAby yFr/V3GNgZqJ6bIDJJCm60Lv8iTuz60hHE1XPpciI6XeP2omcEVweh6DUa9gKHIyqy17 Bhl7RXDED1urw6yXUyUBLx6bY3CKzzZbM1nEZPd0VeI/kucJJYtNVssD8Q8fClrYn2Zf lB7HM4QrCmaRQCtAovh6Xj9wBDtOkYU68Ol6YbJaYxbIzndQCcORhWkH0iTfZHn+AQew 0i9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747304756; x=1747909556; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bObN/GZFYIPXswmzQmBrFY+KFYsdoS+icAznneCd2Ck=; b=J3dYYv/ENL9IBfu0KDPGiw6Tkh1U5CUhNRJ0FVjXftEDeKjYErzTlkD3oMm5i3VwMk u3ZxXg/1pNWSzYpoPrU6igQ1A+uZrYpKEPLBsisAhAqHSLLu/bMZU84QuPZwW8SNfYx4 +byqN5UFLuLdpbmC2gMjBAS5YUtVr2SUs5KJpwTrTNH5L9aWSsFEcqn/GGMWIs+WIRjI 5kugVabbZ7LHnx6GcRFjiRyfHFTtXzktS0/FXSV2w8nZBsqZRMiaIPDxH5cOp7KLk97j wUgzTWUP6bsJnXB2sscHXe9TLhX4Bw3WVxWUBZQQffQ9PWd9oSwSYtU5+vumQm8Nqnyc pa+w== X-Gm-Message-State: AOJu0YzQ1iY5RczHcLPJVR7H1idP+31/oSNrSc8ncNqDjmabxFiJu8XN uWSUMN+3IFeNNlj5RNDwEwidu/9mSK/uOLBz4uO/wOLjNhyzr2nzewhuZYvyI19PJlFkDQ9ubUp Fv7I= X-Gm-Gg: ASbGnct6kqyROTzTpaLagu2azTiHFzq3KEv33MN5ymq+pUoQeHwM68ywK5eqzYvGgzr 5wjNed8Ba+mMj7DjdzGAX6h5Vuvut6dJ5/QFW0eAGzj0c+qyv6RlyQN36dn7+VgjUzLQrn+frok JPqIPwrHoD9m/sNEFVfQmOQnyTDKlUE0M98e+QhTuWnVBya5CGVjUo1Vx+5w92Arg4pi/St+Nls aw/htTv7rdRgOZcWpznKMOXL5dlVH1yqUQucPb5n0F0TmEWtN2oj+5hR2U+oW6Jj+sV9aNwKQHy M5wy9lY+Ch1XenspBvu50GDJJEq7dKxgJRfIfP9qdK4P2jPk8CoegT4vLQ== X-Google-Smtp-Source: AGHT+IFjpRYfpelDs03kn3IXJIUEZ74FQp6xhHfY+3vJl2G2FuerLWetFl1gTD/s8JOln/C9qDkITQ== X-Received: by 2002:a05:600c:1e02:b0:43c:ea36:9840 with SMTP id 5b1f17b1804b1-442f970a8dcmr15027585e9.22.1747304755959; Thu, 15 May 2025 03:25:55 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/58] target/arm: Present AArch64 gdbstub based on ARM_FEATURE_AARCH64 Date: Thu, 15 May 2025 11:24:52 +0100 Message-ID: <20250515102546.2149601-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747304924740116600 Currently we provide an AArch64 gdbstub for CPUs which are TYPE_AARCH64_CPU, and an AArch32 gdbstub for those which are only TYPE_ARM_CPU. This mostly does the right thing, except in the corner case of KVM with -cpu host,aarch64=3Doff. That produces a CPU which is TYPE_AARCH64_CPU but which has ARM_FEATURE_AARCH64 removed and which to the guest is in AArch32 mode. Now we have moved all the handling of AArch64-vs-AArch32 gdbstub behaviour into TYPE_ARM_CPU we can change the condition we use for whether to select the AArch64 gdbstub to look at ARM_FEATURE_AARCH64. This will mean that we now correctly provide an AArch32 gdbstub for aarch64=3Doff CPUs. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20250429132200.605611-5-peter.maydell@linaro.org --- target/arm/internals.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 660d3a88e07..a396c0be3b7 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1833,7 +1833,7 @@ void aarch64_add_sme_properties(Object *obj); /* Return true if the gdbstub is presenting an AArch64 CPU */ static inline bool arm_gdbstub_is_aarch64(ARMCPU *cpu) { - return object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU); + return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); } =20 /* Read the CONTROL register as the MRS instruction would. */ --=20 2.43.0 From nobody Fri Dec 19 17:37:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747305576; cv=none; d=zohomail.com; s=zohoarc; b=dLlfiNrC1z0+bnI79N3KDdSLHnEFkJkHTpsrYIzGnsasNm6ePRRbEXGiqP9nLnSyBXFW3ueRXndFEUofJfwmd/bGOeHF0I0h6n9hR/z2ZYnrIL6/pRgrOpgmJyD6ijYRrx+5szVLOAwjflIQ4LaGJkRqMFOUysAoQUhf69pzMkk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747305576; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=V44BClu19+jvYPw+zjT/7PfwtqiqasGrnUcfMcg673Q=; b=VmV6H3BamFm1/IbpKmTbm1KrqAW5h58+WT6XX8/EHVNxhgJbdctOyh1toOmr8dL0D3V/6FwQRE4PyvXdBR3Iz1yrN+XsyOwaoraJALC73bq3QaJKzKxL+i5sjeqXvePRu4ARIXA30wYIXphfUNAFzvpEduj7F2Q4UxkTAtGhsMg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747305575997921.7608814841304; Thu, 15 May 2025 03:39:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uFVmu-0004NR-Ve; Thu, 15 May 2025 06:26:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uFVmq-0004JH-Mx for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:00 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uFVmo-00087G-NU for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:00 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-442ccf0e1b3so9263445e9.3 for ; Thu, 15 May 2025 03:25:58 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442f396c3a4sm65657855e9.26.2025.05.15.03.25.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 03:25:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747304757; x=1747909557; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=V44BClu19+jvYPw+zjT/7PfwtqiqasGrnUcfMcg673Q=; b=CZS+esSn4X67hdD7niZJW2zNGW1xSZjmt9Vp6kQXA/irzEdJfQCJO9peJ7JSaaaI8W YgHcF8wzJ4ITbP5/Nf9yHxmFzneuQpaGw3tMDlx3T1tmLNtb3zxWysOrP169Cc2UFKqY sOF3so3IYCIhQ9G0bjhfmyWUetoH6tqFNjPLeJcmskXmcoxotE8TpynPMvLz0bgaCbSm ZGkIa+IQmAav/CFdKVEvWt2VYwbChGSIbM+wbBK+XeWUooP4NAcj7t9YqoxvfyT/16Qs qqL4MiTygxm/9JkA9XSL8ozoKY1ZYFcNxG5veQKHrh4esa7PCKD6luQKf5Lj/CJudCFK 3RgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747304757; x=1747909557; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=V44BClu19+jvYPw+zjT/7PfwtqiqasGrnUcfMcg673Q=; b=k12AB/syNHqeXeJ0ZAv3WKeSmnVmXOxHpuDJT1QItSIwloeTAzQIl6OT5cURWW4DCa yYa1Tq03KFnTAi1e6RdKPGAvCJSfqQaPfxV4jUbzY+clcytwt3hxywttCVQh7MYRvFiE rEM6hm71RPU4swr0segb/Kg6LzzmBynBGU/nARJxHA5ln4/aR6IBejRE1xeGRm4jI8I5 7bto8FeCDpol1kiM8mABTFEl6JJKPp9DOxbCkKIJ50OnVJdBhluaAuweQRDULg/moEmZ s9xIGkvv3qVPWYb3TeMsLKFWxe24wNhZeXVyio9iWBem96XRXFeW5MjCz0BLNTwy+5cx AEKA== X-Gm-Message-State: AOJu0YxJYEBIEDhsjsSccZMUEn8p/hzfCKp5+j6XRdccytJBJyJMgzYX eesJ8nSKX2/J/HpwttfQf6txsDsZp0jK29v3wUi+zQsjm/z7k2+XS0s0gn82K8XW/mrTVCjtcoB aMaw= X-Gm-Gg: ASbGncvrDcKvHahGWhib8nivoBSfWkSJ8kFw6ARdgrJDbyHphQFwWCoJkaE8EEpYY0g jMIdPdW+3xi7xomQLzluJMzSUWUuQ7IdT6frik+KRK2NtwErlkoVj1UJF11UMvMJzYCEhJ9q2r2 NLXu4/ULm8EcC0IyUcaBKHYeAoNH4TsUeCQjjiWiEaVJ1CcbPRR7SBljM2ySOIG/04XfUbuVRfg 2L+jmDCP9EhULv1NCUCxfh26gyQ7pnurYAa5Voo5lGFLE1PgIRhLzW3rSBABXwnhCUNBjS6LIC4 MJ7+1+LGeB116N3d2jXFvZSoRaNld5JNLMSRXSNi6leo1mkCO/05FmHBgyCjseEvju/y X-Google-Smtp-Source: AGHT+IF2c+SWv/P9+Tpn2LV7RD4SHoKn+nx5riGwMirs1xFP5ntFGsPXnbFQ/pWSdohybR1ZJfxUGg== X-Received: by 2002:a05:600c:c09:b0:43d:82c:2b23 with SMTP id 5b1f17b1804b1-442f2168c29mr54196595e9.23.1747304756870; Thu, 15 May 2025 03:25:56 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/58] target/arm: Move aarch64 CPU property code to TYPE_ARM_CPU Date: Thu, 15 May 2025 11:24:53 +0100 Message-ID: <20250515102546.2149601-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305577964116600 The only thing we have left in the TYPE_AARCH64_CPU class that makes it different to TYPE_ARM_CPU is that we register the handling of the "aarch64" property there. Move the handling of this property to the base class, where we make it a property of the object rather than of the class, and add it to the CPU if it has the ARM_FEATURE_AARCH64 property present at init. This is in line with how we handle other Arm CPU properties, and should not change which CPUs it's visible for. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20250429132200.605611-6-peter.maydell@linaro.org --- target/arm/cpu.c | 36 ++++++++++++++++++++++++++++++++++++ target/arm/cpu64.c | 33 --------------------------------- 2 files changed, 36 insertions(+), 33 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 45cb6fd7eed..603f08d05a0 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1609,6 +1609,35 @@ static void arm_set_pmu(Object *obj, bool value, Err= or **errp) cpu->has_pmu =3D value; } =20 +static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); +} + +static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + /* + * At this time, this property is only allowed if KVM is enabled. This + * restriction allows us to avoid fixing up functionality that assumes= a + * uniform execution state like do_interrupt. + */ + if (value =3D=3D false) { + if (!kvm_enabled() || !kvm_arm_aarch32_supported()) { + error_setg(errp, "'aarch64' feature cannot be disabled " + "unless KVM is enabled and 32-bit EL1 " + "is supported"); + return; + } + unset_feature(&cpu->env, ARM_FEATURE_AARCH64); + } else { + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + } +} + unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) { /* @@ -1736,6 +1765,13 @@ void arm_cpu_post_init(Object *obj) */ arm_cpu_propagate_feature_implications(cpu); =20 + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64, + aarch64_cpu_set_aarch64); + object_property_set_description(obj, "aarch64", + "Set on/off to enable/disable aarc= h64 " + "execution state "); + } if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property= ); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 00629a5d1d1..e527465a3ca 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -781,45 +781,12 @@ static const ARMCPUInfo aarch64_cpus[] =3D { #endif }; =20 -static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); -} - -static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - /* At this time, this property is only allowed if KVM is enabled. This - * restriction allows us to avoid fixing up functionality that assumes= a - * uniform execution state like do_interrupt. - */ - if (value =3D=3D false) { - if (!kvm_enabled() || !kvm_arm_aarch32_supported()) { - error_setg(errp, "'aarch64' feature cannot be disabled " - "unless KVM is enabled and 32-bit EL1 " - "is supported"); - return; - } - unset_feature(&cpu->env, ARM_FEATURE_AARCH64); - } else { - set_feature(&cpu->env, ARM_FEATURE_AARCH64); - } -} - static void aarch64_cpu_finalizefn(Object *obj) { } =20 static void aarch64_cpu_class_init(ObjectClass *oc, const void *data) { - object_class_property_add_bool(oc, "aarch64", aarch64_cpu_get_aarch64, - aarch64_cpu_set_aarch64); - object_class_property_set_description(oc, "aarch64", - "Set on/off to enable/disable aa= rch64 " - "execution state "); } =20 static void aarch64_cpu_instance_init(Object *obj) --=20 2.43.0 From nobody Fri Dec 19 17:37:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747305270; cv=none; d=zohomail.com; s=zohoarc; b=ACSepJn3aMIvIe8lkUl3hvC5odGxudD4ehuTw2Z2P/UFdUPuRw1VUEKzKmahosKH+GkwiUpwmJa+YZPF80pHRCJN8/aEbsS4Idcz8PFRFeHVej9HdCmn3rdX1a4mg+B0FWS+T9qGm/lW2UjzjpLl4giWmhslcw4iJ9NNNYx2B8Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747305270; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Q1yE9IE70+v4hZl3qoJgdI0L4GqLSUpkP/8flgn4noI=; b=TuprVvJgr5bz0JyEpjALvSPLog7GgKIZqacVnhcotmg0r+0P/DJPyeGsOllxL7C76roPIdjrF2g5ZDWUQBkMITlKlC1we37xJWUARy2tqtB4iEKhfrPmiASv6Z+HXP1Byn6tQT8HjdcFG/ohGJu/Kfb96JP4Jm+qLP8OxBcuyqo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747305270467331.9782120186329; Thu, 15 May 2025 03:34:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uFVmt-0004KO-HK; Thu, 15 May 2025 06:26:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uFVmr-0004JZ-DA for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:01 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uFVmp-00087T-Gh for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:01 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-441ab63a415so8013265e9.3 for ; Thu, 15 May 2025 03:25:58 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442f396c3a4sm65657855e9.26.2025.05.15.03.25.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 03:25:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747304758; x=1747909558; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Q1yE9IE70+v4hZl3qoJgdI0L4GqLSUpkP/8flgn4noI=; b=yGJVnTInvsd8dIPAakjKgOBhjgBWrkHf7RrdiW3toM1YBD0w/x942Y3q3cKRKMdpFb toJfoU43/dwJrFoG/CxiCOR/diVrNfyWaT1kF7ZN+wr0NginrMjU3MEdevaolrfpxJIm wJt36fKIGZLJhWKluLUCJxFBB8AgrCVTKbda/og94uFe6OpD95xYOZsLWSHtgFfrckaY C1verJ1cyP8RQi0U+aFDS40kNqe6zpMoQBDE/p3caDBJYRmWNLemZa5/UQ63Y6f0JLOE 4byiHdg+Kg3Hkk8t81+Pzmt3u5r39mw5LMr/AAMmlO0H4ko/oJutmgJZ0Zrb6ZBXYph5 ytPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747304758; x=1747909558; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Q1yE9IE70+v4hZl3qoJgdI0L4GqLSUpkP/8flgn4noI=; b=J+HOPqDN8qSFwWTa3rnpPWnHTqds0ALB4p5wlgUeCcj1MwrNSLR8rfGpDPOfVFrbYM Ln/emWWQ01Y0qXD/KFWPQxDAF6H61TKoe4r56x74yjw+rodJaQHiqOLKag1xtNZDrPMH ogZ/frIzAShBDJRuVv1RC61ZaitMp3coz1k0zdbDif4U3v0slsbVZ6QhpTg8WWOhHVYJ UFUzeXHaVwrXPU4uXDwOA6iTloV+RN2T7rowfOm/tf+H8QpuLFXMQvaN5pJj8xF0LwKy /KtJlSd7eaQXNvNlnf8quHvETE+MkCJqfNHCWNyDxxT6lZBnAvfg2IUQYtgHjvSUTwvU 2SJQ== X-Gm-Message-State: AOJu0YxXmknUcRLcjLCd6pYameOH7TJwSu+m8vjkG16VV9GNYvTm2gX4 FmbUm7di/zTFWRYr+Sb+6euCNhgRqmW7khsr/a1vFTburW9G39re3EPh3cQQkKvDhRmxFOrwQbA Dmh4= X-Gm-Gg: ASbGnctqAvskGJ2e4G+OqXoxF44qkR7XmF+LbEi8BVYPMTuK2ONHpmmiEUfNKhe8KIa hFUrA9btGVIfx0w2hpn0LkQcN1eOb77gOM3MM8FlASE3QsDJnR9cIj5gEDLUhwcpZq2owkNUVsI sLqd8JwOdSu0fVSxqK/ZXR4vFP8d4KYP46WrsizGY45SBA82cZiF66qWnrWw8NmVLNcVTx6vgqj hBCGTWMYM786fUPg+rgb1UePPwY+OlJgfhci7u/BK5IHxjV0Yi4AqG7sLM9V3bCopECAwAphklZ C4/luFcFuAY991ur2fV6/bpuynhw8dNAUMoT3Yib6zM8gtQBiPaX3O0OYQ== X-Google-Smtp-Source: AGHT+IGf0PBiibZVjOa5cxvBtxTvOfwzYzGPhK4aCTcjK0jfUczZnSf3zVLMkUBuKA7Jz5vY2U9MbQ== X-Received: by 2002:a05:600c:4447:b0:43c:f470:7605 with SMTP id 5b1f17b1804b1-442f20e80cbmr65442325e9.12.1747304757832; Thu, 15 May 2025 03:25:57 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/58] target/arm/kvm: don't check TYPE_AARCH64_CPU Date: Thu, 15 May 2025 11:24:54 +0100 Message-ID: <20250515102546.2149601-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305271666116600 We want to merge TYPE_AARCH64_CPU with TYPE_ARM_CPU, so enforcing in kvm_arch_init_vcpu() that the CPU class is a subclass of TYPE_AARCH64_CPU will no longer be possible. It's safe to just remove this test, because any purely-AArch32 CPU will fail the "kvm_target isn't set" check, because we no longer support the old AArch32-host KVM setup and so CPUs like the Cortex-A7 no longer set cpu->kvm_target. Only the 'host', 'max', and the odd special cases 'cortex-a53' and 'cortex-a57' set kvm_target. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20250429132200.605611-7-peter.maydell@linaro.org --- target/arm/kvm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 9c62d12b233..85911e30242 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1843,8 +1843,7 @@ int kvm_arch_init_vcpu(CPUState *cs) CPUARMState *env =3D &cpu->env; uint64_t psciver; =20 - if (cpu->kvm_target =3D=3D QEMU_KVM_ARM_TARGET_NONE || - !object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) { + if (cpu->kvm_target =3D=3D QEMU_KVM_ARM_TARGET_NONE) { error_report("KVM is not supported for this guest CPU type"); return -EINVAL; } --=20 2.43.0 From nobody Fri Dec 19 17:37:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747305484; cv=none; d=zohomail.com; s=zohoarc; b=jiQuAl4bVylc5Cvl4plUTyV5ssIid5lwg6DUHAT2M9aRQP8hzuhyH5oC2MgT7kvZRBoF3Easl/0ZPxgacYDNc8X+VEM8I9bC2oJhrioRTEJEZKw0cuiHJYO+GV1a82LEKtVm39aNHkmG149c8lgpzFqLN8w1hktGfUAZlUZr0I4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747305484; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=zvEbnDk7n0V5mA6cNTidl4bv1ZVHjjW3TCNPh3U2qMA=; b=AIdyWW6Ay4l+63CQGOUIpwbW0taMdwxf0hO8kttPkgxu6pbs8PYsnXMONu0XlzADErMUkIT5RSGRs1+8Z7tXLVSKt407sfZNIXMsbkh66zPNzNzChbQpY+O/mok5mw9TxVwm44fC6rkMtmocGWEdeAhi7raAMTiOp5BwyaA4sZI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747305484500723.1684220375435; Thu, 15 May 2025 03:38:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uFVmu-0004ND-VU; Thu, 15 May 2025 06:26:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uFVmt-0004KR-DU for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:03 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uFVmr-00087s-Ac for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:03 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-43cec5cd73bso5029985e9.3 for ; Thu, 15 May 2025 03:26:00 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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It now has no special behaviour of its own, so we can eliminate it and make the AArch64 CPUs directly inherit from TYPE_ARM_CPU. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20250429132200.605611-8-peter.maydell@linaro.org --- target/arm/cpu-qom.h | 5 ----- target/arm/cpu.h | 4 ---- target/arm/internals.h | 1 - target/arm/cpu64.c | 49 +----------------------------------------- target/arm/tcg/cpu64.c | 2 +- 5 files changed, 2 insertions(+), 59 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index b497667d61e..2fcb0e12525 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -28,11 +28,6 @@ OBJECT_DECLARE_CPU_TYPE(ARMCPU, ARMCPUClass, ARM_CPU) =20 #define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU =20 -#define TYPE_AARCH64_CPU "aarch64-cpu" -typedef struct AArch64CPUClass AArch64CPUClass; -DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, - TYPE_AARCH64_CPU) - #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) =20 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6ed6409cb7a..302c24e2324 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1138,10 +1138,6 @@ struct ARMCPUClass { ResettablePhases parent_phases; }; =20 -struct AArch64CPUClass { - ARMCPUClass parent_class; -}; - /* Callback functions for the generic timer's timers. */ void arm_gt_ptimer_cb(void *opaque); void arm_gt_vtimer_cb(void *opaque); diff --git a/target/arm/internals.h b/target/arm/internals.h index a396c0be3b7..702eb1a5483 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -354,7 +354,6 @@ static inline int r14_bank_number(int mode) } =20 void arm_cpu_register(const ARMCPUInfo *info); -void aarch64_cpu_register(const ARMCPUInfo *info); =20 void register_cp_regs_for_features(ARMCPU *cpu); void init_cpreg_list(ARMCPU *cpu); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index e527465a3ca..200da1c489b 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -781,59 +781,12 @@ static const ARMCPUInfo aarch64_cpus[] =3D { #endif }; =20 -static void aarch64_cpu_finalizefn(Object *obj) -{ -} - -static void aarch64_cpu_class_init(ObjectClass *oc, const void *data) -{ -} - -static void aarch64_cpu_instance_init(Object *obj) -{ - ARMCPUClass *acc =3D ARM_CPU_GET_CLASS(obj); - - acc->info->initfn(obj); - arm_cpu_post_init(obj); -} - -static void cpu_register_class_init(ObjectClass *oc, const void *data) -{ - ARMCPUClass *acc =3D ARM_CPU_CLASS(oc); - - acc->info =3D data; -} - -void aarch64_cpu_register(const ARMCPUInfo *info) -{ - TypeInfo type_info =3D { - .parent =3D TYPE_AARCH64_CPU, - .instance_init =3D aarch64_cpu_instance_init, - .class_init =3D info->class_init ?: cpu_register_class_init, - .class_data =3D info, - }; - - type_info.name =3D g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); - type_register_static(&type_info); - g_free((void *)type_info.name); -} - -static const TypeInfo aarch64_cpu_type_info =3D { - .name =3D TYPE_AARCH64_CPU, - .parent =3D TYPE_ARM_CPU, - .instance_finalize =3D aarch64_cpu_finalizefn, - .abstract =3D true, - .class_init =3D aarch64_cpu_class_init, -}; - static void aarch64_cpu_register_types(void) { size_t i; =20 - type_register_static(&aarch64_cpu_type_info); - for (i =3D 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { - aarch64_cpu_register(&aarch64_cpus[i]); + arm_cpu_register(&aarch64_cpus[i]); } } =20 diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 29ab0ac79da..5d8ed2794d3 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1316,7 +1316,7 @@ static void aarch64_cpu_register_types(void) size_t i; =20 for (i =3D 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { - aarch64_cpu_register(&aarch64_cpus[i]); + arm_cpu_register(&aarch64_cpus[i]); } } =20 --=20 2.43.0 From nobody Fri Dec 19 17:37:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747305051; cv=none; d=zohomail.com; s=zohoarc; b=eegeKuTSHSpdQaWArUWTDttecFytIM1ALVP4vcZnVFLMO689oT4yGPvsvUHYpiigLyuR/R05UwPVXvXjjziDJZfHVdWeeFeSY/YRFKj/vv5Mf86QsfAIr0nHPnQovtuHBlzwhzyo/6CKrU0b5PBu4Mqa+FnfWnzP0B5S67IGcGs= ARC-Message-Signature: i=1; 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This is much more commentary than we typically quote from a device reference manual, and much of it is not relevant to QEMU. Compress and rephrase the comments so that we are not quoting such a large volume of TRM text. We add a URL for the TRM; readers who need more detail on the function of the register bits can find it there, presented in context with the overall description of the hardware. Signed-off-by: Peter Maydell Reviewed-by: Daniel P. Berrang=C3=A9 --- rust/hw/char/pl011/src/registers.rs | 261 ++++++---------------------- 1 file changed, 51 insertions(+), 210 deletions(-) diff --git a/rust/hw/char/pl011/src/registers.rs b/rust/hw/char/pl011/src/r= egisters.rs index cd92fa2c300..690feb63785 100644 --- a/rust/hw/char/pl011/src/registers.rs +++ b/rust/hw/char/pl011/src/registers.rs @@ -5,13 +5,13 @@ //! Device registers exposed as typed structs which are backed by arbitrary //! integer bitmaps. [`Data`], [`Control`], [`LineControl`], etc. =20 +// For more detail see the PL011 Technical Reference Manual DDI0183: +// https://developer.arm.com/documentation/ddi0183/latest/ + use bilge::prelude::*; use qemu_api::impl_vmstate_bitsized; =20 /// Offset of each register from the base memory address of the device. -/// -/// # Source -/// ARM DDI 0183G, Table 3-1 p.3-3 #[doc(alias =3D "offset")] #[allow(non_camel_case_types)] #[repr(u64)] @@ -87,48 +87,11 @@ pub struct Errors { _reserved_unpredictable: u4, } =20 -// TODO: FIFO Mode has different semantics /// Data Register, `UARTDR` /// -/// The `UARTDR` register is the data register. -/// -/// For words to be transmitted: -/// -/// - if the FIFOs are enabled, data written to this location is pushed on= to the -/// transmit -/// FIFO -/// - if the FIFOs are not enabled, data is stored in the transmitter hold= ing -/// register (the -/// bottom word of the transmit FIFO). -/// -/// The write operation initiates transmission from the UART. The data is -/// prefixed with a start bit, appended with the appropriate parity bit -/// (if parity is enabled), and a stop bit. The resultant word is then -/// transmitted. -/// -/// For received words: -/// -/// - if the FIFOs are enabled, the data byte and the 4-bit status (break, -/// frame, parity, -/// and overrun) is pushed onto the 12-bit wide receive FIFO -/// - if the FIFOs are not enabled, the data byte and status are stored in= the -/// receiving -/// holding register (the bottom word of the receive FIFO). -/// -/// The received data byte is read by performing reads from the `UARTDR` -/// register along with the corresponding status information. The status -/// information can also be read by a read of the `UARTRSR/UARTECR` -/// register. -/// -/// # Note -/// -/// You must disable the UART before any of the control registers are -/// reprogrammed. When the UART is disabled in the middle of -/// transmission or reception, it completes the current character before -/// stopping. -/// -/// # Source -/// ARM DDI 0183G 3.3.1 Data Register, UARTDR +/// The `UARTDR` register is the data register; write for TX and +/// read for RX. It is a 12-bit register, where bits 7..0 are the +/// character and bits 11..8 are error bits. #[bitsize(32)] #[derive(Clone, Copy, Default, DebugBits, FromBits)] #[doc(alias =3D "UARTDR")] @@ -144,30 +107,17 @@ impl Data { pub const BREAK: Self =3D Self { value: 1 << 10 }; } =20 -// TODO: FIFO Mode has different semantics /// Receive Status Register / Error Clear Register, `UARTRSR/UARTECR` /// -/// The UARTRSR/UARTECR register is the receive status register/error clear -/// register. Receive status can also be read from the `UARTRSR` -/// register. If the status is read from this register, then the status -/// information for break, framing and parity corresponds to the -/// data character read from the [Data register](Data), `UARTDR` prior to -/// reading the UARTRSR register. The status information for overrun is -/// set immediately when an overrun condition occurs. +/// This register provides a different way to read the four receive +/// status error bits that can be found in bits 11..8 of the UARTDR +/// on a read. It gets updated when the guest reads UARTDR, and the +/// status bits correspond to that character that was just read. /// -/// -/// # Note -/// The received data character must be read first from the [Data -/// Register](Data), `UARTDR` before reading the error status associated -/// with that data character from the `UARTRSR` register. This read -/// sequence cannot be reversed, because the `UARTRSR` register is -/// updated only when a read occurs from the `UARTDR` register. However, -/// the status information can also be obtained by reading the `UARTDR` -/// register -/// -/// # Source -/// ARM DDI 0183G 3.3.2 Receive Status Register/Error Clear Register, -/// UARTRSR/UARTECR +/// The TRM confusingly describes this offset as UARTRSR for reads +/// and UARTECR for writes, but really it's a single error status +/// register where writing anything to the register clears the error +/// bits. #[bitsize(32)] #[derive(Clone, Copy, DebugBits, FromBits)] pub struct ReceiveStatusErrorClear { @@ -196,54 +146,29 @@ fn default() -> Self { #[bitsize(32)] #[derive(Clone, Copy, DebugBits, FromBits)] /// Flag Register, `UARTFR` +/// +/// This has the usual inbound RS232 modem-control signals, plus flags +/// for RX and TX FIFO fill levels and a BUSY flag. #[doc(alias =3D "UARTFR")] pub struct Flags { - /// CTS Clear to send. This bit is the complement of the UART clear to - /// send, `nUARTCTS`, modem status input. That is, the bit is 1 - /// when `nUARTCTS` is LOW. + /// CTS: Clear to send pub clear_to_send: bool, - /// DSR Data set ready. This bit is the complement of the UART data set - /// ready, `nUARTDSR`, modem status input. That is, the bit is 1 when - /// `nUARTDSR` is LOW. + /// DSR: Data set ready pub data_set_ready: bool, - /// DCD Data carrier detect. This bit is the complement of the UART da= ta - /// carrier detect, `nUARTDCD`, modem status input. That is, the bit is - /// 1 when `nUARTDCD` is LOW. + /// DCD: Data carrier detect pub data_carrier_detect: bool, - /// BUSY UART busy. If this bit is set to 1, the UART is busy - /// transmitting data. This bit remains set until the complete - /// byte, including all the stop bits, has been sent from the - /// shift register. This bit is set as soon as the transmit FIFO - /// becomes non-empty, regardless of whether the UART is enabled - /// or not. + /// BUSY: UART busy. In real hardware, set while the UART is + /// busy transmitting data. QEMU's implementation never sets BUSY. pub busy: bool, - /// RXFE Receive FIFO empty. The meaning of this bit depends on the - /// state of the FEN bit in the UARTLCR_H register. If the FIFO - /// is disabled, this bit is set when the receive holding - /// register is empty. If the FIFO is enabled, the RXFE bit is - /// set when the receive FIFO is empty. + /// RXFE: Receive FIFO empty pub receive_fifo_empty: bool, - /// TXFF Transmit FIFO full. The meaning of this bit depends on the - /// state of the FEN bit in the UARTLCR_H register. If the FIFO - /// is disabled, this bit is set when the transmit holding - /// register is full. If the FIFO is enabled, the TXFF bit is - /// set when the transmit FIFO is full. + /// TXFF: Transmit FIFO full pub transmit_fifo_full: bool, - /// RXFF Receive FIFO full. The meaning of this bit depends on the sta= te - /// of the FEN bit in the UARTLCR_H register. If the FIFO is - /// disabled, this bit is set when the receive holding register - /// is full. If the FIFO is enabled, the RXFF bit is set when - /// the receive FIFO is full. + /// RXFF: Receive FIFO full pub receive_fifo_full: bool, - /// Transmit FIFO empty. The meaning of this bit depends on the state = of - /// the FEN bit in the [Line Control register](LineControl), - /// `UARTLCR_H`. If the FIFO is disabled, this bit is set when the - /// transmit holding register is empty. If the FIFO is enabled, - /// the TXFE bit is set when the transmit FIFO is empty. This - /// bit does not indicate if there is data in the transmit shift - /// register. + /// TXFE: Transmit FIFO empty pub transmit_fifo_empty: bool, - /// `RI`, is `true` when `nUARTRI` is `LOW`. + /// RI: Ring indicator pub ring_indicator: bool, _reserved_zero_no_modify: u23, } @@ -270,54 +195,23 @@ fn default() -> Self { /// Line Control Register, `UARTLCR_H` #[doc(alias =3D "UARTLCR_H")] pub struct LineControl { - /// BRK Send break. - /// - /// If this bit is set to `1`, a low-level is continually output on the - /// `UARTTXD` output, after completing transmission of the - /// current character. For the proper execution of the break command, - /// the software must set this bit for at least two complete - /// frames. For normal use, this bit must be cleared to `0`. + /// BRK: Send break pub send_break: bool, - /// 1 PEN Parity enable: - /// - /// - 0 =3D parity is disabled and no parity bit added to the data fra= me - /// - 1 =3D parity checking and generation is enabled. - /// - /// See Table 3-11 on page 3-14 for the parity truth table. + /// PEN: Parity enable pub parity_enabled: bool, - /// EPS Even parity select. Controls the type of parity the UART uses - /// during transmission and reception: - /// - 0 =3D odd parity. The UART generates or checks for an odd number= of 1s - /// in the data and parity bits. - /// - 1 =3D even parity. The UART generates or checks for an even numb= er of 1s - /// in the data and parity bits. - /// This bit has no effect when the `PEN` bit disables parity checking - /// and generation. See Table 3-11 on page 3-14 for the parity - /// truth table. + /// EPS: Even parity select pub parity: Parity, - /// 3 STP2 Two stop bits select. If this bit is set to 1, two stop bits - /// are transmitted at the end of the frame. The receive - /// logic does not check for two stop bits being received. + /// STP2: Two stop bits select pub two_stops_bits: bool, - /// FEN Enable FIFOs: - /// 0 =3D FIFOs are disabled (character mode) that is, the FIFOs become - /// 1-byte-deep holding registers 1 =3D transmit and receive FIFO - /// buffers are enabled (FIFO mode). + /// FEN: Enable FIFOs pub fifos_enabled: Mode, - /// WLEN Word length. These bits indicate the number of data bits - /// transmitted or received in a frame as follows: b11 =3D 8 bits + /// WLEN: Word length in bits + /// b11 =3D 8 bits /// b10 =3D 7 bits /// b01 =3D 6 bits /// b00 =3D 5 bits. pub word_length: WordLength, - /// 7 SPS Stick parity select. - /// 0 =3D stick parity is disabled - /// 1 =3D either: - /// =E2=80=A2 if the EPS bit is 0 then the parity bit is transmitted a= nd checked - /// as a 1 =E2=80=A2 if the EPS bit is 1 then the parity bit is - /// transmitted and checked as a 0. This bit has no effect when - /// the PEN bit disables parity checking and generation. See Table 3-11 - /// on page 3-14 for the parity truth table. + /// SPS Stick parity select pub sticky_parity: bool, /// 31:8 - Reserved, do not modify, read as zero. _reserved_zero_no_modify: u24, @@ -342,11 +236,7 @@ fn default() -> Self { /// `EPS` "Even parity select", field of [Line Control /// register](LineControl). pub enum Parity { - /// - 0 =3D odd parity. The UART generates or checks for an odd number= of 1s - /// in the data and parity bits. Odd =3D 0, - /// - 1 =3D even parity. The UART generates or checks for an even numb= er of 1s - /// in the data and parity bits. Even =3D 1, } =20 @@ -381,88 +271,39 @@ pub enum WordLength { =20 /// Control Register, `UARTCR` /// -/// The `UARTCR` register is the control register. All the bits are cleared -/// to `0` on reset except for bits `9` and `8` that are set to `1`. -/// -/// # Source -/// ARM DDI 0183G, 3.3.8 Control Register, `UARTCR`, Table 3-12 +/// The `UARTCR` register is the control register. It contains various +/// enable bits, and the bits to write to set the usual outbound RS232 +/// modem control signals. All bits reset to 0 except TXE and RXE. #[bitsize(32)] #[doc(alias =3D "UARTCR")] #[derive(Clone, Copy, DebugBits, FromBits)] pub struct Control { - /// `UARTEN` UART enable: 0 =3D UART is disabled. If the UART is disab= led - /// in the middle of transmission or reception, it completes the curre= nt - /// character before stopping. 1 =3D the UART is enabled. Data - /// transmission and reception occurs for either UART signals or SIR - /// signals depending on the setting of the SIREN bit. + /// `UARTEN` UART enable: 0 =3D UART is disabled. pub enable_uart: bool, - /// `SIREN` `SIR` enable: 0 =3D IrDA SIR ENDEC is disabled. `nSIROUT` - /// remains LOW (no light pulse generated), and signal transitions on - /// SIRIN have no effect. 1 =3D IrDA SIR ENDEC is enabled. Data is - /// transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIG= H, - /// in the marking state. Signal transitions on UARTRXD or modem status - /// inputs have no effect. This bit has no effect if the UARTEN bit - /// disables the UART. + /// `SIREN` `SIR` enable: disable or enable IrDA SIR ENDEC. + /// QEMU does not model this. pub enable_sir: bool, - /// `SIRLP` SIR low-power IrDA mode. This bit selects the IrDA encoding - /// mode. If this bit is cleared to 0, low-level bits are transmitted = as - /// an active high pulse with a width of 3/ 16th of the bit period. If - /// this bit is set to 1, low-level bits are transmitted with a pulse - /// width that is 3 times the period of the IrLPBaud16 input signal, - /// regardless of the selected bit rate. Setting this bit uses less - /// power, but might reduce transmission distances. + /// `SIRLP` SIR low-power IrDA mode. QEMU does not model this. pub sir_lowpower_irda_mode: u1, /// Reserved, do not modify, read as zero. _reserved_zero_no_modify: u4, - /// `LBE` Loopback enable. If this bit is set to 1 and the SIREN bit is - /// set to 1 and the SIRTEST bit in the Test Control register, UARTTCR - /// on page 4-5 is set to 1, then the nSIROUT path is inverted, and fed - /// through to the SIRIN path. The SIRTEST bit in the test register mu= st - /// be set to 1 to override the normal half-duplex SIR operation. This - /// must be the requirement for accessing the test registers during - /// normal operation, and SIRTEST must be cleared to 0 when loopback - /// testing is finished. This feature reduces the amount of external - /// coupling required during system test. If this bit is set to 1, and - /// the SIRTEST bit is set to 0, the UARTTXD path is fed through to the - /// UARTRXD path. In either SIR mode or UART mode, when this bit is se= t, - /// the modem outputs are also fed through to the modem inputs. This b= it - /// is cleared to 0 on reset, to disable loopback. + /// `LBE` Loopback enable: feed UART output back to the input pub enable_loopback: bool, - /// `TXE` Transmit enable. If this bit is set to 1, the transmit secti= on - /// of the UART is enabled. Data transmission occurs for either UART - /// signals, or SIR signals depending on the setting of the SIREN bit. - /// When the UART is disabled in the middle of transmission, it - /// completes the current character before stopping. + /// `TXE` Transmit enable pub enable_transmit: bool, - /// `RXE` Receive enable. If this bit is set to 1, the receive section - /// of the UART is enabled. Data reception occurs for either UART - /// signals or SIR signals depending on the setting of the SIREN bit. - /// When the UART is disabled in the middle of reception, it completes - /// the current character before stopping. + /// `RXE` Receive enable pub enable_receive: bool, - /// `DTR` Data transmit ready. This bit is the complement of the UART - /// data transmit ready, `nUARTDTR`, modem status output. That is, when - /// the bit is programmed to a 1 then `nUARTDTR` is LOW. + /// `DTR` Data transmit ready pub data_transmit_ready: bool, - /// `RTS` Request to send. This bit is the complement of the UART - /// request to send, `nUARTRTS`, modem status output. That is, when the - /// bit is programmed to a 1 then `nUARTRTS` is LOW. + /// `RTS` Request to send pub request_to_send: bool, - /// `Out1` This bit is the complement of the UART Out1 (`nUARTOut1`) - /// modem status output. That is, when the bit is programmed to a 1 the - /// output is 0. For DTE this can be used as Data Carrier Detect (DCD). + /// `Out1` UART Out1 signal; can be used as DCD pub out_1: bool, - /// `Out2` This bit is the complement of the UART Out2 (`nUARTOut2`) - /// modem status output. That is, when the bit is programmed to a 1, t= he - /// output is 0. For DTE this can be used as Ring Indicator (RI). + /// `Out2` UART Out2 signal; can be used as RI pub out_2: bool, - /// `RTSEn` RTS hardware flow control enable. If this bit is set to 1, - /// RTS hardware flow control is enabled. Data is only requested when - /// there is space in the receive FIFO for it to be received. + /// `RTSEn` RTS hardware flow control enable pub rts_hardware_flow_control_enable: bool, - /// `CTSEn` CTS hardware flow control enable. If this bit is set to 1, - /// CTS hardware flow control is enabled. Data is only transmitted when - /// the `nUARTCTS` signal is asserted. + /// `CTSEn` CTS hardware flow control enable pub cts_hardware_flow_control_enable: bool, /// 31:16 - Reserved, do not modify, read as zero. _reserved_zero_no_modify2: u16, --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747305353; cv=none; d=zohomail.com; s=zohoarc; b=VIuWGh6EIemF/CYKsQ+w0ywL/uoFs1OlI4D0qJ6NqlUoGteWYQrTnT0NwRpzoYUfZYHYRI7FteiMaWWvGKUzUYvbcP+bMeB7/DkDw01pMBdlsA1X1skjZOMNtdvgiYGboyhKzIMzRUk0S9P1Rz/rxgbx2JI5EPvPMs6EnYlIrrQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747305353; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=kJS0qdxrcVwU1ns/laR+ZxTJ7In/lnQUzlm7LLPC2Cw=; b=HNXYCpjFUzqnbXFRxTwFJkKLKgvkikskGYs7aRYYk6HHx8x8SGF0WKCDbzJ6QLVPQu7nXpQy4njU9tEkys3X23IdCKft28XZARHnpjEs54eU6WF3B2eRDrGawPKCpCJTPI5q+xgiQoAOYBc4KtY73Ak9Dt2W5o8Oc/mr4AoNG3E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747305353576599.2726834438579; Thu, 15 May 2025 03:35:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uFVn4-0004R0-3B; Thu, 15 May 2025 06:26:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uFVn1-0004QV-SE for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:11 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uFVmw-00088b-6t for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:11 -0400 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-3a0b7fbdde7so668984f8f.2 for ; Thu, 15 May 2025 03:26:05 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442f396c3a4sm65657855e9.26.2025.05.15.03.26.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 03:26:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747304764; x=1747909564; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=kJS0qdxrcVwU1ns/laR+ZxTJ7In/lnQUzlm7LLPC2Cw=; b=PHzEMzLeAuNA36W6cQ1wT8CSV9nVvXP11dRWFEhQjHRAuix2kRKX3NIWLEybWbOhK8 jlHobTRQMJqD0JQY1rIOuZmrGQHE0Rt0T+mmWfBg3w1nFXP1VOt765A/A3fc+QPHjXEb s0FQX4iVtWt6zjfe8k7qOfRQtTUGpLEZF7fWdi9hTuByFEe8W0v/ZYXss1kE6LwTIYF1 44WNS54ugc6CEIywmPEk8sJ8XFA8W3V0CerLRBTYTGGmEhtiIPNmw/92pkI9gUOj+AjX Sx3hRpQDsTdIkrKVeQPyT+4nPGVxWSEencdbtibTtMvq+4EYq32UHj1ljsq0oGkHD4RJ 7f8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747304764; x=1747909564; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kJS0qdxrcVwU1ns/laR+ZxTJ7In/lnQUzlm7LLPC2Cw=; b=w268kuZHRbhNGwhVesJ2UHSd9u90CqJyLp6SQWLPonVDgf+iG19qleb9zFS8QTS3xp AxwnquQWGMY4akuUEJyja900H71n5Z8MOyOzVvLlqPtOQHjnQrTZJgYIyFvzMObi0Lwh NQhZT5z151I00nZp1M0pgV3g8IJrN0wQvOlx9jVNOuMUIJ2LrPY6fwZtnDDpc3SMnfzM FAwjthUbxt+L9OjUPznqHVE+oLXio4L+icbTKsqxZksmu6aELfFNcdnzyLKfF6F5CA44 0eQlXX/oS+MA81DRv4af/oLURgNH24mjjuknG/S63tEehKg1cY5V5S7ax8QFSgZ9veKT oy0w== X-Gm-Message-State: AOJu0Yyda1J4ybcPf7zLS9Og2bprGWOuc3fToCiMIVI8BdNnRFM2oqXv xJHP6QHwa166u0kTwm3V7mjXmq9BSjT6ivUr35vcQir8QJILpVYSa2W8s1BIx0jV5i0uM+C4sJp 9OVA= X-Gm-Gg: ASbGncstCCyJxjz0OAQ4wXkJkrA/jj2XKJsIjY0seXP+EqmmmAzPajLL3z1luAxrDzg XfLlqUYplVfBoI2jg1j6NkH2q1q2YHhWa4tlEQcCKDPziJa62S4VKQ5V65WoxvdIm60TCrLnlXb c+wr6f1xrK56tJALooX73MJGXRK4TMzleUHGYTPhgRu04CdN0twu+gx1Q9xi4rD2ED8nyG2wyni H2ihrp2qBv42TpjNLTbHmABU+MCBXJlPDf5JxFjIYVSjVj/isqup61MmrZS3C76fk2/qHBpbaG3 YLsh3cWMkygP4/mloZpJxhsrTrIZRJ1UnzTbYEpVNt1JGGRqbUwpNkQD8A== X-Google-Smtp-Source: AGHT+IEWxPBmFaSyRhgLmtuPIncMmun0qQVNTEeJAnOEQiOWBLc/bgSM43F8V0ui2wtl6k9cEXHW8A== X-Received: by 2002:a05:6000:2ac:b0:3a3:5ae4:6e8e with SMTP id ffacd0b85a97d-3a35ae471a7mr808069f8f.11.1747304762906; Thu, 15 May 2025 03:26:02 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/58] hw/arm: Replace TABs for spaces in OMAP board and device code Date: Thu, 15 May 2025 11:24:57 +0100 Message-ID: <20250515102546.2149601-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305354242116600 Content-Type: text/plain; charset="utf-8" From: Santiago Monserrat Campanello In hw/arm and include/hw/arm, some source files for the OMAP SoC and the sx1 boards that are our only remaining OMAP boards still have hard-coded tabs (almost entirely used for the indent on inline comments, not for actual code indent). Replace the tabs with spaces using vim :retab. I used 4 spaces except in some defines and comments where I tried to put everything aligned in the same column for better readability. This commit is a purely whitespace-only change. Signed-off-by: Santiago Monserrat Campanello Message-id: 20250505131130.82206-1-santimonserr@gmail.com Resolves: https://gitlab.com/qemu-project/qemu/-/issues/373 [PMM: expanded commit message] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/omap.h | 534 ++++++++++---------- include/hw/arm/sharpsl.h | 2 +- include/hw/arm/soc_dma.h | 4 +- hw/arm/omap1.c | 1016 +++++++++++++++++++------------------- hw/arm/omap_sx1.c | 2 +- hw/dma/omap_dma.c | 334 ++++++------- hw/gpio/omap_gpio.c | 28 +- hw/i2c/omap_i2c.c | 178 +++---- hw/intc/omap_intc.c | 154 +++--- hw/misc/omap_clk.c | 470 +++++++++--------- hw/timer/pxa2xx_timer.c | 76 +-- 11 files changed, 1399 insertions(+), 1399 deletions(-) diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h index 6185507373d..bdb2e887e47 100644 --- a/include/hw/arm/omap.h +++ b/include/hw/arm/omap.h @@ -25,24 +25,24 @@ #include "qemu/log.h" #include "qom/object.h" =20 -# define OMAP_EMIFS_BASE 0x00000000 -# define OMAP_CS0_BASE 0x00000000 -# define OMAP_CS1_BASE 0x04000000 -# define OMAP_CS2_BASE 0x08000000 -# define OMAP_CS3_BASE 0x0c000000 -# define OMAP_EMIFF_BASE 0x10000000 -# define OMAP_IMIF_BASE 0x20000000 -# define OMAP_LOCALBUS_BASE 0x30000000 -# define OMAP_MPUI_BASE 0xe1000000 +#define OMAP_EMIFS_BASE 0x00000000 +#define OMAP_CS0_BASE 0x00000000 +#define OMAP_CS1_BASE 0x04000000 +#define OMAP_CS2_BASE 0x08000000 +#define OMAP_CS3_BASE 0x0c000000 +#define OMAP_EMIFF_BASE 0x10000000 +#define OMAP_IMIF_BASE 0x20000000 +#define OMAP_LOCALBUS_BASE 0x30000000 +#define OMAP_MPUI_BASE 0xe1000000 =20 -# define OMAP730_SRAM_SIZE 0x00032000 -# define OMAP15XX_SRAM_SIZE 0x00030000 -# define OMAP16XX_SRAM_SIZE 0x00004000 -# define OMAP1611_SRAM_SIZE 0x0003e800 -# define OMAP_CS0_SIZE 0x04000000 -# define OMAP_CS1_SIZE 0x04000000 -# define OMAP_CS2_SIZE 0x04000000 -# define OMAP_CS3_SIZE 0x04000000 +#define OMAP730_SRAM_SIZE 0x00032000 +#define OMAP15XX_SRAM_SIZE 0x00030000 +#define OMAP16XX_SRAM_SIZE 0x00004000 +#define OMAP1611_SRAM_SIZE 0x0003e800 +#define OMAP_CS0_SIZE 0x04000000 +#define OMAP_CS1_SIZE 0x04000000 +#define OMAP_CS2_SIZE 0x04000000 +#define OMAP_CS3_SIZE 0x04000000 =20 /* omap_clk.c */ struct omap_mpu_state_s; @@ -103,228 +103,228 @@ void omap_gpio_set_clk(Omap1GpioState *gpio, omap_c= lk clk); * Common IRQ numbers for level 1 interrupt handler * See /usr/include/asm-arm/arch-omap/irqs.h in Linux. */ -# define OMAP_INT_CAMERA 1 -# define OMAP_INT_FIQ 3 -# define OMAP_INT_RTDX 6 -# define OMAP_INT_DSP_MMU_ABORT 7 -# define OMAP_INT_HOST 8 -# define OMAP_INT_ABORT 9 -# define OMAP_INT_BRIDGE_PRIV 13 -# define OMAP_INT_GPIO_BANK1 14 -# define OMAP_INT_UART3 15 -# define OMAP_INT_TIMER3 16 -# define OMAP_INT_DMA_CH0_6 19 -# define OMAP_INT_DMA_CH1_7 20 -# define OMAP_INT_DMA_CH2_8 21 -# define OMAP_INT_DMA_CH3 22 -# define OMAP_INT_DMA_CH4 23 -# define OMAP_INT_DMA_CH5 24 -# define OMAP_INT_DMA_LCD 25 -# define OMAP_INT_TIMER1 26 -# define OMAP_INT_WD_TIMER 27 -# define OMAP_INT_BRIDGE_PUB 28 -# define OMAP_INT_TIMER2 30 -# define OMAP_INT_LCD_CTRL 31 +#define OMAP_INT_CAMERA 1 +#define OMAP_INT_FIQ 3 +#define OMAP_INT_RTDX 6 +#define OMAP_INT_DSP_MMU_ABORT 7 +#define OMAP_INT_HOST 8 +#define OMAP_INT_ABORT 9 +#define OMAP_INT_BRIDGE_PRIV 13 +#define OMAP_INT_GPIO_BANK1 14 +#define OMAP_INT_UART3 15 +#define OMAP_INT_TIMER3 16 +#define OMAP_INT_DMA_CH0_6 19 +#define OMAP_INT_DMA_CH1_7 20 +#define OMAP_INT_DMA_CH2_8 21 +#define OMAP_INT_DMA_CH3 22 +#define OMAP_INT_DMA_CH4 23 +#define OMAP_INT_DMA_CH5 24 +#define OMAP_INT_DMA_LCD 25 +#define OMAP_INT_TIMER1 26 +#define OMAP_INT_WD_TIMER 27 +#define OMAP_INT_BRIDGE_PUB 28 +#define OMAP_INT_TIMER2 30 +#define OMAP_INT_LCD_CTRL 31 =20 /* * Common OMAP-15xx IRQ numbers for level 1 interrupt handler */ -# define OMAP_INT_15XX_IH2_IRQ 0 -# define OMAP_INT_15XX_LB_MMU 17 -# define OMAP_INT_15XX_LOCAL_BUS 29 +#define OMAP_INT_15XX_IH2_IRQ 0 +#define OMAP_INT_15XX_LB_MMU 17 +#define OMAP_INT_15XX_LOCAL_BUS 29 =20 /* * OMAP-1510 specific IRQ numbers for level 1 interrupt handler */ -# define OMAP_INT_1510_SPI_TX 4 -# define OMAP_INT_1510_SPI_RX 5 -# define OMAP_INT_1510_DSP_MAILBOX1 10 -# define OMAP_INT_1510_DSP_MAILBOX2 11 +#define OMAP_INT_1510_SPI_TX 4 +#define OMAP_INT_1510_SPI_RX 5 +#define OMAP_INT_1510_DSP_MAILBOX1 10 +#define OMAP_INT_1510_DSP_MAILBOX2 11 =20 /* * OMAP-310 specific IRQ numbers for level 1 interrupt handler */ -# define OMAP_INT_310_McBSP2_TX 4 -# define OMAP_INT_310_McBSP2_RX 5 -# define OMAP_INT_310_HSB_MAILBOX1 12 -# define OMAP_INT_310_HSAB_MMU 18 +#define OMAP_INT_310_McBSP2_TX 4 +#define OMAP_INT_310_McBSP2_RX 5 +#define OMAP_INT_310_HSB_MAILBOX1 12 +#define OMAP_INT_310_HSAB_MMU 18 =20 /* * OMAP-1610 specific IRQ numbers for level 1 interrupt handler */ -# define OMAP_INT_1610_IH2_IRQ 0 -# define OMAP_INT_1610_IH2_FIQ 2 -# define OMAP_INT_1610_McBSP2_TX 4 -# define OMAP_INT_1610_McBSP2_RX 5 -# define OMAP_INT_1610_DSP_MAILBOX1 10 -# define OMAP_INT_1610_DSP_MAILBOX2 11 -# define OMAP_INT_1610_LCD_LINE 12 -# define OMAP_INT_1610_GPTIMER1 17 -# define OMAP_INT_1610_GPTIMER2 18 -# define OMAP_INT_1610_SSR_FIFO_0 29 +#define OMAP_INT_1610_IH2_IRQ 0 +#define OMAP_INT_1610_IH2_FIQ 2 +#define OMAP_INT_1610_McBSP2_TX 4 +#define OMAP_INT_1610_McBSP2_RX 5 +#define OMAP_INT_1610_DSP_MAILBOX1 10 +#define OMAP_INT_1610_DSP_MAILBOX2 11 +#define OMAP_INT_1610_LCD_LINE 12 +#define OMAP_INT_1610_GPTIMER1 17 +#define OMAP_INT_1610_GPTIMER2 18 +#define OMAP_INT_1610_SSR_FIFO_0 29 =20 /* * OMAP-730 specific IRQ numbers for level 1 interrupt handler */ -# define OMAP_INT_730_IH2_FIQ 0 -# define OMAP_INT_730_IH2_IRQ 1 -# define OMAP_INT_730_USB_NON_ISO 2 -# define OMAP_INT_730_USB_ISO 3 -# define OMAP_INT_730_ICR 4 -# define OMAP_INT_730_EAC 5 -# define OMAP_INT_730_GPIO_BANK1 6 -# define OMAP_INT_730_GPIO_BANK2 7 -# define OMAP_INT_730_GPIO_BANK3 8 -# define OMAP_INT_730_McBSP2TX 10 -# define OMAP_INT_730_McBSP2RX 11 -# define OMAP_INT_730_McBSP2RX_OVF 12 -# define OMAP_INT_730_LCD_LINE 14 -# define OMAP_INT_730_GSM_PROTECT 15 -# define OMAP_INT_730_TIMER3 16 -# define OMAP_INT_730_GPIO_BANK5 17 -# define OMAP_INT_730_GPIO_BANK6 18 -# define OMAP_INT_730_SPGIO_WR 29 +#define OMAP_INT_730_IH2_FIQ 0 +#define OMAP_INT_730_IH2_IRQ 1 +#define OMAP_INT_730_USB_NON_ISO 2 +#define OMAP_INT_730_USB_ISO 3 +#define OMAP_INT_730_ICR 4 +#define OMAP_INT_730_EAC 5 +#define OMAP_INT_730_GPIO_BANK1 6 +#define OMAP_INT_730_GPIO_BANK2 7 +#define OMAP_INT_730_GPIO_BANK3 8 +#define OMAP_INT_730_McBSP2TX 10 +#define OMAP_INT_730_McBSP2RX 11 +#define OMAP_INT_730_McBSP2RX_OVF 12 +#define OMAP_INT_730_LCD_LINE 14 +#define OMAP_INT_730_GSM_PROTECT 15 +#define OMAP_INT_730_TIMER3 16 +#define OMAP_INT_730_GPIO_BANK5 17 +#define OMAP_INT_730_GPIO_BANK6 18 +#define OMAP_INT_730_SPGIO_WR 29 =20 /* * Common IRQ numbers for level 2 interrupt handler */ -# define OMAP_INT_KEYBOARD 1 -# define OMAP_INT_uWireTX 2 -# define OMAP_INT_uWireRX 3 -# define OMAP_INT_I2C 4 -# define OMAP_INT_MPUIO 5 -# define OMAP_INT_USB_HHC_1 6 -# define OMAP_INT_McBSP3TX 10 -# define OMAP_INT_McBSP3RX 11 -# define OMAP_INT_McBSP1TX 12 -# define OMAP_INT_McBSP1RX 13 -# define OMAP_INT_UART1 14 -# define OMAP_INT_UART2 15 -# define OMAP_INT_USB_W2FC 20 -# define OMAP_INT_1WIRE 21 -# define OMAP_INT_OS_TIMER 22 -# define OMAP_INT_OQN 23 -# define OMAP_INT_GAUGE_32K 24 -# define OMAP_INT_RTC_TIMER 25 -# define OMAP_INT_RTC_ALARM 26 -# define OMAP_INT_DSP_MMU 28 +#define OMAP_INT_KEYBOARD 1 +#define OMAP_INT_uWireTX 2 +#define OMAP_INT_uWireRX 3 +#define OMAP_INT_I2C 4 +#define OMAP_INT_MPUIO 5 +#define OMAP_INT_USB_HHC_1 6 +#define OMAP_INT_McBSP3TX 10 +#define OMAP_INT_McBSP3RX 11 +#define OMAP_INT_McBSP1TX 12 +#define OMAP_INT_McBSP1RX 13 +#define OMAP_INT_UART1 14 +#define OMAP_INT_UART2 15 +#define OMAP_INT_USB_W2FC 20 +#define OMAP_INT_1WIRE 21 +#define OMAP_INT_OS_TIMER 22 +#define OMAP_INT_OQN 23 +#define OMAP_INT_GAUGE_32K 24 +#define OMAP_INT_RTC_TIMER 25 +#define OMAP_INT_RTC_ALARM 26 +#define OMAP_INT_DSP_MMU 28 =20 /* * OMAP-1510 specific IRQ numbers for level 2 interrupt handler */ -# define OMAP_INT_1510_BT_MCSI1TX 16 -# define OMAP_INT_1510_BT_MCSI1RX 17 -# define OMAP_INT_1510_SoSSI_MATCH 19 -# define OMAP_INT_1510_MEM_STICK 27 -# define OMAP_INT_1510_COM_SPI_RO 31 +#define OMAP_INT_1510_BT_MCSI1TX 16 +#define OMAP_INT_1510_BT_MCSI1RX 17 +#define OMAP_INT_1510_SoSSI_MATCH 19 +#define OMAP_INT_1510_MEM_STICK 27 +#define OMAP_INT_1510_COM_SPI_RO 31 =20 /* * OMAP-310 specific IRQ numbers for level 2 interrupt handler */ -# define OMAP_INT_310_FAC 0 -# define OMAP_INT_310_USB_HHC_2 7 -# define OMAP_INT_310_MCSI1_FE 16 -# define OMAP_INT_310_MCSI2_FE 17 -# define OMAP_INT_310_USB_W2FC_ISO 29 -# define OMAP_INT_310_USB_W2FC_NON_ISO 30 -# define OMAP_INT_310_McBSP2RX_OF 31 +#define OMAP_INT_310_FAC 0 +#define OMAP_INT_310_USB_HHC_2 7 +#define OMAP_INT_310_MCSI1_FE 16 +#define OMAP_INT_310_MCSI2_FE 17 +#define OMAP_INT_310_USB_W2FC_ISO 29 +#define OMAP_INT_310_USB_W2FC_NON_ISO 30 +#define OMAP_INT_310_McBSP2RX_OF 31 =20 /* * OMAP-1610 specific IRQ numbers for level 2 interrupt handler */ -# define OMAP_INT_1610_FAC 0 -# define OMAP_INT_1610_USB_HHC_2 7 -# define OMAP_INT_1610_USB_OTG 8 -# define OMAP_INT_1610_SoSSI 9 -# define OMAP_INT_1610_BT_MCSI1TX 16 -# define OMAP_INT_1610_BT_MCSI1RX 17 -# define OMAP_INT_1610_SoSSI_MATCH 19 -# define OMAP_INT_1610_MEM_STICK 27 -# define OMAP_INT_1610_McBSP2RX_OF 31 -# define OMAP_INT_1610_STI 32 -# define OMAP_INT_1610_STI_WAKEUP 33 -# define OMAP_INT_1610_GPTIMER3 34 -# define OMAP_INT_1610_GPTIMER4 35 -# define OMAP_INT_1610_GPTIMER5 36 -# define OMAP_INT_1610_GPTIMER6 37 -# define OMAP_INT_1610_GPTIMER7 38 -# define OMAP_INT_1610_GPTIMER8 39 -# define OMAP_INT_1610_GPIO_BANK2 40 -# define OMAP_INT_1610_GPIO_BANK3 41 -# define OMAP_INT_1610_MMC2 42 -# define OMAP_INT_1610_CF 43 -# define OMAP_INT_1610_WAKE_UP_REQ 46 -# define OMAP_INT_1610_GPIO_BANK4 48 -# define OMAP_INT_1610_SPI 49 -# define OMAP_INT_1610_DMA_CH6 53 -# define OMAP_INT_1610_DMA_CH7 54 -# define OMAP_INT_1610_DMA_CH8 55 -# define OMAP_INT_1610_DMA_CH9 56 -# define OMAP_INT_1610_DMA_CH10 57 -# define OMAP_INT_1610_DMA_CH11 58 -# define OMAP_INT_1610_DMA_CH12 59 -# define OMAP_INT_1610_DMA_CH13 60 -# define OMAP_INT_1610_DMA_CH14 61 -# define OMAP_INT_1610_DMA_CH15 62 -# define OMAP_INT_1610_NAND 63 +#define OMAP_INT_1610_FAC 0 +#define OMAP_INT_1610_USB_HHC_2 7 +#define OMAP_INT_1610_USB_OTG 8 +#define OMAP_INT_1610_SoSSI 9 +#define OMAP_INT_1610_BT_MCSI1TX 16 +#define OMAP_INT_1610_BT_MCSI1RX 17 +#define OMAP_INT_1610_SoSSI_MATCH 19 +#define OMAP_INT_1610_MEM_STICK 27 +#define OMAP_INT_1610_McBSP2RX_OF 31 +#define OMAP_INT_1610_STI 32 +#define OMAP_INT_1610_STI_WAKEUP 33 +#define OMAP_INT_1610_GPTIMER3 34 +#define OMAP_INT_1610_GPTIMER4 35 +#define OMAP_INT_1610_GPTIMER5 36 +#define OMAP_INT_1610_GPTIMER6 37 +#define OMAP_INT_1610_GPTIMER7 38 +#define OMAP_INT_1610_GPTIMER8 39 +#define OMAP_INT_1610_GPIO_BANK2 40 +#define OMAP_INT_1610_GPIO_BANK3 41 +#define OMAP_INT_1610_MMC2 42 +#define OMAP_INT_1610_CF 43 +#define OMAP_INT_1610_WAKE_UP_REQ 46 +#define OMAP_INT_1610_GPIO_BANK4 48 +#define OMAP_INT_1610_SPI 49 +#define OMAP_INT_1610_DMA_CH6 53 +#define OMAP_INT_1610_DMA_CH7 54 +#define OMAP_INT_1610_DMA_CH8 55 +#define OMAP_INT_1610_DMA_CH9 56 +#define OMAP_INT_1610_DMA_CH10 57 +#define OMAP_INT_1610_DMA_CH11 58 +#define OMAP_INT_1610_DMA_CH12 59 +#define OMAP_INT_1610_DMA_CH13 60 +#define OMAP_INT_1610_DMA_CH14 61 +#define OMAP_INT_1610_DMA_CH15 62 +#define OMAP_INT_1610_NAND 63 =20 /* * OMAP-730 specific IRQ numbers for level 2 interrupt handler */ -# define OMAP_INT_730_HW_ERRORS 0 -# define OMAP_INT_730_NFIQ_PWR_FAIL 1 -# define OMAP_INT_730_CFCD 2 -# define OMAP_INT_730_CFIREQ 3 -# define OMAP_INT_730_I2C 4 -# define OMAP_INT_730_PCC 5 -# define OMAP_INT_730_MPU_EXT_NIRQ 6 -# define OMAP_INT_730_SPI_100K_1 7 -# define OMAP_INT_730_SYREN_SPI 8 -# define OMAP_INT_730_VLYNQ 9 -# define OMAP_INT_730_GPIO_BANK4 10 -# define OMAP_INT_730_McBSP1TX 11 -# define OMAP_INT_730_McBSP1RX 12 -# define OMAP_INT_730_McBSP1RX_OF 13 -# define OMAP_INT_730_UART_MODEM_IRDA_2 14 -# define OMAP_INT_730_UART_MODEM_1 15 -# define OMAP_INT_730_MCSI 16 -# define OMAP_INT_730_uWireTX 17 -# define OMAP_INT_730_uWireRX 18 -# define OMAP_INT_730_SMC_CD 19 -# define OMAP_INT_730_SMC_IREQ 20 -# define OMAP_INT_730_HDQ_1WIRE 21 -# define OMAP_INT_730_TIMER32K 22 -# define OMAP_INT_730_MMC_SDIO 23 -# define OMAP_INT_730_UPLD 24 -# define OMAP_INT_730_USB_HHC_1 27 -# define OMAP_INT_730_USB_HHC_2 28 -# define OMAP_INT_730_USB_GENI 29 -# define OMAP_INT_730_USB_OTG 30 -# define OMAP_INT_730_CAMERA_IF 31 -# define OMAP_INT_730_RNG 32 -# define OMAP_INT_730_DUAL_MODE_TIMER 33 -# define OMAP_INT_730_DBB_RF_EN 34 -# define OMAP_INT_730_MPUIO_KEYPAD 35 -# define OMAP_INT_730_SHA1_MD5 36 -# define OMAP_INT_730_SPI_100K_2 37 -# define OMAP_INT_730_RNG_IDLE 38 -# define OMAP_INT_730_MPUIO 39 -# define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40 -# define OMAP_INT_730_LLPC_OE_FALLING 41 -# define OMAP_INT_730_LLPC_OE_RISING 42 -# define OMAP_INT_730_LLPC_VSYNC 43 -# define OMAP_INT_730_WAKE_UP_REQ 46 -# define OMAP_INT_730_DMA_CH6 53 -# define OMAP_INT_730_DMA_CH7 54 -# define OMAP_INT_730_DMA_CH8 55 -# define OMAP_INT_730_DMA_CH9 56 -# define OMAP_INT_730_DMA_CH10 57 -# define OMAP_INT_730_DMA_CH11 58 -# define OMAP_INT_730_DMA_CH12 59 -# define OMAP_INT_730_DMA_CH13 60 -# define OMAP_INT_730_DMA_CH14 61 -# define OMAP_INT_730_DMA_CH15 62 -# define OMAP_INT_730_NAND 63 +#define OMAP_INT_730_HW_ERRORS 0 +#define OMAP_INT_730_NFIQ_PWR_FAIL 1 +#define OMAP_INT_730_CFCD 2 +#define OMAP_INT_730_CFIREQ 3 +#define OMAP_INT_730_I2C 4 +#define OMAP_INT_730_PCC 5 +#define OMAP_INT_730_MPU_EXT_NIRQ 6 +#define OMAP_INT_730_SPI_100K_1 7 +#define OMAP_INT_730_SYREN_SPI 8 +#define OMAP_INT_730_VLYNQ 9 +#define OMAP_INT_730_GPIO_BANK4 10 +#define OMAP_INT_730_McBSP1TX 11 +#define OMAP_INT_730_McBSP1RX 12 +#define OMAP_INT_730_McBSP1RX_OF 13 +#define OMAP_INT_730_UART_MODEM_IRDA_2 14 +#define OMAP_INT_730_UART_MODEM_1 15 +#define OMAP_INT_730_MCSI 16 +#define OMAP_INT_730_uWireTX 17 +#define OMAP_INT_730_uWireRX 18 +#define OMAP_INT_730_SMC_CD 19 +#define OMAP_INT_730_SMC_IREQ 20 +#define OMAP_INT_730_HDQ_1WIRE 21 +#define OMAP_INT_730_TIMER32K 22 +#define OMAP_INT_730_MMC_SDIO 23 +#define OMAP_INT_730_UPLD 24 +#define OMAP_INT_730_USB_HHC_1 27 +#define OMAP_INT_730_USB_HHC_2 28 +#define OMAP_INT_730_USB_GENI 29 +#define OMAP_INT_730_USB_OTG 30 +#define OMAP_INT_730_CAMERA_IF 31 +#define OMAP_INT_730_RNG 32 +#define OMAP_INT_730_DUAL_MODE_TIMER 33 +#define OMAP_INT_730_DBB_RF_EN 34 +#define OMAP_INT_730_MPUIO_KEYPAD 35 +#define OMAP_INT_730_SHA1_MD5 36 +#define OMAP_INT_730_SPI_100K_2 37 +#define OMAP_INT_730_RNG_IDLE 38 +#define OMAP_INT_730_MPUIO 39 +#define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40 +#define OMAP_INT_730_LLPC_OE_FALLING 41 +#define OMAP_INT_730_LLPC_OE_RISING 42 +#define OMAP_INT_730_LLPC_VSYNC 43 +#define OMAP_INT_730_WAKE_UP_REQ 46 +#define OMAP_INT_730_DMA_CH6 53 +#define OMAP_INT_730_DMA_CH7 54 +#define OMAP_INT_730_DMA_CH8 55 +#define OMAP_INT_730_DMA_CH9 56 +#define OMAP_INT_730_DMA_CH10 57 +#define OMAP_INT_730_DMA_CH11 58 +#define OMAP_INT_730_DMA_CH12 59 +#define OMAP_INT_730_DMA_CH13 60 +#define OMAP_INT_730_DMA_CH14 61 +#define OMAP_INT_730_DMA_CH15 62 +#define OMAP_INT_730_NAND 63 =20 /* omap_dma.c */ enum omap_dma_model { @@ -353,9 +353,9 @@ struct dma_irq_map { enum omap_dma_port { emiff =3D 0, emifs, - imif, /* omap16xx: ocp_t1 */ + imif, /* omap16xx: ocp_t1 */ tipb, - local, /* omap16xx: ocp_t2 */ + local, /* omap16xx: ocp_t2 */ tipb_mpui, __omap_dma_port_last, }; @@ -418,65 +418,65 @@ struct omap_dma_lcd_channel_s { * DMA request numbers for OMAP1 * See /usr/include/asm-arm/arch-omap/dma.h in Linux. */ -# define OMAP_DMA_NO_DEVICE 0 -# define OMAP_DMA_MCSI1_TX 1 -# define OMAP_DMA_MCSI1_RX 2 -# define OMAP_DMA_I2C_RX 3 -# define OMAP_DMA_I2C_TX 4 -# define OMAP_DMA_EXT_NDMA_REQ0 5 -# define OMAP_DMA_EXT_NDMA_REQ1 6 -# define OMAP_DMA_UWIRE_TX 7 -# define OMAP_DMA_MCBSP1_TX 8 -# define OMAP_DMA_MCBSP1_RX 9 -# define OMAP_DMA_MCBSP3_TX 10 -# define OMAP_DMA_MCBSP3_RX 11 -# define OMAP_DMA_UART1_TX 12 -# define OMAP_DMA_UART1_RX 13 -# define OMAP_DMA_UART2_TX 14 -# define OMAP_DMA_UART2_RX 15 -# define OMAP_DMA_MCBSP2_TX 16 -# define OMAP_DMA_MCBSP2_RX 17 -# define OMAP_DMA_UART3_TX 18 -# define OMAP_DMA_UART3_RX 19 -# define OMAP_DMA_CAMERA_IF_RX 20 -# define OMAP_DMA_MMC_TX 21 -# define OMAP_DMA_MMC_RX 22 -# define OMAP_DMA_NAND 23 /* Not in OMAP310 */ -# define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */ -# define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */ -# define OMAP_DMA_USB_W2FC_RX0 26 -# define OMAP_DMA_USB_W2FC_RX1 27 -# define OMAP_DMA_USB_W2FC_RX2 28 -# define OMAP_DMA_USB_W2FC_TX0 29 -# define OMAP_DMA_USB_W2FC_TX1 30 -# define OMAP_DMA_USB_W2FC_TX2 31 +#define OMAP_DMA_NO_DEVICE 0 +#define OMAP_DMA_MCSI1_TX 1 +#define OMAP_DMA_MCSI1_RX 2 +#define OMAP_DMA_I2C_RX 3 +#define OMAP_DMA_I2C_TX 4 +#define OMAP_DMA_EXT_NDMA_REQ0 5 +#define OMAP_DMA_EXT_NDMA_REQ1 6 +#define OMAP_DMA_UWIRE_TX 7 +#define OMAP_DMA_MCBSP1_TX 8 +#define OMAP_DMA_MCBSP1_RX 9 +#define OMAP_DMA_MCBSP3_TX 10 +#define OMAP_DMA_MCBSP3_RX 11 +#define OMAP_DMA_UART1_TX 12 +#define OMAP_DMA_UART1_RX 13 +#define OMAP_DMA_UART2_TX 14 +#define OMAP_DMA_UART2_RX 15 +#define OMAP_DMA_MCBSP2_TX 16 +#define OMAP_DMA_MCBSP2_RX 17 +#define OMAP_DMA_UART3_TX 18 +#define OMAP_DMA_UART3_RX 19 +#define OMAP_DMA_CAMERA_IF_RX 20 +#define OMAP_DMA_MMC_TX 21 +#define OMAP_DMA_MMC_RX 22 +#define OMAP_DMA_NAND 23 /* Not in OMAP310 */ +#define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */ +#define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */ +#define OMAP_DMA_USB_W2FC_RX0 26 +#define OMAP_DMA_USB_W2FC_RX1 27 +#define OMAP_DMA_USB_W2FC_RX2 28 +#define OMAP_DMA_USB_W2FC_TX0 29 +#define OMAP_DMA_USB_W2FC_TX1 30 +#define OMAP_DMA_USB_W2FC_TX2 31 =20 /* These are only for 1610 */ -# define OMAP_DMA_CRYPTO_DES_IN 32 -# define OMAP_DMA_SPI_TX 33 -# define OMAP_DMA_SPI_RX 34 -# define OMAP_DMA_CRYPTO_HASH 35 -# define OMAP_DMA_CCP_ATTN 36 -# define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37 -# define OMAP_DMA_CMT_APE_TX_CHAN_0 38 -# define OMAP_DMA_CMT_APE_RV_CHAN_0 39 -# define OMAP_DMA_CMT_APE_TX_CHAN_1 40 -# define OMAP_DMA_CMT_APE_RV_CHAN_1 41 -# define OMAP_DMA_CMT_APE_TX_CHAN_2 42 -# define OMAP_DMA_CMT_APE_RV_CHAN_2 43 -# define OMAP_DMA_CMT_APE_TX_CHAN_3 44 -# define OMAP_DMA_CMT_APE_RV_CHAN_3 45 -# define OMAP_DMA_CMT_APE_TX_CHAN_4 46 -# define OMAP_DMA_CMT_APE_RV_CHAN_4 47 -# define OMAP_DMA_CMT_APE_TX_CHAN_5 48 -# define OMAP_DMA_CMT_APE_RV_CHAN_5 49 -# define OMAP_DMA_CMT_APE_TX_CHAN_6 50 -# define OMAP_DMA_CMT_APE_RV_CHAN_6 51 -# define OMAP_DMA_CMT_APE_TX_CHAN_7 52 -# define OMAP_DMA_CMT_APE_RV_CHAN_7 53 -# define OMAP_DMA_MMC2_TX 54 -# define OMAP_DMA_MMC2_RX 55 -# define OMAP_DMA_CRYPTO_DES_OUT 56 +#define OMAP_DMA_CRYPTO_DES_IN 32 +#define OMAP_DMA_SPI_TX 33 +#define OMAP_DMA_SPI_RX 34 +#define OMAP_DMA_CRYPTO_HASH 35 +#define OMAP_DMA_CCP_ATTN 36 +#define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37 +#define OMAP_DMA_CMT_APE_TX_CHAN_0 38 +#define OMAP_DMA_CMT_APE_RV_CHAN_0 39 +#define OMAP_DMA_CMT_APE_TX_CHAN_1 40 +#define OMAP_DMA_CMT_APE_RV_CHAN_1 41 +#define OMAP_DMA_CMT_APE_TX_CHAN_2 42 +#define OMAP_DMA_CMT_APE_RV_CHAN_2 43 +#define OMAP_DMA_CMT_APE_TX_CHAN_3 44 +#define OMAP_DMA_CMT_APE_RV_CHAN_3 45 +#define OMAP_DMA_CMT_APE_TX_CHAN_4 46 +#define OMAP_DMA_CMT_APE_RV_CHAN_4 47 +#define OMAP_DMA_CMT_APE_TX_CHAN_5 48 +#define OMAP_DMA_CMT_APE_RV_CHAN_5 49 +#define OMAP_DMA_CMT_APE_TX_CHAN_6 50 +#define OMAP_DMA_CMT_APE_RV_CHAN_6 51 +#define OMAP_DMA_CMT_APE_TX_CHAN_7 52 +#define OMAP_DMA_CMT_APE_RV_CHAN_7 53 +#define OMAP_DMA_MMC2_TX 54 +#define OMAP_DMA_MMC2_RX 55 +#define OMAP_DMA_CRYPTO_DES_OUT 56 =20 struct omap_uart_s; struct omap_uart_s *omap_uart_init(hwaddr base, @@ -542,14 +542,14 @@ void omap_mmc_set_clk(DeviceState *dev, omap_clk clk); /* omap_i2c.c */ I2CBus *omap_i2c_bus(DeviceState *omap_i2c); =20 -# define cpu_is_omap310(cpu) (cpu->mpu_model =3D=3D omap310) -# define cpu_is_omap1510(cpu) (cpu->mpu_model =3D=3D omap1510) -# define cpu_is_omap1610(cpu) (cpu->mpu_model =3D=3D omap1610) -# define cpu_is_omap1710(cpu) (cpu->mpu_model =3D=3D omap1710) +#define cpu_is_omap310(cpu) (cpu->mpu_model =3D=3D omap310) +#define cpu_is_omap1510(cpu) (cpu->mpu_model =3D=3D omap1510) +#define cpu_is_omap1610(cpu) (cpu->mpu_model =3D=3D omap1610) +#define cpu_is_omap1710(cpu) (cpu->mpu_model =3D=3D omap1710) =20 -# define cpu_is_omap15xx(cpu) \ +#define cpu_is_omap15xx(cpu) \ (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu)) -# define cpu_is_omap16xx(cpu) \ +#define cpu_is_omap16xx(cpu) \ (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu)) =20 struct omap_mpu_state_s { @@ -685,14 +685,14 @@ void omap_badwidth_write32(void *opaque, hwaddr addr, =20 void omap_mpu_wakeup(void *opaque, int irq, int req); =20 -# define OMAP_BAD_REG(paddr) \ +#define OMAP_BAD_REG(paddr) \ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad register %#08"HWADDR_PRIx"= \n", \ __func__, paddr) -# define OMAP_RO_REG(paddr) \ +#define OMAP_RO_REG(paddr) \ qemu_log_mask(LOG_GUEST_ERROR, "%s: Read-only register %#08" \ HWADDR_PRIx "\n", \ __func__, paddr) =20 -# define OMAP_MPUI_REG_MASK 0x000007ff +#define OMAP_MPUI_REG_MASK 0x000007ff =20 #endif diff --git a/include/hw/arm/sharpsl.h b/include/hw/arm/sharpsl.h index e986b28c527..1e3992fcd00 100644 --- a/include/hw/arm/sharpsl.h +++ b/include/hw/arm/sharpsl.h @@ -11,7 +11,7 @@ =20 /* zaurus.c */ =20 -#define SL_PXA_PARAM_BASE 0xa0000a00 +#define SL_PXA_PARAM_BASE 0xa0000a00 void sl_bootparam_write(hwaddr ptr); =20 #endif diff --git a/include/hw/arm/soc_dma.h b/include/hw/arm/soc_dma.h index e93a7499a80..bcdb91425a5 100644 --- a/include/hw/arm/soc_dma.h +++ b/include/hw/arm/soc_dma.h @@ -54,7 +54,7 @@ struct soc_dma_ch_s { int bytes; /* Initialised by the DMA module, call soc_dma_ch_update after writing= . */ enum soc_dma_access_type type[2]; - hwaddr vaddr[2]; /* Updated by .transfer_fn(). */ + hwaddr vaddr[2]; /* Updated by .transfer_fn(). */ /* Private */ void *paddr[2]; soc_dma_io_t io_fn[2]; @@ -70,7 +70,7 @@ struct soc_dma_ch_s { struct soc_dma_s { /* Following fields are set by the SoC DMA module and can be used * by anybody. */ - uint64_t drqbmp; /* Is zeroed by soc_dma_reset() */ + uint64_t drqbmp; /* Is zeroed by soc_dma_reset() */ qemu_irq *drq; void *opaque; int64_t freq; diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c index 91d7e3f04b5..74458fb7c69 100644 --- a/hw/arm/omap1.c +++ b/hw/arm/omap1.c @@ -144,7 +144,7 @@ static inline void omap_timer_update(struct omap_mpu_ti= mer_s *timer) int64_t expires; =20 if (timer->enable && timer->st && timer->rate) { - timer->val =3D timer->reset_val; /* Should skip this on clk enable= */ + timer->val =3D timer->reset_val; /* Should skip this on clk enabl= e */ expires =3D muldiv64((uint64_t) timer->val << (timer->ptv + 1), NANOSECONDS_PER_SECOND, timer->rate); =20 @@ -212,13 +212,13 @@ static uint64_t omap_mpu_timer_read(void *opaque, hwa= ddr addr, } =20 switch (addr) { - case 0x00: /* CNTL_TIMER */ + case 0x00: /* CNTL_TIMER */ return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st; =20 - case 0x04: /* LOAD_TIM */ + case 0x04: /* LOAD_TIM */ break; =20 - case 0x08: /* READ_TIM */ + case 0x08: /* READ_TIM */ return omap_timer_read(s); } =20 @@ -237,7 +237,7 @@ static void omap_mpu_timer_write(void *opaque, hwaddr a= ddr, } =20 switch (addr) { - case 0x00: /* CNTL_TIMER */ + case 0x00: /* CNTL_TIMER */ omap_timer_sync(s); s->enable =3D (value >> 5) & 1; s->ptv =3D (value >> 2) & 7; @@ -246,11 +246,11 @@ static void omap_mpu_timer_write(void *opaque, hwaddr= addr, omap_timer_update(s); return; =20 - case 0x04: /* LOAD_TIM */ + case 0x04: /* LOAD_TIM */ s->reset_val =3D value; return; =20 - case 0x08: /* READ_TIM */ + case 0x08: /* READ_TIM */ OMAP_RO_REG(addr); break; =20 @@ -318,14 +318,14 @@ static uint64_t omap_wd_timer_read(void *opaque, hwad= dr addr, } =20 switch (addr) { - case 0x00: /* CNTL_TIMER */ + case 0x00: /* CNTL_TIMER */ return (s->timer.ptv << 9) | (s->timer.ar << 8) | (s->timer.st << 7) | (s->free << 1); =20 - case 0x04: /* READ_TIMER */ + case 0x04: /* READ_TIMER */ return omap_timer_read(&s->timer); =20 - case 0x08: /* TIMER_MODE */ + case 0x08: /* TIMER_MODE */ return s->mode << 15; } =20 @@ -344,7 +344,7 @@ static void omap_wd_timer_write(void *opaque, hwaddr ad= dr, } =20 switch (addr) { - case 0x00: /* CNTL_TIMER */ + case 0x00: /* CNTL_TIMER */ omap_timer_sync(&s->timer); s->timer.ptv =3D (value >> 9) & 7; s->timer.ar =3D (value >> 8) & 1; @@ -353,11 +353,11 @@ static void omap_wd_timer_write(void *opaque, hwaddr = addr, omap_timer_update(&s->timer); break; =20 - case 0x04: /* LOAD_TIMER */ + case 0x04: /* LOAD_TIMER */ s->timer.reset_val =3D value & 0xffff; break; =20 - case 0x08: /* TIMER_MODE */ + case 0x08: /* TIMER_MODE */ if (!s->mode && ((value >> 15) & 1)) omap_clk_get(s->timer.clk); s->mode |=3D (value >> 15) & 1; @@ -442,13 +442,13 @@ static uint64_t omap_os_timer_read(void *opaque, hwad= dr addr, } =20 switch (offset) { - case 0x00: /* TVR */ + case 0x00: /* TVR */ return s->timer.reset_val; =20 - case 0x04: /* TCR */ + case 0x04: /* TCR */ return omap_timer_read(&s->timer); =20 - case 0x08: /* CR */ + case 0x08: /* CR */ return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st; =20 default: @@ -470,15 +470,15 @@ static void omap_os_timer_write(void *opaque, hwaddr = addr, } =20 switch (offset) { - case 0x00: /* TVR */ + case 0x00: /* TVR */ s->timer.reset_val =3D value & 0x00ffffff; break; =20 - case 0x04: /* TCR */ + case 0x04: /* TCR */ OMAP_RO_REG(addr); break; =20 - case 0x08: /* CR */ + case 0x08: /* CR */ s->timer.ar =3D (value >> 3) & 1; s->timer.it_ena =3D (value >> 2) & 1; if (s->timer.st !=3D (value & 1) || (value & 2)) { @@ -543,34 +543,34 @@ static uint64_t omap_ulpd_pm_read(void *opaque, hwadd= r addr, } =20 switch (addr) { - case 0x14: /* IT_STATUS */ + case 0x14: /* IT_STATUS */ ret =3D s->ulpd_pm_regs[addr >> 2]; s->ulpd_pm_regs[addr >> 2] =3D 0; qemu_irq_lower(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K)); return ret; =20 - case 0x18: /* Reserved */ - case 0x1c: /* Reserved */ - case 0x20: /* Reserved */ - case 0x28: /* Reserved */ - case 0x2c: /* Reserved */ + case 0x18: /* Reserved */ + case 0x1c: /* Reserved */ + case 0x20: /* Reserved */ + case 0x28: /* Reserved */ + case 0x2c: /* Reserved */ OMAP_BAD_REG(addr); /* fall through */ - case 0x00: /* COUNTER_32_LSB */ - case 0x04: /* COUNTER_32_MSB */ - case 0x08: /* COUNTER_HIGH_FREQ_LSB */ - case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ - case 0x10: /* GAUGING_CTRL */ - case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ - case 0x30: /* CLOCK_CTRL */ - case 0x34: /* SOFT_REQ */ - case 0x38: /* COUNTER_32_FIQ */ - case 0x3c: /* DPLL_CTRL */ - case 0x40: /* STATUS_REQ */ + case 0x00: /* COUNTER_32_LSB */ + case 0x04: /* COUNTER_32_MSB */ + case 0x08: /* COUNTER_HIGH_FREQ_LSB */ + case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ + case 0x10: /* GAUGING_CTRL */ + case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ + case 0x30: /* CLOCK_CTRL */ + case 0x34: /* SOFT_REQ */ + case 0x38: /* COUNTER_32_FIQ */ + case 0x3c: /* DPLL_CTRL */ + case 0x40: /* STATUS_REQ */ /* XXX: check clk::usecount state for every clock */ - case 0x48: /* LOCL_TIME */ - case 0x4c: /* APLL_CTRL */ - case 0x50: /* POWER_CTRL */ + case 0x48: /* LOCL_TIME */ + case 0x4c: /* APLL_CTRL */ + case 0x50: /* POWER_CTRL */ return s->ulpd_pm_regs[addr >> 2]; } =20 @@ -581,22 +581,22 @@ static uint64_t omap_ulpd_pm_read(void *opaque, hwadd= r addr, static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s, uint16_t diff, uint16_t value) { - if (diff & (1 << 4)) /* USB_MCLK_EN */ + if (diff & (1 << 4)) /* USB_MCLK_EN */ omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1); - if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */ + if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */ omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1); } =20 static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s, uint16_t diff, uint16_t value) { - if (diff & (1 << 0)) /* SOFT_DPLL_REQ */ + if (diff & (1 << 0)) /* SOFT_DPLL_REQ */ omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1); - if (diff & (1 << 1)) /* SOFT_COM_REQ */ + if (diff & (1 << 1)) /* SOFT_COM_REQ */ omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & = 1); - if (diff & (1 << 2)) /* SOFT_SDW_REQ */ + if (diff & (1 << 2)) /* SOFT_SDW_REQ */ omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1= ); - if (diff & (1 << 3)) /* SOFT_USB_REQ */ + if (diff & (1 << 3)) /* SOFT_USB_REQ */ omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1); } =20 @@ -615,16 +615,16 @@ static void omap_ulpd_pm_write(void *opaque, hwaddr a= ddr, } =20 switch (addr) { - case 0x00: /* COUNTER_32_LSB */ - case 0x04: /* COUNTER_32_MSB */ - case 0x08: /* COUNTER_HIGH_FREQ_LSB */ - case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ - case 0x14: /* IT_STATUS */ - case 0x40: /* STATUS_REQ */ + case 0x00: /* COUNTER_32_LSB */ + case 0x04: /* COUNTER_32_MSB */ + case 0x08: /* COUNTER_HIGH_FREQ_LSB */ + case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ + case 0x14: /* IT_STATUS */ + case 0x40: /* STATUS_REQ */ OMAP_RO_REG(addr); break; =20 - case 0x10: /* GAUGING_CTRL */ + case 0x10: /* GAUGING_CTRL */ /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */ if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) { now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); @@ -638,50 +638,50 @@ static void omap_ulpd_pm_write(void *opaque, hwaddr a= ddr, ticks =3D muldiv64(now, 32768, NANOSECONDS_PER_SECOND); s->ulpd_pm_regs[0x00 >> 2] =3D (ticks >> 0) & 0xffff; s->ulpd_pm_regs[0x04 >> 2] =3D (ticks >> 16) & 0xffff; - if (ticks >> 32) /* OVERFLOW_32K */ + if (ticks >> 32) /* OVERFLOW_32K */ s->ulpd_pm_regs[0x14 >> 2] |=3D 1 << 2; =20 /* High frequency ticks */ ticks =3D muldiv64(now, 12000000, NANOSECONDS_PER_SECOND); s->ulpd_pm_regs[0x08 >> 2] =3D (ticks >> 0) & 0xffff; s->ulpd_pm_regs[0x0c >> 2] =3D (ticks >> 16) & 0xffff; - if (ticks >> 32) /* OVERFLOW_HI_FREQ */ + if (ticks >> 32) /* OVERFLOW_HI_FREQ */ s->ulpd_pm_regs[0x14 >> 2] |=3D 1 << 1; =20 - s->ulpd_pm_regs[0x14 >> 2] |=3D 1 << 0; /* IT_GAUGING */ + s->ulpd_pm_regs[0x14 >> 2] |=3D 1 << 0; /* IT_GAUGING */ qemu_irq_raise(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_3= 2K)); } } s->ulpd_pm_regs[addr >> 2] =3D value; break; =20 - case 0x18: /* Reserved */ - case 0x1c: /* Reserved */ - case 0x20: /* Reserved */ - case 0x28: /* Reserved */ - case 0x2c: /* Reserved */ + case 0x18: /* Reserved */ + case 0x1c: /* Reserved */ + case 0x20: /* Reserved */ + case 0x28: /* Reserved */ + case 0x2c: /* Reserved */ OMAP_BAD_REG(addr); /* fall through */ - case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ - case 0x38: /* COUNTER_32_FIQ */ - case 0x48: /* LOCL_TIME */ - case 0x50: /* POWER_CTRL */ + case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ + case 0x38: /* COUNTER_32_FIQ */ + case 0x48: /* LOCL_TIME */ + case 0x50: /* POWER_CTRL */ s->ulpd_pm_regs[addr >> 2] =3D value; break; =20 - case 0x30: /* CLOCK_CTRL */ + case 0x30: /* CLOCK_CTRL */ diff =3D s->ulpd_pm_regs[addr >> 2] ^ value; s->ulpd_pm_regs[addr >> 2] =3D value & 0x3f; omap_ulpd_clk_update(s, diff, value); break; =20 - case 0x34: /* SOFT_REQ */ + case 0x34: /* SOFT_REQ */ diff =3D s->ulpd_pm_regs[addr >> 2] ^ value; s->ulpd_pm_regs[addr >> 2] =3D value & 0x1f; omap_ulpd_req_update(s, diff, value); break; =20 - case 0x3c: /* DPLL_CTRL */ + case 0x3c: /* DPLL_CTRL */ /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is * omitted altogether, probably a typo. */ /* This register has identical semantics with DPLL(1:3) control @@ -689,11 +689,11 @@ static void omap_ulpd_pm_write(void *opaque, hwaddr a= ddr, diff =3D s->ulpd_pm_regs[addr >> 2] & value; s->ulpd_pm_regs[addr >> 2] =3D value & 0x2fff; if (diff & (0x3ff << 2)) { - if (value & (1 << 4)) { /* PLL_ENABLE */ - div =3D ((value >> 5) & 3) + 1; /* PLL_DIV */ - mult =3D MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ + if (value & (1 << 4)) { /* PLL_ENABLE */ + div =3D ((value >> 5) & 3) + 1; /* PLL_DIV */ + mult =3D MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ } else { - div =3D bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ + div =3D bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ mult =3D 1; } omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult); @@ -708,10 +708,10 @@ static void omap_ulpd_pm_write(void *opaque, hwaddr a= ddr, s->ulpd_pm_regs[addr >> 2] |=3D 2; break; =20 - case 0x4c: /* APLL_CTRL */ + case 0x4c: /* APLL_CTRL */ diff =3D s->ulpd_pm_regs[addr >> 2] & value; s->ulpd_pm_regs[addr >> 2] =3D value & 0xf; - if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */ + if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */ omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s, (value & (1 << 0)) ? "apll" : "dpll4")= ); break; @@ -775,43 +775,43 @@ static uint64_t omap_pin_cfg_read(void *opaque, hwadd= r addr, } =20 switch (addr) { - case 0x00: /* FUNC_MUX_CTRL_0 */ - case 0x04: /* FUNC_MUX_CTRL_1 */ - case 0x08: /* FUNC_MUX_CTRL_2 */ + case 0x00: /* FUNC_MUX_CTRL_0 */ + case 0x04: /* FUNC_MUX_CTRL_1 */ + case 0x08: /* FUNC_MUX_CTRL_2 */ return s->func_mux_ctrl[addr >> 2]; =20 - case 0x0c: /* COMP_MODE_CTRL_0 */ + case 0x0c: /* COMP_MODE_CTRL_0 */ return s->comp_mode_ctrl[0]; =20 - case 0x10: /* FUNC_MUX_CTRL_3 */ - case 0x14: /* FUNC_MUX_CTRL_4 */ - case 0x18: /* FUNC_MUX_CTRL_5 */ - case 0x1c: /* FUNC_MUX_CTRL_6 */ - case 0x20: /* FUNC_MUX_CTRL_7 */ - case 0x24: /* FUNC_MUX_CTRL_8 */ - case 0x28: /* FUNC_MUX_CTRL_9 */ - case 0x2c: /* FUNC_MUX_CTRL_A */ - case 0x30: /* FUNC_MUX_CTRL_B */ - case 0x34: /* FUNC_MUX_CTRL_C */ - case 0x38: /* FUNC_MUX_CTRL_D */ + case 0x10: /* FUNC_MUX_CTRL_3 */ + case 0x14: /* FUNC_MUX_CTRL_4 */ + case 0x18: /* FUNC_MUX_CTRL_5 */ + case 0x1c: /* FUNC_MUX_CTRL_6 */ + case 0x20: /* FUNC_MUX_CTRL_7 */ + case 0x24: /* FUNC_MUX_CTRL_8 */ + case 0x28: /* FUNC_MUX_CTRL_9 */ + case 0x2c: /* FUNC_MUX_CTRL_A */ + case 0x30: /* FUNC_MUX_CTRL_B */ + case 0x34: /* FUNC_MUX_CTRL_C */ + case 0x38: /* FUNC_MUX_CTRL_D */ return s->func_mux_ctrl[(addr >> 2) - 1]; =20 - case 0x40: /* PULL_DWN_CTRL_0 */ - case 0x44: /* PULL_DWN_CTRL_1 */ - case 0x48: /* PULL_DWN_CTRL_2 */ - case 0x4c: /* PULL_DWN_CTRL_3 */ + case 0x40: /* PULL_DWN_CTRL_0 */ + case 0x44: /* PULL_DWN_CTRL_1 */ + case 0x48: /* PULL_DWN_CTRL_2 */ + case 0x4c: /* PULL_DWN_CTRL_3 */ return s->pull_dwn_ctrl[(addr & 0xf) >> 2]; =20 - case 0x50: /* GATE_INH_CTRL_0 */ + case 0x50: /* GATE_INH_CTRL_0 */ return s->gate_inh_ctrl[0]; =20 - case 0x60: /* VOLTAGE_CTRL_0 */ + case 0x60: /* VOLTAGE_CTRL_0 */ return s->voltage_ctrl[0]; =20 - case 0x70: /* TEST_DBG_CTRL_0 */ + case 0x70: /* TEST_DBG_CTRL_0 */ return s->test_dbg_ctrl[0]; =20 - case 0x80: /* MOD_CONF_CTRL_0 */ + case 0x80: /* MOD_CONF_CTRL_0 */ return s->mod_conf_ctrl[0]; } =20 @@ -823,10 +823,10 @@ static inline void omap_pin_funcmux0_update(struct om= ap_mpu_state_s *s, uint32_t diff, uint32_t value) { if (s->compat1509) { - if (diff & (1 << 9)) /* BLUETOOTH */ + if (diff & (1 << 9)) /* BLUETOOTH */ omap_clk_onoff(omap_findclk(s, "bt_mclk_out"), (~value >> 9) & 1); - if (diff & (1 << 7)) /* USB.CLKO */ + if (diff & (1 << 7)) /* USB.CLKO */ omap_clk_onoff(omap_findclk(s, "usb.clko"), (value >> 7) & 1); } @@ -856,23 +856,23 @@ static inline void omap_pin_modconf1_update(struct om= ap_mpu_state_s *s, omap_findclk(s, ((value >> 31) & 1) ? "ck_48m" : "armper_ck")); } - if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */ + if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */ omap_clk_reparent(omap_findclk(s, "uart2_ck"), omap_findclk(s, ((value >> 30) & 1) ? "ck_48m" : "armper_ck")); - if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */ + if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */ omap_clk_reparent(omap_findclk(s, "uart1_ck"), omap_findclk(s, ((value >> 29) & 1) ? "ck_48m" : "armper_ck")); - if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */ + if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */ omap_clk_reparent(omap_findclk(s, "mmc_ck"), omap_findclk(s, ((value >> 23) & 1) ? "ck_48m" : "armper_ck")); - if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */ + if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */ omap_clk_reparent(omap_findclk(s, "com_mclk_out"), omap_findclk(s, ((value >> 12) & 1) ? "ck_48m" : "armper_ck")); - if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */ + if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */ omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1); } =20 @@ -888,63 +888,63 @@ static void omap_pin_cfg_write(void *opaque, hwaddr a= ddr, } =20 switch (addr) { - case 0x00: /* FUNC_MUX_CTRL_0 */ + case 0x00: /* FUNC_MUX_CTRL_0 */ diff =3D s->func_mux_ctrl[addr >> 2] ^ value; s->func_mux_ctrl[addr >> 2] =3D value; omap_pin_funcmux0_update(s, diff, value); return; =20 - case 0x04: /* FUNC_MUX_CTRL_1 */ + case 0x04: /* FUNC_MUX_CTRL_1 */ diff =3D s->func_mux_ctrl[addr >> 2] ^ value; s->func_mux_ctrl[addr >> 2] =3D value; omap_pin_funcmux1_update(s, diff, value); return; =20 - case 0x08: /* FUNC_MUX_CTRL_2 */ + case 0x08: /* FUNC_MUX_CTRL_2 */ s->func_mux_ctrl[addr >> 2] =3D value; return; =20 - case 0x0c: /* COMP_MODE_CTRL_0 */ + case 0x0c: /* COMP_MODE_CTRL_0 */ s->comp_mode_ctrl[0] =3D value; s->compat1509 =3D (value !=3D 0x0000eaef); omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]); omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]); return; =20 - case 0x10: /* FUNC_MUX_CTRL_3 */ - case 0x14: /* FUNC_MUX_CTRL_4 */ - case 0x18: /* FUNC_MUX_CTRL_5 */ - case 0x1c: /* FUNC_MUX_CTRL_6 */ - case 0x20: /* FUNC_MUX_CTRL_7 */ - case 0x24: /* FUNC_MUX_CTRL_8 */ - case 0x28: /* FUNC_MUX_CTRL_9 */ - case 0x2c: /* FUNC_MUX_CTRL_A */ - case 0x30: /* FUNC_MUX_CTRL_B */ - case 0x34: /* FUNC_MUX_CTRL_C */ - case 0x38: /* FUNC_MUX_CTRL_D */ + case 0x10: /* FUNC_MUX_CTRL_3 */ + case 0x14: /* FUNC_MUX_CTRL_4 */ + case 0x18: /* FUNC_MUX_CTRL_5 */ + case 0x1c: /* FUNC_MUX_CTRL_6 */ + case 0x20: /* FUNC_MUX_CTRL_7 */ + case 0x24: /* FUNC_MUX_CTRL_8 */ + case 0x28: /* FUNC_MUX_CTRL_9 */ + case 0x2c: /* FUNC_MUX_CTRL_A */ + case 0x30: /* FUNC_MUX_CTRL_B */ + case 0x34: /* FUNC_MUX_CTRL_C */ + case 0x38: /* FUNC_MUX_CTRL_D */ s->func_mux_ctrl[(addr >> 2) - 1] =3D value; return; =20 - case 0x40: /* PULL_DWN_CTRL_0 */ - case 0x44: /* PULL_DWN_CTRL_1 */ - case 0x48: /* PULL_DWN_CTRL_2 */ - case 0x4c: /* PULL_DWN_CTRL_3 */ + case 0x40: /* PULL_DWN_CTRL_0 */ + case 0x44: /* PULL_DWN_CTRL_1 */ + case 0x48: /* PULL_DWN_CTRL_2 */ + case 0x4c: /* PULL_DWN_CTRL_3 */ s->pull_dwn_ctrl[(addr & 0xf) >> 2] =3D value; return; =20 - case 0x50: /* GATE_INH_CTRL_0 */ + case 0x50: /* GATE_INH_CTRL_0 */ s->gate_inh_ctrl[0] =3D value; return; =20 - case 0x60: /* VOLTAGE_CTRL_0 */ + case 0x60: /* VOLTAGE_CTRL_0 */ s->voltage_ctrl[0] =3D value; return; =20 - case 0x70: /* TEST_DBG_CTRL_0 */ + case 0x70: /* TEST_DBG_CTRL_0 */ s->test_dbg_ctrl[0] =3D value; return; =20 - case 0x80: /* MOD_CONF_CTRL_0 */ + case 0x80: /* MOD_CONF_CTRL_0 */ diff =3D s->mod_conf_ctrl[0] ^ value; s->mod_conf_ctrl[0] =3D value; omap_pin_modconf1_update(s, diff, value); @@ -998,17 +998,17 @@ static uint64_t omap_id_read(void *opaque, hwaddr add= r, } =20 switch (addr) { - case 0xfffe1800: /* DIE_ID_LSB */ + case 0xfffe1800: /* DIE_ID_LSB */ return 0xc9581f0e; - case 0xfffe1804: /* DIE_ID_MSB */ + case 0xfffe1804: /* DIE_ID_MSB */ return 0xa8858bfa; =20 - case 0xfffe2000: /* PRODUCT_ID_LSB */ + case 0xfffe2000: /* PRODUCT_ID_LSB */ return 0x00aaaafc; - case 0xfffe2004: /* PRODUCT_ID_MSB */ + case 0xfffe2004: /* PRODUCT_ID_MSB */ return 0xcafeb574; =20 - case 0xfffed400: /* JTAG_ID_LSB */ + case 0xfffed400: /* JTAG_ID_LSB */ switch (s->mpu_model) { case omap310: return 0x03310315; @@ -1019,7 +1019,7 @@ static uint64_t omap_id_read(void *opaque, hwaddr add= r, } break; =20 - case 0xfffed404: /* JTAG_ID_MSB */ + case 0xfffed404: /* JTAG_ID_MSB */ switch (s->mpu_model) { case omap310: return 0xfb57402f; @@ -1080,22 +1080,22 @@ static uint64_t omap_mpui_read(void *opaque, hwaddr= addr, } =20 switch (addr) { - case 0x00: /* CTRL */ + case 0x00: /* CTRL */ return s->mpui_ctrl; - case 0x04: /* DEBUG_ADDR */ + case 0x04: /* DEBUG_ADDR */ return 0x01ffffff; - case 0x08: /* DEBUG_DATA */ + case 0x08: /* DEBUG_DATA */ return 0xffffffff; - case 0x0c: /* DEBUG_FLAG */ + case 0x0c: /* DEBUG_FLAG */ return 0x00000800; - case 0x10: /* STATUS */ + case 0x10: /* STATUS */ return 0x00000000; =20 /* Not in OMAP310 */ - case 0x14: /* DSP_STATUS */ - case 0x18: /* DSP_BOOT_CONFIG */ + case 0x14: /* DSP_STATUS */ + case 0x18: /* DSP_BOOT_CONFIG */ return 0x00000000; - case 0x1c: /* DSP_MPUI_CONFIG */ + case 0x1c: /* DSP_MPUI_CONFIG */ return 0x0000ffff; } =20 @@ -1114,20 +1114,20 @@ static void omap_mpui_write(void *opaque, hwaddr ad= dr, } =20 switch (addr) { - case 0x00: /* CTRL */ + case 0x00: /* CTRL */ s->mpui_ctrl =3D value & 0x007fffff; break; =20 - case 0x04: /* DEBUG_ADDR */ - case 0x08: /* DEBUG_DATA */ - case 0x0c: /* DEBUG_FLAG */ - case 0x10: /* STATUS */ + case 0x04: /* DEBUG_ADDR */ + case 0x08: /* DEBUG_DATA */ + case 0x0c: /* DEBUG_FLAG */ + case 0x10: /* STATUS */ /* Not in OMAP310 */ - case 0x14: /* DSP_STATUS */ + case 0x14: /* DSP_STATUS */ OMAP_RO_REG(addr); break; - case 0x18: /* DSP_BOOT_CONFIG */ - case 0x1c: /* DSP_MPUI_CONFIG */ + case 0x18: /* DSP_BOOT_CONFIG */ + case 0x1c: /* DSP_MPUI_CONFIG */ break; =20 default: @@ -1178,19 +1178,19 @@ static uint64_t omap_tipb_bridge_read(void *opaque,= hwaddr addr, } =20 switch (addr) { - case 0x00: /* TIPB_CNTL */ + case 0x00: /* TIPB_CNTL */ return s->control; - case 0x04: /* TIPB_BUS_ALLOC */ + case 0x04: /* TIPB_BUS_ALLOC */ return s->alloc; - case 0x08: /* MPU_TIPB_CNTL */ + case 0x08: /* MPU_TIPB_CNTL */ return s->buffer; - case 0x0c: /* ENHANCED_TIPB_CNTL */ + case 0x0c: /* ENHANCED_TIPB_CNTL */ return s->enh_control; - case 0x10: /* ADDRESS_DBG */ - case 0x14: /* DATA_DEBUG_LOW */ - case 0x18: /* DATA_DEBUG_HIGH */ + case 0x10: /* ADDRESS_DBG */ + case 0x14: /* DATA_DEBUG_LOW */ + case 0x18: /* DATA_DEBUG_HIGH */ return 0xffff; - case 0x1c: /* DEBUG_CNTR_SIG */ + case 0x1c: /* DEBUG_CNTR_SIG */ return 0x00f8; } =20 @@ -1209,27 +1209,27 @@ static void omap_tipb_bridge_write(void *opaque, hw= addr addr, } =20 switch (addr) { - case 0x00: /* TIPB_CNTL */ + case 0x00: /* TIPB_CNTL */ s->control =3D value & 0xffff; break; =20 - case 0x04: /* TIPB_BUS_ALLOC */ + case 0x04: /* TIPB_BUS_ALLOC */ s->alloc =3D value & 0x003f; break; =20 - case 0x08: /* MPU_TIPB_CNTL */ + case 0x08: /* MPU_TIPB_CNTL */ s->buffer =3D value & 0x0003; break; =20 - case 0x0c: /* ENHANCED_TIPB_CNTL */ + case 0x0c: /* ENHANCED_TIPB_CNTL */ s->width_intr =3D !(value & 2); s->enh_control =3D value & 0x000f; break; =20 - case 0x10: /* ADDRESS_DBG */ - case 0x14: /* DATA_DEBUG_LOW */ - case 0x18: /* DATA_DEBUG_HIGH */ - case 0x1c: /* DEBUG_CNTR_SIG */ + case 0x10: /* ADDRESS_DBG */ + case 0x14: /* DATA_DEBUG_LOW */ + case 0x18: /* DATA_DEBUG_HIGH */ + case 0x1c: /* DEBUG_CNTR_SIG */ OMAP_RO_REG(addr); break; =20 @@ -1280,23 +1280,23 @@ static uint64_t omap_tcmi_read(void *opaque, hwaddr= addr, } =20 switch (addr) { - case 0x00: /* IMIF_PRIO */ - case 0x04: /* EMIFS_PRIO */ - case 0x08: /* EMIFF_PRIO */ - case 0x0c: /* EMIFS_CONFIG */ - case 0x10: /* EMIFS_CS0_CONFIG */ - case 0x14: /* EMIFS_CS1_CONFIG */ - case 0x18: /* EMIFS_CS2_CONFIG */ - case 0x1c: /* EMIFS_CS3_CONFIG */ - case 0x24: /* EMIFF_MRS */ - case 0x28: /* TIMEOUT1 */ - case 0x2c: /* TIMEOUT2 */ - case 0x30: /* TIMEOUT3 */ - case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ - case 0x40: /* EMIFS_CFG_DYN_WAIT */ + case 0x00: /* IMIF_PRIO */ + case 0x04: /* EMIFS_PRIO */ + case 0x08: /* EMIFF_PRIO */ + case 0x0c: /* EMIFS_CONFIG */ + case 0x10: /* EMIFS_CS0_CONFIG */ + case 0x14: /* EMIFS_CS1_CONFIG */ + case 0x18: /* EMIFS_CS2_CONFIG */ + case 0x1c: /* EMIFS_CS3_CONFIG */ + case 0x24: /* EMIFF_MRS */ + case 0x28: /* TIMEOUT1 */ + case 0x2c: /* TIMEOUT2 */ + case 0x30: /* TIMEOUT3 */ + case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ + case 0x40: /* EMIFS_CFG_DYN_WAIT */ return s->tcmi_regs[addr >> 2]; =20 - case 0x20: /* EMIFF_SDRAM_CONFIG */ + case 0x20: /* EMIFF_SDRAM_CONFIG */ ret =3D s->tcmi_regs[addr >> 2]; s->tcmi_regs[addr >> 2] &=3D ~1; /* XXX: Clear SLRF on SDRAM acces= s */ /* XXX: We can try using the VGA_DIRTY flag for this */ @@ -1318,23 +1318,23 @@ static void omap_tcmi_write(void *opaque, hwaddr ad= dr, } =20 switch (addr) { - case 0x00: /* IMIF_PRIO */ - case 0x04: /* EMIFS_PRIO */ - case 0x08: /* EMIFF_PRIO */ - case 0x10: /* EMIFS_CS0_CONFIG */ - case 0x14: /* EMIFS_CS1_CONFIG */ - case 0x18: /* EMIFS_CS2_CONFIG */ - case 0x1c: /* EMIFS_CS3_CONFIG */ - case 0x20: /* EMIFF_SDRAM_CONFIG */ - case 0x24: /* EMIFF_MRS */ - case 0x28: /* TIMEOUT1 */ - case 0x2c: /* TIMEOUT2 */ - case 0x30: /* TIMEOUT3 */ - case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ - case 0x40: /* EMIFS_CFG_DYN_WAIT */ + case 0x00: /* IMIF_PRIO */ + case 0x04: /* EMIFS_PRIO */ + case 0x08: /* EMIFF_PRIO */ + case 0x10: /* EMIFS_CS0_CONFIG */ + case 0x14: /* EMIFS_CS1_CONFIG */ + case 0x18: /* EMIFS_CS2_CONFIG */ + case 0x1c: /* EMIFS_CS3_CONFIG */ + case 0x20: /* EMIFF_SDRAM_CONFIG */ + case 0x24: /* EMIFF_MRS */ + case 0x28: /* TIMEOUT1 */ + case 0x2c: /* TIMEOUT2 */ + case 0x30: /* TIMEOUT3 */ + case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ + case 0x40: /* EMIFS_CFG_DYN_WAIT */ s->tcmi_regs[addr >> 2] =3D value; break; - case 0x0c: /* EMIFS_CONFIG */ + case 0x0c: /* EMIFS_CONFIG */ s->tcmi_regs[addr >> 2] =3D (value & 0xf) | (1 << 4); break; =20 @@ -1393,7 +1393,7 @@ static uint64_t omap_dpll_read(void *opaque, hwaddr a= ddr, return omap_badwidth_read16(opaque, addr); } =20 - if (addr =3D=3D 0x00) /* CTL_REG */ + if (addr =3D=3D 0x00) /* CTL_REG */ return s->mode; =20 OMAP_BAD_REG(addr); @@ -1413,16 +1413,16 @@ static void omap_dpll_write(void *opaque, hwaddr ad= dr, return; } =20 - if (addr =3D=3D 0x00) { /* CTL_REG */ + if (addr =3D=3D 0x00) { /* CTL_REG */ /* See omap_ulpd_pm_write() too */ diff =3D s->mode & value; s->mode =3D value & 0x2fff; if (diff & (0x3ff << 2)) { - if (value & (1 << 4)) { /* PLL_ENABLE */ - div =3D ((value >> 5) & 3) + 1; /* PLL_DIV */ - mult =3D MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ + if (value & (1 << 4)) { /* PLL_ENABLE */ + div =3D ((value >> 5) & 3) + 1; /* PLL_DIV */ + mult =3D MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ } else { - div =3D bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ + div =3D bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ mult =3D 1; } omap_clk_setrate(s->dpll, div, mult); @@ -1474,31 +1474,31 @@ static uint64_t omap_clkm_read(void *opaque, hwaddr= addr, } =20 switch (addr) { - case 0x00: /* ARM_CKCTL */ + case 0x00: /* ARM_CKCTL */ return s->clkm.arm_ckctl; =20 - case 0x04: /* ARM_IDLECT1 */ + case 0x04: /* ARM_IDLECT1 */ return s->clkm.arm_idlect1; =20 - case 0x08: /* ARM_IDLECT2 */ + case 0x08: /* ARM_IDLECT2 */ return s->clkm.arm_idlect2; =20 - case 0x0c: /* ARM_EWUPCT */ + case 0x0c: /* ARM_EWUPCT */ return s->clkm.arm_ewupct; =20 - case 0x10: /* ARM_RSTCT1 */ + case 0x10: /* ARM_RSTCT1 */ return s->clkm.arm_rstct1; =20 - case 0x14: /* ARM_RSTCT2 */ + case 0x14: /* ARM_RSTCT2 */ return s->clkm.arm_rstct2; =20 - case 0x18: /* ARM_SYSST */ + case 0x18: /* ARM_SYSST */ return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start; =20 - case 0x1c: /* ARM_CKOUT1 */ + case 0x1c: /* ARM_CKOUT1 */ return s->clkm.arm_ckout1; =20 - case 0x20: /* ARM_CKOUT2 */ + case 0x20: /* ARM_CKOUT2 */ break; } =20 @@ -1511,7 +1511,7 @@ static inline void omap_clkm_ckctl_update(struct omap= _mpu_state_s *s, { omap_clk clk; =20 - if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */ + if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */ if (value & (1 << 14)) /* Reserved */; else { @@ -1519,7 +1519,7 @@ static inline void omap_clkm_ckctl_update(struct omap= _mpu_state_s *s, omap_clk_reparent(clk, omap_findclk(s, "tc_ck")); } } - if (diff & (1 << 12)) { /* ARM_TIMXO */ + if (diff & (1 << 12)) { /* ARM_TIMXO */ clk =3D omap_findclk(s, "armtim_ck"); if (value & (1 << 12)) omap_clk_reparent(clk, omap_findclk(s, "clkin")); @@ -1527,27 +1527,27 @@ static inline void omap_clkm_ckctl_update(struct om= ap_mpu_state_s *s, omap_clk_reparent(clk, omap_findclk(s, "ck_gen1")); } /* XXX: en_dspck */ - if (diff & (3 << 10)) { /* DSPMMUDIV */ + if (diff & (3 << 10)) { /* DSPMMUDIV */ clk =3D omap_findclk(s, "dspmmu_ck"); omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1); } - if (diff & (3 << 8)) { /* TCDIV */ + if (diff & (3 << 8)) { /* TCDIV */ clk =3D omap_findclk(s, "tc_ck"); omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1); } - if (diff & (3 << 6)) { /* DSPDIV */ + if (diff & (3 << 6)) { /* DSPDIV */ clk =3D omap_findclk(s, "dsp_ck"); omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1); } - if (diff & (3 << 4)) { /* ARMDIV */ + if (diff & (3 << 4)) { /* ARMDIV */ clk =3D omap_findclk(s, "arm_ck"); omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1); } - if (diff & (3 << 2)) { /* LCDDIV */ + if (diff & (3 << 2)) { /* LCDDIV */ clk =3D omap_findclk(s, "lcd_ck"); omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1); } - if (diff & (3 << 0)) { /* PERDIV */ + if (diff & (3 << 0)) { /* PERDIV */ clk =3D omap_findclk(s, "armper_ck"); omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1); } @@ -1566,25 +1566,25 @@ static inline void omap_clkm_idlect1_update(struct = omap_mpu_state_s *s, qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); } =20 -#define SET_CANIDLE(clock, bit) \ - if (diff & (1 << bit)) { \ - clk =3D omap_findclk(s, clock); \ - omap_clk_canidle(clk, (value >> bit) & 1); \ +#define SET_CANIDLE(clock, bit) \ + if (diff & (1 << bit)) { \ + clk =3D omap_findclk(s, clock); \ + omap_clk_canidle(clk, (value >> bit) & 1); \ } - SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */ - SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */ - SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */ - SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */ - SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */ - SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */ - SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */ - SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */ - SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */ - SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */ - SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */ - SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */ - SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */ - SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */ + SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */ + SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */ + SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */ + SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */ + SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */ + SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */ + SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */ + SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */ + SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */ + SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */ + SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */ + SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */ + SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */ + SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */ } =20 static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s, @@ -1592,22 +1592,22 @@ static inline void omap_clkm_idlect2_update(struct = omap_mpu_state_s *s, { omap_clk clk; =20 -#define SET_ONOFF(clock, bit) \ - if (diff & (1 << bit)) { \ - clk =3D omap_findclk(s, clock); \ - omap_clk_onoff(clk, (value >> bit) & 1); \ +#define SET_ONOFF(clock, bit) \ + if (diff & (1 << bit)) { \ + clk =3D omap_findclk(s, clock); \ + omap_clk_onoff(clk, (value >> bit) & 1); \ } - SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */ - SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */ - SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */ - SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */ - SET_ONOFF("lb_ck", 4) /* EN_LBCK */ - SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */ - SET_ONOFF("mpui_ck", 6) /* EN_APICK */ - SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */ - SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */ - SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */ - SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */ + SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */ + SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */ + SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */ + SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */ + SET_ONOFF("lb_ck", 4) /* EN_LBCK */ + SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */ + SET_ONOFF("mpui_ck", 6) /* EN_APICK */ + SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */ + SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */ + SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */ + SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */ } =20 static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s, @@ -1615,7 +1615,7 @@ static inline void omap_clkm_ckout1_update(struct oma= p_mpu_state_s *s, { omap_clk clk; =20 - if (diff & (3 << 4)) { /* TCLKOUT */ + if (diff & (3 << 4)) { /* TCLKOUT */ clk =3D omap_findclk(s, "tclk_out"); switch ((value >> 4) & 3) { case 1: @@ -1630,7 +1630,7 @@ static inline void omap_clkm_ckout1_update(struct oma= p_mpu_state_s *s, omap_clk_onoff(clk, 0); } } - if (diff & (3 << 2)) { /* DCLKOUT */ + if (diff & (3 << 2)) { /* DCLKOUT */ clk =3D omap_findclk(s, "dclk_out"); switch ((value >> 2) & 3) { case 0: @@ -1647,7 +1647,7 @@ static inline void omap_clkm_ckout1_update(struct oma= p_mpu_state_s *s, break; } } - if (diff & (3 << 0)) { /* ACLKOUT */ + if (diff & (3 << 0)) { /* ACLKOUT */ clk =3D omap_findclk(s, "aclk_out"); switch ((value >> 0) & 3) { case 1: @@ -1685,51 +1685,51 @@ static void omap_clkm_write(void *opaque, hwaddr ad= dr, } =20 switch (addr) { - case 0x00: /* ARM_CKCTL */ + case 0x00: /* ARM_CKCTL */ diff =3D s->clkm.arm_ckctl ^ value; s->clkm.arm_ckctl =3D value & 0x7fff; omap_clkm_ckctl_update(s, diff, value); return; =20 - case 0x04: /* ARM_IDLECT1 */ + case 0x04: /* ARM_IDLECT1 */ diff =3D s->clkm.arm_idlect1 ^ value; s->clkm.arm_idlect1 =3D value & 0x0fff; omap_clkm_idlect1_update(s, diff, value); return; =20 - case 0x08: /* ARM_IDLECT2 */ + case 0x08: /* ARM_IDLECT2 */ diff =3D s->clkm.arm_idlect2 ^ value; s->clkm.arm_idlect2 =3D value & 0x07ff; omap_clkm_idlect2_update(s, diff, value); return; =20 - case 0x0c: /* ARM_EWUPCT */ + case 0x0c: /* ARM_EWUPCT */ s->clkm.arm_ewupct =3D value & 0x003f; return; =20 - case 0x10: /* ARM_RSTCT1 */ + case 0x10: /* ARM_RSTCT1 */ diff =3D s->clkm.arm_rstct1 ^ value; s->clkm.arm_rstct1 =3D value & 0x0007; if (value & 9) { qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); s->clkm.cold_start =3D 0xa; } - if (diff & ~value & 4) { /* DSP_RST */ + if (diff & ~value & 4) { /* DSP_RST */ omap_mpui_reset(s); omap_tipb_bridge_reset(s->private_tipb); omap_tipb_bridge_reset(s->public_tipb); } - if (diff & 2) { /* DSP_EN */ + if (diff & 2) { /* DSP_EN */ clk =3D omap_findclk(s, "dsp_ck"); omap_clk_canidle(clk, (~value >> 1) & 1); } return; =20 - case 0x14: /* ARM_RSTCT2 */ + case 0x14: /* ARM_RSTCT2 */ s->clkm.arm_rstct2 =3D value & 0x0001; return; =20 - case 0x18: /* ARM_SYSST */ + case 0x18: /* ARM_SYSST */ if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) { s->clkm.clocking_scheme =3D (value >> 11) & 7; trace_omap1_pwl_clocking_scheme( @@ -1738,13 +1738,13 @@ static void omap_clkm_write(void *opaque, hwaddr ad= dr, s->clkm.cold_start &=3D value & 0x3f; return; =20 - case 0x1c: /* ARM_CKOUT1 */ + case 0x1c: /* ARM_CKOUT1 */ diff =3D s->clkm.arm_ckout1 ^ value; s->clkm.arm_ckout1 =3D value & 0x003f; omap_clkm_ckout1_update(s, diff, value); return; =20 - case 0x20: /* ARM_CKOUT2 */ + case 0x20: /* ARM_CKOUT2 */ default: OMAP_BAD_REG(addr); } @@ -1767,16 +1767,16 @@ static uint64_t omap_clkdsp_read(void *opaque, hwad= dr addr, } =20 switch (addr) { - case 0x04: /* DSP_IDLECT1 */ + case 0x04: /* DSP_IDLECT1 */ return s->clkm.dsp_idlect1; =20 - case 0x08: /* DSP_IDLECT2 */ + case 0x08: /* DSP_IDLECT2 */ return s->clkm.dsp_idlect2; =20 - case 0x14: /* DSP_RSTCT2 */ + case 0x14: /* DSP_RSTCT2 */ return s->clkm.dsp_rstct2; =20 - case 0x18: /* DSP_SYSST */ + case 0x18: /* DSP_SYSST */ return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start | (cpu->halted << 6); /* Quite useless... */ } @@ -1790,7 +1790,7 @@ static inline void omap_clkdsp_idlect1_update(struct = omap_mpu_state_s *s, { omap_clk clk; =20 - SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */ + SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */ } =20 static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s, @@ -1798,7 +1798,7 @@ static inline void omap_clkdsp_idlect2_update(struct = omap_mpu_state_s *s, { omap_clk clk; =20 - SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */ + SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */ } =20 static void omap_clkdsp_write(void *opaque, hwaddr addr, @@ -1813,23 +1813,23 @@ static void omap_clkdsp_write(void *opaque, hwaddr = addr, } =20 switch (addr) { - case 0x04: /* DSP_IDLECT1 */ + case 0x04: /* DSP_IDLECT1 */ diff =3D s->clkm.dsp_idlect1 ^ value; s->clkm.dsp_idlect1 =3D value & 0x01f7; omap_clkdsp_idlect1_update(s, diff, value); break; =20 - case 0x08: /* DSP_IDLECT2 */ + case 0x08: /* DSP_IDLECT2 */ s->clkm.dsp_idlect2 =3D value & 0x0037; diff =3D s->clkm.dsp_idlect1 ^ value; omap_clkdsp_idlect2_update(s, diff, value); break; =20 - case 0x14: /* DSP_RSTCT2 */ + case 0x14: /* DSP_RSTCT2 */ s->clkm.dsp_rstct2 =3D value & 0x0001; break; =20 - case 0x18: /* DSP_SYSST */ + case 0x18: /* DSP_SYSST */ s->clkm.cold_start &=3D value & 0x3f; break; =20 @@ -1928,8 +1928,8 @@ static void omap_mpuio_set(void *opaque, int line, in= t level) qemu_irq_raise(s->irq); /* TODO: wakeup */ } - if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */ - (s->event >> 1) =3D=3D line) /* PIN_SELECT */ + if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */ + (s->event >> 1) =3D=3D line) /* PIN_SELECT */ s->latch =3D s->inputs; } } @@ -1959,47 +1959,47 @@ static uint64_t omap_mpuio_read(void *opaque, hwadd= r addr, } =20 switch (offset) { - case 0x00: /* INPUT_LATCH */ + case 0x00: /* INPUT_LATCH */ return s->inputs; =20 - case 0x04: /* OUTPUT_REG */ + case 0x04: /* OUTPUT_REG */ return s->outputs; =20 - case 0x08: /* IO_CNTL */ + case 0x08: /* IO_CNTL */ return s->dir; =20 - case 0x10: /* KBR_LATCH */ + case 0x10: /* KBR_LATCH */ return s->row_latch; =20 - case 0x14: /* KBC_REG */ + case 0x14: /* KBC_REG */ return s->cols; =20 - case 0x18: /* GPIO_EVENT_MODE_REG */ + case 0x18: /* GPIO_EVENT_MODE_REG */ return s->event; =20 - case 0x1c: /* GPIO_INT_EDGE_REG */ + case 0x1c: /* GPIO_INT_EDGE_REG */ return s->edge; =20 - case 0x20: /* KBD_INT */ + case 0x20: /* KBD_INT */ return (~s->row_latch & 0x1f) && !s->kbd_mask; =20 - case 0x24: /* GPIO_INT */ + case 0x24: /* GPIO_INT */ ret =3D s->ints; s->ints &=3D s->mask; if (ret) qemu_irq_lower(s->irq); return ret; =20 - case 0x28: /* KBD_MASKIT */ + case 0x28: /* KBD_MASKIT */ return s->kbd_mask; =20 - case 0x2c: /* GPIO_MASKIT */ + case 0x2c: /* GPIO_MASKIT */ return s->mask; =20 - case 0x30: /* GPIO_DEBOUNCING_REG */ + case 0x30: /* GPIO_DEBOUNCING_REG */ return s->debounce; =20 - case 0x34: /* GPIO_LATCH_REG */ + case 0x34: /* GPIO_LATCH_REG */ return s->latch; } =20 @@ -2021,7 +2021,7 @@ static void omap_mpuio_write(void *opaque, hwaddr add= r, } =20 switch (offset) { - case 0x04: /* OUTPUT_REG */ + case 0x04: /* OUTPUT_REG */ diff =3D (s->outputs ^ value) & ~s->dir; s->outputs =3D value; while ((ln =3D ctz32(diff)) !=3D 32) { @@ -2031,7 +2031,7 @@ static void omap_mpuio_write(void *opaque, hwaddr add= r, } break; =20 - case 0x08: /* IO_CNTL */ + case 0x08: /* IO_CNTL */ diff =3D s->outputs & (s->dir ^ value); s->dir =3D value; =20 @@ -2043,37 +2043,37 @@ static void omap_mpuio_write(void *opaque, hwaddr a= ddr, } break; =20 - case 0x14: /* KBC_REG */ + case 0x14: /* KBC_REG */ s->cols =3D value; omap_mpuio_kbd_update(s); break; =20 - case 0x18: /* GPIO_EVENT_MODE_REG */ + case 0x18: /* GPIO_EVENT_MODE_REG */ s->event =3D value & 0x1f; break; =20 - case 0x1c: /* GPIO_INT_EDGE_REG */ + case 0x1c: /* GPIO_INT_EDGE_REG */ s->edge =3D value; break; =20 - case 0x28: /* KBD_MASKIT */ + case 0x28: /* KBD_MASKIT */ s->kbd_mask =3D value & 1; omap_mpuio_kbd_update(s); break; =20 - case 0x2c: /* GPIO_MASKIT */ + case 0x2c: /* GPIO_MASKIT */ s->mask =3D value; break; =20 - case 0x30: /* GPIO_DEBOUNCING_REG */ + case 0x30: /* GPIO_DEBOUNCING_REG */ s->debounce =3D value & 0x1ff; break; =20 - case 0x00: /* INPUT_LATCH */ - case 0x10: /* KBR_LATCH */ - case 0x20: /* KBD_INT */ - case 0x24: /* GPIO_INT */ - case 0x34: /* GPIO_LATCH_REG */ + case 0x00: /* INPUT_LATCH */ + case 0x10: /* KBR_LATCH */ + case 0x20: /* KBD_INT */ + case 0x24: /* GPIO_INT */ + case 0x34: /* GPIO_LATCH_REG */ OMAP_RO_REG(addr); return; =20 @@ -2176,24 +2176,24 @@ struct omap_uwire_s { =20 static void omap_uwire_transfer_start(struct omap_uwire_s *s) { - int chipselect =3D (s->control >> 10) & 3; /* INDEX */ + int chipselect =3D (s->control >> 10) & 3; /* INDEX */ =20 - if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */ + if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */ if (s->control & (1 << 12)) { /* CS_CMD */ qemu_log_mask(LOG_UNIMP, "uWireSlave TX CS:%d data:0x%04x\n", chipselect, s->txbuf >> (16 - ((s->control >> 5) & 0x1f))); } - s->control &=3D ~(1 << 14); /* CSRB */ + s->control &=3D ~(1 << 14); /* CSRB */ /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or * a DRQ. When is the level IRQ supposed to be reset? */ } =20 - if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */ + if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */ if (s->control & (1 << 12)) { /* CS_CMD */ qemu_log_mask(LOG_UNIMP, "uWireSlave RX CS:%d\n", chipselect); } - s->control |=3D 1 << 15; /* RDRB */ + s->control |=3D 1 << 15; /* RDRB */ /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or * a DRQ. When is the level IRQ supposed to be reset? */ } @@ -2209,22 +2209,22 @@ static uint64_t omap_uwire_read(void *opaque, hwadd= r addr, unsigned size) } =20 switch (offset) { - case 0x00: /* RDR */ - s->control &=3D ~(1 << 15); /* RDRB */ + case 0x00: /* RDR */ + s->control &=3D ~(1 << 15); /* RDRB */ return s->rxbuf; =20 - case 0x04: /* CSR */ + case 0x04: /* CSR */ return s->control; =20 - case 0x08: /* SR1 */ + case 0x08: /* SR1 */ return s->setup[0]; - case 0x0c: /* SR2 */ + case 0x0c: /* SR2 */ return s->setup[1]; - case 0x10: /* SR3 */ + case 0x10: /* SR3 */ return s->setup[2]; - case 0x14: /* SR4 */ + case 0x14: /* SR4 */ return s->setup[3]; - case 0x18: /* SR5 */ + case 0x18: /* SR5 */ return s->setup[4]; } =20 @@ -2244,39 +2244,39 @@ static void omap_uwire_write(void *opaque, hwaddr a= ddr, } =20 switch (offset) { - case 0x00: /* TDR */ - s->txbuf =3D value; /* TD */ - if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */ - ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */ - (s->control & (1 << 12)))) { /* CS_CMD */ - s->control |=3D 1 << 14; /* CSRB */ + case 0x00: /* TDR */ + s->txbuf =3D value; /* TD */ + if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */ + ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN= */ + (s->control & (1 << 12)))) { /* CS_CMD */ + s->control |=3D 1 << 14; /* CSRB */ omap_uwire_transfer_start(s); } break; =20 - case 0x04: /* CSR */ + case 0x04: /* CSR */ s->control =3D value & 0x1fff; - if (value & (1 << 13)) /* START */ + if (value & (1 << 13)) /* START */ omap_uwire_transfer_start(s); break; =20 - case 0x08: /* SR1 */ + case 0x08: /* SR1 */ s->setup[0] =3D value & 0x003f; break; =20 - case 0x0c: /* SR2 */ + case 0x0c: /* SR2 */ s->setup[1] =3D value & 0x0fc0; break; =20 - case 0x10: /* SR3 */ + case 0x10: /* SR3 */ s->setup[2] =3D value & 0x0003; break; =20 - case 0x14: /* SR4 */ + case 0x14: /* SR4 */ s->setup[3] =3D value & 0x0001; break; =20 - case 0x18: /* SR5 */ + case 0x18: /* SR5 */ s->setup[4] =3D value & 0x000f; break; =20 @@ -2350,9 +2350,9 @@ static uint64_t omap_pwl_read(void *opaque, hwaddr ad= dr, unsigned size) } =20 switch (offset) { - case 0x00: /* PWL_LEVEL */ + case 0x00: /* PWL_LEVEL */ return s->level; - case 0x04: /* PWL_CTRL */ + case 0x04: /* PWL_CTRL */ return s->enable; } OMAP_BAD_REG(addr); @@ -2371,11 +2371,11 @@ static void omap_pwl_write(void *opaque, hwaddr add= r, } =20 switch (offset) { - case 0x00: /* PWL_LEVEL */ + case 0x00: /* PWL_LEVEL */ s->level =3D value; omap_pwl_update(s); break; - case 0x04: /* PWL_CTRL */ + case 0x04: /* PWL_CTRL */ s->enable =3D value & 1; omap_pwl_update(s); break; @@ -2443,11 +2443,11 @@ static uint64_t omap_pwt_read(void *opaque, hwaddr = addr, unsigned size) } =20 switch (offset) { - case 0x00: /* FRC */ + case 0x00: /* FRC */ return s->frc; - case 0x04: /* VCR */ + case 0x04: /* VCR */ return s->vrc; - case 0x08: /* GCR */ + case 0x08: /* GCR */ return s->gcr; } OMAP_BAD_REG(addr); @@ -2466,10 +2466,10 @@ static void omap_pwt_write(void *opaque, hwaddr add= r, } =20 switch (offset) { - case 0x00: /* FRC */ + case 0x00: /* FRC */ s->frc =3D value & 0x3f; break; - case 0x04: /* VRC */ + case 0x04: /* VRC */ if ((value ^ s->vrc) & 1) { if (value & 1) { trace_omap1_pwt_buzz( @@ -2494,7 +2494,7 @@ static void omap_pwt_write(void *opaque, hwaddr addr, } s->vrc =3D value & 0x7f; break; - case 0x08: /* GCR */ + case 0x08: /* GCR */ s->gcr =3D value & 3; break; default: @@ -2577,69 +2577,69 @@ static uint64_t omap_rtc_read(void *opaque, hwaddr = addr, unsigned size) } =20 switch (offset) { - case 0x00: /* SECONDS_REG */ + case 0x00: /* SECONDS_REG */ return to_bcd(s->current_tm.tm_sec); =20 - case 0x04: /* MINUTES_REG */ + case 0x04: /* MINUTES_REG */ return to_bcd(s->current_tm.tm_min); =20 - case 0x08: /* HOURS_REG */ + case 0x08: /* HOURS_REG */ if (s->pm_am) return ((s->current_tm.tm_hour > 11) << 7) | to_bcd(((s->current_tm.tm_hour - 1) % 12) + 1); else return to_bcd(s->current_tm.tm_hour); =20 - case 0x0c: /* DAYS_REG */ + case 0x0c: /* DAYS_REG */ return to_bcd(s->current_tm.tm_mday); =20 - case 0x10: /* MONTHS_REG */ + case 0x10: /* MONTHS_REG */ return to_bcd(s->current_tm.tm_mon + 1); =20 - case 0x14: /* YEARS_REG */ + case 0x14: /* YEARS_REG */ return to_bcd(s->current_tm.tm_year % 100); =20 - case 0x18: /* WEEK_REG */ + case 0x18: /* WEEK_REG */ return s->current_tm.tm_wday; =20 - case 0x20: /* ALARM_SECONDS_REG */ + case 0x20: /* ALARM_SECONDS_REG */ return to_bcd(s->alarm_tm.tm_sec); =20 - case 0x24: /* ALARM_MINUTES_REG */ + case 0x24: /* ALARM_MINUTES_REG */ return to_bcd(s->alarm_tm.tm_min); =20 - case 0x28: /* ALARM_HOURS_REG */ + case 0x28: /* ALARM_HOURS_REG */ if (s->pm_am) return ((s->alarm_tm.tm_hour > 11) << 7) | to_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1); else return to_bcd(s->alarm_tm.tm_hour); =20 - case 0x2c: /* ALARM_DAYS_REG */ + case 0x2c: /* ALARM_DAYS_REG */ return to_bcd(s->alarm_tm.tm_mday); =20 - case 0x30: /* ALARM_MONTHS_REG */ + case 0x30: /* ALARM_MONTHS_REG */ return to_bcd(s->alarm_tm.tm_mon + 1); =20 - case 0x34: /* ALARM_YEARS_REG */ + case 0x34: /* ALARM_YEARS_REG */ return to_bcd(s->alarm_tm.tm_year % 100); =20 - case 0x40: /* RTC_CTRL_REG */ + case 0x40: /* RTC_CTRL_REG */ return (s->pm_am << 3) | (s->auto_comp << 2) | (s->round << 1) | s->running; =20 - case 0x44: /* RTC_STATUS_REG */ + case 0x44: /* RTC_STATUS_REG */ i =3D s->status; s->status &=3D ~0x3d; return i; =20 - case 0x48: /* RTC_INTERRUPTS_REG */ + case 0x48: /* RTC_INTERRUPTS_REG */ return s->interrupts; =20 - case 0x4c: /* RTC_COMP_LSB_REG */ + case 0x4c: /* RTC_COMP_LSB_REG */ return ((uint16_t) s->comp_reg) & 0xff; =20 - case 0x50: /* RTC_COMP_MSB_REG */ + case 0x50: /* RTC_COMP_MSB_REG */ return ((uint16_t) s->comp_reg) >> 8; } =20 @@ -2661,17 +2661,17 @@ static void omap_rtc_write(void *opaque, hwaddr add= r, } =20 switch (offset) { - case 0x00: /* SECONDS_REG */ + case 0x00: /* SECONDS_REG */ s->ti -=3D s->current_tm.tm_sec; s->ti +=3D from_bcd(value); return; =20 - case 0x04: /* MINUTES_REG */ + case 0x04: /* MINUTES_REG */ s->ti -=3D s->current_tm.tm_min * 60; s->ti +=3D from_bcd(value) * 60; return; =20 - case 0x08: /* HOURS_REG */ + case 0x08: /* HOURS_REG */ s->ti -=3D s->current_tm.tm_hour * 3600; if (s->pm_am) { s->ti +=3D (from_bcd(value & 0x3f) & 12) * 3600; @@ -2680,12 +2680,12 @@ static void omap_rtc_write(void *opaque, hwaddr add= r, s->ti +=3D from_bcd(value & 0x3f) * 3600; return; =20 - case 0x0c: /* DAYS_REG */ + case 0x0c: /* DAYS_REG */ s->ti -=3D s->current_tm.tm_mday * 86400; s->ti +=3D from_bcd(value) * 86400; return; =20 - case 0x10: /* MONTHS_REG */ + case 0x10: /* MONTHS_REG */ memcpy(&new_tm, &s->current_tm, sizeof(new_tm)); new_tm.tm_mon =3D from_bcd(value); ti[0] =3D mktimegm(&s->current_tm); @@ -2701,7 +2701,7 @@ static void omap_rtc_write(void *opaque, hwaddr addr, } return; =20 - case 0x14: /* YEARS_REG */ + case 0x14: /* YEARS_REG */ memcpy(&new_tm, &s->current_tm, sizeof(new_tm)); new_tm.tm_year +=3D from_bcd(value) - (new_tm.tm_year % 100); ti[0] =3D mktimegm(&s->current_tm); @@ -2717,20 +2717,20 @@ static void omap_rtc_write(void *opaque, hwaddr add= r, } return; =20 - case 0x18: /* WEEK_REG */ - return; /* Ignored */ + case 0x18: /* WEEK_REG */ + return; /* Ignored */ =20 - case 0x20: /* ALARM_SECONDS_REG */ + case 0x20: /* ALARM_SECONDS_REG */ s->alarm_tm.tm_sec =3D from_bcd(value); omap_rtc_alarm_update(s); return; =20 - case 0x24: /* ALARM_MINUTES_REG */ + case 0x24: /* ALARM_MINUTES_REG */ s->alarm_tm.tm_min =3D from_bcd(value); omap_rtc_alarm_update(s); return; =20 - case 0x28: /* ALARM_HOURS_REG */ + case 0x28: /* ALARM_HOURS_REG */ if (s->pm_am) s->alarm_tm.tm_hour =3D ((from_bcd(value & 0x3f)) % 12) + @@ -2740,22 +2740,22 @@ static void omap_rtc_write(void *opaque, hwaddr add= r, omap_rtc_alarm_update(s); return; =20 - case 0x2c: /* ALARM_DAYS_REG */ + case 0x2c: /* ALARM_DAYS_REG */ s->alarm_tm.tm_mday =3D from_bcd(value); omap_rtc_alarm_update(s); return; =20 - case 0x30: /* ALARM_MONTHS_REG */ + case 0x30: /* ALARM_MONTHS_REG */ s->alarm_tm.tm_mon =3D from_bcd(value); omap_rtc_alarm_update(s); return; =20 - case 0x34: /* ALARM_YEARS_REG */ + case 0x34: /* ALARM_YEARS_REG */ s->alarm_tm.tm_year =3D from_bcd(value); omap_rtc_alarm_update(s); return; =20 - case 0x40: /* RTC_CTRL_REG */ + case 0x40: /* RTC_CTRL_REG */ s->pm_am =3D (value >> 3) & 1; s->auto_comp =3D (value >> 2) & 1; s->round =3D (value >> 1) & 1; @@ -2764,21 +2764,21 @@ static void omap_rtc_write(void *opaque, hwaddr add= r, s->status |=3D s->running << 1; return; =20 - case 0x44: /* RTC_STATUS_REG */ + case 0x44: /* RTC_STATUS_REG */ s->status &=3D ~((value & 0xc0) ^ 0x80); omap_rtc_interrupts_update(s); return; =20 - case 0x48: /* RTC_INTERRUPTS_REG */ + case 0x48: /* RTC_INTERRUPTS_REG */ s->interrupts =3D value; return; =20 - case 0x4c: /* RTC_COMP_LSB_REG */ + case 0x4c: /* RTC_COMP_LSB_REG */ s->comp_reg &=3D 0xff00; s->comp_reg |=3D 0x00ff & value; return; =20 - case 0x50: /* RTC_COMP_MSB_REG */ + case 0x50: /* RTC_COMP_MSB_REG */ s->comp_reg &=3D 0x00ff; s->comp_reg |=3D 0xff00 & (value << 8); return; @@ -2929,12 +2929,12 @@ static void omap_mcbsp_intr_update(struct omap_mcbs= p_s *s) { int irq; =20 - switch ((s->spcr[0] >> 4) & 3) { /* RINTM */ + switch ((s->spcr[0] >> 4) & 3) { /* RINTM */ case 0: - irq =3D (s->spcr[0] >> 1) & 1; /* RRDY */ + irq =3D (s->spcr[0] >> 1) & 1; /* RRDY */ break; case 3: - irq =3D (s->spcr[0] >> 3) & 1; /* RSYNCERR */ + irq =3D (s->spcr[0] >> 3) & 1; /* RSYNCERR */ break; default: irq =3D 0; @@ -2944,12 +2944,12 @@ static void omap_mcbsp_intr_update(struct omap_mcbs= p_s *s) if (irq) qemu_irq_pulse(s->rxirq); =20 - switch ((s->spcr[1] >> 4) & 3) { /* XINTM */ + switch ((s->spcr[1] >> 4) & 3) { /* XINTM */ case 0: - irq =3D (s->spcr[1] >> 1) & 1; /* XRDY */ + irq =3D (s->spcr[1] >> 1) & 1; /* XRDY */ break; case 3: - irq =3D (s->spcr[1] >> 3) & 1; /* XSYNCERR */ + irq =3D (s->spcr[1] >> 3) & 1; /* XSYNCERR */ break; default: irq =3D 0; @@ -2962,9 +2962,9 @@ static void omap_mcbsp_intr_update(struct omap_mcbsp_= s *s) =20 static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s) { - if ((s->spcr[0] >> 1) & 1) /* RRDY */ - s->spcr[0] |=3D 1 << 2; /* RFULL */ - s->spcr[0] |=3D 1 << 1; /* RRDY */ + if ((s->spcr[0] >> 1) & 1) /* RRDY */ + s->spcr[0] |=3D 1 << 2; /* RFULL */ + s->spcr[0] |=3D 1 << 1; /* RRDY */ qemu_irq_raise(s->rxdrq); omap_mcbsp_intr_update(s); } @@ -3004,14 +3004,14 @@ static void omap_mcbsp_rx_stop(struct omap_mcbsp_s = *s) =20 static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s) { - s->spcr[0] &=3D ~(1 << 1); /* RRDY */ + s->spcr[0] &=3D ~(1 << 1); /* RRDY */ qemu_irq_lower(s->rxdrq); omap_mcbsp_intr_update(s); } =20 static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s) { - s->spcr[1] |=3D 1 << 1; /* XRDY */ + s->spcr[1] |=3D 1 << 1; /* XRDY */ qemu_irq_raise(s->txdrq); omap_mcbsp_intr_update(s); } @@ -3046,7 +3046,7 @@ static void omap_mcbsp_tx_start(struct omap_mcbsp_s *= s) =20 static void omap_mcbsp_tx_done(struct omap_mcbsp_s *s) { - s->spcr[1] &=3D ~(1 << 1); /* XRDY */ + s->spcr[1] &=3D ~(1 << 1); /* XRDY */ qemu_irq_lower(s->txdrq); omap_mcbsp_intr_update(s); if (s->codec && s->codec->cts) @@ -3064,27 +3064,27 @@ static void omap_mcbsp_req_update(struct omap_mcbsp= _s *s) { int prev_rx_rate, prev_tx_rate; int rx_rate =3D 0, tx_rate =3D 0; - int cpu_rate =3D 1500000; /* XXX */ + int cpu_rate =3D 1500000; /* XXX */ =20 /* TODO: check CLKSTP bit */ - if (s->spcr[1] & (1 << 6)) { /* GRST */ - if (s->spcr[0] & (1 << 0)) { /* RRST */ - if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ - (s->pcr & (1 << 8))) { /* CLKRM */ - if (~s->pcr & (1 << 7)) /* SCLKME */ + if (s->spcr[1] & (1 << 6)) { /* GRST */ + if (s->spcr[0] & (1 << 0)) { /* RRST */ + if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ + (s->pcr & (1 << 8))) { /* CLKRM */ + if (~s->pcr & (1 << 7)) /* SCLKME */ rx_rate =3D cpu_rate / - ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ + ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ } else if (s->codec) rx_rate =3D s->codec->rx_rate; } =20 - if (s->spcr[1] & (1 << 0)) { /* XRST */ - if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ - (s->pcr & (1 << 9))) { /* CLKXM */ - if (~s->pcr & (1 << 7)) /* SCLKME */ + if (s->spcr[1] & (1 << 0)) { /* XRST */ + if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ + (s->pcr & (1 << 9))) { /* CLKXM */ + if (~s->pcr & (1 << 7)) /* SCLKME */ tx_rate =3D cpu_rate / - ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ + ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ } else if (s->codec) tx_rate =3D s->codec->tx_rate; @@ -3121,11 +3121,11 @@ static uint64_t omap_mcbsp_read(void *opaque, hwadd= r addr, } =20 switch (offset) { - case 0x00: /* DRR2 */ - if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */ + case 0x00: /* DRR2 */ + if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */ return 0x0000; /* Fall through. */ - case 0x02: /* DRR1 */ + case 0x02: /* DRR1 */ if (s->rx_req < 2) { qemu_log_mask(LOG_GUEST_ERROR, "%s: Rx FIFO underrun\n", __fun= c__); omap_mcbsp_rx_done(s); @@ -3143,63 +3143,63 @@ static uint64_t omap_mcbsp_read(void *opaque, hwadd= r addr, } return 0x0000; =20 - case 0x04: /* DXR2 */ - case 0x06: /* DXR1 */ + case 0x04: /* DXR2 */ + case 0x06: /* DXR1 */ return 0x0000; =20 - case 0x08: /* SPCR2 */ + case 0x08: /* SPCR2 */ return s->spcr[1]; - case 0x0a: /* SPCR1 */ + case 0x0a: /* SPCR1 */ return s->spcr[0]; - case 0x0c: /* RCR2 */ + case 0x0c: /* RCR2 */ return s->rcr[1]; - case 0x0e: /* RCR1 */ + case 0x0e: /* RCR1 */ return s->rcr[0]; - case 0x10: /* XCR2 */ + case 0x10: /* XCR2 */ return s->xcr[1]; - case 0x12: /* XCR1 */ + case 0x12: /* XCR1 */ return s->xcr[0]; - case 0x14: /* SRGR2 */ + case 0x14: /* SRGR2 */ return s->srgr[1]; - case 0x16: /* SRGR1 */ + case 0x16: /* SRGR1 */ return s->srgr[0]; - case 0x18: /* MCR2 */ + case 0x18: /* MCR2 */ return s->mcr[1]; - case 0x1a: /* MCR1 */ + case 0x1a: /* MCR1 */ return s->mcr[0]; - case 0x1c: /* RCERA */ + case 0x1c: /* RCERA */ return s->rcer[0]; - case 0x1e: /* RCERB */ + case 0x1e: /* RCERB */ return s->rcer[1]; - case 0x20: /* XCERA */ + case 0x20: /* XCERA */ return s->xcer[0]; - case 0x22: /* XCERB */ + case 0x22: /* XCERB */ return s->xcer[1]; - case 0x24: /* PCR0 */ + case 0x24: /* PCR0 */ return s->pcr; - case 0x26: /* RCERC */ + case 0x26: /* RCERC */ return s->rcer[2]; - case 0x28: /* RCERD */ + case 0x28: /* RCERD */ return s->rcer[3]; - case 0x2a: /* XCERC */ + case 0x2a: /* XCERC */ return s->xcer[2]; - case 0x2c: /* XCERD */ + case 0x2c: /* XCERD */ return s->xcer[3]; - case 0x2e: /* RCERE */ + case 0x2e: /* RCERE */ return s->rcer[4]; - case 0x30: /* RCERF */ + case 0x30: /* RCERF */ return s->rcer[5]; - case 0x32: /* XCERE */ + case 0x32: /* XCERE */ return s->xcer[4]; - case 0x34: /* XCERF */ + case 0x34: /* XCERF */ return s->xcer[5]; - case 0x36: /* RCERG */ + case 0x36: /* RCERG */ return s->rcer[6]; - case 0x38: /* RCERH */ + case 0x38: /* RCERH */ return s->rcer[7]; - case 0x3a: /* XCERG */ + case 0x3a: /* XCERG */ return s->xcer[6]; - case 0x3c: /* XCERH */ + case 0x3c: /* XCERH */ return s->xcer[7]; } =20 @@ -3214,16 +3214,16 @@ static void omap_mcbsp_writeh(void *opaque, hwaddr = addr, int offset =3D addr & OMAP_MPUI_REG_MASK; =20 switch (offset) { - case 0x00: /* DRR2 */ - case 0x02: /* DRR1 */ + case 0x00: /* DRR2 */ + case 0x02: /* DRR1 */ OMAP_RO_REG(addr); return; =20 - case 0x04: /* DXR2 */ - if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ + case 0x04: /* DXR2 */ + if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ return; /* Fall through. */ - case 0x06: /* DXR1 */ + case 0x06: /* DXR1 */ if (s->tx_req > 1) { s->tx_req -=3D 2; if (s->codec && s->codec->cts) { @@ -3237,15 +3237,15 @@ static void omap_mcbsp_writeh(void *opaque, hwaddr = addr, } return; =20 - case 0x08: /* SPCR2 */ + case 0x08: /* SPCR2 */ s->spcr[1] &=3D 0x0002; s->spcr[1] |=3D 0x03f9 & value; - s->spcr[1] |=3D 0x0004 & (value << 2); /* XEMPTY :=3D XRST */ - if (~value & 1) /* XRST */ + s->spcr[1] |=3D 0x0004 & (value << 2); /* XEMPTY :=3D XRST = */ + if (~value & 1) /* XRST */ s->spcr[1] &=3D ~6; omap_mcbsp_req_update(s); return; - case 0x0a: /* SPCR1 */ + case 0x0a: /* SPCR1 */ s->spcr[0] &=3D 0x0006; s->spcr[0] |=3D 0xf8f9 & value; if (value & (1 << 15)) { /* DLB */ @@ -3253,7 +3253,7 @@ static void omap_mcbsp_writeh(void *opaque, hwaddr ad= dr, "%s: Digital Loopback mode enable attempt\n", __func__); } - if (~value & 1) { /* RRST */ + if (~value & 1) { /* RRST */ s->spcr[0] &=3D ~6; s->rx_req =3D 0; omap_mcbsp_rx_done(s); @@ -3261,27 +3261,27 @@ static void omap_mcbsp_writeh(void *opaque, hwaddr = addr, omap_mcbsp_req_update(s); return; =20 - case 0x0c: /* RCR2 */ + case 0x0c: /* RCR2 */ s->rcr[1] =3D value & 0xffff; return; - case 0x0e: /* RCR1 */ + case 0x0e: /* RCR1 */ s->rcr[0] =3D value & 0x7fe0; return; - case 0x10: /* XCR2 */ + case 0x10: /* XCR2 */ s->xcr[1] =3D value & 0xffff; return; - case 0x12: /* XCR1 */ + case 0x12: /* XCR1 */ s->xcr[0] =3D value & 0x7fe0; return; - case 0x14: /* SRGR2 */ + case 0x14: /* SRGR2 */ s->srgr[1] =3D value & 0xffff; omap_mcbsp_req_update(s); return; - case 0x16: /* SRGR1 */ + case 0x16: /* SRGR1 */ s->srgr[0] =3D value & 0xffff; omap_mcbsp_req_update(s); return; - case 0x18: /* MCR2 */ + case 0x18: /* MCR2 */ s->mcr[1] =3D value & 0x03e3; if (value & 3) { /* XMCM */ qemu_log_mask(LOG_UNIMP, @@ -3289,7 +3289,7 @@ static void omap_mcbsp_writeh(void *opaque, hwaddr ad= dr, __func__); } return; - case 0x1a: /* MCR1 */ + case 0x1a: /* MCR1 */ s->mcr[0] =3D value & 0x03e1; if (value & 1) { /* RMCM */ qemu_log_mask(LOG_UNIMP, @@ -3297,55 +3297,55 @@ static void omap_mcbsp_writeh(void *opaque, hwaddr = addr, __func__); } return; - case 0x1c: /* RCERA */ + case 0x1c: /* RCERA */ s->rcer[0] =3D value & 0xffff; return; - case 0x1e: /* RCERB */ + case 0x1e: /* RCERB */ s->rcer[1] =3D value & 0xffff; return; - case 0x20: /* XCERA */ + case 0x20: /* XCERA */ s->xcer[0] =3D value & 0xffff; return; - case 0x22: /* XCERB */ + case 0x22: /* XCERB */ s->xcer[1] =3D value & 0xffff; return; - case 0x24: /* PCR0 */ + case 0x24: /* PCR0 */ s->pcr =3D value & 0x7faf; return; - case 0x26: /* RCERC */ + case 0x26: /* RCERC */ s->rcer[2] =3D value & 0xffff; return; - case 0x28: /* RCERD */ + case 0x28: /* RCERD */ s->rcer[3] =3D value & 0xffff; return; - case 0x2a: /* XCERC */ + case 0x2a: /* XCERC */ s->xcer[2] =3D value & 0xffff; return; - case 0x2c: /* XCERD */ + case 0x2c: /* XCERD */ s->xcer[3] =3D value & 0xffff; return; - case 0x2e: /* RCERE */ + case 0x2e: /* RCERE */ s->rcer[4] =3D value & 0xffff; return; - case 0x30: /* RCERF */ + case 0x30: /* RCERF */ s->rcer[5] =3D value & 0xffff; return; - case 0x32: /* XCERE */ + case 0x32: /* XCERE */ s->xcer[4] =3D value & 0xffff; return; - case 0x34: /* XCERF */ + case 0x34: /* XCERF */ s->xcer[5] =3D value & 0xffff; return; - case 0x36: /* RCERG */ + case 0x36: /* RCERG */ s->rcer[6] =3D value & 0xffff; return; - case 0x38: /* RCERH */ + case 0x38: /* RCERH */ s->rcer[7] =3D value & 0xffff; return; - case 0x3a: /* XCERG */ + case 0x3a: /* XCERG */ s->xcer[6] =3D value & 0xffff; return; - case 0x3c: /* XCERH */ + case 0x3c: /* XCERH */ s->xcer[7] =3D value & 0xffff; return; } @@ -3359,8 +3359,8 @@ static void omap_mcbsp_writew(void *opaque, hwaddr ad= dr, struct omap_mcbsp_s *s =3D opaque; int offset =3D addr & OMAP_MPUI_REG_MASK; =20 - if (offset =3D=3D 0x04) { /* DXR */ - if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ + if (offset =3D=3D 0x04) { /* DXR */ + if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ return; if (s->tx_req > 3) { s->tx_req -=3D 4; @@ -3504,15 +3504,15 @@ static void omap_lpg_update(struct omap_lpg_s *s) int64_t on, period =3D 1, ticks =3D 1000; static const int per[8] =3D { 1, 2, 4, 8, 12, 16, 20, 24 }; =20 - if (~s->control & (1 << 6)) /* LPGRES */ + if (~s->control & (1 << 6)) /* LPGRES */ on =3D 0; - else if (s->control & (1 << 7)) /* PERM_ON */ + else if (s->control & (1 << 7)) /* PERM_ON */ on =3D period; else { - period =3D muldiv64(ticks, per[s->control & 7], /* PERCTRL */ + period =3D muldiv64(ticks, per[s->control & 7], /* PERCTRL */ 256 / 32); on =3D (s->clk && s->power) ? muldiv64(ticks, - per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */ + per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL = */ } =20 timer_del(s->tm); @@ -3550,10 +3550,10 @@ static uint64_t omap_lpg_read(void *opaque, hwaddr = addr, unsigned size) } =20 switch (offset) { - case 0x00: /* LCR */ + case 0x00: /* LCR */ return s->control; =20 - case 0x04: /* PMR */ + case 0x04: /* PMR */ return s->power; } =20 @@ -3573,14 +3573,14 @@ static void omap_lpg_write(void *opaque, hwaddr add= r, } =20 switch (offset) { - case 0x00: /* LCR */ - if (~value & (1 << 6)) /* LPGRES */ + case 0x00: /* LCR */ + if (~value & (1 << 6)) /* LPGRES */ omap_lpg_reset(s); s->control =3D value & 0xff; omap_lpg_update(s); return; =20 - case 0x04: /* PMR */ + case 0x04: /* PMR */ s->power =3D value & 0x01; omap_lpg_update(s); return; @@ -3630,7 +3630,7 @@ static uint64_t omap_mpui_io_read(void *opaque, hwadd= r addr, return omap_badwidth_read16(opaque, addr); } =20 - if (addr =3D=3D OMAP_MPUI_BASE) /* CMR */ + if (addr =3D=3D OMAP_MPUI_BASE) /* CMR */ return 0xfe4d; =20 OMAP_BAD_REG(addr); @@ -3703,25 +3703,25 @@ static const struct omap_map_s { const char *name; } omap15xx_dsp_mm[] =3D { /* Strobe 0 */ - { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */ - { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */ - { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */ - { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */ - { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */ - { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */ - { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */ - { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */ - { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */ - { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */ - { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */ - { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */ - { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */ - { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */ - { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */ - { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */ - { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */ + { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */ + { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */ + { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */ + { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */ + { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */ + { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */ + { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */ + { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */ + { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */ + { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */ + { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */ + { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */ + { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */ + { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */ + { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */ + { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */ + { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */ /* Strobe 1 */ - { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */ + { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */ =20 { 0 } }; @@ -4025,18 +4025,18 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryReg= ion *dram, 0xfffbd800, omap_findclk(s, "clk32-kHz")); =20 /* Register mappings not currently implemented: - * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310) - * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310) - * USB W2FC fffb4000 - fffb47ff - * Camera Interface fffb6800 - fffb6fff - * USB Host fffba000 - fffba7ff - * FAC fffba800 - fffbafff - * HDQ/1-Wire fffbc000 - fffbc7ff - * TIPB switches fffbc800 - fffbcfff - * Mailbox fffcf000 - fffcf7ff - * Local bus IF fffec100 - fffec1ff - * Local bus MMU fffec200 - fffec2ff - * DSP MMU fffed200 - fffed2ff + * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310) + * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310) + * USB W2FC fffb4000 - fffb47ff + * Camera Interface fffb6800 - fffb6fff + * USB Host fffba000 - fffba7ff + * FAC fffba800 - fffbafff + * HDQ/1-Wire fffbc000 - fffbc7ff + * TIPB switches fffbc800 - fffbcfff + * Mailbox fffcf000 - fffcf7ff + * Local bus IF fffec100 - fffec1ff + * Local bus MMU fffec200 - fffec2ff + * DSP MMU fffed200 - fffed2ff */ =20 omap_setup_dsp_mapping(system_memory, omap15xx_dsp_mm); diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c index 1d89a202bb9..5d4a31b7aed 100644 --- a/hw/arm/omap_sx1.c +++ b/hw/arm/omap_sx1.c @@ -1,7 +1,7 @@ /* omap_sx1.c Support for the Siemens SX1 smartphone emulation. * * Copyright (C) 2008 - * Jean-Christophe PLAGNIOL-VILLARD + * Jean-Christophe PLAGNIOL-VILLARD * Copyright (C) 2007 Vladimir Ananiev * * based on PalmOne's (TM) PDAs support (palm.c) diff --git a/hw/dma/omap_dma.c b/hw/dma/omap_dma.c index 9a8c3c34a07..101f91f4a33 100644 --- a/hw/dma/omap_dma.c +++ b/hw/dma/omap_dma.c @@ -131,9 +131,9 @@ struct omap_dma_s { #define LAST_FRAME_INTR (1 << 4) #define END_BLOCK_INTR (1 << 5) #define SYNC (1 << 6) -#define END_PKT_INTR (1 << 7) -#define TRANS_ERR_INTR (1 << 8) -#define MISALIGN_INTR (1 << 11) +#define END_PKT_INTR (1 << 7) +#define TRANS_ERR_INTR (1 << 8) +#define MISALIGN_INTR (1 << 11) =20 static inline void omap_dma_interrupts_update(struct omap_dma_s *s) { @@ -526,12 +526,12 @@ static void omap_dma_transfer_setup(struct soc_dma_ch= _s *dma) =20 /* Check all the conditions that terminate the transfer starting * with those that can occur the soonest. */ -#define INTR_CHECK(cond, id, nelements) \ - if (cond) { \ - elements[id] =3D nelements; \ - if (elements[id] < min_elems) \ - min_elems =3D elements[id]; \ - } else \ +#define INTR_CHECK(cond, id, nelements) \ + if (cond) { \ + elements[id] =3D nelements; \ + if (elements[id] < min_elems) \ + min_elems =3D elements[id]; \ + } else \ elements[id] =3D INT_MAX; =20 /* Elements */ @@ -740,7 +740,7 @@ static int omap_dma_ch_reg_read(struct omap_dma_s *s, struct omap_dma_channel_s *ch, int reg, uint16_t *value) { switch (reg) { - case 0x00: /* SYS_DMA_CSDP_CH0 */ + case 0x00: /* SYS_DMA_CSDP_CH0 */ *value =3D (ch->burst[1] << 14) | (ch->pack[1] << 13) | (ch->port[1] << 9) | @@ -750,9 +750,9 @@ static int omap_dma_ch_reg_read(struct omap_dma_s *s, (ch->data_type >> 1); break; =20 - case 0x02: /* SYS_DMA_CCR_CH0 */ + case 0x02: /* SYS_DMA_CCR_CH0 */ if (s->model <=3D omap_dma_3_1) - *value =3D 0 << 10; /* FIFO_FLUSH reads as 0 */ + *value =3D 0 << 10; /* FIFO_FLUSH reads as 0 */ else *value =3D ch->omap_3_1_compatible_disable << 10; *value |=3D (ch->mode[1] << 14) | @@ -765,11 +765,11 @@ static int omap_dma_ch_reg_read(struct omap_dma_s *s, (ch->fs << 5) | ch->sync; break; =20 - case 0x04: /* SYS_DMA_CICR_CH0 */ + case 0x04: /* SYS_DMA_CICR_CH0 */ *value =3D ch->interrupts; break; =20 - case 0x06: /* SYS_DMA_CSR_CH0 */ + case 0x06: /* SYS_DMA_CSR_CH0 */ *value =3D ch->status; ch->status &=3D SYNC; if (!ch->omap_3_1_compatible_disable && ch->sibling) { @@ -779,77 +779,77 @@ static int omap_dma_ch_reg_read(struct omap_dma_s *s, qemu_irq_lower(ch->irq); break; =20 - case 0x08: /* SYS_DMA_CSSA_L_CH0 */ + case 0x08: /* SYS_DMA_CSSA_L_CH0 */ *value =3D ch->addr[0] & 0x0000ffff; break; =20 - case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ + case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ *value =3D ch->addr[0] >> 16; break; =20 - case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ + case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ *value =3D ch->addr[1] & 0x0000ffff; break; =20 - case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ + case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ *value =3D ch->addr[1] >> 16; break; =20 - case 0x10: /* SYS_DMA_CEN_CH0 */ + case 0x10: /* SYS_DMA_CEN_CH0 */ *value =3D ch->elements; break; =20 - case 0x12: /* SYS_DMA_CFN_CH0 */ + case 0x12: /* SYS_DMA_CFN_CH0 */ *value =3D ch->frames; break; =20 - case 0x14: /* SYS_DMA_CFI_CH0 */ + case 0x14: /* SYS_DMA_CFI_CH0 */ *value =3D ch->frame_index[0]; break; =20 - case 0x16: /* SYS_DMA_CEI_CH0 */ + case 0x16: /* SYS_DMA_CEI_CH0 */ *value =3D ch->element_index[0]; break; =20 - case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */ + case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */ if (ch->omap_3_1_compatible_disable) - *value =3D ch->active_set.src & 0xffff; /* CSAC */ + *value =3D ch->active_set.src & 0xffff; /* CSAC */ else *value =3D ch->cpc; break; =20 - case 0x1a: /* DMA_CDAC */ - *value =3D ch->active_set.dest & 0xffff; /* CDAC */ + case 0x1a: /* DMA_CDAC */ + *value =3D ch->active_set.dest & 0xffff; /* CDAC */ break; =20 - case 0x1c: /* DMA_CDEI */ + case 0x1c: /* DMA_CDEI */ *value =3D ch->element_index[1]; break; =20 - case 0x1e: /* DMA_CDFI */ + case 0x1e: /* DMA_CDFI */ *value =3D ch->frame_index[1]; break; =20 - case 0x20: /* DMA_COLOR_L */ + case 0x20: /* DMA_COLOR_L */ *value =3D ch->color & 0xffff; break; =20 - case 0x22: /* DMA_COLOR_U */ + case 0x22: /* DMA_COLOR_U */ *value =3D ch->color >> 16; break; =20 - case 0x24: /* DMA_CCR2 */ + case 0x24: /* DMA_CCR2 */ *value =3D (ch->bs << 2) | (ch->transparent_copy << 1) | ch->constant_fill; break; =20 - case 0x28: /* DMA_CLNK_CTRL */ + case 0x28: /* DMA_CLNK_CTRL */ *value =3D (ch->link_enabled << 15) | (ch->link_next_ch & 0xf); break; =20 - case 0x2a: /* DMA_LCH_CTRL */ + case 0x2a: /* DMA_LCH_CTRL */ *value =3D (ch->interleave_disabled << 15) | ch->type; break; @@ -864,7 +864,7 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s, struct omap_dma_channel_s *ch, int reg, uint16_t value) { switch (reg) { - case 0x00: /* SYS_DMA_CSDP_CH0 */ + case 0x00: /* SYS_DMA_CSDP_CH0 */ ch->burst[1] =3D (value & 0xc000) >> 14; ch->pack[1] =3D (value & 0x2000) >> 13; ch->port[1] =3D (enum omap_dma_port) ((value & 0x1e00) >> 9); @@ -887,7 +887,7 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s, } break; =20 - case 0x02: /* SYS_DMA_CCR_CH0 */ + case 0x02: /* SYS_DMA_CCR_CH0 */ ch->mode[1] =3D (omap_dma_addressing_t) ((value & 0xc000) >> 14); ch->mode[0] =3D (omap_dma_addressing_t) ((value & 0x3000) >> 12); ch->end_prog =3D (value & 0x0800) >> 11; @@ -909,88 +909,88 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s, =20 break; =20 - case 0x04: /* SYS_DMA_CICR_CH0 */ + case 0x04: /* SYS_DMA_CICR_CH0 */ ch->interrupts =3D value & 0x3f; break; =20 - case 0x06: /* SYS_DMA_CSR_CH0 */ + case 0x06: /* SYS_DMA_CSR_CH0 */ OMAP_RO_REG((hwaddr) reg); break; =20 - case 0x08: /* SYS_DMA_CSSA_L_CH0 */ + case 0x08: /* SYS_DMA_CSSA_L_CH0 */ ch->addr[0] &=3D 0xffff0000; ch->addr[0] |=3D value; break; =20 - case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ + case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ ch->addr[0] &=3D 0x0000ffff; ch->addr[0] |=3D (uint32_t) value << 16; break; =20 - case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ + case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ ch->addr[1] &=3D 0xffff0000; ch->addr[1] |=3D value; break; =20 - case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ + case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ ch->addr[1] &=3D 0x0000ffff; ch->addr[1] |=3D (uint32_t) value << 16; break; =20 - case 0x10: /* SYS_DMA_CEN_CH0 */ + case 0x10: /* SYS_DMA_CEN_CH0 */ ch->elements =3D value; break; =20 - case 0x12: /* SYS_DMA_CFN_CH0 */ + case 0x12: /* SYS_DMA_CFN_CH0 */ ch->frames =3D value; break; =20 - case 0x14: /* SYS_DMA_CFI_CH0 */ + case 0x14: /* SYS_DMA_CFI_CH0 */ ch->frame_index[0] =3D (int16_t) value; break; =20 - case 0x16: /* SYS_DMA_CEI_CH0 */ + case 0x16: /* SYS_DMA_CEI_CH0 */ ch->element_index[0] =3D (int16_t) value; break; =20 - case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */ + case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */ OMAP_RO_REG((hwaddr) reg); break; =20 - case 0x1c: /* DMA_CDEI */ + case 0x1c: /* DMA_CDEI */ ch->element_index[1] =3D (int16_t) value; break; =20 - case 0x1e: /* DMA_CDFI */ + case 0x1e: /* DMA_CDFI */ ch->frame_index[1] =3D (int16_t) value; break; =20 - case 0x20: /* DMA_COLOR_L */ + case 0x20: /* DMA_COLOR_L */ ch->color &=3D 0xffff0000; ch->color |=3D value; break; =20 - case 0x22: /* DMA_COLOR_U */ + case 0x22: /* DMA_COLOR_U */ ch->color &=3D 0xffff; ch->color |=3D (uint32_t)value << 16; break; =20 - case 0x24: /* DMA_CCR2 */ + case 0x24: /* DMA_CCR2 */ ch->bs =3D (value >> 2) & 0x1; ch->transparent_copy =3D (value >> 1) & 0x1; ch->constant_fill =3D value & 0x1; break; =20 - case 0x28: /* DMA_CLNK_CTRL */ + case 0x28: /* DMA_CLNK_CTRL */ ch->link_enabled =3D (value >> 15) & 0x1; - if (value & (1 << 14)) { /* Stop_Lnk */ + if (value & (1 << 14)) { /* Stop_Lnk */ ch->link_enabled =3D 0; omap_dma_disable_channel(s, ch); } ch->link_next_ch =3D value & 0x1f; break; =20 - case 0x2a: /* DMA_LCH_CTRL */ + case 0x2a: /* DMA_LCH_CTRL */ ch->interleave_disabled =3D (value >> 15) & 0x1; ch->type =3D value & 0xf; break; @@ -1005,7 +1005,7 @@ static int omap_dma_3_2_lcd_write(struct omap_dma_lcd= _channel_s *s, int offset, uint16_t value) { switch (offset) { - case 0xbc0: /* DMA_LCD_CSDP */ + case 0xbc0: /* DMA_LCD_CSDP */ s->brust_f2 =3D (value >> 14) & 0x3; s->pack_f2 =3D (value >> 13) & 0x1; s->data_type_f2 =3D (1 << ((value >> 11) & 0x3)); @@ -1014,7 +1014,7 @@ static int omap_dma_3_2_lcd_write(struct omap_dma_lcd= _channel_s *s, int offset, s->data_type_f1 =3D (1 << ((value >> 0) & 0x3)); break; =20 - case 0xbc2: /* DMA_LCD_CCR */ + case 0xbc2: /* DMA_LCD_CCR */ s->mode_f2 =3D (value >> 14) & 0x3; s->mode_f1 =3D (value >> 12) & 0x3; s->end_prog =3D (value >> 11) & 0x1; @@ -1026,7 +1026,7 @@ static int omap_dma_3_2_lcd_write(struct omap_dma_lcd= _channel_s *s, int offset, s->bs =3D (value >> 4) & 0x1; break; =20 - case 0xbc4: /* DMA_LCD_CTRL */ + case 0xbc4: /* DMA_LCD_CTRL */ s->dst =3D (value >> 8) & 0x1; s->src =3D ((value >> 6) & 0x3) << 1; s->condition =3D 0; @@ -1035,91 +1035,91 @@ static int omap_dma_3_2_lcd_write(struct omap_dma_l= cd_channel_s *s, int offset, s->dual =3D value & 1; break; =20 - case 0xbc8: /* TOP_B1_L */ + case 0xbc8: /* TOP_B1_L */ s->src_f1_top &=3D 0xffff0000; s->src_f1_top |=3D 0x0000ffff & value; break; =20 - case 0xbca: /* TOP_B1_U */ + case 0xbca: /* TOP_B1_U */ s->src_f1_top &=3D 0x0000ffff; s->src_f1_top |=3D (uint32_t)value << 16; break; =20 - case 0xbcc: /* BOT_B1_L */ + case 0xbcc: /* BOT_B1_L */ s->src_f1_bottom &=3D 0xffff0000; s->src_f1_bottom |=3D 0x0000ffff & value; break; =20 - case 0xbce: /* BOT_B1_U */ + case 0xbce: /* BOT_B1_U */ s->src_f1_bottom &=3D 0x0000ffff; s->src_f1_bottom |=3D (uint32_t) value << 16; break; =20 - case 0xbd0: /* TOP_B2_L */ + case 0xbd0: /* TOP_B2_L */ s->src_f2_top &=3D 0xffff0000; s->src_f2_top |=3D 0x0000ffff & value; break; =20 - case 0xbd2: /* TOP_B2_U */ + case 0xbd2: /* TOP_B2_U */ s->src_f2_top &=3D 0x0000ffff; s->src_f2_top |=3D (uint32_t) value << 16; break; =20 - case 0xbd4: /* BOT_B2_L */ + case 0xbd4: /* BOT_B2_L */ s->src_f2_bottom &=3D 0xffff0000; s->src_f2_bottom |=3D 0x0000ffff & value; break; =20 - case 0xbd6: /* BOT_B2_U */ + case 0xbd6: /* BOT_B2_U */ s->src_f2_bottom &=3D 0x0000ffff; s->src_f2_bottom |=3D (uint32_t) value << 16; break; =20 - case 0xbd8: /* DMA_LCD_SRC_EI_B1 */ + case 0xbd8: /* DMA_LCD_SRC_EI_B1 */ s->element_index_f1 =3D value; break; =20 - case 0xbda: /* DMA_LCD_SRC_FI_B1_L */ + case 0xbda: /* DMA_LCD_SRC_FI_B1_L */ s->frame_index_f1 &=3D 0xffff0000; s->frame_index_f1 |=3D 0x0000ffff & value; break; =20 - case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */ + case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */ s->frame_index_f1 &=3D 0x0000ffff; s->frame_index_f1 |=3D (uint32_t) value << 16; break; =20 - case 0xbdc: /* DMA_LCD_SRC_EI_B2 */ + case 0xbdc: /* DMA_LCD_SRC_EI_B2 */ s->element_index_f2 =3D value; break; =20 - case 0xbde: /* DMA_LCD_SRC_FI_B2_L */ + case 0xbde: /* DMA_LCD_SRC_FI_B2_L */ s->frame_index_f2 &=3D 0xffff0000; s->frame_index_f2 |=3D 0x0000ffff & value; break; =20 - case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */ + case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */ s->frame_index_f2 &=3D 0x0000ffff; s->frame_index_f2 |=3D (uint32_t) value << 16; break; =20 - case 0xbe0: /* DMA_LCD_SRC_EN_B1 */ + case 0xbe0: /* DMA_LCD_SRC_EN_B1 */ s->elements_f1 =3D value; break; =20 - case 0xbe4: /* DMA_LCD_SRC_FN_B1 */ + case 0xbe4: /* DMA_LCD_SRC_FN_B1 */ s->frames_f1 =3D value; break; =20 - case 0xbe2: /* DMA_LCD_SRC_EN_B2 */ + case 0xbe2: /* DMA_LCD_SRC_EN_B2 */ s->elements_f2 =3D value; break; =20 - case 0xbe6: /* DMA_LCD_SRC_FN_B2 */ + case 0xbe6: /* DMA_LCD_SRC_FN_B2 */ s->frames_f2 =3D value; break; =20 - case 0xbea: /* DMA_LCD_LCH_CTRL */ + case 0xbea: /* DMA_LCD_LCH_CTRL */ s->lch_type =3D value & 0xf; break; =20 @@ -1133,7 +1133,7 @@ static int omap_dma_3_2_lcd_read(struct omap_dma_lcd_= channel_s *s, int offset, uint16_t *ret) { switch (offset) { - case 0xbc0: /* DMA_LCD_CSDP */ + case 0xbc0: /* DMA_LCD_CSDP */ *ret =3D (s->brust_f2 << 14) | (s->pack_f2 << 13) | ((s->data_type_f2 >> 1) << 11) | @@ -1142,7 +1142,7 @@ static int omap_dma_3_2_lcd_read(struct omap_dma_lcd_= channel_s *s, int offset, ((s->data_type_f1 >> 1) << 0); break; =20 - case 0xbc2: /* DMA_LCD_CCR */ + case 0xbc2: /* DMA_LCD_CCR */ *ret =3D (s->mode_f2 << 14) | (s->mode_f1 << 12) | (s->end_prog << 11) | @@ -1154,7 +1154,7 @@ static int omap_dma_3_2_lcd_read(struct omap_dma_lcd_= channel_s *s, int offset, (s->bs << 4); break; =20 - case 0xbc4: /* DMA_LCD_CTRL */ + case 0xbc4: /* DMA_LCD_CTRL */ qemu_irq_lower(s->irq); *ret =3D (s->dst << 8) | ((s->src & 0x6) << 5) | @@ -1163,79 +1163,79 @@ static int omap_dma_3_2_lcd_read(struct omap_dma_lc= d_channel_s *s, int offset, s->dual; break; =20 - case 0xbc8: /* TOP_B1_L */ + case 0xbc8: /* TOP_B1_L */ *ret =3D s->src_f1_top & 0xffff; break; =20 - case 0xbca: /* TOP_B1_U */ + case 0xbca: /* TOP_B1_U */ *ret =3D s->src_f1_top >> 16; break; =20 - case 0xbcc: /* BOT_B1_L */ + case 0xbcc: /* BOT_B1_L */ *ret =3D s->src_f1_bottom & 0xffff; break; =20 - case 0xbce: /* BOT_B1_U */ + case 0xbce: /* BOT_B1_U */ *ret =3D s->src_f1_bottom >> 16; break; =20 - case 0xbd0: /* TOP_B2_L */ + case 0xbd0: /* TOP_B2_L */ *ret =3D s->src_f2_top & 0xffff; break; =20 - case 0xbd2: /* TOP_B2_U */ + case 0xbd2: /* TOP_B2_U */ *ret =3D s->src_f2_top >> 16; break; =20 - case 0xbd4: /* BOT_B2_L */ + case 0xbd4: /* BOT_B2_L */ *ret =3D s->src_f2_bottom & 0xffff; break; =20 - case 0xbd6: /* BOT_B2_U */ + case 0xbd6: /* BOT_B2_U */ *ret =3D s->src_f2_bottom >> 16; break; =20 - case 0xbd8: /* DMA_LCD_SRC_EI_B1 */ + case 0xbd8: /* DMA_LCD_SRC_EI_B1 */ *ret =3D s->element_index_f1; break; =20 - case 0xbda: /* DMA_LCD_SRC_FI_B1_L */ + case 0xbda: /* DMA_LCD_SRC_FI_B1_L */ *ret =3D s->frame_index_f1 & 0xffff; break; =20 - case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */ + case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */ *ret =3D s->frame_index_f1 >> 16; break; =20 - case 0xbdc: /* DMA_LCD_SRC_EI_B2 */ + case 0xbdc: /* DMA_LCD_SRC_EI_B2 */ *ret =3D s->element_index_f2; break; =20 - case 0xbde: /* DMA_LCD_SRC_FI_B2_L */ + case 0xbde: /* DMA_LCD_SRC_FI_B2_L */ *ret =3D s->frame_index_f2 & 0xffff; break; =20 - case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */ + case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */ *ret =3D s->frame_index_f2 >> 16; break; =20 - case 0xbe0: /* DMA_LCD_SRC_EN_B1 */ + case 0xbe0: /* DMA_LCD_SRC_EN_B1 */ *ret =3D s->elements_f1; break; =20 - case 0xbe4: /* DMA_LCD_SRC_FN_B1 */ + case 0xbe4: /* DMA_LCD_SRC_FN_B1 */ *ret =3D s->frames_f1; break; =20 - case 0xbe2: /* DMA_LCD_SRC_EN_B2 */ + case 0xbe2: /* DMA_LCD_SRC_EN_B2 */ *ret =3D s->elements_f2; break; =20 - case 0xbe6: /* DMA_LCD_SRC_FN_B2 */ + case 0xbe6: /* DMA_LCD_SRC_FN_B2 */ *ret =3D s->frames_f2; break; =20 - case 0xbea: /* DMA_LCD_LCH_CTRL */ + case 0xbea: /* DMA_LCD_LCH_CTRL */ *ret =3D s->lch_type; break; =20 @@ -1249,7 +1249,7 @@ static int omap_dma_3_1_lcd_write(struct omap_dma_lcd= _channel_s *s, int offset, uint16_t value) { switch (offset) { - case 0x300: /* SYS_DMA_LCD_CTRL */ + case 0x300: /* SYS_DMA_LCD_CTRL */ s->src =3D (value & 0x40) ? imif : emiff; s->condition =3D 0; /* Assume no bus errors and thus no BUS_ERROR irq bits. */ @@ -1257,42 +1257,42 @@ static int omap_dma_3_1_lcd_write(struct omap_dma_l= cd_channel_s *s, int offset, s->dual =3D value & 1; break; =20 - case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ + case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ s->src_f1_top &=3D 0xffff0000; s->src_f1_top |=3D 0x0000ffff & value; break; =20 - case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ + case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ s->src_f1_top &=3D 0x0000ffff; s->src_f1_top |=3D (uint32_t)value << 16; break; =20 - case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ + case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ s->src_f1_bottom &=3D 0xffff0000; s->src_f1_bottom |=3D 0x0000ffff & value; break; =20 - case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ + case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ s->src_f1_bottom &=3D 0x0000ffff; s->src_f1_bottom |=3D (uint32_t)value << 16; break; =20 - case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ + case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ s->src_f2_top &=3D 0xffff0000; s->src_f2_top |=3D 0x0000ffff & value; break; =20 - case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ + case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ s->src_f2_top &=3D 0x0000ffff; s->src_f2_top |=3D (uint32_t)value << 16; break; =20 - case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ + case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ s->src_f2_bottom &=3D 0xffff0000; s->src_f2_bottom |=3D 0x0000ffff & value; break; =20 - case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ + case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ s->src_f2_bottom &=3D 0x0000ffff; s->src_f2_bottom |=3D (uint32_t)value << 16; break; @@ -1309,7 +1309,7 @@ static int omap_dma_3_1_lcd_read(struct omap_dma_lcd_= channel_s *s, int offset, int i; =20 switch (offset) { - case 0x300: /* SYS_DMA_LCD_CTRL */ + case 0x300: /* SYS_DMA_LCD_CTRL */ i =3D s->condition; s->condition =3D 0; qemu_irq_lower(s->irq); @@ -1317,35 +1317,35 @@ static int omap_dma_3_1_lcd_read(struct omap_dma_lc= d_channel_s *s, int offset, (s->interrupts << 1) | s->dual; break; =20 - case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ + case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ *ret =3D s->src_f1_top & 0xffff; break; =20 - case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ + case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ *ret =3D s->src_f1_top >> 16; break; =20 - case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ + case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ *ret =3D s->src_f1_bottom & 0xffff; break; =20 - case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ + case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ *ret =3D s->src_f1_bottom >> 16; break; =20 - case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ + case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ *ret =3D s->src_f2_top & 0xffff; break; =20 - case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ + case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ *ret =3D s->src_f2_top >> 16; break; =20 - case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ + case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ *ret =3D s->src_f2_bottom & 0xffff; break; =20 - case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ + case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ *ret =3D s->src_f2_bottom >> 16; break; =20 @@ -1358,18 +1358,18 @@ static int omap_dma_3_1_lcd_read(struct omap_dma_lc= d_channel_s *s, int offset, static int omap_dma_sys_write(struct omap_dma_s *s, int offset, uint16_t v= alue) { switch (offset) { - case 0x400: /* SYS_DMA_GCR */ + case 0x400: /* SYS_DMA_GCR */ s->gcr =3D value; break; =20 - case 0x404: /* DMA_GSCR */ + case 0x404: /* DMA_GSCR */ if (value & 0x8) omap_dma_disable_3_1_mapping(s); else omap_dma_enable_3_1_mapping(s); break; =20 - case 0x408: /* DMA_GRST */ + case 0x408: /* DMA_GRST */ if (value & 0x1) omap_dma_reset(s->dma); break; @@ -1384,57 +1384,57 @@ static int omap_dma_sys_read(struct omap_dma_s *s, = int offset, uint16_t *ret) { switch (offset) { - case 0x400: /* SYS_DMA_GCR */ + case 0x400: /* SYS_DMA_GCR */ *ret =3D s->gcr; break; =20 - case 0x404: /* DMA_GSCR */ + case 0x404: /* DMA_GSCR */ *ret =3D s->omap_3_1_mapping_disabled << 3; break; =20 - case 0x408: /* DMA_GRST */ + case 0x408: /* DMA_GRST */ *ret =3D 0; break; =20 - case 0x442: /* DMA_HW_ID */ - case 0x444: /* DMA_PCh2_ID */ - case 0x446: /* DMA_PCh0_ID */ - case 0x448: /* DMA_PCh1_ID */ - case 0x44a: /* DMA_PChG_ID */ - case 0x44c: /* DMA_PChD_ID */ + case 0x442: /* DMA_HW_ID */ + case 0x444: /* DMA_PCh2_ID */ + case 0x446: /* DMA_PCh0_ID */ + case 0x448: /* DMA_PCh1_ID */ + case 0x44a: /* DMA_PChG_ID */ + case 0x44c: /* DMA_PChD_ID */ *ret =3D 1; break; =20 - case 0x44e: /* DMA_CAPS_0_U */ + case 0x44e: /* DMA_CAPS_0_U */ *ret =3D (s->caps[0] >> 16) & 0xffff; break; - case 0x450: /* DMA_CAPS_0_L */ + case 0x450: /* DMA_CAPS_0_L */ *ret =3D (s->caps[0] >> 0) & 0xffff; break; =20 - case 0x452: /* DMA_CAPS_1_U */ + case 0x452: /* DMA_CAPS_1_U */ *ret =3D (s->caps[1] >> 16) & 0xffff; break; - case 0x454: /* DMA_CAPS_1_L */ + case 0x454: /* DMA_CAPS_1_L */ *ret =3D (s->caps[1] >> 0) & 0xffff; break; =20 - case 0x456: /* DMA_CAPS_2 */ + case 0x456: /* DMA_CAPS_2 */ *ret =3D s->caps[2]; break; =20 - case 0x458: /* DMA_CAPS_3 */ + case 0x458: /* DMA_CAPS_3 */ *ret =3D s->caps[3]; break; =20 - case 0x45a: /* DMA_CAPS_4 */ + case 0x45a: /* DMA_CAPS_4 */ *ret =3D s->caps[4]; break; =20 - case 0x460: /* DMA_PCh2_SR */ - case 0x480: /* DMA_PCh0_SR */ - case 0x482: /* DMA_PCh1_SR */ - case 0x4c0: /* DMA_PChD_SR_0 */ + case 0x460: /* DMA_PCh2_SR */ + case 0x480: /* DMA_PCh0_SR */ + case 0x482: /* DMA_PCh1_SR */ + case 0x4c0: /* DMA_PChD_SR_0 */ qemu_log_mask(LOG_UNIMP, "%s: Physical Channel Status Registers not implement= ed\n", __func__); @@ -1582,38 +1582,38 @@ static void omap_dma_setcaps(struct omap_dma_s *s) case omap_dma_3_2: /* XXX Only available for sDMA */ s->caps[0] =3D - (1 << 19) | /* Constant Fill Capability */ - (1 << 18); /* Transparent BLT Capability */ + (1 << 19) | /* Constant Fill Capability */ + (1 << 18); /* Transparent BLT Capability */ s->caps[1] =3D - (1 << 1); /* 1-bit palettized capability (DMA 3.2 only) */ + (1 << 1); /* 1-bit palettized capability (DMA 3.2 only) = */ s->caps[2] =3D - (1 << 8) | /* SEPARATE_SRC_AND_DST_INDEX_CPBLTY */ - (1 << 7) | /* DST_DOUBLE_INDEX_ADRS_CPBLTY */ - (1 << 6) | /* DST_SINGLE_INDEX_ADRS_CPBLTY */ - (1 << 5) | /* DST_POST_INCRMNT_ADRS_CPBLTY */ - (1 << 4) | /* DST_CONST_ADRS_CPBLTY */ - (1 << 3) | /* SRC_DOUBLE_INDEX_ADRS_CPBLTY */ - (1 << 2) | /* SRC_SINGLE_INDEX_ADRS_CPBLTY */ - (1 << 1) | /* SRC_POST_INCRMNT_ADRS_CPBLTY */ - (1 << 0); /* SRC_CONST_ADRS_CPBLTY */ + (1 << 8) | /* SEPARATE_SRC_AND_DST_INDEX_CPBLTY */ + (1 << 7) | /* DST_DOUBLE_INDEX_ADRS_CPBLTY */ + (1 << 6) | /* DST_SINGLE_INDEX_ADRS_CPBLTY */ + (1 << 5) | /* DST_POST_INCRMNT_ADRS_CPBLTY */ + (1 << 4) | /* DST_CONST_ADRS_CPBLTY */ + (1 << 3) | /* SRC_DOUBLE_INDEX_ADRS_CPBLTY */ + (1 << 2) | /* SRC_SINGLE_INDEX_ADRS_CPBLTY */ + (1 << 1) | /* SRC_POST_INCRMNT_ADRS_CPBLTY */ + (1 << 0); /* SRC_CONST_ADRS_CPBLTY */ s->caps[3] =3D - (1 << 6) | /* BLOCK_SYNCHR_CPBLTY (DMA 4 only) */ - (1 << 7) | /* PKT_SYNCHR_CPBLTY (DMA 4 only) */ - (1 << 5) | /* CHANNEL_CHAINING_CPBLTY */ - (1 << 4) | /* LCh_INTERLEAVE_CPBLTY */ - (1 << 3) | /* AUTOINIT_REPEAT_CPBLTY (DMA 3.2 only) */ - (1 << 2) | /* AUTOINIT_ENDPROG_CPBLTY (DMA 3.2 only) */ - (1 << 1) | /* FRAME_SYNCHR_CPBLTY */ - (1 << 0); /* ELMNT_SYNCHR_CPBLTY */ + (1 << 6) | /* BLOCK_SYNCHR_CPBLTY (DMA 4 only) */ + (1 << 7) | /* PKT_SYNCHR_CPBLTY (DMA 4 only) */ + (1 << 5) | /* CHANNEL_CHAINING_CPBLTY */ + (1 << 4) | /* LCh_INTERLEAVE_CPBLTY */ + (1 << 3) | /* AUTOINIT_REPEAT_CPBLTY (DMA 3.2 only) */ + (1 << 2) | /* AUTOINIT_ENDPROG_CPBLTY (DMA 3.2 only) */ + (1 << 1) | /* FRAME_SYNCHR_CPBLTY */ + (1 << 0); /* ELMNT_SYNCHR_CPBLTY */ s->caps[4] =3D - (1 << 7) | /* PKT_INTERRUPT_CPBLTY (DMA 4 only) */ - (1 << 6) | /* SYNC_STATUS_CPBLTY */ - (1 << 5) | /* BLOCK_INTERRUPT_CPBLTY */ - (1 << 4) | /* LAST_FRAME_INTERRUPT_CPBLTY */ - (1 << 3) | /* FRAME_INTERRUPT_CPBLTY */ - (1 << 2) | /* HALF_FRAME_INTERRUPT_CPBLTY */ - (1 << 1) | /* EVENT_DROP_INTERRUPT_CPBLTY */ - (1 << 0); /* TIMEOUT_INTERRUPT_CPBLTY (DMA 3.2 only) */ + (1 << 7) | /* PKT_INTERRUPT_CPBLTY (DMA 4 only) */ + (1 << 6) | /* SYNC_STATUS_CPBLTY */ + (1 << 5) | /* BLOCK_INTERRUPT_CPBLTY */ + (1 << 4) | /* LAST_FRAME_INTERRUPT_CPBLTY */ + (1 << 3) | /* FRAME_INTERRUPT_CPBLTY */ + (1 << 2) | /* HALF_FRAME_INTERRUPT_CPBLTY */ + (1 << 1) | /* EVENT_DROP_INTERRUPT_CPBLTY */ + (1 << 0); /* TIMEOUT_INTERRUPT_CPBLTY (DMA 3.2 only) */ break; } } diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c index 61ea7862afe..f27806b774a 100644 --- a/hw/gpio/omap_gpio.c +++ b/hw/gpio/omap_gpio.c @@ -80,25 +80,25 @@ static uint64_t omap_gpio_read(void *opaque, hwaddr add= r, } =20 switch (offset) { - case 0x00: /* DATA_INPUT */ + case 0x00: /* DATA_INPUT */ return s->inputs & s->pins; =20 - case 0x04: /* DATA_OUTPUT */ + case 0x04: /* DATA_OUTPUT */ return s->outputs; =20 - case 0x08: /* DIRECTION_CONTROL */ + case 0x08: /* DIRECTION_CONTROL */ return s->dir; =20 - case 0x0c: /* INTERRUPT_CONTROL */ + case 0x0c: /* INTERRUPT_CONTROL */ return s->edge; =20 - case 0x10: /* INTERRUPT_MASK */ + case 0x10: /* INTERRUPT_MASK */ return s->mask; =20 - case 0x14: /* INTERRUPT_STATUS */ + case 0x14: /* INTERRUPT_STATUS */ return s->ints; =20 - case 0x18: /* PIN_CONTROL (not in OMAP310) */ + case 0x18: /* PIN_CONTROL (not in OMAP310) */ OMAP_BAD_REG(addr); return s->pins; } @@ -121,11 +121,11 @@ static void omap_gpio_write(void *opaque, hwaddr addr, } =20 switch (offset) { - case 0x00: /* DATA_INPUT */ + case 0x00: /* DATA_INPUT */ OMAP_RO_REG(addr); return; =20 - case 0x04: /* DATA_OUTPUT */ + case 0x04: /* DATA_OUTPUT */ diff =3D (s->outputs ^ value) & ~s->dir; s->outputs =3D value; while ((ln =3D ctz32(diff)) !=3D 32) { @@ -135,7 +135,7 @@ static void omap_gpio_write(void *opaque, hwaddr addr, } break; =20 - case 0x08: /* DIRECTION_CONTROL */ + case 0x08: /* DIRECTION_CONTROL */ diff =3D s->outputs & (s->dir ^ value); s->dir =3D value; =20 @@ -147,21 +147,21 @@ static void omap_gpio_write(void *opaque, hwaddr addr, } break; =20 - case 0x0c: /* INTERRUPT_CONTROL */ + case 0x0c: /* INTERRUPT_CONTROL */ s->edge =3D value; break; =20 - case 0x10: /* INTERRUPT_MASK */ + case 0x10: /* INTERRUPT_MASK */ s->mask =3D value; break; =20 - case 0x14: /* INTERRUPT_STATUS */ + case 0x14: /* INTERRUPT_STATUS */ s->ints &=3D ~value; if (!s->ints) qemu_irq_lower(s->irq); break; =20 - case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */ + case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */ OMAP_BAD_REG(addr); s->pins =3D value; break; diff --git a/hw/i2c/omap_i2c.c b/hw/i2c/omap_i2c.c index 2e45266e74b..751bf748fd9 100644 --- a/hw/i2c/omap_i2c.c +++ b/hw/i2c/omap_i2c.c @@ -55,16 +55,16 @@ struct OMAPI2CState { uint16_t test; }; =20 -#define OMAP2_INTR_REV 0x34 -#define OMAP2_GC_REV 0x34 +#define OMAP2_INTR_REV 0x34 +#define OMAP2_GC_REV 0x34 =20 static void omap_i2c_interrupts_update(OMAPI2CState *s) { qemu_set_irq(s->irq, s->stat & s->mask); - if ((s->dma >> 15) & 1) /* RDMA_EN */ - qemu_set_irq(s->drq[0], (s->stat >> 3) & 1); /* RRDY */ - if ((s->dma >> 7) & 1) /* XDMA_EN */ - qemu_set_irq(s->drq[1], (s->stat >> 4) & 1); /* XRDY */ + if ((s->dma >> 15) & 1) /* RDMA_EN */ + qemu_set_irq(s->drq[0], (s->stat >> 3) & 1); /* RRDY */ + if ((s->dma >> 7) & 1) /* XDMA_EN */ + qemu_set_irq(s->drq[1], (s->stat >> 4) & 1); /* XRDY */ } =20 static void omap_i2c_fifo_run(OMAPI2CState *s) @@ -74,25 +74,25 @@ static void omap_i2c_fifo_run(OMAPI2CState *s) if (!i2c_bus_busy(s->bus)) return; =20 - if ((s->control >> 2) & 1) { /* RM */ - if ((s->control >> 1) & 1) { /* STP */ + if ((s->control >> 2) & 1) { /* RM */ + if ((s->control >> 1) & 1) { /* STP */ i2c_end_transfer(s->bus); - s->control &=3D ~(1 << 1); /* STP */ + s->control &=3D ~(1 << 1); /* STP */ s->count_cur =3D s->count; s->txlen =3D 0; - } else if ((s->control >> 9) & 1) { /* TRX */ + } else if ((s->control >> 9) & 1) { /* TRX */ while (ack && s->txlen) ack =3D (i2c_send(s->bus, (s->fifo >> ((-- s->txlen) << 3)) & 0xff) >=3D 0); - s->stat |=3D 1 << 4; /* XRDY */ + s->stat |=3D 1 << 4; /* XRDY */ } else { while (s->rxlen < 4) s->fifo |=3D i2c_recv(s->bus) << ((s->rxlen ++) << 3); - s->stat |=3D 1 << 3; /* RRDY */ + s->stat |=3D 1 << 3; /* RRDY */ } } else { - if ((s->control >> 9) & 1) { /* TRX */ + if ((s->control >> 9) & 1) { /* TRX */ while (ack && s->count_cur && s->txlen) { ack =3D (i2c_send(s->bus, (s->fifo >> ((-- s->txlen) << 3)) & @@ -100,12 +100,12 @@ static void omap_i2c_fifo_run(OMAPI2CState *s) s->count_cur --; } if (ack && s->count_cur) - s->stat |=3D 1 << 4; /* XRDY */ + s->stat |=3D 1 << 4; /* XRDY */ else - s->stat &=3D ~(1 << 4); /* XRDY */ + s->stat &=3D ~(1 << 4); /* XRDY */ if (!s->count_cur) { - s->stat |=3D 1 << 2; /* ARDY */ - s->control &=3D ~(1 << 10); /* MST */ + s->stat |=3D 1 << 2; /* ARDY */ + s->control &=3D ~(1 << 10); /* MST */ } } else { while (s->count_cur && s->rxlen < 4) { @@ -113,26 +113,26 @@ static void omap_i2c_fifo_run(OMAPI2CState *s) s->count_cur --; } if (s->rxlen) - s->stat |=3D 1 << 3; /* RRDY */ + s->stat |=3D 1 << 3; /* RRDY */ else - s->stat &=3D ~(1 << 3); /* RRDY */ + s->stat &=3D ~(1 << 3); /* RRDY */ } if (!s->count_cur) { - if ((s->control >> 1) & 1) { /* STP */ + if ((s->control >> 1) & 1) { /* STP */ i2c_end_transfer(s->bus); - s->control &=3D ~(1 << 1); /* STP */ + s->control &=3D ~(1 << 1); /* STP */ s->count_cur =3D s->count; s->txlen =3D 0; } else { - s->stat |=3D 1 << 2; /* ARDY */ - s->control &=3D ~(1 << 10); /* MST */ + s->stat |=3D 1 << 2; /* ARDY */ + s->control &=3D ~(1 << 10); /* MST */ } } } =20 - s->stat |=3D (!ack) << 1; /* NACK */ + s->stat |=3D (!ack) << 1; /* NACK */ if (!ack) - s->control &=3D ~(1 << 1); /* STP */ + s->control &=3D ~(1 << 1); /* STP */ } =20 static void omap_i2c_reset(DeviceState *dev) @@ -163,16 +163,16 @@ static uint32_t omap_i2c_read(void *opaque, hwaddr ad= dr) uint16_t ret; =20 switch (offset) { - case 0x00: /* I2C_REV */ - return s->revision; /* REV */ + case 0x00: /* I2C_REV */ + return s->revision; /* REV */ =20 - case 0x04: /* I2C_IE */ + case 0x04: /* I2C_IE */ return s->mask; =20 - case 0x08: /* I2C_STAT */ + case 0x08: /* I2C_STAT */ return s->stat | (i2c_bus_busy(s->bus) << 12); =20 - case 0x0c: /* I2C_IV */ + case 0x0c: /* I2C_IV */ if (s->revision >=3D OMAP2_INTR_REV) break; ret =3D ctz32(s->stat & s->mask); @@ -185,18 +185,18 @@ static uint32_t omap_i2c_read(void *opaque, hwaddr ad= dr) omap_i2c_interrupts_update(s); return ret; =20 - case 0x10: /* I2C_SYSS */ - return (s->control >> 15) & 1; /* I2C_EN */ + case 0x10: /* I2C_SYSS */ + return (s->control >> 15) & 1; /* I2C_EN */ =20 - case 0x14: /* I2C_BUF */ + case 0x14: /* I2C_BUF */ return s->dma; =20 - case 0x18: /* I2C_CNT */ - return s->count_cur; /* DCOUNT */ + case 0x18: /* I2C_CNT */ + return s->count_cur; /* DCOUNT */ =20 - case 0x1c: /* I2C_DATA */ + case 0x1c: /* I2C_DATA */ ret =3D 0; - if (s->control & (1 << 14)) { /* BE */ + if (s->control & (1 << 14)) { /* BE */ ret |=3D ((s->fifo >> 0) & 0xff) << 8; ret |=3D ((s->fifo >> 8) & 0xff) << 0; } else { @@ -204,7 +204,7 @@ static uint32_t omap_i2c_read(void *opaque, hwaddr addr) ret |=3D ((s->fifo >> 0) & 0xff) << 0; } if (s->rxlen =3D=3D 1) { - s->stat |=3D 1 << 15; /* SBD */ + s->stat |=3D 1 << 15; /* SBD */ s->rxlen =3D 0; } else if (s->rxlen > 1) { if (s->rxlen > 2) @@ -214,41 +214,41 @@ static uint32_t omap_i2c_read(void *opaque, hwaddr ad= dr) /* XXX: remote access (qualifier) error - what's that? */ } if (!s->rxlen) { - s->stat &=3D ~(1 << 3); /* RRDY */ - if (((s->control >> 10) & 1) && /* MST */ - ((~s->control >> 9) & 1)) { /* TRX */ - s->stat |=3D 1 << 2; /* ARDY */ - s->control &=3D ~(1 << 10); /* MST */ + s->stat &=3D ~(1 << 3); /* RRDY */ + if (((s->control >> 10) & 1) && /* MST */ + ((~s->control >> 9) & 1)) { /* TRX */ + s->stat |=3D 1 << 2; /* ARDY */ + s->control &=3D ~(1 << 10); /* MST */ } } - s->stat &=3D ~(1 << 11); /* ROVR */ + s->stat &=3D ~(1 << 11); /* ROVR */ omap_i2c_fifo_run(s); omap_i2c_interrupts_update(s); return ret; =20 - case 0x20: /* I2C_SYSC */ + case 0x20: /* I2C_SYSC */ return 0; =20 - case 0x24: /* I2C_CON */ + case 0x24: /* I2C_CON */ return s->control; =20 - case 0x28: /* I2C_OA */ + case 0x28: /* I2C_OA */ return s->addr[0]; =20 - case 0x2c: /* I2C_SA */ + case 0x2c: /* I2C_SA */ return s->addr[1]; =20 - case 0x30: /* I2C_PSC */ + case 0x30: /* I2C_PSC */ return s->divider; =20 - case 0x34: /* I2C_SCLL */ + case 0x34: /* I2C_SCLL */ return s->times[0]; =20 - case 0x38: /* I2C_SCLH */ + case 0x38: /* I2C_SCLH */ return s->times[1]; =20 - case 0x3c: /* I2C_SYSTEST */ - if (s->test & (1 << 15)) { /* ST_EN */ + case 0x3c: /* I2C_SYSTEST */ + if (s->test & (1 << 15)) { /* ST_EN */ s->test ^=3D 0xa; return s->test; } else @@ -267,17 +267,17 @@ static void omap_i2c_write(void *opaque, hwaddr addr, int nack; =20 switch (offset) { - case 0x00: /* I2C_REV */ - case 0x0c: /* I2C_IV */ - case 0x10: /* I2C_SYSS */ + case 0x00: /* I2C_REV */ + case 0x0c: /* I2C_IV */ + case 0x10: /* I2C_SYSS */ OMAP_RO_REG(addr); return; =20 - case 0x04: /* I2C_IE */ + case 0x04: /* I2C_IE */ s->mask =3D value & (s->revision < OMAP2_GC_REV ? 0x1f : 0x3f); break; =20 - case 0x08: /* I2C_STAT */ + case 0x08: /* I2C_STAT */ if (s->revision < OMAP2_INTR_REV) { OMAP_RO_REG(addr); return; @@ -288,40 +288,40 @@ static void omap_i2c_write(void *opaque, hwaddr addr, omap_i2c_interrupts_update(s); break; =20 - case 0x14: /* I2C_BUF */ + case 0x14: /* I2C_BUF */ s->dma =3D value & 0x8080; - if (value & (1 << 15)) /* RDMA_EN */ - s->mask &=3D ~(1 << 3); /* RRDY_IE */ - if (value & (1 << 7)) /* XDMA_EN */ - s->mask &=3D ~(1 << 4); /* XRDY_IE */ + if (value & (1 << 15)) /* RDMA_EN */ + s->mask &=3D ~(1 << 3); /* RRDY_IE */ + if (value & (1 << 7)) /* XDMA_EN */ + s->mask &=3D ~(1 << 4); /* XRDY_IE */ break; =20 - case 0x18: /* I2C_CNT */ - s->count =3D value; /* DCOUNT */ + case 0x18: /* I2C_CNT */ + s->count =3D value; /* DCOUNT */ break; =20 - case 0x1c: /* I2C_DATA */ + case 0x1c: /* I2C_DATA */ if (s->txlen > 2) { /* XXX: remote access (qualifier) error - what's that? */ break; } s->fifo <<=3D 16; s->txlen +=3D 2; - if (s->control & (1 << 14)) { /* BE */ + if (s->control & (1 << 14)) { /* BE */ s->fifo |=3D ((value >> 8) & 0xff) << 8; s->fifo |=3D ((value >> 0) & 0xff) << 0; } else { s->fifo |=3D ((value >> 0) & 0xff) << 8; s->fifo |=3D ((value >> 8) & 0xff) << 0; } - s->stat &=3D ~(1 << 10); /* XUDF */ + s->stat &=3D ~(1 << 10); /* XUDF */ if (s->txlen > 2) - s->stat &=3D ~(1 << 4); /* XRDY */ + s->stat &=3D ~(1 << 4); /* XRDY */ omap_i2c_fifo_run(s); omap_i2c_interrupts_update(s); break; =20 - case 0x20: /* I2C_SYSC */ + case 0x20: /* I2C_SYSC */ if (s->revision < OMAP2_INTR_REV) { OMAP_BAD_REG(addr); return; @@ -332,9 +332,9 @@ static void omap_i2c_write(void *opaque, hwaddr addr, } break; =20 - case 0x24: /* I2C_CON */ + case 0x24: /* I2C_CON */ s->control =3D value & 0xcf87; - if (~value & (1 << 15)) { /* I2C_EN */ + if (~value & (1 << 15)) { /* I2C_EN */ if (s->revision < OMAP2_INTR_REV) { omap_i2c_reset(DEVICE(s)); } @@ -351,14 +351,14 @@ static void omap_i2c_write(void *opaque, hwaddr addr, __func__); break; } - if ((value & (1 << 15)) && value & (1 << 0)) { /* STT */ - nack =3D !!i2c_start_transfer(s->bus, s->addr[1], /* SA */ - (~value >> 9) & 1); /* TRX */ - s->stat |=3D nack << 1; /* NACK */ - s->control &=3D ~(1 << 0); /* STT */ + if ((value & (1 << 15)) && value & (1 << 0)) { /* STT */ + nack =3D !!i2c_start_transfer(s->bus, s->addr[1], /* SA */ + (~value >> 9) & 1); /* TRX */ + s->stat |=3D nack << 1; /* NACK */ + s->control &=3D ~(1 << 0); /* STT */ s->fifo =3D 0; if (nack) - s->control &=3D ~(1 << 1); /* STP */ + s->control &=3D ~(1 << 1); /* STP */ else { s->count_cur =3D s->count; omap_i2c_fifo_run(s); @@ -367,34 +367,34 @@ static void omap_i2c_write(void *opaque, hwaddr addr, } break; =20 - case 0x28: /* I2C_OA */ + case 0x28: /* I2C_OA */ s->addr[0] =3D value & 0x3ff; break; =20 - case 0x2c: /* I2C_SA */ + case 0x2c: /* I2C_SA */ s->addr[1] =3D value & 0x3ff; break; =20 - case 0x30: /* I2C_PSC */ + case 0x30: /* I2C_PSC */ s->divider =3D value; break; =20 - case 0x34: /* I2C_SCLL */ + case 0x34: /* I2C_SCLL */ s->times[0] =3D value; break; =20 - case 0x38: /* I2C_SCLH */ + case 0x38: /* I2C_SCLH */ s->times[1] =3D value; break; =20 - case 0x3c: /* I2C_SYSTEST */ + case 0x3c: /* I2C_SYSTEST */ s->test =3D value & 0xf80f; - if (value & (1 << 11)) /* SBB */ + if (value & (1 << 11)) /* SBB */ if (s->revision >=3D OMAP2_INTR_REV) { s->stat |=3D 0x3f; omap_i2c_interrupts_update(s); } - if (value & (1 << 15)) { /* ST_EN */ + if (value & (1 << 15)) { /* ST_EN */ qemu_log_mask(LOG_UNIMP, "%s: System Test not supported\n", __func__); } @@ -413,7 +413,7 @@ static void omap_i2c_writeb(void *opaque, hwaddr addr, int offset =3D addr & OMAP_MPUI_REG_MASK; =20 switch (offset) { - case 0x1c: /* I2C_DATA */ + case 0x1c: /* I2C_DATA */ if (s->txlen > 2) { /* XXX: remote access (qualifier) error - what's that? */ break; @@ -421,9 +421,9 @@ static void omap_i2c_writeb(void *opaque, hwaddr addr, s->fifo <<=3D 8; s->txlen +=3D 1; s->fifo |=3D value & 0xff; - s->stat &=3D ~(1 << 10); /* XUDF */ + s->stat &=3D ~(1 << 10); /* XUDF */ if (s->txlen > 2) - s->stat &=3D ~(1 << 4); /* XRDY */ + s->stat &=3D ~(1 << 4); /* XRDY */ omap_i2c_fifo_run(s); omap_i2c_interrupts_update(s); break; diff --git a/hw/intc/omap_intc.c b/hw/intc/omap_intc.c index 9e8737be338..c61158bddd3 100644 --- a/hw/intc/omap_intc.c +++ b/hw/intc/omap_intc.c @@ -102,8 +102,8 @@ static inline void omap_inth_update(OMAPIntcState *s, i= nt is_fiq) } } =20 -#define INT_FALLING_EDGE 0 -#define INT_LOW_LEVEL 1 +#define INT_FALLING_EDGE 0 +#define INT_LOW_LEVEL 1 =20 static void omap_set_intr(void *opaque, int irq, int req) { @@ -142,13 +142,13 @@ static uint64_t omap_inth_read(void *opaque, hwaddr a= ddr, offset &=3D 0xff; =20 switch (offset) { - case 0x00: /* ITR */ + case 0x00: /* ITR */ return bank->irqs; =20 - case 0x04: /* MIR */ + case 0x04: /* MIR */ return bank->mask; =20 - case 0x10: /* SIR_IRQ_CODE */ + case 0x10: /* SIR_IRQ_CODE */ case 0x14: /* SIR_FIQ_CODE */ if (bank_no !=3D 0) break; @@ -159,49 +159,49 @@ static uint64_t omap_inth_read(void *opaque, hwaddr a= ddr, bank->irqs &=3D ~(1 << i); return line_no; =20 - case 0x18: /* CONTROL_REG */ + case 0x18: /* CONTROL_REG */ if (bank_no !=3D 0) break; return 0; =20 - case 0x1c: /* ILR0 */ - case 0x20: /* ILR1 */ - case 0x24: /* ILR2 */ - case 0x28: /* ILR3 */ - case 0x2c: /* ILR4 */ - case 0x30: /* ILR5 */ - case 0x34: /* ILR6 */ - case 0x38: /* ILR7 */ - case 0x3c: /* ILR8 */ - case 0x40: /* ILR9 */ - case 0x44: /* ILR10 */ - case 0x48: /* ILR11 */ - case 0x4c: /* ILR12 */ - case 0x50: /* ILR13 */ - case 0x54: /* ILR14 */ - case 0x58: /* ILR15 */ - case 0x5c: /* ILR16 */ - case 0x60: /* ILR17 */ - case 0x64: /* ILR18 */ - case 0x68: /* ILR19 */ - case 0x6c: /* ILR20 */ - case 0x70: /* ILR21 */ - case 0x74: /* ILR22 */ - case 0x78: /* ILR23 */ - case 0x7c: /* ILR24 */ - case 0x80: /* ILR25 */ - case 0x84: /* ILR26 */ - case 0x88: /* ILR27 */ - case 0x8c: /* ILR28 */ - case 0x90: /* ILR29 */ - case 0x94: /* ILR30 */ - case 0x98: /* ILR31 */ + case 0x1c: /* ILR0 */ + case 0x20: /* ILR1 */ + case 0x24: /* ILR2 */ + case 0x28: /* ILR3 */ + case 0x2c: /* ILR4 */ + case 0x30: /* ILR5 */ + case 0x34: /* ILR6 */ + case 0x38: /* ILR7 */ + case 0x3c: /* ILR8 */ + case 0x40: /* ILR9 */ + case 0x44: /* ILR10 */ + case 0x48: /* ILR11 */ + case 0x4c: /* ILR12 */ + case 0x50: /* ILR13 */ + case 0x54: /* ILR14 */ + case 0x58: /* ILR15 */ + case 0x5c: /* ILR16 */ + case 0x60: /* ILR17 */ + case 0x64: /* ILR18 */ + case 0x68: /* ILR19 */ + case 0x6c: /* ILR20 */ + case 0x70: /* ILR21 */ + case 0x74: /* ILR22 */ + case 0x78: /* ILR23 */ + case 0x7c: /* ILR24 */ + case 0x80: /* ILR25 */ + case 0x84: /* ILR26 */ + case 0x88: /* ILR27 */ + case 0x8c: /* ILR28 */ + case 0x90: /* ILR29 */ + case 0x94: /* ILR30 */ + case 0x98: /* ILR31 */ i =3D (offset - 0x1c) >> 2; return (bank->priority[i] << 2) | (((bank->sens_edge >> i) & 1) << 1) | ((bank->fiq >> i) & 1); =20 - case 0x9c: /* ISR */ + case 0x9c: /* ISR */ return 0x00000000; =20 } @@ -219,24 +219,24 @@ static void omap_inth_write(void *opaque, hwaddr addr, offset &=3D 0xff; =20 switch (offset) { - case 0x00: /* ITR */ + case 0x00: /* ITR */ /* Important: ignore the clearing if the IRQ is level-triggered and the input bit is 1 */ bank->irqs &=3D value | (bank->inputs & bank->sens_edge); return; =20 - case 0x04: /* MIR */ + case 0x04: /* MIR */ bank->mask =3D value; omap_inth_update(s, 0); omap_inth_update(s, 1); return; =20 - case 0x10: /* SIR_IRQ_CODE */ - case 0x14: /* SIR_FIQ_CODE */ + case 0x10: /* SIR_IRQ_CODE */ + case 0x14: /* SIR_FIQ_CODE */ OMAP_RO_REG(addr); break; =20 - case 0x18: /* CONTROL_REG */ + case 0x18: /* CONTROL_REG */ if (bank_no !=3D 0) break; if (value & 2) { @@ -251,38 +251,38 @@ static void omap_inth_write(void *opaque, hwaddr addr, } return; =20 - case 0x1c: /* ILR0 */ - case 0x20: /* ILR1 */ - case 0x24: /* ILR2 */ - case 0x28: /* ILR3 */ - case 0x2c: /* ILR4 */ - case 0x30: /* ILR5 */ - case 0x34: /* ILR6 */ - case 0x38: /* ILR7 */ - case 0x3c: /* ILR8 */ - case 0x40: /* ILR9 */ - case 0x44: /* ILR10 */ - case 0x48: /* ILR11 */ - case 0x4c: /* ILR12 */ - case 0x50: /* ILR13 */ - case 0x54: /* ILR14 */ - case 0x58: /* ILR15 */ - case 0x5c: /* ILR16 */ - case 0x60: /* ILR17 */ - case 0x64: /* ILR18 */ - case 0x68: /* ILR19 */ - case 0x6c: /* ILR20 */ - case 0x70: /* ILR21 */ - case 0x74: /* ILR22 */ - case 0x78: /* ILR23 */ - case 0x7c: /* ILR24 */ - case 0x80: /* ILR25 */ - case 0x84: /* ILR26 */ - case 0x88: /* ILR27 */ - case 0x8c: /* ILR28 */ - case 0x90: /* ILR29 */ - case 0x94: /* ILR30 */ - case 0x98: /* ILR31 */ + case 0x1c: /* ILR0 */ + case 0x20: /* ILR1 */ + case 0x24: /* ILR2 */ + case 0x28: /* ILR3 */ + case 0x2c: /* ILR4 */ + case 0x30: /* ILR5 */ + case 0x34: /* ILR6 */ + case 0x38: /* ILR7 */ + case 0x3c: /* ILR8 */ + case 0x40: /* ILR9 */ + case 0x44: /* ILR10 */ + case 0x48: /* ILR11 */ + case 0x4c: /* ILR12 */ + case 0x50: /* ILR13 */ + case 0x54: /* ILR14 */ + case 0x58: /* ILR15 */ + case 0x5c: /* ILR16 */ + case 0x60: /* ILR17 */ + case 0x64: /* ILR18 */ + case 0x68: /* ILR19 */ + case 0x6c: /* ILR20 */ + case 0x70: /* ILR21 */ + case 0x74: /* ILR22 */ + case 0x78: /* ILR23 */ + case 0x7c: /* ILR24 */ + case 0x80: /* ILR25 */ + case 0x84: /* ILR26 */ + case 0x88: /* ILR27 */ + case 0x8c: /* ILR28 */ + case 0x90: /* ILR29 */ + case 0x94: /* ILR30 */ + case 0x98: /* ILR31 */ i =3D (offset - 0x1c) >> 2; bank->priority[i] =3D (value >> 2) & 0x1f; bank->sens_edge &=3D ~(1 << i); @@ -291,7 +291,7 @@ static void omap_inth_write(void *opaque, hwaddr addr, bank->fiq |=3D (value & 1) << i; return; =20 - case 0x9c: /* ISR */ + case 0x9c: /* ISR */ for (i =3D 0; i < 32; i ++) if (value & (1 << i)) { omap_set_intr(s, 32 * bank_no + i, 1); diff --git a/hw/misc/omap_clk.c b/hw/misc/omap_clk.c index 0157c9be759..da95c4ace58 100644 --- a/hw/misc/omap_clk.c +++ b/hw/misc/omap_clk.c @@ -30,170 +30,170 @@ struct clk { struct clk *parent; struct clk *child1; struct clk *sibling; -#define ALWAYS_ENABLED (1 << 0) -#define CLOCK_IN_OMAP310 (1 << 10) -#define CLOCK_IN_OMAP730 (1 << 11) -#define CLOCK_IN_OMAP1510 (1 << 12) -#define CLOCK_IN_OMAP16XX (1 << 13) +#define ALWAYS_ENABLED (1 << 0) +#define CLOCK_IN_OMAP310 (1 << 10) +#define CLOCK_IN_OMAP730 (1 << 11) +#define CLOCK_IN_OMAP1510 (1 << 12) +#define CLOCK_IN_OMAP16XX (1 << 13) uint32_t flags; int id; =20 - int running; /* Is currently ticking */ - int enabled; /* Is enabled, regardless of its input clk */ - unsigned long rate; /* Current rate (if .running) */ - unsigned int divisor; /* Rate relative to input (if .enabled) */ - unsigned int multiplier; /* Rate relative to input (if .enabled) */ - qemu_irq users[16]; /* Who to notify on change */ - int usecount; /* Automatically idle when unused */ + int running; /* Is currently ticking */ + int enabled; /* Is enabled, regardless of its input clk */ + unsigned long rate; /* Current rate (if .running) */ + unsigned int divisor; /* Rate relative to input (if .enabled) */ + unsigned int multiplier; /* Rate relative to input (if .enabled) */ + qemu_irq users[16]; /* Who to notify on change */ + int usecount; /* Automatically idle when unused */ }; =20 static struct clk xtal_osc12m =3D { - .name =3D "xtal_osc_12m", - .rate =3D 12000000, - .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, + .name =3D "xtal_osc_12m", + .rate =3D 12000000, + .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, }; =20 static struct clk xtal_osc32k =3D { - .name =3D "xtal_osc_32k", - .rate =3D 32768, - .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, + .name =3D "xtal_osc_32k", + .rate =3D 32768, + .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, }; =20 static struct clk ck_ref =3D { - .name =3D "ck_ref", - .alias =3D "clkin", - .parent =3D &xtal_osc12m, - .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | + .name =3D "ck_ref", + .alias =3D "clkin", + .parent =3D &xtal_osc12m, + .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, }; =20 /* If a dpll is disabled it becomes a bypass, child clocks don't stop */ static struct clk dpll1 =3D { - .name =3D "dpll1", - .parent =3D &ck_ref, - .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | + .name =3D "dpll1", + .parent =3D &ck_ref, + .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, }; =20 static struct clk dpll2 =3D { - .name =3D "dpll2", - .parent =3D &ck_ref, - .flags =3D CLOCK_IN_OMAP310 | ALWAYS_ENABLED, + .name =3D "dpll2", + .parent =3D &ck_ref, + .flags =3D CLOCK_IN_OMAP310 | ALWAYS_ENABLED, }; =20 static struct clk dpll3 =3D { - .name =3D "dpll3", - .parent =3D &ck_ref, - .flags =3D CLOCK_IN_OMAP310 | ALWAYS_ENABLED, + .name =3D "dpll3", + .parent =3D &ck_ref, + .flags =3D CLOCK_IN_OMAP310 | ALWAYS_ENABLED, }; =20 static struct clk dpll4 =3D { - .name =3D "dpll4", - .parent =3D &ck_ref, - .multiplier =3D 4, - .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, + .name =3D "dpll4", + .parent =3D &ck_ref, + .multiplier =3D 4, + .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, }; =20 static struct clk apll =3D { - .name =3D "apll", - .parent =3D &ck_ref, - .multiplier =3D 48, - .divisor =3D 12, - .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, + .name =3D "apll", + .parent =3D &ck_ref, + .multiplier =3D 48, + .divisor =3D 12, + .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, }; =20 static struct clk ck_48m =3D { - .name =3D "ck_48m", - .parent =3D &dpll4, /* either dpll4 or apll */ - .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, + .name =3D "ck_48m", + .parent =3D &dpll4, /* either dpll4 or apll */ + .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, }; =20 static struct clk ck_dpll1out =3D { - .name =3D "ck_dpll1out", - .parent =3D &dpll1, - .flags =3D CLOCK_IN_OMAP16XX, + .name =3D "ck_dpll1out", + .parent =3D &dpll1, + .flags =3D CLOCK_IN_OMAP16XX, }; =20 static struct clk sossi_ck =3D { - .name =3D "ck_sossi", - .parent =3D &ck_dpll1out, - .flags =3D CLOCK_IN_OMAP16XX, + .name =3D "ck_sossi", + .parent =3D &ck_dpll1out, + .flags =3D CLOCK_IN_OMAP16XX, }; =20 static struct clk clkm1 =3D { - .name =3D "clkm1", - .alias =3D "ck_gen1", - .parent =3D &dpll1, - .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | + .name =3D "clkm1", + .alias =3D "ck_gen1", + .parent =3D &dpll1, + .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, }; =20 static struct clk clkm2 =3D { - .name =3D "clkm2", - .alias =3D "ck_gen2", - .parent =3D &dpll1, - .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | + .name =3D "clkm2", + .alias =3D "ck_gen2", + .parent =3D &dpll1, + .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, }; =20 static struct clk clkm3 =3D { - .name =3D "clkm3", - .alias =3D "ck_gen3", - .parent =3D &dpll1, /* either dpll1 or ck_ref */ - .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | + .name =3D "clkm3", + .alias =3D "ck_gen3", + .parent =3D &dpll1, /* either dpll1 or ck_ref */ + .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, }; =20 static struct clk arm_ck =3D { - .name =3D "arm_ck", - .alias =3D "mpu_ck", - .parent =3D &clkm1, - .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | + .name =3D "arm_ck", + .alias =3D "mpu_ck", + .parent =3D &clkm1, + .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, }; =20 static struct clk armper_ck =3D { - .name =3D "armper_ck", - .alias =3D "mpuper_ck", - .parent =3D &clkm1, - .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, + .name =3D "armper_ck", + .alias =3D "mpuper_ck", + .parent =3D &clkm1, + .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, }; =20 static struct clk arm_gpio_ck =3D { - .name =3D "arm_gpio_ck", - .alias =3D "mpu_gpio_ck", - .parent =3D &clkm1, - .divisor =3D 1, - .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, + .name =3D "arm_gpio_ck", + .alias =3D "mpu_gpio_ck", + .parent =3D &clkm1, + .divisor =3D 1, + .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, }; =20 static struct clk armxor_ck =3D { - .name =3D "armxor_ck", - .alias =3D "mpuxor_ck", - .parent =3D &ck_ref, - .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, + .name =3D "armxor_ck", + .alias =3D "mpuxor_ck", + .parent =3D &ck_ref, + .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, }; =20 static struct clk armtim_ck =3D { - .name =3D "armtim_ck", - .alias =3D "mputim_ck", - .parent =3D &ck_ref, /* either CLKIN or DPLL1 */ - .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, + .name =3D "armtim_ck", + .alias =3D "mputim_ck", + .parent =3D &ck_ref, /* either CLKIN or DPLL1 */ + .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, }; =20 static struct clk armwdt_ck =3D { - .name =3D "armwdt_ck", - .alias =3D "mpuwd_ck", - .parent =3D &clkm1, - .divisor =3D 14, - .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | + .name =3D "armwdt_ck", + .alias =3D "mpuwd_ck", + .parent =3D &clkm1, + .divisor =3D 14, + .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, }; =20 static struct clk arminth_ck16xx =3D { - .name =3D "arminth_ck", - .parent =3D &arm_ck, - .flags =3D CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, + .name =3D "arminth_ck", + .parent =3D &arm_ck, + .flags =3D CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, /* Note: On 16xx the frequency can be divided by 2 by programming * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 * @@ -202,48 +202,48 @@ static struct clk arminth_ck16xx =3D { }; =20 static struct clk dsp_ck =3D { - .name =3D "dsp_ck", - .parent =3D &clkm2, - .flags =3D CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, + .name =3D "dsp_ck", + .parent =3D &clkm2, + .flags =3D CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, }; =20 static struct clk dspmmu_ck =3D { - .name =3D "dspmmu_ck", - .parent =3D &clkm2, - .flags =3D CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + .name =3D "dspmmu_ck", + .parent =3D &clkm2, + .flags =3D CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, }; =20 static struct clk dspper_ck =3D { - .name =3D "dspper_ck", - .parent =3D &clkm2, - .flags =3D CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, + .name =3D "dspper_ck", + .parent =3D &clkm2, + .flags =3D CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, }; =20 static struct clk dspxor_ck =3D { - .name =3D "dspxor_ck", - .parent =3D &ck_ref, - .flags =3D CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, + .name =3D "dspxor_ck", + .parent =3D &ck_ref, + .flags =3D CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, }; =20 static struct clk dsptim_ck =3D { - .name =3D "dsptim_ck", - .parent =3D &ck_ref, - .flags =3D CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, + .name =3D "dsptim_ck", + .parent =3D &ck_ref, + .flags =3D CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, }; =20 static struct clk tc_ck =3D { - .name =3D "tc_ck", - .parent =3D &clkm3, - .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + .name =3D "tc_ck", + .parent =3D &clkm3, + .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, }; =20 static struct clk arminth_ck15xx =3D { - .name =3D "arminth_ck", - .parent =3D &tc_ck, - .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, + .name =3D "arminth_ck", + .parent =3D &tc_ck, + .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, /* Note: On 1510 the frequency follows TC_CK * * 16xx version is in MPU clocks. @@ -252,259 +252,259 @@ static struct clk arminth_ck15xx =3D { =20 static struct clk tipb_ck =3D { /* No-idle controlled by "tc_ck" */ - .name =3D "tipb_ck", - .parent =3D &tc_ck, - .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, + .name =3D "tipb_ck", + .parent =3D &tc_ck, + .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, }; =20 static struct clk l3_ocpi_ck =3D { /* No-idle controlled by "tc_ck" */ - .name =3D "l3_ocpi_ck", - .parent =3D &tc_ck, - .flags =3D CLOCK_IN_OMAP16XX, + .name =3D "l3_ocpi_ck", + .parent =3D &tc_ck, + .flags =3D CLOCK_IN_OMAP16XX, }; =20 static struct clk tc1_ck =3D { - .name =3D "tc1_ck", - .parent =3D &tc_ck, - .flags =3D CLOCK_IN_OMAP16XX, + .name =3D "tc1_ck", + .parent =3D &tc_ck, + .flags =3D CLOCK_IN_OMAP16XX, }; =20 static struct clk tc2_ck =3D { - .name =3D "tc2_ck", - .parent =3D &tc_ck, - .flags =3D CLOCK_IN_OMAP16XX, + .name =3D "tc2_ck", + .parent =3D &tc_ck, + .flags =3D CLOCK_IN_OMAP16XX, }; =20 static struct clk dma_ck =3D { /* No-idle controlled by "tc_ck" */ - .name =3D "dma_ck", - .parent =3D &tc_ck, - .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | + .name =3D "dma_ck", + .parent =3D &tc_ck, + .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, }; =20 static struct clk dma_lcdfree_ck =3D { - .name =3D "dma_lcdfree_ck", - .parent =3D &tc_ck, - .flags =3D CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, + .name =3D "dma_lcdfree_ck", + .parent =3D &tc_ck, + .flags =3D CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, }; =20 static struct clk api_ck =3D { - .name =3D "api_ck", - .alias =3D "mpui_ck", - .parent =3D &tc_ck, - .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, + .name =3D "api_ck", + .alias =3D "mpui_ck", + .parent =3D &tc_ck, + .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, }; =20 static struct clk lb_ck =3D { - .name =3D "lb_ck", - .parent =3D &tc_ck, - .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, + .name =3D "lb_ck", + .parent =3D &tc_ck, + .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, }; =20 static struct clk lbfree_ck =3D { - .name =3D "lbfree_ck", - .parent =3D &tc_ck, - .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, + .name =3D "lbfree_ck", + .parent =3D &tc_ck, + .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, }; =20 static struct clk hsab_ck =3D { - .name =3D "hsab_ck", - .parent =3D &tc_ck, - .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, + .name =3D "hsab_ck", + .parent =3D &tc_ck, + .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, }; =20 static struct clk rhea1_ck =3D { - .name =3D "rhea1_ck", - .parent =3D &tc_ck, - .flags =3D CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, + .name =3D "rhea1_ck", + .parent =3D &tc_ck, + .flags =3D CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, }; =20 static struct clk rhea2_ck =3D { - .name =3D "rhea2_ck", - .parent =3D &tc_ck, - .flags =3D CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, + .name =3D "rhea2_ck", + .parent =3D &tc_ck, + .flags =3D CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, }; =20 static struct clk lcd_ck_16xx =3D { - .name =3D "lcd_ck", - .parent =3D &clkm3, - .flags =3D CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730, + .name =3D "lcd_ck", + .parent =3D &clkm3, + .flags =3D CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730, }; =20 static struct clk lcd_ck_1510 =3D { - .name =3D "lcd_ck", - .parent =3D &clkm3, - .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, + .name =3D "lcd_ck", + .parent =3D &clkm3, + .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, }; =20 static struct clk uart1_1510 =3D { - .name =3D "uart1_ck", + .name =3D "uart1_ck", /* Direct from ULPD, no real parent */ - .parent =3D &armper_ck, /* either armper_ck or dpll4 */ - .rate =3D 12000000, - .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, + .parent =3D &armper_ck, /* either armper_ck or dpll4 */ + .rate =3D 12000000, + .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, }; =20 static struct clk uart1_16xx =3D { - .name =3D "uart1_ck", + .name =3D "uart1_ck", /* Direct from ULPD, no real parent */ - .parent =3D &armper_ck, - .rate =3D 48000000, - .flags =3D CLOCK_IN_OMAP16XX, + .parent =3D &armper_ck, + .rate =3D 48000000, + .flags =3D CLOCK_IN_OMAP16XX, }; =20 static struct clk uart2_ck =3D { - .name =3D "uart2_ck", + .name =3D "uart2_ck", /* Direct from ULPD, no real parent */ - .parent =3D &armper_ck, /* either armper_ck or dpll4 */ - .rate =3D 12000000, - .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | + .parent =3D &armper_ck, /* either armper_ck or dpll4 */ + .rate =3D 12000000, + .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, }; =20 static struct clk uart3_1510 =3D { - .name =3D "uart3_ck", + .name =3D "uart3_ck", /* Direct from ULPD, no real parent */ - .parent =3D &armper_ck, /* either armper_ck or dpll4 */ - .rate =3D 12000000, - .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, + .parent =3D &armper_ck, /* either armper_ck or dpll4 */ + .rate =3D 12000000, + .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, }; =20 static struct clk uart3_16xx =3D { - .name =3D "uart3_ck", + .name =3D "uart3_ck", /* Direct from ULPD, no real parent */ - .parent =3D &armper_ck, - .rate =3D 48000000, - .flags =3D CLOCK_IN_OMAP16XX, + .parent =3D &armper_ck, + .rate =3D 48000000, + .flags =3D CLOCK_IN_OMAP16XX, }; =20 -static struct clk usb_clk0 =3D { /* 6 MHz output on W4_USB_CLK0 */ - .name =3D "usb_clk0", - .alias =3D "usb.clko", +static struct clk usb_clk0 =3D { /* 6 MHz output on W4_USB_CLK0 */ + .name =3D "usb_clk0", + .alias =3D "usb.clko", /* Direct from ULPD, no parent */ - .rate =3D 6000000, - .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, + .rate =3D 6000000, + .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, }; =20 static struct clk usb_hhc_ck1510 =3D { - .name =3D "usb_hhc_ck", + .name =3D "usb_hhc_ck", /* Direct from ULPD, no parent */ - .rate =3D 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ - .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, + .rate =3D 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ + .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, }; =20 static struct clk usb_hhc_ck16xx =3D { - .name =3D "usb_hhc_ck", + .name =3D "usb_hhc_ck", /* Direct from ULPD, no parent */ - .rate =3D 48000000, + .rate =3D 48000000, /* OTG_SYSCON_2.OTG_PADEN =3D=3D 0 (not 1510-compatible) */ - .flags =3D CLOCK_IN_OMAP16XX, + .flags =3D CLOCK_IN_OMAP16XX, }; =20 static struct clk usb_w2fc_mclk =3D { - .name =3D "usb_w2fc_mclk", - .alias =3D "usb_w2fc_ck", - .parent =3D &ck_48m, - .rate =3D 48000000, - .flags =3D CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, + .name =3D "usb_w2fc_mclk", + .alias =3D "usb_w2fc_ck", + .parent =3D &ck_48m, + .rate =3D 48000000, + .flags =3D CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, }; =20 static struct clk mclk_1510 =3D { - .name =3D "mclk", + .name =3D "mclk", /* Direct from ULPD, no parent. May be enabled by ext hardware. */ - .rate =3D 12000000, - .flags =3D CLOCK_IN_OMAP1510, + .rate =3D 12000000, + .flags =3D CLOCK_IN_OMAP1510, }; =20 static struct clk bclk_310 =3D { - .name =3D "bt_mclk_out", /* Alias midi_mclk_out? */ - .parent =3D &armper_ck, - .flags =3D CLOCK_IN_OMAP310, + .name =3D "bt_mclk_out", /* Alias midi_mclk_out? */ + .parent =3D &armper_ck, + .flags =3D CLOCK_IN_OMAP310, }; =20 static struct clk mclk_310 =3D { - .name =3D "com_mclk_out", - .parent =3D &armper_ck, - .flags =3D CLOCK_IN_OMAP310, + .name =3D "com_mclk_out", + .parent =3D &armper_ck, + .flags =3D CLOCK_IN_OMAP310, }; =20 static struct clk mclk_16xx =3D { - .name =3D "mclk", + .name =3D "mclk", /* Direct from ULPD, no parent. May be enabled by ext hardware. */ - .flags =3D CLOCK_IN_OMAP16XX, + .flags =3D CLOCK_IN_OMAP16XX, }; =20 static struct clk bclk_1510 =3D { - .name =3D "bclk", + .name =3D "bclk", /* Direct from ULPD, no parent. May be enabled by ext hardware. */ - .rate =3D 12000000, - .flags =3D CLOCK_IN_OMAP1510, + .rate =3D 12000000, + .flags =3D CLOCK_IN_OMAP1510, }; =20 static struct clk bclk_16xx =3D { - .name =3D "bclk", + .name =3D "bclk", /* Direct from ULPD, no parent. May be enabled by ext hardware. */ - .flags =3D CLOCK_IN_OMAP16XX, + .flags =3D CLOCK_IN_OMAP16XX, }; =20 static struct clk mmc1_ck =3D { - .name =3D "mmc_ck", - .id =3D 1, + .name =3D "mmc_ck", + .id =3D 1, /* Functional clock is direct from ULPD, interface clock is ARMPER */ - .parent =3D &armper_ck, /* either armper_ck or dpll4 */ - .rate =3D 48000000, - .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, + .parent =3D &armper_ck, /* either armper_ck or dpll4 */ + .rate =3D 48000000, + .flags =3D CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, }; =20 static struct clk mmc2_ck =3D { - .name =3D "mmc_ck", - .id =3D 2, + .name =3D "mmc_ck", + .id =3D 2, /* Functional clock is direct from ULPD, interface clock is ARMPER */ - .parent =3D &armper_ck, - .rate =3D 48000000, - .flags =3D CLOCK_IN_OMAP16XX, + .parent =3D &armper_ck, + .rate =3D 48000000, + .flags =3D CLOCK_IN_OMAP16XX, }; =20 static struct clk cam_mclk =3D { - .name =3D "cam.mclk", - .flags =3D CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, - .rate =3D 12000000, + .name =3D "cam.mclk", + .flags =3D CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, + .rate =3D 12000000, }; =20 static struct clk cam_exclk =3D { - .name =3D "cam.exclk", - .flags =3D CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, + .name =3D "cam.exclk", + .flags =3D CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, /* Either 12M from cam.mclk or 48M from dpll4 */ - .parent =3D &cam_mclk, + .parent =3D &cam_mclk, }; =20 static struct clk cam_lclk =3D { - .name =3D "cam.lclk", - .flags =3D CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, + .name =3D "cam.lclk", + .flags =3D CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, }; =20 static struct clk i2c_fck =3D { - .name =3D "i2c_fck", - .id =3D 1, - .flags =3D CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + .name =3D "i2c_fck", + .id =3D 1, + .flags =3D CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, - .parent =3D &armxor_ck, + .parent =3D &armxor_ck, }; =20 static struct clk i2c_ick =3D { - .name =3D "i2c_ick", - .id =3D 1, - .flags =3D CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, - .parent =3D &armper_ck, + .name =3D "i2c_ick", + .id =3D 1, + .flags =3D CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, + .parent =3D &armper_ck, }; =20 static struct clk clk32k =3D { - .name =3D "clk32-kHz", - .flags =3D CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + .name =3D "clk32-kHz", + .flags =3D CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, - .parent =3D &xtal_osc32k, + .parent =3D &xtal_osc32k, }; =20 static struct clk *onchip_clks[] =3D { diff --git a/hw/timer/pxa2xx_timer.c b/hw/timer/pxa2xx_timer.c index 7a94366b0f8..6d4ac31574e 100644 --- a/hw/timer/pxa2xx_timer.c +++ b/hw/timer/pxa2xx_timer.c @@ -19,41 +19,41 @@ #include "qom/object.h" #include "system/watchdog.h" =20 -#define OSMR0 0x00 -#define OSMR1 0x04 -#define OSMR2 0x08 -#define OSMR3 0x0c -#define OSMR4 0x80 -#define OSMR5 0x84 -#define OSMR6 0x88 -#define OSMR7 0x8c -#define OSMR8 0x90 -#define OSMR9 0x94 -#define OSMR10 0x98 -#define OSMR11 0x9c -#define OSCR 0x10 /* OS Timer Count */ -#define OSCR4 0x40 -#define OSCR5 0x44 -#define OSCR6 0x48 -#define OSCR7 0x4c -#define OSCR8 0x50 -#define OSCR9 0x54 -#define OSCR10 0x58 -#define OSCR11 0x5c -#define OSSR 0x14 /* Timer status register */ -#define OWER 0x18 -#define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */ -#define OMCR4 0xc0 /* OS Match Control registers */ -#define OMCR5 0xc4 -#define OMCR6 0xc8 -#define OMCR7 0xcc -#define OMCR8 0xd0 -#define OMCR9 0xd4 -#define OMCR10 0xd8 -#define OMCR11 0xdc -#define OSNR 0x20 +#define OSMR0 0x00 +#define OSMR1 0x04 +#define OSMR2 0x08 +#define OSMR3 0x0c +#define OSMR4 0x80 +#define OSMR5 0x84 +#define OSMR6 0x88 +#define OSMR7 0x8c +#define OSMR8 0x90 +#define OSMR9 0x94 +#define OSMR10 0x98 +#define OSMR11 0x9c +#define OSCR 0x10 /* OS Timer Count */ +#define OSCR4 0x40 +#define OSCR5 0x44 +#define OSCR6 0x48 +#define OSCR7 0x4c +#define OSCR8 0x50 +#define OSCR9 0x54 +#define OSCR10 0x58 +#define OSCR11 0x5c +#define OSSR 0x14 /* Timer status register */ +#define OWER 0x18 +#define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */ +#define OMCR4 0xc0 /* OS Match Control registers */ +#define OMCR5 0xc4 +#define OMCR6 0xc8 +#define OMCR7 0xcc +#define OMCR8 0xd0 +#define OMCR9 0xd4 +#define OMCR10 0xd8 +#define OMCR11 0xdc +#define OSNR 0x20 =20 -#define PXA25X_FREQ 3686400 /* 3.6864 MHz */ +#define PXA25X_FREQ 3686400 /* 3.6864 MHz */ =20 static int pxa2xx_timer4_freq[8] =3D { [0] =3D 0, @@ -106,7 +106,7 @@ struct PXA2xxTimerInfo { PXA2xxTimer4 tm4[8]; }; =20 -#define PXA2XX_TIMER_HAVE_TM4 0 +#define PXA2XX_TIMER_HAVE_TM4 0 =20 static inline int pxa2xx_timer_has_tm4(PXA2xxTimerInfo *s) { @@ -230,7 +230,7 @@ static uint64_t pxa2xx_timer_read(void *opaque, hwaddr = offset, NANOSECONDS_PER_SECOND); case OIER: return s->irq_enabled; - case OSSR: /* Status register */ + case OSSR: /* Status register */ return s->events; case OWER: return s->reset3; @@ -336,7 +336,7 @@ static void pxa2xx_timer_write(void *opaque, hwaddr off= set, case OIER: s->irq_enabled =3D value & 0xfff; break; - case OSSR: /* Status register */ + case OSSR: /* Status register */ value &=3D s->events; s->events &=3D ~value; for (i =3D 0; i < 4; i ++, value >>=3D 1) @@ -345,7 +345,7 @@ static void pxa2xx_timer_write(void *opaque, hwaddr off= set, if (pxa2xx_timer_has_tm4(s) && !(s->events & 0xff0) && value) qemu_irq_lower(s->irq4); break; - case OWER: /* XXX: Reset on OSMR3 match? */ + case OWER: /* XXX: Reset on OSMR3 match? */ s->reset3 =3D value; break; case OMCR7: tm ++; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442f396c3a4sm65657855e9.26.2025.05.15.03.26.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 03:26:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747304764; x=1747909564; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=CEFPr6cyWXqfoeIE3F4AoQQqrdnfTceL/5vMmBbgJT4=; b=Nqrp2efDTgsLTiFHqLZe5cKN+FDHNvXNTAQpyZljW6+t30mRPNNP3Zhtu5k0Kwfqq5 4wZfHzh26Cf7inGTB1TCsPN4DgdhhBu6B+AIF9sHU77SY1iZw3/shn+e84+VCkvsBtK+ wzJZINsNpgFkKV4ci5XegeaRrcYo+evOWVC1Wddw7S57avNt7Gb5JHkzKB1Vo4U3ILiK sVLEwUx6UUk05f5dQGhxCrWFl06+Of5VErn4b1m/FTSm2qys+RZZfctfdTSYIvMPHhbw iGngC1dCe/t+T+Qt3j2ecEXxkSIO/m0dob9xE/xu9pBsn1oZBQrC7CuHM6PwUZZIsZG2 Pxsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747304764; x=1747909564; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CEFPr6cyWXqfoeIE3F4AoQQqrdnfTceL/5vMmBbgJT4=; b=KSJxY0g3+beG5n4E8l+k/y67l3C7WdkN1AWJdHkn75QDXpu3dLfd4a+tlobjnGvgUz XA/FGpQtP5DJYbTbzWMImf1WyLys5UAkeev+L5iD+sk5Vk7coRUzSjGbCgZlOb3c8Pil hP73qvidS+FrKa1oURZdZTuIJcj9y1uSjbt2Dtasj2aJwgJvRX/HKSjtLag3kTeN0Ea9 LKe/Ew1fzWNIOqnY1AkEn1VkWBTvTEVWcKD0HVPyAtn0+O/HdvYGSSq6LQcTnq0o8O1l OSn+nfhg6e/1Ea2CDngtr2+AizQiz4Gnb0pdG/P2+SYr88kjxnmPIqlYomhs/0rZ3dlV SjQg== X-Gm-Message-State: AOJu0YzT4PRGZC9j28GyHfQcTWpaWiG+qjz0VaJllLxGsbEvEi61Ygra Pes1owTHnbsyKc3giQT64dn5xWg+qpTtFRkXftP/QV+Fg8Kf0jj0afLHr2gAbPRntzZLfomPN4Z QEdM= X-Gm-Gg: ASbGncsX+ABY3gtNXWfuYu/jOI2ymRI7NQWN7lP3IgF5GqgJov62me+yggBP6x57xI1 32RGrQJXpOciqhmvNgcA07LksWnTC8FRLBjbU342eyU8CvYlOwuNGsxtCDauf9UH4VfWpgrfz/q gGnM3iNeZ48B51iZpVFeY/iZp6z7AC6v0qxfd3CBzGGSdPxAAqGxMs+LavPn0rBoOgXKgF8rq0L 7xITHM/HRlBAHEMVtgXxKN+VjIzj5I7petXw/dP0cSGZaIzO0D1e66hL+n5/mATjcTwflyswmel Pnm3LDLo+CFQrwEBOvnExM63arGo6pEkLxgaeIMM1tJYWuDeq9Se8WYGPQ== X-Google-Smtp-Source: AGHT+IHzFiNDe0GOFzQDGvtqDXuCYMjfffNSQC2wVlL47O70U0WdZveSFY2+QtxaK3Pm9fZPA/H8sw== X-Received: by 2002:a05:600c:4508:b0:439:5f04:4f8d with SMTP id 5b1f17b1804b1-442f84f8ec2mr26475245e9.12.1747304764095; Thu, 15 May 2025 03:26:04 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/58] MAINTAINERS: Add an entry for the Bananapi machine Date: Thu, 15 May 2025 11:24:58 +0100 Message-ID: <20250515102546.2149601-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305239134116600 Content-Type: text/plain; charset="utf-8" From: Thomas Huth This machine was still missing from the MAINTAINERS file. Since there is likely no active maintainer around for this machine (I didn't spot any contributions from Qianfan Zhao in the git log after 2023), I'm suggesting Peter as maintainer with status set to "Odd fixes". Signed-off-by: Thomas Huth Message-id: 20250508072706.114278-1-thuth@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- MAINTAINERS | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 6dacd6d004d..ca0ffc02d4c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -732,6 +732,16 @@ F: include/hw/timer/armv7m_systick.h F: include/hw/misc/armv7m_ras.h F: tests/qtest/test-arm-mptimer.c =20 +Bananapi M2U +M: Peter Maydell +L: qemu-arm@nongnu.org +S: Odd Fixes +F: docs/system/arm/bananapi_m2u.rst +F: hw/*/allwinner-r40*.c +F: hw/arm/bananapi_m2u.c +F: include/hw/*/allwinner-r40*.h +F: tests/functional/test_arm_bpim2u.py + B-L475E-IOT01A IoT Node M: Samuel Tardieu L: qemu-arm@nongnu.org --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747304930; cv=none; d=zohomail.com; s=zohoarc; b=mNZ/PKBKS9w6zjxiGf6ubsafXnD2eM9GWUX/NPksB6c1nGRV2YAFkwaWYr82DoqHh2n+VTL0U1iMooNiefYc+6o8eyxONoYXjntjchd9We448gCMxE1AfxhhzDnh0LW6YZlZjYpMuBbrCCFS2LiHDQfoqNHkpjgVEf6it/vvhxs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747304930; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=45OXTNzjwjDe6TE6ZCe7ioq6XmOCBuiCA+I7gKEs7n0=; b=Emzzg+GFTqRHYyE2QDWbqNyb/OwPIVOvPDZdD5E27brlma9twHZ4OorUgZoqJYpxZg6+3VG/i/qoXunNrUSZ0/3cDYA39DPayN1wkaceoiVYtay4vyNJ//uJpeh91phCYkLFIzz7LCq1uYRp0KhZkV36LjSo91u4HubFfPcxJro= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747304930760276.0866026123051; Thu, 15 May 2025 03:28:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uFVmz-0004PN-DS; Thu, 15 May 2025 06:26:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uFVmy-0004P8-O0 for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:08 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uFVmw-00088i-NT for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:08 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-43cfba466b2so8368895e9.3 for ; Thu, 15 May 2025 03:26:06 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Thu, 15 May 2025 03:26:05 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/58] target/arm: Replace target_ulong -> vaddr for HWBreakpoint Date: Thu, 15 May 2025 11:24:59 +0100 Message-ID: <20250515102546.2149601-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747304932192116600 From: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Pierrick Bouvier Message-id: 20250512180502.2395029-2-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 6 +++--- target/arm/hyp_gdbstub.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 702eb1a5483..3360de9150f 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1948,9 +1948,9 @@ extern GArray *hw_breakpoints, *hw_watchpoints; #define get_hw_bp(i) (&g_array_index(hw_breakpoints, HWBreakpoint, i)) #define get_hw_wp(i) (&g_array_index(hw_watchpoints, HWWatchpoint, i)) =20 -bool find_hw_breakpoint(CPUState *cpu, target_ulong pc); -int insert_hw_breakpoint(target_ulong pc); -int delete_hw_breakpoint(target_ulong pc); +bool find_hw_breakpoint(CPUState *cpu, vaddr pc); +int insert_hw_breakpoint(vaddr pc); +int delete_hw_breakpoint(vaddr pc); =20 bool check_watchpoint_in_range(int i, vaddr addr); CPUWatchpoint *find_hw_watchpoint(CPUState *cpu, vaddr addr); diff --git a/target/arm/hyp_gdbstub.c b/target/arm/hyp_gdbstub.c index 0512d67f8cf..bb5969720ce 100644 --- a/target/arm/hyp_gdbstub.c +++ b/target/arm/hyp_gdbstub.c @@ -54,7 +54,7 @@ GArray *hw_breakpoints, *hw_watchpoints; * here so future PC comparisons will work properly. */ =20 -int insert_hw_breakpoint(target_ulong addr) +int insert_hw_breakpoint(vaddr addr) { HWBreakpoint brk =3D { .bcr =3D 0x1, /* BCR E=3D1, enable */ @@ -80,7 +80,7 @@ int insert_hw_breakpoint(target_ulong addr) * Delete a breakpoint and shuffle any above down */ =20 -int delete_hw_breakpoint(target_ulong pc) +int delete_hw_breakpoint(vaddr pc) { int i; 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Thu, 15 May 2025 03:26:06 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/58] include/system/hvf: missing vaddr include Date: Thu, 15 May 2025 11:25:00 +0100 Message-ID: <20250515102546.2149601-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305372210116600 From: Pierrick Bouvier On MacOS x86_64: In file included from ../target/i386/hvf/x86_task.c:13: /Users/runner/work/qemu/qemu/include/system/hvf.h:42:5: error: unknown type= name 'vaddr' vaddr pc; ^ /Users/runner/work/qemu/qemu/include/system/hvf.h:43:5: error: unknown type= name 'vaddr' vaddr saved_insn; ^ /Users/runner/work/qemu/qemu/include/system/hvf.h:45:5: error: type name re= quires a specifier or qualifier QTAILQ_ENTRY(hvf_sw_breakpoint) entry; ^ /Users/runner/work/qemu/qemu/include/system/hvf.h:45:18: error: a parameter= list without types is only allowed in a function definition QTAILQ_ENTRY(hvf_sw_breakpoint) entry; ^ /Users/runner/work/qemu/qemu/include/system/hvf.h:45:36: error: expected ';= ' at end of declaration list QTAILQ_ENTRY(hvf_sw_breakpoint) entry; Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-id: 20250512180502.2395029-3-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- include/system/hvf.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/system/hvf.h b/include/system/hvf.h index 7b45a2e1988..a9a502f0c8f 100644 --- a/include/system/hvf.h +++ b/include/system/hvf.h @@ -17,6 +17,7 @@ #include "qemu/queue.h" #include "exec/vaddr.h" #include "qom/object.h" +#include "exec/vaddr.h" =20 #ifdef COMPILING_PER_TARGET # ifdef CONFIG_HVF --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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We need 2 different libraries: - code common to a base architecture - system code common to a base architecture For user code, it can stay compiled per target for now. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-id: 20250512180502.2395029-4-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- meson.build | 78 +++++++++++++++++++++++++++++++++++++++++------------ 1 file changed, 61 insertions(+), 17 deletions(-) diff --git a/meson.build b/meson.build index 7f91500bb73..ad2053f968b 100644 --- a/meson.build +++ b/meson.build @@ -3709,6 +3709,8 @@ target_arch =3D {} target_system_arch =3D {} target_user_arch =3D {} hw_common_arch =3D {} +target_common_arch =3D {} +target_common_system_arch =3D {} =20 # NOTE: the trace/ subdirectory needs the qapi_trace_events variable # that is filled in by qapi/. @@ -4107,29 +4109,59 @@ common_all =3D static_library('common', =20 # construct common libraries per base architecture hw_common_arch_libs =3D {} +target_common_arch_libs =3D {} +target_common_system_arch_libs =3D {} foreach target : target_dirs config_target =3D config_target_mak[target] target_base_arch =3D config_target['TARGET_BASE_ARCH'] + target_inc =3D [include_directories('target' / target_base_arch)] + inc =3D [common_user_inc + target_inc] =20 - # check if already generated - if target_base_arch in hw_common_arch_libs - continue - endif + # prevent common code to access cpu compile time definition, + # but still allow access to cpu.h + target_c_args =3D ['-DCPU_DEFS_H'] + target_system_c_args =3D target_c_args + ['-DCOMPILING_SYSTEM_VS_USER', = '-DCONFIG_SOFTMMU'] =20 if target_base_arch in hw_common_arch - target_inc =3D [include_directories('target' / target_base_arch)] - src =3D hw_common_arch[target_base_arch] - lib =3D static_library( - 'hw_' + target_base_arch, - build_by_default: false, - sources: src.all_sources() + genh, - include_directories: common_user_inc + target_inc, - implicit_include_directories: false, - # prevent common code to access cpu compile time - # definition, but still allow access to cpu.h - c_args: ['-DCPU_DEFS_H', '-DCOMPILING_SYSTEM_VS_USER', '-DCONFIG_SOF= TMMU'], - dependencies: src.all_dependencies()) - hw_common_arch_libs +=3D {target_base_arch: lib} + if target_base_arch not in hw_common_arch_libs + src =3D hw_common_arch[target_base_arch] + lib =3D static_library( + 'hw_' + target_base_arch, + build_by_default: false, + sources: src.all_sources() + genh, + include_directories: inc, + c_args: target_system_c_args, + dependencies: src.all_dependencies()) + hw_common_arch_libs +=3D {target_base_arch: lib} + endif + endif + + if target_base_arch in target_common_arch + if target_base_arch not in target_common_arch_libs + src =3D target_common_arch[target_base_arch] + lib =3D static_library( + 'target_' + target_base_arch, + build_by_default: false, + sources: src.all_sources() + genh, + include_directories: inc, + c_args: target_c_args, + dependencies: src.all_dependencies()) + target_common_arch_libs +=3D {target_base_arch: lib} + endif + endif + + if target_base_arch in target_common_system_arch + if target_base_arch not in target_common_system_arch_libs + src =3D target_common_system_arch[target_base_arch] + lib =3D static_library( + 'target_system_' + target_base_arch, + build_by_default: false, + sources: src.all_sources() + genh, + include_directories: inc, + c_args: target_system_c_args, + dependencies: src.all_dependencies()) + target_common_system_arch_libs +=3D {target_base_arch: lib} + endif endif endforeach =20 @@ -4300,12 +4332,24 @@ foreach target : target_dirs target_common =3D common_ss.apply(config_target, strict: false) objects =3D [common_all.extract_objects(target_common.sources())] arch_deps +=3D target_common.dependencies() + if target_base_arch in target_common_arch_libs + src =3D target_common_arch[target_base_arch].apply(config_target, stri= ct: false) + lib =3D target_common_arch_libs[target_base_arch] + objects +=3D lib.extract_objects(src.sources()) + arch_deps +=3D src.dependencies() + endif if target_type =3D=3D 'system' and target_base_arch in hw_common_arch_li= bs src =3D hw_common_arch[target_base_arch].apply(config_target, strict: = false) lib =3D hw_common_arch_libs[target_base_arch] objects +=3D lib.extract_objects(src.sources()) arch_deps +=3D src.dependencies() endif + if target_type =3D=3D 'system' and target_base_arch in target_common_sys= tem_arch_libs + src =3D target_common_system_arch[target_base_arch].apply(config_targe= t, strict: false) + lib =3D target_common_system_arch_libs[target_base_arch] + objects +=3D lib.extract_objects(src.sources()) + arch_deps +=3D src.dependencies() + endif =20 target_specific =3D specific_ss.apply(config_target, strict: false) arch_srcs +=3D target_specific.sources() --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442f396c3a4sm65657855e9.26.2025.05.15.03.26.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 03:26:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747304769; x=1747909569; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=HJ2vzUkmCNfhfxZp85kg68jtmVNXafBvWG/WJXtDBrM=; b=fSGTL+wwtDiiH4Qr0OI450+U8UOvSznFmjCc23siJq85ZmoThSd9cEaxFhEbNFCBRr dJCdIx4FaBnjlgs3EtrKfVLpxxI5t1rTPRKJfevVSaFUClXc2/xu0QzZi1yiGNOY9ov7 biL6pcWrh6WvJDdNtejkhVlj5cWQXTNAyHJszGJhVzxtBegtfNVKEHDHtEPg73Vqu6UZ GjL1omSjSAa8ncYpO8WP7LMuUaI5e9u+r7CVqIJwETm7KiAZXMP+/AY67R1kmqAlOTxD iVtlNif2SjmfanKl6+0DOaB1YGHfvHsW4n2+f4/36U/nR7reDsNMX09rZi6SyKJ2J3KX mw4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747304769; x=1747909569; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HJ2vzUkmCNfhfxZp85kg68jtmVNXafBvWG/WJXtDBrM=; b=hj5GndYg6PG8IRfov9obkwMBDAn1hT/jjJpPzNDMCCfrtvyqq6uIByufvQgFzLCfxZ 0SUfxlltxaHYBAFdkrQq6V896AN4MM/UGgmIjGybp45uBKyQS4H4NhLpTazDsGKChrfH X/N5MMTkyAqQ2yucBRbSez3CpMUubtB8zLVsKkvt7xS2teN5RBXo91wgO06/uhDENxnG BfGzezb+FmKXmSkX9HYxTF0mDYrqN9E3uPG+2EkeePneKRy+dtZPbj+5rnJwGtQQwgQE jlHr0MFlO7Z4fZgL5dgbQQsMg3hvETvZUBKq52Q95iHJi9qAUcDSgxG35Cde2GtvMK5q 8Nmg== X-Gm-Message-State: AOJu0YxQQj41411/zTsf6Pi/1sdRgDZ9NHp3RCED0d1smLsR2zlWnsE7 V7Kzlgnf4OUSKonT5CTW2P/hioibFM6g9zEgvGoFzJs5CRata+k7x21EC93cJ9L99zpTKH6aw9l CUBE= X-Gm-Gg: ASbGncsafX82ig+Y30VX6Bw9hWLohGLTi0wGlPxH3TBdPOgkBwtFleqA0EYcLdSKkzQ pgM8HMhTZ9o7y9ij/J905ZmLPQ4BCo8o8wBu/zmTDZMM9haQwGCPO0v46k+D0apo1ZhO/ozxwby 11YBLpK3llWVoSGM6rHU3+fMOoxuJh5c7KK+NVT0ZKrLSbCO4UB7CCgGW4KavP9S4L3AD4Bs7vS WZ1EXwrcpYWLHZugsz6ThZ8B5xlYjENt1Uz+Qikf0Ln4fKWrlZP2Ag3uF47Wo9h+SQpo7FIDAuI wAi+vhH1yRdZW07pdvpO6b+9aAIsC/Qx/X8Ivtl7+vFLXNx6hT6lzXccpg== X-Google-Smtp-Source: AGHT+IF++aw10p+JMjrAJMTYyjK4P3m9CsxNUT6eVRVxkY7GRbOqUaA81qo3Rv8dwD3KZz2jyIB4Sg== X-Received: by 2002:a05:6000:4007:b0:39f:175b:a68d with SMTP id ffacd0b85a97d-3a349699c4fmr6323255f8f.11.1747304768816; Thu, 15 May 2025 03:26:08 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/58] target/arm: move kvm stubs and remove CONFIG_KVM from kvm_arm.h Date: Thu, 15 May 2025 11:25:02 +0100 Message-ID: <20250515102546.2149601-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747304922303116600 From: Pierrick Bouvier Add a forward decl for struct kvm_vcpu_init to avoid pulling all kvm headers. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20250512180502.2395029-5-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 83 +------------------------------------------ target/arm/kvm-stub.c | 77 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 78 insertions(+), 82 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 5f17fc2f3d5..5bf5d56648f 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -94,7 +94,7 @@ void kvm_arm_cpu_post_load(ARMCPU *cpu); */ void kvm_arm_reset_vcpu(ARMCPU *cpu); =20 -#ifdef CONFIG_KVM +struct kvm_vcpu_init; /** * kvm_arm_create_scratch_host_vcpu: * @fdarray: filled in with kvmfd, vmfd, cpufd file descriptors in that or= der @@ -216,85 +216,4 @@ int kvm_arm_set_irq(int cpu, int irqtype, int irq, int= level); =20 void kvm_arm_enable_mte(Object *cpuobj, Error **errp); =20 -#else - -/* - * It's safe to call these functions without KVM support. - * They should either do nothing or return "not supported". - */ -static inline bool kvm_arm_aarch32_supported(void) -{ - return false; -} - -static inline bool kvm_arm_pmu_supported(void) -{ - return false; -} - -static inline bool kvm_arm_sve_supported(void) -{ - return false; -} - -static inline bool kvm_arm_mte_supported(void) -{ - return false; -} - -/* - * These functions should never actually be called without KVM support. - */ -static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) -{ - g_assert_not_reached(); -} - -static inline void kvm_arm_add_vcpu_properties(ARMCPU *cpu) -{ - g_assert_not_reached(); -} - -static inline int kvm_arm_get_max_vm_ipa_size(MachineState *ms, bool *fixe= d_ipa) -{ - g_assert_not_reached(); -} - -static inline int kvm_arm_vgic_probe(void) -{ - g_assert_not_reached(); -} - -static inline void kvm_arm_pmu_set_irq(ARMCPU *cpu, int irq) -{ - g_assert_not_reached(); -} - -static inline void kvm_arm_pmu_init(ARMCPU *cpu) -{ - g_assert_not_reached(); -} - -static inline void kvm_arm_pvtime_init(ARMCPU *cpu, uint64_t ipa) -{ - g_assert_not_reached(); -} - -static inline void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp) -{ - g_assert_not_reached(); -} - -static inline uint32_t kvm_arm_sve_get_vls(ARMCPU *cpu) -{ - g_assert_not_reached(); -} - -static inline void kvm_arm_enable_mte(Object *cpuobj, Error **errp) -{ - g_assert_not_reached(); -} - -#endif - #endif diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c index 965a486b320..2b73d0598c1 100644 --- a/target/arm/kvm-stub.c +++ b/target/arm/kvm-stub.c @@ -22,3 +22,80 @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level) { g_assert_not_reached(); } + +/* + * It's safe to call these functions without KVM support. + * They should either do nothing or return "not supported". + */ +bool kvm_arm_aarch32_supported(void) +{ + return false; +} + +bool kvm_arm_pmu_supported(void) +{ + return false; +} + +bool kvm_arm_sve_supported(void) +{ + return false; +} + +bool kvm_arm_mte_supported(void) +{ + return false; +} + +/* + * These functions should never actually be called without KVM support. + */ +void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) +{ + g_assert_not_reached(); +} + +void kvm_arm_add_vcpu_properties(ARMCPU *cpu) +{ + g_assert_not_reached(); +} + +int kvm_arm_get_max_vm_ipa_size(MachineState *ms, bool *fixed_ipa) +{ + g_assert_not_reached(); +} + +int kvm_arm_vgic_probe(void) +{ + g_assert_not_reached(); +} + +void kvm_arm_pmu_set_irq(ARMCPU *cpu, int irq) +{ + g_assert_not_reached(); +} + +void kvm_arm_pmu_init(ARMCPU *cpu) +{ + g_assert_not_reached(); +} + +void kvm_arm_pvtime_init(ARMCPU *cpu, uint64_t ipa) +{ + g_assert_not_reached(); +} + +void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp) +{ + g_assert_not_reached(); +} + +uint32_t kvm_arm_sve_get_vls(ARMCPU *cpu) +{ + g_assert_not_reached(); +} + +void kvm_arm_enable_mte(Object *cpuobj, Error **errp) +{ + g_assert_not_reached(); +} --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442f396c3a4sm65657855e9.26.2025.05.15.03.26.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 03:26:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747304770; x=1747909570; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=+6ury5Sg2Jud9itYU7h3OKlx8pJe0hJxXUnirJFm93U=; b=vpNslmbw+gzKOlII17nWYqzxxc48EtkrqbqTkv6QLobr8wcVYHjgY/WvudQEn2eNdN pyc8uw4trLsaQGqqLmeCovvAmK10ts026LCzwfIiFcZuxAPudEYWo5JiO96GZlb6LsRA M/XZ5MevUCyV1Bt17M74SbtGTqJPpuZyFBHK8HHpEr8TI22+c8abpvmR4ut06KmDEozo mF4mOwJL7MD048xnQVMXTLoUKAOSUtou8e58HVjZ7O27qsZBC8E0evyJug+UN6754DsF DhG5hoy/4b9R32xwz1d7qkAzwokNQLb3ziNBGXqJICWag7vv58cOtRGksmfVz/hunDLW BqkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747304770; x=1747909570; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+6ury5Sg2Jud9itYU7h3OKlx8pJe0hJxXUnirJFm93U=; b=F/kwZJzEWXxOOQ9WbRQ4c3cCRL/U4kaDIaaNi1F5yIcda4QUj3MnEEGhW5ImwdCwQi NA0V6ZxpJj/1r47Kh6ByzGsT9mnIKVo/LncjL+s69pT5d6varylfUPpkfxTdvVh2Gwxb 0oZsfmCRs8if/cKfBNXmdayL5AgIxIWWlVzTcnVT9Of2ozTqK7kt+f2XahC51LF7tBqR GxBHrszxOuXzbtD9YDS4+apZ2/V3pYKWQ8o6cGq1/nx+3wmOvldiPs1t+zYnNTU5Dy6G Z29EE9YrU92bjveajZ9SEfVJ2cSShhK6/FnQLielr8tYp9bCAWOEdJ98x9Iuu++APfyU y04A== X-Gm-Message-State: AOJu0YxXWJlAyHZJvOWNQdnRuTsXIW84PHb1GZtxbLUGVIDGbed4Cg1n /DAFz0YUE4RXE7ZTg04t+M0GR1TSGiMFAbDd1e4Dp7uyjpUd0sSLgvNE/WJCbfJH82237pmxAJt wiCw= X-Gm-Gg: ASbGncvYhLfzbA49m40cQcLcbxY9Qk0B3hTpVp7BgOyHLDDindtIAjwKB1hmCJhEX0l cCvWNbdCanZigk5FN0sZ2+M93OodsazyFgiUGli3xoHb9DrDCbIXsDuvXtDJwri6INgu32Mg84f Z4JBzqRCDThjOF1gvjGpo+4Oi0dLDMFPOGhaIqSZ2gED4u/KVbG8IXfRRO8gIalojBZA+AP2iVY 3wLxZpu0N79STqU/wsD1AOsRm+vTw1Rr9AtkpdeI3NzlfKbEkNlOLAgZmMpQIV0bGf3h4VOjOCz XitYbmH5oQqnHvqzD+gt/f/xggx2JannUZo8sS03WUDS1xRE2fOAPpmerA== X-Google-Smtp-Source: AGHT+IFDDQtrqxqe4Z8se7EPVpp2BwPBFRAoIi3J+dkn+959IVAVHBNADKiXKVehrcgEoC8ktmKouw== X-Received: by 2002:a05:600c:a014:b0:43c:ef13:7e5e with SMTP id 5b1f17b1804b1-442f970b0d5mr15516245e9.26.1747304769921; Thu, 15 May 2025 03:26:09 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/58] target/arm/kvm-stub: add kvm_arm_reset_vcpu stub Date: Thu, 15 May 2025 11:25:03 +0100 Message-ID: <20250515102546.2149601-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747304819119116600 From: Pierrick Bouvier Needed in target/arm/cpu.c once kvm is possible. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20250512180502.2395029-6-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm-stub.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c index 2b73d0598c1..e34d3f5e6b4 100644 --- a/target/arm/kvm-stub.c +++ b/target/arm/kvm-stub.c @@ -99,3 +99,8 @@ void kvm_arm_enable_mte(Object *cpuobj, Error **errp) { g_assert_not_reached(); } + +void kvm_arm_reset_vcpu(ARMCPU *cpu) +{ + g_assert_not_reached(); +} --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747304883; cv=none; d=zohomail.com; s=zohoarc; b=EdtwXXXs+4qFWthQr2aAeKlOKjbUTAlB8eQTTx+lA11WuRRsdIWglcCgREihZ6ST4YNPStKC1cfwKVZGTVmCsfNxKtGzrid37PuBmIXuNnZ+1YWdAXp1x2XtaftYg4Jt2tvgcH+eatMjhaB9t1guf4eCBxjOb/cnlw2EVg+Eg5A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747304883; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=FaYh3VlkdCKvRFw8QcW3CmdcVFOTvth6Gi2E4GKc2o0=; b=BPhOgHGsBUu/w4tSh5U6i6RHjplYKTxHuAXMtnd9Q8Q+glY/1DU+nfOo//cF4wviTDgnlH3ymcrgsJz+bdCTClBvSUWFvCZRamFakTyXnS3jMU6p7qMuYyc8crjsvE6tgFn8A243cpEe07mvIrenqXJ5Voyzd7WlA4st0XZi7xE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747304883597838.1889299664035; Thu, 15 May 2025 03:28:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uFVnF-0004uE-Ca; Thu, 15 May 2025 06:26:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uFVn6-0004Zu-RM for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:17 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uFVn3-0008A7-DV for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:15 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-440685d6afcso8443035e9.0 for ; Thu, 15 May 2025 03:26:12 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Thu, 15 May 2025 03:26:11 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/58] target/arm/cpu: move arm_cpu_kvm_set_irq to kvm.c Date: Thu, 15 May 2025 11:25:04 +0100 Message-ID: <20250515102546.2149601-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747304885727116600 From: Pierrick Bouvier Allow to get rid of CONFIG_KVM in target/arm/cpu.c Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Pierrick Bouvier Message-id: 20250512180502.2395029-7-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 2 ++ target/arm/cpu.c | 31 ------------------------------- target/arm/kvm-stub.c | 5 +++++ target/arm/kvm.c | 29 +++++++++++++++++++++++++++++ 4 files changed, 36 insertions(+), 31 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 5bf5d56648f..b638e09a687 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -216,4 +216,6 @@ int kvm_arm_set_irq(int cpu, int irqtype, int irq, int = level); =20 void kvm_arm_enable_mte(Object *cpuobj, Error **errp); =20 +void arm_cpu_kvm_set_irq(void *arm_cpu, int irq, int level); + #endif diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 603f08d05a0..66047693415 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1098,37 +1098,6 @@ static void arm_cpu_set_irq(void *opaque, int irq, i= nt level) } } =20 -static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) -{ -#ifdef CONFIG_KVM - ARMCPU *cpu =3D opaque; - CPUARMState *env =3D &cpu->env; - CPUState *cs =3D CPU(cpu); - uint32_t linestate_bit; - int irq_id; - - switch (irq) { - case ARM_CPU_IRQ: - irq_id =3D KVM_ARM_IRQ_CPU_IRQ; - linestate_bit =3D CPU_INTERRUPT_HARD; - break; - case ARM_CPU_FIQ: - irq_id =3D KVM_ARM_IRQ_CPU_FIQ; - linestate_bit =3D CPU_INTERRUPT_FIQ; - break; - default: - g_assert_not_reached(); - } - - if (level) { - env->irq_line_state |=3D linestate_bit; - } else { - env->irq_line_state &=3D ~linestate_bit; - } - kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); -#endif -} - static bool arm_cpu_virtio_is_big_endian(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c index e34d3f5e6b4..4806365cdc5 100644 --- a/target/arm/kvm-stub.c +++ b/target/arm/kvm-stub.c @@ -104,3 +104,8 @@ void kvm_arm_reset_vcpu(ARMCPU *cpu) { g_assert_not_reached(); } + +void arm_cpu_kvm_set_irq(void *arm_cpu, int irq, int level) +{ + g_assert_not_reached(); +} diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 85911e30242..82668d64385 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -2428,3 +2428,32 @@ void kvm_arm_enable_mte(Object *cpuobj, Error **errp) cpu->kvm_mte =3D true; } } + +void arm_cpu_kvm_set_irq(void *arm_cpu, int irq, int level) +{ + ARMCPU *cpu =3D arm_cpu; + CPUARMState *env =3D &cpu->env; + CPUState *cs =3D CPU(cpu); + uint32_t linestate_bit; + int irq_id; + + switch (irq) { + case ARM_CPU_IRQ: + irq_id =3D KVM_ARM_IRQ_CPU_IRQ; + linestate_bit =3D CPU_INTERRUPT_HARD; + break; + case ARM_CPU_FIQ: + irq_id =3D KVM_ARM_IRQ_CPU_FIQ; + linestate_bit =3D CPU_INTERRUPT_FIQ; + break; + default: + g_assert_not_reached(); + } + + if (level) { + env->irq_line_state |=3D linestate_bit; + } else { + env->irq_line_state &=3D ~linestate_bit; + } + kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); +} --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747305346; cv=none; d=zohomail.com; s=zohoarc; b=N8lWsNdtu0/B/9JSFR8mM/Gpqn39MiWpNZfyEOLC1vfoTLIjx6wJMwrAbnPhFj/O743bAMuEQGCBpuBP4J0ei8f5tEq4Y3X0L9jaYawWjztF/QSDSZFe4/2WlYIE8fIv8E9YeoWLIpXW75jjc8ZlOh0pnRB/BS4EXU6/6lBqnAs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747305346; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442f396c3a4sm65657855e9.26.2025.05.15.03.26.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 03:26:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747304773; x=1747909573; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=NyucHiYe/4GviI/GxcYBQGa71mt/U6jQw0yXKQyqmn0=; b=Sl+MJctAAI5E1mqTHDKU8hrIWKtBmQgkrwWxmYGdq7Iaw6GIVyqK5nPMPTYkcxT/nR 1XR92lQyd/PfKTygKcBPKkA9LkD55CpFUyfE64wwGy/V/hWBk3tFM87wW86nnrE9bxPJ LkhMeglq08znvYzQ7GZK9qMvICvGwQ6rYvF/HmJt6AOirYO7iO1FGiplHry4prrUgtpS 9a/Ko6jwzWr8okxH2bHidwsb1giqh5RkJo6LTA4S3agHarjekXZanWWvljlgfODaGodq lcS+nwFpMtUNSK42BXxRb3ohaY4l+6BpD1s3ahjr9+iKWtI3egoY/xGPKtWPO9jfZDO3 XowQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747304773; x=1747909573; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NyucHiYe/4GviI/GxcYBQGa71mt/U6jQw0yXKQyqmn0=; b=TgO/LHY5xFrS+C5pJ2lfF05qIQUf5Zsxe+v7tJtNXdsB1xXlrLh69FFQPXV4ZZCA4Z 7S4GYfqv+AGQ0NROMl2fwl1sF3IHkA08lInQyTp/3bhmrG2tNcTk4D8DkZMUq1hY9/p6 C1oTYbkWHKDeSeOvZ+VoSsXaCuf9cBi2DoExRmkY8Xjr6xTUeAXSYSMRLpi/r6tC+Qlb cZgasKUG0xWQiIoOtb2A/20WcCeiUUTRgls86PZ1FRuGF9PyTmTYwEfGFaYuG/byhGn1 tGQTjwwLcXSCE/zt88fZgK+3wad3OuQUlxRQV19aei4kWtcm3FMV20/q9/uOzo7mO13c NSog== X-Gm-Message-State: AOJu0YzAH3K9CB9BXPNJwwB2AZntkYXaWBAMYz9gkr6HFZ1Xbv8jN+eq 8YhuJfAOd8I9arx/1tC4+dPJAXFNC7wS0Cd7jntfkz1mrGnHe7EUKxxdvZf5jT9mYvnSoV73JWX WVG8= X-Gm-Gg: ASbGnctQyfGEQkn08SZpyT/tUJs16esslSj87gGfsR+WX5prYu8GYkPxFDpp0KDxiUA HyYVsPypwwDHS3jckjNZzM82l4dQwRxBgrkLwhTOaICJsDpBac9riZ4YY0dU2ksu1Z2kn5W2k3j JPwp0TSZEkaV7rgo04WmseV5AY6jkjlDBOe+G/CHNu+K/IlKK2WXK8CfPPvo4sHjWwianrwYY67 gRIELRcBt0NZDBWbie+mhwF37YnR6KfAfv/dCb+b0CeNOsXtIk5dlm22ULbdTIUgCYq44lN8ZNl ceGQp5cZBZT5CPGTmBCxb0PqL/O00TfGv4FMhAxD02Tz0bjtGEZOAsGO/A== X-Google-Smtp-Source: AGHT+IGnR2GHyBea4gaX82ziwXlMzNKX8P4ywH9sE+rgI4wQv3cddtqVNABt9h/U/UA8/Pt7yTEDKQ== X-Received: by 2002:a05:6000:4007:b0:3a0:88d5:7fca with SMTP id ffacd0b85a97d-3a3496999ebmr5471488f8f.12.1747304773392; Thu, 15 May 2025 03:26:13 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/58] target/arm/cpu: remove TARGET_BIG_ENDIAN dependency Date: Thu, 15 May 2025 11:25:05 +0100 Message-ID: <20250515102546.2149601-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305347873116600 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Reviewed-by: Richard Henderson Reviewed-by: Anton Johansson Signed-off-by: Pierrick Bouvier Message-id: 20250512180502.2395029-8-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 66047693415..c7e00e64325 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -23,6 +23,7 @@ #include "qemu/timer.h" #include "qemu/log.h" #include "exec/page-vary.h" +#include "exec/tswap.h" #include "target/arm/idau.h" #include "qemu/module.h" #include "qapi/error.h" @@ -1171,7 +1172,7 @@ static void arm_disas_set_info(CPUState *cpu, disasse= mble_info *info) =20 info->endian =3D BFD_ENDIAN_LITTLE; if (bswap_code(sctlr_b)) { - info->endian =3D TARGET_BIG_ENDIAN ? BFD_ENDIAN_LITTLE : BFD_ENDIA= N_BIG; + info->endian =3D target_big_endian() ? BFD_ENDIAN_LITTLE : BFD_END= IAN_BIG; } info->flags &=3D ~INSN_ARM_BE32; #ifndef CONFIG_USER_ONLY --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747305484; cv=none; d=zohomail.com; s=zohoarc; b=XJJIVLef1xUt5/6YcNVr0yKtyIgQCUVAHdlIglaYZYoNLbikeaHFUOR+x8/FIGurJV8q1J3R5iqq5ClL3uZHbm7hA0ED5Bl7sWR/3OJriYnOyB0sfFw4hrOi9K2apGBRhmEArsNrclsHU8uZh1HiG+I2HNKEBqYIt6/tEIMKrYs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747305484; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=8Dy35+lWv+I9/27nBCmYWY9enGRMPHxuuOHBDG39r8w=; b=W1T+phU27/x5ch0w0OUTn+Hv1LzWWWRNlE+JNDimi0oJCzhcisutA7VLO//9lARqn00jrnqtxKeCrC/bEq2D7q/qKe1orJTQiY56OurXQe3Hfoblv390HShSabFjaVkT4oC7VUs12sXYr5/mKaSevJ0iiYC1XV6VheOGdppvrLU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747305484534249.69841923866124; Thu, 15 May 2025 03:38:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uFVnu-0005fC-BP; Thu, 15 May 2025 06:27:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uFVn9-0004f3-Lo for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:19 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uFVn7-0008AX-Ku for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:19 -0400 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-43cf257158fso5247835e9.2 for ; Thu, 15 May 2025 03:26:15 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442f396c3a4sm65657855e9.26.2025.05.15.03.26.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 03:26:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747304774; x=1747909574; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=8Dy35+lWv+I9/27nBCmYWY9enGRMPHxuuOHBDG39r8w=; b=CiJh5cxgTUOrZlT0zNgLpGafG1jhFbrxrPYnQaPMcOeXmgVWT1KDNsJ6Bgxpbyyyd2 Bj6erS8bqxLT5H1o1TtPcvfm9VLGwf16HVAJS1OXZgHKCx+1bysJxBOCdBb5TMFwuCYM PSsmaI63BDCxB3R8A6T+vyjTKUOytQP5eZXPP6MzLPx+D+aQ1wNUyMpX30i54owMPKXS 28uKA1urNKB0ruSDZeydQlks58ZbIBeVtUe01LCFI37kZhD54fgAZ+HL+q2+D+2xnC61 KvY1JB3r8RtdTgfofjR0w+RziMSxGtjzMUArSOAGSJ5YI+lVE/nXzReyh6pTi8r11Z4x +3oA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747304774; x=1747909574; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8Dy35+lWv+I9/27nBCmYWY9enGRMPHxuuOHBDG39r8w=; b=eH/0BBgZfouI/PI6mA5SffsPkaeEDroDPj/Vve8L1eshWGXVs8mAsZRoEdv17hfpKI UcbSvFt1KlE4grooJsnQI8kFypKdX4wW/ZWvks2ivnZlqnw+DQGdKJmsL551N0pKE+uJ UOLDYe3vUrWF64ccBqvpaSSMGY6z4lAZt+hLIk7o56HpR36vLJfAkIE3NfhAHTvSmsFk wag7zpgknMI2Jk8gFZZLvUKnLAhD4NLwOBny8B7x/gsp7OIZD6mBMM9lhy0HypJa6p0w l6gq7by1/r9CWExjLHib1ffpILcwL/PJ4Hr1wE7sxKXGsgs+y9hIUNmH9KdW9M/gBNd+ UmyA== X-Gm-Message-State: AOJu0YxyTJMgqK9e67FfSDrSsBotUHDu3dSBxmINmtPawCv70TecWdZ+ lcVVmE1noNC+V6Q+IQrb9QIUDcP+6KwikroxsmHG1Z5X10BcVyGcSW8RwawUOguyelOgYsF0Wa8 P3wg= X-Gm-Gg: ASbGncsuzq/GrzgXJAjygf6zZIPlDUhNuK5gDuNC207wwwM2l1wdyQn7lkSjCWaOdev QOycH9Nx3TIUqM6KryrCZzOs5Yy0GnGBLQzodxCXBObnWkJ7cYtyMR+5GvBnDg8jsQizmiE/q0R M8IA71uyqQ/gjK8eUCFVNV1yYfQYothj05ebURPYdGotklkv/DfcPT925i4IekvGSwrNQcTwJVk ROwMNFG3gWfl5ZNB0Kau2L6NFdcKARoogecJtMx1c5rWlfFUpHH0GmvnPKON3pVjoMZcP242wz1 SgwgHz+U71vaT2i3TvfFDNA5vFAKED20NN/QKuthlXzxLD66MAiTznv+7g== X-Google-Smtp-Source: AGHT+IEux5BITD43FWgl6eNKalTYpC6/BmLEc1Dou2+Hx4D4PtdVw/cQtd3Yrs0YXLxGN67vlVnzZg== X-Received: by 2002:a05:600c:a014:b0:43b:d0fe:b8ac with SMTP id 5b1f17b1804b1-442f9714d93mr20815915e9.30.1747304774408; Thu, 15 May 2025 03:26:14 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/58] target/arm/cpu: remove TARGET_AARCH64 around aarch64_cpu_dump_state common Date: Thu, 15 May 2025 11:25:06 +0100 Message-ID: <20250515102546.2149601-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305485123116600 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Call is guarded by is_a64(env), so it's safe to expose without needing to assert anything. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-id: 20250512180502.2395029-9-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index c7e00e64325..ec9bc72c3d6 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1182,8 +1182,6 @@ static void arm_disas_set_info(CPUState *cpu, disasse= mble_info *info) #endif } =20 -#ifdef TARGET_AARCH64 - static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) { ARMCPU *cpu =3D ARM_CPU(cs); @@ -1341,15 +1339,6 @@ static void aarch64_cpu_dump_state(CPUState *cs, FIL= E *f, int flags) } } =20 -#else - -static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) -{ - g_assert_not_reached(); -} - -#endif - static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) { ARMCPU *cpu =3D ARM_CPU(cs); --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747304819; cv=none; d=zohomail.com; s=zohoarc; b=SK99dnUtdcY96YAs64RiacTJzfYiVzaoDw6EaTJLkzmi8iOaFNh7KVY8HtpvRJFsVas01uHP/ibO7gq1W2CPbGtgag74htQwkPuXxMaGJKNjwqR97Nah9+YdmTavAlQwftwjV3IToGl/34U/pV59r89unqfYZ+GV2zDsMdNTlZs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747304819; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=RG8Ka89WGECPxEN9oHVhNLbmDepbN7rDBbuob6DhDg4=; b=Uy4zsoKQALbwJBtkPGpmMylf/9Nz35IYbK6V3Fz4W7qNhnsJePMigB3UnEcC/8sa424ccCLYcfCtx6/k4BUsLrNchw2fqbasgh5DBosVC3qv/7x8yheKBWqGAcJrbMU0EoEZlmBwwzK+sSyjIO6mdlNYSp25Kh5fRvyZUSeK6Q0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174730481996650.69195453216321; Thu, 15 May 2025 03:26:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uFVnJ-0004yb-KD; Thu, 15 May 2025 06:26:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uFVn8-0004cO-VA for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:19 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uFVn7-0008Af-5n for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:18 -0400 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-3a1d8c0966fso530966f8f.1 for ; Thu, 15 May 2025 03:26:16 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442f396c3a4sm65657855e9.26.2025.05.15.03.26.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 03:26:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747304775; x=1747909575; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=RG8Ka89WGECPxEN9oHVhNLbmDepbN7rDBbuob6DhDg4=; b=se4HmPfr6ryKxfn9E7+km11kM5AJ3U/zw3vAN2k4jgWKyML1X0reLjrGWGsYrSaFhG uSAbc8VS99WGAxyYn39KFZWfHbJFDuLKXnPj7j2M40aa6q3cT+KW1J0whKvkf5ghpbSc hzUH51YiKJJctFK1/c9YTnzKcu4TD3O+jwYAozbVuc6boUIbHxpwlTrb+L7fXN+gZwew 4P821+9vgEgFpd8+nLBtGu1WOsp2Q9sme2Vb6OXaxTuZ9hEv7DrzPwIzIUmgPClt09Yp y6S4EaGMJ5GtqluJvdJx/siEQSCCebQ8A2Z6i0/ipqhObgavEWS4hs+ted0v/gIBwPM9 zJoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747304775; x=1747909575; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RG8Ka89WGECPxEN9oHVhNLbmDepbN7rDBbuob6DhDg4=; b=MInsAtC8Uf8ueunT0d8aXkQIzyx+aHHK/2OjqeZkz2fu8cYHLldjC0B2ao08mLcTFg ycyoFu8GXJaftSkzO6hWqAQ6QQ76Z2EbCiWMwfTvox7H/qG0yaBmv8LUcJ5K4HoY7+jf e6hLCdDazgYuolKlD6i202/MI7+BK8nxv4YLh0Ucq2W2mjezM3tGE1b/x1UDmdhdVB8V WvHiWIXrloFh5l1bBmDbeVdlv93ths4c4WAqbHD6zi7T17/cIoZtBy1qAmMTSUhRTb+E t5fUPRbDyFoAgKe6gMKJc+qBxXjjhav1TcdAPzH/QsYsjpWSXYQN1ysSmrAl3FK7mQsz vYYQ== X-Gm-Message-State: AOJu0YxOK0q4SOMq4BojN/tEp9pOw20kL9BLx2vk49XEVjFXnwwSVDB9 SpYp7MBA8g447X5Qh79hAiVx/92JgcoQXl2Q9kbqhS3naumjkj8B1P5ZlZ4GfJIIhogNp7t+XZG jv6xqjIE= X-Gm-Gg: ASbGnctifTtY6rMflW24IjQ71by0mhf8VqEXYzUFUSOc207jPBs82u+u37NRPPT5AB2 5wU7QhLv+oo/AwGdtZdSBRDQ/A/evAIldlxW65MvUvnpm9BDImkSG1jRlhk7BlADz8mUAS2n7LS pqSVfvDK6yM2oPTvfNMl+qrAQKwhSE/Ou25W9VptHb6RFilTeezhJzXwC8aqOGK46AaLLCwHlge 5nZKnrfUpQHe9P85DVOxOtbmokq7HihqLdd6XLWYBbjXi30AcI5B+Gsbri6D/WDxPKnfL5qTlsQ bi6JKchtqHF7AGeLMU+9/jM3g0cTjietO4WwDddZrJ11LjN30J05mhf6pg== X-Google-Smtp-Source: AGHT+IE1BLszunUFW8kOr6VdkRYO7w48uBOhjgUsErGAKRDeUrrlxU77B2+lqzKpRLb38/LWTA/sSg== X-Received: by 2002:a05:6000:2a5:b0:3a0:b817:2d7a with SMTP id ffacd0b85a97d-3a351222edemr2489026f8f.29.1747304775317; Thu, 15 May 2025 03:26:15 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/58] target/arm/cpu: remove TARGET_AARCH64 in arm_cpu_finalize_features Date: Thu, 15 May 2025 11:25:07 +0100 Message-ID: <20250515102546.2149601-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747304821027116600 From: Pierrick Bouvier Need to stub cpu64 finalize functions. Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Pierrick Bouvier Message-id: 20250512180502.2395029-10-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.c | 2 -- target/arm/cpu32-stubs.c | 26 ++++++++++++++++++++++++++ target/arm/meson.build | 11 +++++++---- 3 files changed, 33 insertions(+), 6 deletions(-) create mode 100644 target/arm/cpu32-stubs.c diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ec9bc72c3d6..ca5ed7892e4 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1913,7 +1913,6 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **e= rrp) { Error *local_err =3D NULL; =20 -#ifdef TARGET_AARCH64 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { arm_cpu_sve_finalize(cpu, &local_err); if (local_err !=3D NULL) { @@ -1949,7 +1948,6 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **e= rrp) return; } } -#endif =20 if (kvm_enabled()) { kvm_arm_steal_time_finalize(cpu, &local_err); diff --git a/target/arm/cpu32-stubs.c b/target/arm/cpu32-stubs.c new file mode 100644 index 00000000000..81be44d8462 --- /dev/null +++ b/target/arm/cpu32-stubs.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include "qemu/osdep.h" +#include "target/arm/cpu.h" +#include "target/arm/internals.h" +#include + +void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp) +{ + g_assert_not_reached(); +} + +void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) +{ + g_assert_not_reached(); +} + +void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) +{ + g_assert_not_reached(); +} + +void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) +{ + g_assert_not_reached(); +} diff --git a/target/arm/meson.build b/target/arm/meson.build index 3065081d241..c39ddc4427b 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -11,10 +11,13 @@ arm_ss.add(zlib) arm_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm.c'), i= f_false: files('kvm-stub.c')) arm_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c')) =20 -arm_ss.add(when: 'TARGET_AARCH64', if_true: files( - 'cpu64.c', - 'gdbstub64.c', -)) +arm_ss.add(when: 'TARGET_AARCH64', + if_true: files( + 'cpu64.c', + 'gdbstub64.c'), + if_false: files( + 'cpu32-stubs.c'), +) =20 arm_system_ss =3D ss.source_set() arm_system_ss.add(files( --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747305346; cv=none; d=zohomail.com; s=zohoarc; b=FAij1Ka/KtRjME8r3RtIW+6bTWg+FCgH+zZPUpZvH2uON/3tUJpW9OW/LnrtJyuCyHfpV8wbgwEd+4VYkDFi2Y5dPFCHv+mQbVOPNUsJWgg0R2jrN30W71pg8PTOdSFsOYECb7l32o1m/dyXYYBreZXqhQJfWrRI7gGuQSLCMG4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747305346; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=5iuDbPPf5lEYT71cv+B0giQZmGA3HvyTgZbPr6A9ErE=; b=D3BWf+BTVk4mx9nYuyEZJWfFEdHgB+tu818h+ncJ9F4TTIHiVXLFF+rF/z0TT0WdP6cu9HiKdQcjSiB2noWqDSa+W7xj8mgRriV6YN50bJ0/XMXLcOEIhcwy9OBdsrYvNiOXSsegWVxSCtWq1PayXvt1xPsjddfjVq+oLr0ESRQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747305346218925.8135625770041; Thu, 15 May 2025 03:35:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uFVnc-0005Ks-9E; Thu, 15 May 2025 06:26:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uFVn9-0004gJ-TT for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:20 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uFVn7-0008Aq-Q7 for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:19 -0400 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-43d04dc73b7so8012725e9.3 for ; Thu, 15 May 2025 03:26:17 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Thu, 15 May 2025 03:26:16 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/58] target/arm/cpu: compile file twice (user, system) only Date: Thu, 15 May 2025 11:25:08 +0100 Message-ID: <20250515102546.2149601-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305347893116600 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-id: 20250512180502.2395029-11-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/meson.build | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index c39ddc4427b..89e305eb56a 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -1,6 +1,6 @@ arm_ss =3D ss.source_set() +arm_common_ss =3D ss.source_set() arm_ss.add(files( - 'cpu.c', 'debug_helper.c', 'gdbstub.c', 'helper.c', @@ -20,6 +20,7 @@ arm_ss.add(when: 'TARGET_AARCH64', ) =20 arm_system_ss =3D ss.source_set() +arm_common_system_ss =3D ss.source_set() arm_system_ss.add(files( 'arch_dump.c', 'arm-powerctl.c', @@ -30,6 +31,9 @@ arm_system_ss.add(files( )) =20 arm_user_ss =3D ss.source_set() +arm_user_ss.add(files('cpu.c')) + +arm_common_system_ss.add(files('cpu.c'), capstone) =20 subdir('hvf') =20 @@ -42,3 +46,5 @@ endif target_arch +=3D {'arm': arm_ss} target_system_arch +=3D {'arm': arm_system_ss} target_user_arch +=3D {'arm': arm_user_ss} +target_common_arch +=3D {'arm': arm_common_ss} +target_common_system_arch +=3D {'arm': arm_common_system_ss} --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442f396c3a4sm65657855e9.26.2025.05.15.03.26.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 03:26:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747304777; x=1747909577; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ZkRqD+LMx6swHQ6xUEIIe9lCbzC5g6w0oxlU/fhgdns=; b=xrtVaEQm9jSjMWAhfgxfzNuJ7t9MrRWT6xnCCusKvbwOaoi4BCwU8T0VpLG2gD7V2d Per4h4YwYuBCedbGJueC25cubgveFeL0dVV+NbHjxeGkBIuvSTfUNOr620zcjlU7/eWv 1cW4ivrDzP5jyLeO/h8YNtPTzi5g28R9/yvldo8UlC57HXmENVmzZFFcN1hOp/S2G1D8 7MG49ZNGmoUaK3dqsCdSUJBG1huRztEWwoNWJwtBGdilmLCYruqY1t/YG2ivyrLfJpvt zGD+aSPIPeLZAKX6kuD/AYAh3NFfAtwR8iNsjSwgI7dxYoGNWNl7+jCv3lSGbZdzNcg6 4YZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747304777; x=1747909577; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZkRqD+LMx6swHQ6xUEIIe9lCbzC5g6w0oxlU/fhgdns=; b=m1PpK3cVW5LWtL0n138gqBRyhR+Fbmw5VJiNT2FqQWjomL1fdueX9B4DFTw8lrlGD6 YiRdyH7xi4ucS8mio/X/PaIXpl4IBL7EgSHwS2i972XI1uBjX6nm2Q5zr9O+1pkiRGD4 4D0GKAKKoSDHImxMQPlMIgHWfbDnBrzCPSmJYHqmJFl1HjhDWbwEScv7DrF7Wwsegiqm 4Sv59k6TTskr6EBtxg+Pvf+SmThOQhjt0HHtl3PjMHwH9TJJKNP1ZapkcdVmxRjcWar8 0+D1KWf9gSLvruY87/hTSdiEkfxJ0T8pVc41pj0fH+lVNDfqpakzCfXzTKuWdQslNQcD vATg== X-Gm-Message-State: AOJu0YxlK5509Ky1Rx6bc51SsSzllfzDSFBJ/0mhZ6faFEP1BObjixKP zxCzpwo/ibzNkEDbD+Xgk21JMrbZGiH4KtMGBQKkpJiXx6dG6w460XtYRCIE9NX8nwVh6lqg7xZ upwY= X-Gm-Gg: ASbGncsGPdW6socxIqG5FV3VIn5gyCozwxf1V8W3Df3xZb4QTgSuHq84oxqCEbgCyuM OJY5jHcODURCUUViRTSRusNEAu/1AAIDzwryL9IIy+mwkplv0szowRI0NM1+7Ob4VQR3iIMjvJY MalTQU1b6FSaa8fVg9C6tsvGYlHQFTVnlhryJ+wpbDnWfPZgEMLlmdXwGdNcc4CKOYsqozvWkPx X7s2hOBTjMgQ0vb37+Z8oeIhgBx01qMm9pJc7fmymPsODahmo9E6H+349BOZ/Ty7rkFTYXV9r9A I5h+MZwr4Nv3pNBCdYfcVraXX65NCyL3ef3/gP4mwGLJz123GWu5u/R4+Q== X-Google-Smtp-Source: AGHT+IF5O7HbINRD69gyaPxOPZyNjz5dF2FMdUWYEBmFax0WLG7DrmBZvTmfaGLRVSQIsrhQPlZJJQ== X-Received: by 2002:a05:600c:1d1c:b0:43c:fda5:41e9 with SMTP id 5b1f17b1804b1-442f2178679mr71249315e9.31.1747304777280; Thu, 15 May 2025 03:26:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/58] target/arm/cpu32-stubs.c: compile file twice (user, system) Date: Thu, 15 May 2025 11:25:09 +0100 Message-ID: <20250515102546.2149601-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747304895616116600 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier It could be squashed with commit introducing it, but I would prefer to introduce target/arm/cpu.c first. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-id: 20250512180502.2395029-12-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/meson.build | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index 89e305eb56a..de214fe5d56 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -11,13 +11,9 @@ arm_ss.add(zlib) arm_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm.c'), i= f_false: files('kvm-stub.c')) arm_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c')) =20 -arm_ss.add(when: 'TARGET_AARCH64', - if_true: files( - 'cpu64.c', - 'gdbstub64.c'), - if_false: files( - 'cpu32-stubs.c'), -) +arm_ss.add(when: 'TARGET_AARCH64', if_true: files( + 'cpu64.c', + 'gdbstub64.c')) =20 arm_system_ss =3D ss.source_set() arm_common_system_ss =3D ss.source_set() @@ -32,8 +28,12 @@ arm_system_ss.add(files( =20 arm_user_ss =3D ss.source_set() arm_user_ss.add(files('cpu.c')) +arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files( + 'cpu32-stubs.c')) =20 arm_common_system_ss.add(files('cpu.c'), capstone) +arm_common_system_ss.add(when: 'TARGET_AARCH64', if_false: files( + 'cpu32-stubs.c')) =20 subdir('hvf') =20 --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747304883; cv=none; d=zohomail.com; s=zohoarc; b=BtcI/hfs5Gdz/ijam3UD4fRG8jFMVY/KLgZ74stXCLMWHdU5nPNl7xSNJ4wbFUld6q3S+9cwfOkdlcxXmq6CBaD+vIFO6JM5Rpc3OhVWdRZClxHIfGIv2HtZ3zp3ihNH6Q5We/vqt/r+FfQf2qUznGWvTGlzoL3IC3ZLzTva89M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747304883; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=JBwP4MINLJbGQNTaVfNpgXGCUDV61F8mAdNh5p7lyQQ=; b=DREW1b/zC2SW8/qfTB56eq0xFxl03FtXWeZ44GmH+a9w1ne2gQ74CJBTFWklqL6Fk9zFOFmCSs501bgIVvGAiEX0SQnleL44zTBXS9T2dHE8s3ha2Vh9e04TbnkQWdef8f4WgXu5cgbm1wB3MBZhpMHZS6Ihxax7ijEdkVGs8Lc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747304883661852.2398832191784; Thu, 15 May 2025 03:28:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uFVo9-00065E-U0; Thu, 15 May 2025 06:27:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uFVnB-0004ot-Rz for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:21 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uFVn9-0008BE-Rz for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:21 -0400 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-3a206845eadso427406f8f.3 for ; Thu, 15 May 2025 03:26:19 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442f396c3a4sm65657855e9.26.2025.05.15.03.26.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 03:26:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747304778; x=1747909578; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=JBwP4MINLJbGQNTaVfNpgXGCUDV61F8mAdNh5p7lyQQ=; b=PKsc4F5CRS4zcTDIm1s32VA3CEvfJAnm1cDEui6MQ/4cy7JWx3dUyeADSFcJDDw9HX U638S0wIleTnv0HYFvneL3nX/7C13k3x8cm98kwbwpUbrdEXBRU9sGl1y8YwdrdN+cXe hqff1fzB9OyboWw1pWXZHsr7zR5I8302vd+Erfaag5jgxZD6vX+stWMqJsMU9rAkc0K0 bZmkewarMAnwI0vr+FN4FmT11vXXq5okNX6eTgHLA0vf0t0fspBX5VjVwQvoZeTgoR6V JncSY+t+67ALMmzyoC5chGe2DrI7hP6CVtVq8Tlr+sL7XP7QV+f4aXGa/hfjukcVGkBK 4BaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747304778; x=1747909578; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JBwP4MINLJbGQNTaVfNpgXGCUDV61F8mAdNh5p7lyQQ=; b=Lxl3pF3YxNTK0a+aGYf4o6ocwF8FkoGUXo1T8DL7LrxyIiCxRNSXyH2o285DCE2mmF ZQdwKNqT2vKm1Rp7Cn2bvZkOQ/8S7nZCGjvUqP0qkojHQrp80uV3L7t5tn1shP95iDl3 TAEqJoYLxfxBiFVC+MHfcCl7Ia/YRlebo3S8YuggGr6LH/RjV5twLPBZtCguOHtezway rzUAcAXvpYHU9vCHgsB8jNLb+fGL9x9SHKU9L6PB5ik7WGIkZy9LducIdwxSO8hx9efs vggvIhWXqo/WlGUrfSmQLAW7n4fhygolEBGbNWJtXqQdpH9+jR/FT86XvT8IHra/MoIp kIzw== X-Gm-Message-State: AOJu0Yw9N5LQxw/Sd7J5B4M1MllNoOGBTUlSCNl4Cydf8cy591nGn87D ZdVI3re3E7EXLAschhApeGyVIkL0Jg8QJCQVq8mXGccUBnaSILXVPbg0l4P/9vgtywUTBApFcTj jdEU= X-Gm-Gg: ASbGnctpBFd3CcldbnZgglOg6j/FRcndOubiR9dhInib1HSkmQ0z4OVrJojSsG7LPfF AZ+8inCRbfedb7KE3tXedlDcGaC8gZJfy4lGIaf33V5St7KFXupsWYVgGhIq2EhrGESk1V2N4Dw 2tY2Chn/QlS/Ygy01mDYVwOPji5X+/fwVg5QXCodx+nI9TDLrhKPFvCbVzDW/oyLVpTaT/zUM0o pcWvxUvtulWn+5I/2CLUiyQcMvOLgSkGA4maAHmn40TIdVWxQDO32FRqBpjoKhsYtCv96ArHQv2 FqChsABFHKSPrF7jdMlWrZjvN+n7rXnt1JBXRVenQFnNP72CtHY2XFTSGPR7ZnAKlXO3 X-Google-Smtp-Source: AGHT+IGtOQlUXFzwrnfc12eEZhS72PYLuZHeqzaV60tY8lD4yR24nuiRcKt6AKL17Swek2FWbMVt1A== X-Received: by 2002:a5d:598f:0:b0:3a3:4a1a:de6f with SMTP id ffacd0b85a97d-3a353748601mr1742158f8f.26.1747304778277; Thu, 15 May 2025 03:26:18 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/58] tcg: add vaddr type for helpers Date: Thu, 15 May 2025 11:25:10 +0100 Message-ID: <20250515102546.2149601-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747304885693116600 From: Pierrick Bouvier Defined as an alias of i32/i64 depending on host pointer size. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20250512180502.2395029-13-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- include/tcg/tcg-op-common.h | 1 + include/tcg/tcg.h | 14 ++++++++++++++ include/exec/helper-head.h.inc | 11 +++++++++++ tcg/tcg.c | 5 +++++ 4 files changed, 31 insertions(+) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index b439bdb385a..e1071adebf2 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -14,6 +14,7 @@ =20 TCGv_i32 tcg_constant_i32(int32_t val); TCGv_i64 tcg_constant_i64(int64_t val); +TCGv_vaddr tcg_constant_vaddr(uintptr_t val); TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val); TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t = val); =20 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index a8c00c72cc8..3fa5a7aed2c 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -189,6 +189,7 @@ typedef tcg_target_ulong TCGArg; * TCGv_i64 : 64 bit integer type * TCGv_i128 : 128 bit integer type * TCGv_ptr : a host pointer type + * TCGv_vaddr: an integer type wide enough to hold a target pointer type * TCGv_vec : a host vector type; the exact size is not exposed to the CPU front-end code. * TCGv : an integer type the same size as target_ulong @@ -217,6 +218,14 @@ typedef struct TCGv_ptr_d *TCGv_ptr; typedef struct TCGv_vec_d *TCGv_vec; typedef TCGv_ptr TCGv_env; =20 +#if __SIZEOF_POINTER__ =3D=3D 4 +typedef TCGv_i32 TCGv_vaddr; +#elif __SIZEOF_POINTER__ =3D=3D 8 +typedef TCGv_i64 TCGv_vaddr; +#else +# error "sizeof pointer is different from {4,8}" +#endif /* __SIZEOF_POINTER__ */ + /* call flags */ /* Helper does not read globals (either directly or through an exception).= It implies TCG_CALL_NO_WRITE_GLOBALS. */ @@ -577,6 +586,11 @@ static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t) return (TCGv_ptr)temp_tcgv_i32(t); } =20 +static inline TCGv_vaddr temp_tcgv_vaddr(TCGTemp *t) +{ + return (TCGv_vaddr)temp_tcgv_i32(t); +} + static inline TCGv_vec temp_tcgv_vec(TCGTemp *t) { return (TCGv_vec)temp_tcgv_i32(t); diff --git a/include/exec/helper-head.h.inc b/include/exec/helper-head.h.inc index bce5db06ef3..5b248fd7138 100644 --- a/include/exec/helper-head.h.inc +++ b/include/exec/helper-head.h.inc @@ -58,6 +58,17 @@ # define dh_ctype_tl target_ulong #endif /* COMPILING_PER_TARGET */ =20 +#if __SIZEOF_POINTER__ =3D=3D 4 +# define dh_alias_vaddr i32 +# define dh_typecode_vaddr dh_typecode_i32 +#elif __SIZEOF_POINTER__ =3D=3D 8 +# define dh_alias_vaddr i64 +# define dh_typecode_vaddr dh_typecode_i64 +#else +# error "sizeof pointer is different from {4,8}" +#endif /* __SIZEOF_POINTER__ */ +# define dh_ctype_vaddr uintptr_t + /* We can't use glue() here because it falls foul of C preprocessor recursive expansion rules. */ #define dh_retvar_decl0_void void diff --git a/tcg/tcg.c b/tcg/tcg.c index 648333a9fb7..ae27a2607df 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2367,6 +2367,11 @@ TCGv_i64 tcg_constant_i64(int64_t val) return temp_tcgv_i64(tcg_constant_internal(TCG_TYPE_I64, val)); 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Thu, 15 May 2025 03:26:19 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/58] target/arm/helper: use vaddr instead of target_ulong for exception_pc_alignment Date: Thu, 15 May 2025 11:25:11 +0100 Message-ID: <20250515102546.2149601-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305319880116600 From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20250512180502.2395029-14-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.h | 2 +- target/arm/tcg/tlb_helper.c | 2 +- target/arm/tcg/translate-a64.c | 2 +- target/arm/tcg/translate.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 09075058391..95b9211c6f4 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -49,7 +49,7 @@ DEF_HELPER_3(exception_with_syndrome, noreturn, env, i32,= i32) DEF_HELPER_4(exception_with_syndrome_el, noreturn, env, i32, i32, i32) DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32) DEF_HELPER_2(exception_swstep, noreturn, env, i32) -DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl) +DEF_HELPER_2(exception_pc_alignment, noreturn, env, vaddr) DEF_HELPER_1(setend, void, env) DEF_HELPER_2(wfi, void, env, i32) DEF_HELPER_1(wfe, void, env) diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 5ea4d6590f2..d9e6c827d43 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -276,7 +276,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr va= ddr, arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); } =20 -void helper_exception_pc_alignment(CPUARMState *env, target_ulong pc) +void helper_exception_pc_alignment(CPUARMState *env, vaddr pc) { ARMMMUFaultInfo fi =3D { .type =3D ARMFault_Alignment }; int target_el =3D exception_target_el(env); diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 52cf47e775f..ac80f572a2d 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -10242,7 +10242,7 @@ static void aarch64_tr_translate_insn(DisasContextB= ase *dcbase, CPUState *cpu) * start of the TB. */ assert(s->base.num_insns =3D=3D 1); - gen_helper_exception_pc_alignment(tcg_env, tcg_constant_tl(pc)); + gen_helper_exception_pc_alignment(tcg_env, tcg_constant_vaddr(pc)); s->base.is_jmp =3D DISAS_NORETURN; s->base.pc_next =3D QEMU_ALIGN_UP(pc, 4); return; diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index e773ab72685..9962f43b1d0 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -7791,7 +7791,7 @@ static void arm_tr_translate_insn(DisasContextBase *d= cbase, CPUState *cpu) * be possible after an indirect branch, at the start of the TB. */ assert(dc->base.num_insns =3D=3D 1); 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Thu, 15 May 2025 03:26:20 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/58] target/arm/helper: use vaddr instead of target_ulong for probe_access Date: Thu, 15 May 2025 11:25:12 +0100 Message-ID: <20250515102546.2149601-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305091797116600 From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20250512180502.2395029-15-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.h | 2 +- target/arm/tcg/op_helper.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 95b9211c6f4..0a4fc90fa8b 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -104,7 +104,7 @@ DEF_HELPER_FLAGS_1(rebuild_hflags_a32_newel, TCG_CALL_N= O_RWG, void, env) DEF_HELPER_FLAGS_2(rebuild_hflags_a32, TCG_CALL_NO_RWG, void, env, int) DEF_HELPER_FLAGS_2(rebuild_hflags_a64, TCG_CALL_NO_RWG, void, env, int) =20 -DEF_HELPER_FLAGS_5(probe_access, TCG_CALL_NO_WG, void, env, tl, i32, i32, = i32) +DEF_HELPER_FLAGS_5(probe_access, TCG_CALL_NO_WG, void, env, vaddr, i32, i3= 2, i32) =20 DEF_HELPER_1(vfp_get_fpscr, i32, env) DEF_HELPER_2(vfp_set_fpscr, void, env, i32) diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index dc3f83c37dc..575e566280b 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -1222,7 +1222,7 @@ uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x,= uint32_t i) } } =20 -void HELPER(probe_access)(CPUARMState *env, target_ulong ptr, +void HELPER(probe_access)(CPUARMState *env, vaddr ptr, uint32_t access_type, uint32_t mmu_idx, uint32_t size) { --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442f396c3a4sm65657855e9.26.2025.05.15.03.26.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 03:26:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747304782; x=1747909582; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=LysuqBZEQ7TEXzoI4X5szGeQ4D/3+Ej8EqCa4rKNEJg=; b=B8Ps/ZoqSqAwT+al6sJlLEzvFRn/wuLCAmctmvTUVsfVTqpzdxahdiMZYcdy8ZiN9T 48odWcK1rFEwCXoTjaM+DHxNoSMedXvJUtZNjCUxAMY2jJdkZrJ3ZBqtfCoTkoS6tuZR HtXk56wlz1HG0Rty+JsMeSZ08l6ITFG5g/d27PV/XTm9DN3U1ZUuyQoui/+dcEMqk1KP z+EsoQhkZooooHn3vg+xrUAOGmfAaA9g1Fcc37GSU7aE4TFcmYVbMWcxlH5x3jbfGzMi Wha1XQoKUFYMSnBOJIM+rMs6s7lFcDrVdbcBhGl4aoc5mJDSsv13B9/gqNRjP2C8QzyD Zo8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747304782; x=1747909582; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LysuqBZEQ7TEXzoI4X5szGeQ4D/3+Ej8EqCa4rKNEJg=; b=kB8oljs9e71Vt5GZTaP+3o18PCt6pFPMB7g/vvbW1V++MybBwVEPAzAWzNhY5Qi8Nd FVRAMIS3Mv/Idw3hBg7L9m5z6fXv8Lqxn4hIcfUZebuht4hVUgc7QfeZlfRndxgv1LSB qj4fl4hJTTzi4tSwWcHEKIkvhjEVcU133W5VTjVD+VCsttY50s84rh58ZjWS/0Lhxfye VI+GlNh3dGyH9/EaONFnZXynhznNdVpoXVQakE0y7DsxVmsPWU3lgA1XqO0P9DQ2V6hv zbFU9NDOrotxwE1CM3e7A1EnbuWxx1O0kd+QZjcFW1TYrdHzbzmh79QvTj3OXeqp4Zo0 ZSyg== X-Gm-Message-State: AOJu0YwCLJ8Y7px1PMXHEJ8jHpTtpoFVUBCcfD01miDQm9ulo20HhSOT WrmO80q7+n1Gn32IwMWZa9J7KBQrxnmnXaF/hcfcDMBTi9gT0dTUEVghs3cPkuo6M3TAKdI3IDe 7h80= X-Gm-Gg: ASbGncvUvDtSlv5RlwtWkKWtCLn2TZh6KShQmaQBKKjJCPr+CUQd8y+/xSJdgbuT9Gj PhqvO8dlTRPfq09/vMgLqMI862c2rYQi21SGzmuzA0i8S/Ns2fXd4AHqSxp9zTP7dDjjQWuOmCl RCyFZQHdc7HKrjFRYS3GUJpp2R5nsJTly3JI/vIl8BhoNofgHXhe634hmjgU8+MYpx1S9+tUDU6 u6hQ3Y/sLV4t7xJSZDaWtqYB6UahJMDirkYGjLX9iLghk4K6+dgS6skFzEcyRtiD3yPt+SktOVC TRvxc/39/v86Vw/JWDLyF++lJWSp0gJpYE2UeFsT8d54Ed9OnN9nmYnhlQ== X-Google-Smtp-Source: AGHT+IEJ3+1RGBrXn5vGI+ERFqCxp4b1pA2uzt6bahe4Aw4PTcLZ2g4f18dtJIt4diaQ9W9ROAFNRQ== X-Received: by 2002:a05:600c:154a:b0:442:d9f2:c6ef with SMTP id 5b1f17b1804b1-442f96e5234mr16640345e9.2.1747304782024; Thu, 15 May 2025 03:26:22 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/58] target/arm/helper: extract common helpers Date: Thu, 15 May 2025 11:25:13 +0100 Message-ID: <20250515102546.2149601-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305053729116600 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Allow later commits to include only the "new" tcg/helper.h, thus preventing to pull aarch64 helpers (+ target/arm/helper.h contains a ifdef TARGET_AARCH64). Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-id: 20250512180502.2395029-16-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.h | 1152 +-------------------------------- target/arm/{ =3D> tcg}/helper.h | 10 +- 2 files changed, 4 insertions(+), 1158 deletions(-) copy target/arm/{ =3D> tcg}/helper.h (99%) diff --git a/target/arm/helper.h b/target/arm/helper.h index 0a4fc90fa8b..f340a49a28a 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -1,1154 +1,6 @@ -DEF_HELPER_FLAGS_1(sxtb16, TCG_CALL_NO_RWG_SE, i32, i32) -DEF_HELPER_FLAGS_1(uxtb16, TCG_CALL_NO_RWG_SE, i32, i32) +/* SPDX-License-Identifier: GPL-2.0-or-later */ =20 -DEF_HELPER_3(add_setq, i32, env, i32, i32) -DEF_HELPER_3(add_saturate, i32, env, i32, i32) -DEF_HELPER_3(sub_saturate, i32, env, i32, i32) -DEF_HELPER_3(add_usaturate, i32, env, i32, i32) -DEF_HELPER_3(sub_usaturate, i32, env, i32, i32) -DEF_HELPER_FLAGS_3(sdiv, TCG_CALL_NO_RWG, s32, env, s32, s32) -DEF_HELPER_FLAGS_3(udiv, TCG_CALL_NO_RWG, i32, env, i32, i32) -DEF_HELPER_FLAGS_1(rbit, TCG_CALL_NO_RWG_SE, i32, i32) - -#define PAS_OP(pfx) \ - DEF_HELPER_3(pfx ## add8, i32, i32, i32, ptr) \ - DEF_HELPER_3(pfx ## sub8, i32, i32, i32, ptr) \ - DEF_HELPER_3(pfx ## sub16, i32, i32, i32, ptr) \ - DEF_HELPER_3(pfx ## add16, i32, i32, i32, ptr) \ - DEF_HELPER_3(pfx ## addsubx, i32, i32, i32, ptr) \ - DEF_HELPER_3(pfx ## subaddx, i32, i32, i32, ptr) - -PAS_OP(s) -PAS_OP(u) -#undef PAS_OP - -#define PAS_OP(pfx) \ - DEF_HELPER_2(pfx ## add8, i32, i32, i32) \ - DEF_HELPER_2(pfx ## sub8, i32, i32, i32) \ - DEF_HELPER_2(pfx ## sub16, i32, i32, i32) \ - DEF_HELPER_2(pfx ## add16, i32, i32, i32) \ - DEF_HELPER_2(pfx ## addsubx, i32, i32, i32) \ - DEF_HELPER_2(pfx ## subaddx, i32, i32, i32) -PAS_OP(q) -PAS_OP(sh) -PAS_OP(uq) -PAS_OP(uh) -#undef PAS_OP - -DEF_HELPER_3(ssat, i32, env, i32, i32) -DEF_HELPER_3(usat, i32, env, i32, i32) -DEF_HELPER_3(ssat16, i32, env, i32, i32) -DEF_HELPER_3(usat16, i32, env, i32, i32) - -DEF_HELPER_FLAGS_2(usad8, TCG_CALL_NO_RWG_SE, i32, i32, i32) - -DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, - i32, i32, i32, i32) -DEF_HELPER_2(exception_internal, noreturn, env, i32) -DEF_HELPER_3(exception_with_syndrome, noreturn, env, i32, i32) -DEF_HELPER_4(exception_with_syndrome_el, noreturn, env, i32, i32, i32) -DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32) -DEF_HELPER_2(exception_swstep, noreturn, env, i32) -DEF_HELPER_2(exception_pc_alignment, noreturn, env, vaddr) -DEF_HELPER_1(setend, void, env) -DEF_HELPER_2(wfi, void, env, i32) -DEF_HELPER_1(wfe, void, env) -DEF_HELPER_2(wfit, void, env, i64) -DEF_HELPER_1(yield, void, env) -DEF_HELPER_1(pre_hvc, void, env) -DEF_HELPER_2(pre_smc, void, env, i32) -DEF_HELPER_1(vesb, void, env) - -DEF_HELPER_3(cpsr_write, void, env, i32, i32) -DEF_HELPER_2(cpsr_write_eret, void, env, i32) -DEF_HELPER_1(cpsr_read, i32, env) - -DEF_HELPER_3(v7m_msr, void, env, i32, i32) -DEF_HELPER_2(v7m_mrs, i32, env, i32) - -DEF_HELPER_2(v7m_bxns, void, env, i32) -DEF_HELPER_2(v7m_blxns, void, env, i32) - -DEF_HELPER_3(v7m_tt, i32, env, i32, i32) - -DEF_HELPER_1(v7m_preserve_fp_state, void, env) - -DEF_HELPER_2(v7m_vlstm, void, env, i32) -DEF_HELPER_2(v7m_vlldm, void, env, i32) - -DEF_HELPER_2(v8m_stackcheck, void, env, i32) - -DEF_HELPER_FLAGS_2(check_bxj_trap, TCG_CALL_NO_WG, void, env, i32) - -DEF_HELPER_4(access_check_cp_reg, cptr, env, i32, i32, i32) -DEF_HELPER_FLAGS_2(lookup_cp_reg, TCG_CALL_NO_RWG_SE, cptr, env, i32) -DEF_HELPER_FLAGS_2(tidcp_el0, TCG_CALL_NO_WG, void, env, i32) -DEF_HELPER_FLAGS_2(tidcp_el1, TCG_CALL_NO_WG, void, env, i32) -DEF_HELPER_3(set_cp_reg, void, env, cptr, i32) -DEF_HELPER_2(get_cp_reg, i32, env, cptr) -DEF_HELPER_3(set_cp_reg64, void, env, cptr, i64) -DEF_HELPER_2(get_cp_reg64, i64, env, cptr) - -DEF_HELPER_2(get_r13_banked, i32, env, i32) -DEF_HELPER_3(set_r13_banked, void, env, i32, i32) - -DEF_HELPER_3(mrs_banked, i32, env, i32, i32) -DEF_HELPER_4(msr_banked, void, env, i32, i32, i32) - -DEF_HELPER_2(get_user_reg, i32, env, i32) -DEF_HELPER_3(set_user_reg, void, env, i32, i32) - -DEF_HELPER_FLAGS_1(rebuild_hflags_m32_newel, TCG_CALL_NO_RWG, void, env) -DEF_HELPER_FLAGS_2(rebuild_hflags_m32, TCG_CALL_NO_RWG, void, env, int) -DEF_HELPER_FLAGS_1(rebuild_hflags_a32_newel, TCG_CALL_NO_RWG, void, env) -DEF_HELPER_FLAGS_2(rebuild_hflags_a32, TCG_CALL_NO_RWG, void, env, int) -DEF_HELPER_FLAGS_2(rebuild_hflags_a64, TCG_CALL_NO_RWG, void, env, int) - -DEF_HELPER_FLAGS_5(probe_access, TCG_CALL_NO_WG, void, env, vaddr, i32, i3= 2, i32) - -DEF_HELPER_1(vfp_get_fpscr, i32, env) -DEF_HELPER_2(vfp_set_fpscr, void, env, i32) - -DEF_HELPER_3(vfp_addh, f16, f16, f16, fpst) -DEF_HELPER_3(vfp_adds, f32, f32, f32, fpst) -DEF_HELPER_3(vfp_addd, f64, f64, f64, fpst) -DEF_HELPER_3(vfp_subh, f16, f16, f16, fpst) -DEF_HELPER_3(vfp_subs, f32, f32, f32, fpst) -DEF_HELPER_3(vfp_subd, f64, f64, f64, fpst) -DEF_HELPER_3(vfp_mulh, f16, f16, f16, fpst) -DEF_HELPER_3(vfp_muls, f32, f32, f32, fpst) -DEF_HELPER_3(vfp_muld, f64, f64, f64, fpst) -DEF_HELPER_3(vfp_divh, f16, f16, f16, fpst) -DEF_HELPER_3(vfp_divs, f32, f32, f32, fpst) -DEF_HELPER_3(vfp_divd, f64, f64, f64, fpst) -DEF_HELPER_3(vfp_maxh, f16, f16, f16, fpst) -DEF_HELPER_3(vfp_maxs, f32, f32, f32, fpst) -DEF_HELPER_3(vfp_maxd, f64, f64, f64, fpst) -DEF_HELPER_3(vfp_minh, f16, f16, f16, fpst) -DEF_HELPER_3(vfp_mins, f32, f32, f32, fpst) -DEF_HELPER_3(vfp_mind, f64, f64, f64, fpst) -DEF_HELPER_3(vfp_maxnumh, f16, f16, f16, fpst) -DEF_HELPER_3(vfp_maxnums, f32, f32, f32, fpst) -DEF_HELPER_3(vfp_maxnumd, f64, f64, f64, fpst) -DEF_HELPER_3(vfp_minnumh, f16, f16, f16, fpst) -DEF_HELPER_3(vfp_minnums, f32, f32, f32, fpst) -DEF_HELPER_3(vfp_minnumd, f64, f64, f64, fpst) -DEF_HELPER_2(vfp_sqrth, f16, f16, fpst) -DEF_HELPER_2(vfp_sqrts, f32, f32, fpst) -DEF_HELPER_2(vfp_sqrtd, f64, f64, fpst) -DEF_HELPER_3(vfp_cmph, void, f16, f16, env) -DEF_HELPER_3(vfp_cmps, void, f32, f32, env) -DEF_HELPER_3(vfp_cmpd, void, f64, f64, env) -DEF_HELPER_3(vfp_cmpeh, void, f16, f16, env) -DEF_HELPER_3(vfp_cmpes, void, f32, f32, env) -DEF_HELPER_3(vfp_cmped, void, f64, f64, env) - -DEF_HELPER_2(vfp_fcvtds, f64, f32, fpst) -DEF_HELPER_2(vfp_fcvtsd, f32, f64, fpst) -DEF_HELPER_FLAGS_2(bfcvt, TCG_CALL_NO_RWG, i32, f32, fpst) -DEF_HELPER_FLAGS_2(bfcvt_pair, TCG_CALL_NO_RWG, i32, i64, fpst) - -DEF_HELPER_2(vfp_uitoh, f16, i32, fpst) -DEF_HELPER_2(vfp_uitos, f32, i32, fpst) -DEF_HELPER_2(vfp_uitod, f64, i32, fpst) -DEF_HELPER_2(vfp_sitoh, f16, i32, fpst) -DEF_HELPER_2(vfp_sitos, f32, i32, fpst) -DEF_HELPER_2(vfp_sitod, f64, i32, fpst) - -DEF_HELPER_2(vfp_touih, i32, f16, fpst) -DEF_HELPER_2(vfp_touis, i32, f32, fpst) -DEF_HELPER_2(vfp_touid, i32, f64, fpst) -DEF_HELPER_2(vfp_touizh, i32, f16, fpst) -DEF_HELPER_2(vfp_touizs, i32, f32, fpst) -DEF_HELPER_2(vfp_touizd, i32, f64, fpst) -DEF_HELPER_2(vfp_tosih, s32, f16, fpst) -DEF_HELPER_2(vfp_tosis, s32, f32, fpst) -DEF_HELPER_2(vfp_tosid, s32, f64, fpst) -DEF_HELPER_2(vfp_tosizh, s32, f16, fpst) -DEF_HELPER_2(vfp_tosizs, s32, f32, fpst) -DEF_HELPER_2(vfp_tosizd, s32, f64, fpst) - -DEF_HELPER_3(vfp_toshh_round_to_zero, i32, f16, i32, fpst) -DEF_HELPER_3(vfp_toslh_round_to_zero, i32, f16, i32, fpst) -DEF_HELPER_3(vfp_touhh_round_to_zero, i32, f16, i32, fpst) -DEF_HELPER_3(vfp_toulh_round_to_zero, i32, f16, i32, fpst) -DEF_HELPER_3(vfp_toshs_round_to_zero, i32, f32, i32, fpst) -DEF_HELPER_3(vfp_tosls_round_to_zero, i32, f32, i32, fpst) -DEF_HELPER_3(vfp_touhs_round_to_zero, i32, f32, i32, fpst) -DEF_HELPER_3(vfp_touls_round_to_zero, i32, f32, i32, fpst) -DEF_HELPER_3(vfp_toshd_round_to_zero, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_tosld_round_to_zero, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_tosqd_round_to_zero, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_touqd_round_to_zero, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_touhh, i32, f16, i32, fpst) -DEF_HELPER_3(vfp_toshh, i32, f16, i32, fpst) -DEF_HELPER_3(vfp_toulh, i32, f16, i32, fpst) -DEF_HELPER_3(vfp_toslh, i32, f16, i32, fpst) -DEF_HELPER_3(vfp_touqh, i64, f16, i32, fpst) -DEF_HELPER_3(vfp_tosqh, i64, f16, i32, fpst) -DEF_HELPER_3(vfp_toshs, i32, f32, i32, fpst) -DEF_HELPER_3(vfp_tosls, i32, f32, i32, fpst) -DEF_HELPER_3(vfp_tosqs, i64, f32, i32, fpst) -DEF_HELPER_3(vfp_touhs, i32, f32, i32, fpst) -DEF_HELPER_3(vfp_touls, i32, f32, i32, fpst) -DEF_HELPER_3(vfp_touqs, i64, f32, i32, fpst) -DEF_HELPER_3(vfp_toshd, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_tosld, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_tosqd, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_touhd, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_tould, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_touqd, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_shtos, f32, i32, i32, fpst) -DEF_HELPER_3(vfp_sltos, f32, i32, i32, fpst) -DEF_HELPER_3(vfp_sqtos, f32, i64, i32, fpst) -DEF_HELPER_3(vfp_uhtos, f32, i32, i32, fpst) -DEF_HELPER_3(vfp_ultos, f32, i32, i32, fpst) -DEF_HELPER_3(vfp_uqtos, f32, i64, i32, fpst) -DEF_HELPER_3(vfp_shtod, f64, i64, i32, fpst) -DEF_HELPER_3(vfp_sltod, f64, i64, i32, fpst) -DEF_HELPER_3(vfp_sqtod, f64, i64, i32, fpst) -DEF_HELPER_3(vfp_uhtod, f64, i64, i32, fpst) -DEF_HELPER_3(vfp_ultod, f64, i64, i32, fpst) -DEF_HELPER_3(vfp_uqtod, f64, i64, i32, fpst) -DEF_HELPER_3(vfp_shtoh, f16, i32, i32, fpst) -DEF_HELPER_3(vfp_uhtoh, f16, i32, i32, fpst) -DEF_HELPER_3(vfp_sltoh, f16, i32, i32, fpst) -DEF_HELPER_3(vfp_ultoh, f16, i32, i32, fpst) -DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, fpst) -DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, fpst) - -DEF_HELPER_3(vfp_shtos_round_to_nearest, f32, i32, i32, fpst) -DEF_HELPER_3(vfp_sltos_round_to_nearest, f32, i32, i32, fpst) -DEF_HELPER_3(vfp_uhtos_round_to_nearest, f32, i32, i32, fpst) -DEF_HELPER_3(vfp_ultos_round_to_nearest, f32, i32, i32, fpst) -DEF_HELPER_3(vfp_shtod_round_to_nearest, f64, i64, i32, fpst) -DEF_HELPER_3(vfp_sltod_round_to_nearest, f64, i64, i32, fpst) -DEF_HELPER_3(vfp_uhtod_round_to_nearest, f64, i64, i32, fpst) -DEF_HELPER_3(vfp_ultod_round_to_nearest, f64, i64, i32, fpst) -DEF_HELPER_3(vfp_shtoh_round_to_nearest, f16, i32, i32, fpst) -DEF_HELPER_3(vfp_uhtoh_round_to_nearest, f16, i32, i32, fpst) -DEF_HELPER_3(vfp_sltoh_round_to_nearest, f16, i32, i32, fpst) -DEF_HELPER_3(vfp_ultoh_round_to_nearest, f16, i32, i32, fpst) - -DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, fpst) - -DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f32, TCG_CALL_NO_RWG, f32, f16, fpst, i= 32) -DEF_HELPER_FLAGS_3(vfp_fcvt_f32_to_f16, TCG_CALL_NO_RWG, f16, f32, fpst, i= 32) -DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f64, TCG_CALL_NO_RWG, f64, f16, fpst, i= 32) -DEF_HELPER_FLAGS_3(vfp_fcvt_f64_to_f16, TCG_CALL_NO_RWG, f16, f64, fpst, i= 32) - -DEF_HELPER_4(vfp_muladdd, f64, f64, f64, f64, fpst) -DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, fpst) -DEF_HELPER_4(vfp_muladdh, f16, f16, f16, f16, fpst) - -DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, fpst) -DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, fpst) -DEF_HELPER_FLAGS_2(recpe_rpres_f32, TCG_CALL_NO_RWG, f32, f32, fpst) -DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, fpst) -DEF_HELPER_FLAGS_2(rsqrte_f16, TCG_CALL_NO_RWG, f16, f16, fpst) -DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, fpst) -DEF_HELPER_FLAGS_2(rsqrte_rpres_f32, TCG_CALL_NO_RWG, f32, f32, fpst) -DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, fpst) -DEF_HELPER_FLAGS_1(recpe_u32, TCG_CALL_NO_RWG, i32, i32) -DEF_HELPER_FLAGS_1(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32) -DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64) - -DEF_HELPER_3(shl_cc, i32, env, i32, i32) -DEF_HELPER_3(shr_cc, i32, env, i32, i32) -DEF_HELPER_3(sar_cc, i32, env, i32, i32) -DEF_HELPER_3(ror_cc, i32, env, i32, i32) - -DEF_HELPER_FLAGS_2(rinth_exact, TCG_CALL_NO_RWG, f16, f16, fpst) -DEF_HELPER_FLAGS_2(rints_exact, TCG_CALL_NO_RWG, f32, f32, fpst) -DEF_HELPER_FLAGS_2(rintd_exact, TCG_CALL_NO_RWG, f64, f64, fpst) -DEF_HELPER_FLAGS_2(rinth, TCG_CALL_NO_RWG, f16, f16, fpst) -DEF_HELPER_FLAGS_2(rints, TCG_CALL_NO_RWG, f32, f32, fpst) -DEF_HELPER_FLAGS_2(rintd, TCG_CALL_NO_RWG, f64, f64, fpst) - -DEF_HELPER_FLAGS_2(vjcvt, TCG_CALL_NO_RWG, i32, f64, env) -DEF_HELPER_FLAGS_2(fjcvtzs, TCG_CALL_NO_RWG, i64, f64, fpst) - -DEF_HELPER_FLAGS_3(check_hcr_el2_trap, TCG_CALL_NO_WG, void, env, i32, i32) - -/* neon_helper.c */ -DEF_HELPER_2(neon_pmin_u8, i32, i32, i32) -DEF_HELPER_2(neon_pmin_s8, i32, i32, i32) -DEF_HELPER_2(neon_pmin_u16, i32, i32, i32) -DEF_HELPER_2(neon_pmin_s16, i32, i32, i32) -DEF_HELPER_2(neon_pmax_u8, i32, i32, i32) -DEF_HELPER_2(neon_pmax_s8, i32, i32, i32) -DEF_HELPER_2(neon_pmax_u16, i32, i32, i32) -DEF_HELPER_2(neon_pmax_s16, i32, i32, i32) - -DEF_HELPER_2(neon_shl_u16, i32, i32, i32) -DEF_HELPER_2(neon_shl_s16, i32, i32, i32) -DEF_HELPER_2(neon_rshl_u8, i32, i32, i32) -DEF_HELPER_2(neon_rshl_s8, i32, i32, i32) -DEF_HELPER_2(neon_rshl_u16, i32, i32, i32) -DEF_HELPER_2(neon_rshl_s16, i32, i32, i32) -DEF_HELPER_2(neon_rshl_u32, i32, i32, i32) -DEF_HELPER_2(neon_rshl_s32, i32, i32, i32) -DEF_HELPER_2(neon_rshl_u64, i64, i64, i64) -DEF_HELPER_2(neon_rshl_s64, i64, i64, i64) -DEF_HELPER_3(neon_qshl_u8, i32, env, i32, i32) -DEF_HELPER_3(neon_qshl_s8, i32, env, i32, i32) -DEF_HELPER_3(neon_qshl_u16, i32, env, i32, i32) -DEF_HELPER_3(neon_qshl_s16, i32, env, i32, i32) -DEF_HELPER_3(neon_qshl_u32, i32, env, i32, i32) -DEF_HELPER_3(neon_qshl_s32, i32, env, i32, i32) -DEF_HELPER_3(neon_qshl_u64, i64, env, i64, i64) -DEF_HELPER_3(neon_qshl_s64, i64, env, i64, i64) -DEF_HELPER_3(neon_qshlu_s8, i32, env, i32, i32) -DEF_HELPER_3(neon_qshlu_s16, i32, env, i32, i32) -DEF_HELPER_3(neon_qshlu_s32, i32, env, i32, i32) -DEF_HELPER_3(neon_qshlu_s64, i64, env, i64, i64) -DEF_HELPER_3(neon_qrshl_u8, i32, env, i32, i32) -DEF_HELPER_3(neon_qrshl_s8, i32, env, i32, i32) -DEF_HELPER_3(neon_qrshl_u16, i32, env, i32, i32) -DEF_HELPER_3(neon_qrshl_s16, i32, env, i32, i32) -DEF_HELPER_3(neon_qrshl_u32, i32, env, i32, i32) -DEF_HELPER_3(neon_qrshl_s32, i32, env, i32, i32) -DEF_HELPER_3(neon_qrshl_u64, i64, env, i64, i64) -DEF_HELPER_3(neon_qrshl_s64, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(neon_sqshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env= , i32) -DEF_HELPER_FLAGS_5(neon_sqshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env= , i32) -DEF_HELPER_FLAGS_5(neon_sqshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env= , i32) -DEF_HELPER_FLAGS_5(neon_sqshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env= , i32) -DEF_HELPER_FLAGS_5(neon_uqshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env= , i32) -DEF_HELPER_FLAGS_5(neon_uqshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env= , i32) -DEF_HELPER_FLAGS_5(neon_uqshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env= , i32) -DEF_HELPER_FLAGS_5(neon_uqshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env= , i32) -DEF_HELPER_FLAGS_5(neon_sqrshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, en= v, i32) -DEF_HELPER_FLAGS_5(neon_sqrshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, en= v, i32) -DEF_HELPER_FLAGS_5(neon_sqrshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, en= v, i32) -DEF_HELPER_FLAGS_5(neon_sqrshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, en= v, i32) -DEF_HELPER_FLAGS_5(neon_uqrshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, en= v, i32) -DEF_HELPER_FLAGS_5(neon_uqrshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, en= v, i32) -DEF_HELPER_FLAGS_5(neon_uqrshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, en= v, i32) -DEF_HELPER_FLAGS_5(neon_uqrshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, en= v, i32) -DEF_HELPER_FLAGS_4(neon_sqshli_b, TCG_CALL_NO_RWG, void, ptr, ptr, env, i3= 2) -DEF_HELPER_FLAGS_4(neon_sqshli_h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i3= 2) -DEF_HELPER_FLAGS_4(neon_sqshli_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i3= 2) -DEF_HELPER_FLAGS_4(neon_sqshli_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i3= 2) -DEF_HELPER_FLAGS_4(neon_uqshli_b, TCG_CALL_NO_RWG, void, ptr, ptr, env, i3= 2) -DEF_HELPER_FLAGS_4(neon_uqshli_h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i3= 2) -DEF_HELPER_FLAGS_4(neon_uqshli_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i3= 2) -DEF_HELPER_FLAGS_4(neon_uqshli_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i3= 2) -DEF_HELPER_FLAGS_4(neon_sqshlui_b, TCG_CALL_NO_RWG, void, ptr, ptr, env, i= 32) -DEF_HELPER_FLAGS_4(neon_sqshlui_h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i= 32) -DEF_HELPER_FLAGS_4(neon_sqshlui_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i= 32) -DEF_HELPER_FLAGS_4(neon_sqshlui_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i= 32) - -DEF_HELPER_FLAGS_4(gvec_srshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_srshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_srshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_srshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_urshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_urshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_urshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_urshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_2(neon_add_u8, i32, i32, i32) -DEF_HELPER_2(neon_add_u16, i32, i32, i32) -DEF_HELPER_2(neon_sub_u8, i32, i32, i32) -DEF_HELPER_2(neon_sub_u16, i32, i32, i32) -DEF_HELPER_2(neon_mul_u8, i32, i32, i32) -DEF_HELPER_2(neon_mul_u16, i32, i32, i32) - -DEF_HELPER_2(neon_tst_u8, i32, i32, i32) -DEF_HELPER_2(neon_tst_u16, i32, i32, i32) -DEF_HELPER_2(neon_tst_u32, i32, i32, i32) - -DEF_HELPER_1(neon_clz_u8, i32, i32) -DEF_HELPER_1(neon_clz_u16, i32, i32) -DEF_HELPER_1(neon_cls_s8, i32, i32) -DEF_HELPER_1(neon_cls_s16, i32, i32) -DEF_HELPER_1(neon_cls_s32, i32, i32) -DEF_HELPER_FLAGS_3(gvec_cnt_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_rbit_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_3(neon_qdmulh_s16, i32, env, i32, i32) -DEF_HELPER_3(neon_qrdmulh_s16, i32, env, i32, i32) -DEF_HELPER_4(neon_qrdmlah_s16, i32, env, i32, i32, i32) -DEF_HELPER_4(neon_qrdmlsh_s16, i32, env, i32, i32, i32) -DEF_HELPER_3(neon_qdmulh_s32, i32, env, i32, i32) -DEF_HELPER_3(neon_qrdmulh_s32, i32, env, i32, i32) -DEF_HELPER_4(neon_qrdmlah_s32, i32, env, s32, s32, s32) -DEF_HELPER_4(neon_qrdmlsh_s32, i32, env, s32, s32, s32) - -DEF_HELPER_1(neon_narrow_u8, i64, i64) -DEF_HELPER_1(neon_narrow_u16, i64, i64) -DEF_HELPER_2(neon_unarrow_sat8, i64, env, i64) -DEF_HELPER_2(neon_narrow_sat_u8, i64, env, i64) -DEF_HELPER_2(neon_narrow_sat_s8, i64, env, i64) -DEF_HELPER_2(neon_unarrow_sat16, i64, env, i64) -DEF_HELPER_2(neon_narrow_sat_u16, i64, env, i64) -DEF_HELPER_2(neon_narrow_sat_s16, i64, env, i64) -DEF_HELPER_2(neon_unarrow_sat32, i64, env, i64) -DEF_HELPER_2(neon_narrow_sat_u32, i64, env, i64) -DEF_HELPER_2(neon_narrow_sat_s32, i64, env, i64) -DEF_HELPER_1(neon_narrow_high_u8, i32, i64) -DEF_HELPER_1(neon_narrow_high_u16, i32, i64) -DEF_HELPER_1(neon_narrow_round_high_u8, i32, i64) -DEF_HELPER_1(neon_narrow_round_high_u16, i32, i64) -DEF_HELPER_1(neon_widen_u8, i64, i32) -DEF_HELPER_1(neon_widen_s8, i64, i32) -DEF_HELPER_1(neon_widen_u16, i64, i32) -DEF_HELPER_1(neon_widen_s16, i64, i32) - -DEF_HELPER_FLAGS_1(neon_addlp_s8, TCG_CALL_NO_RWG_SE, i64, i64) -DEF_HELPER_FLAGS_1(neon_addlp_s16, TCG_CALL_NO_RWG_SE, i64, i64) -DEF_HELPER_3(neon_addl_saturate_s32, i64, env, i64, i64) -DEF_HELPER_3(neon_addl_saturate_s64, i64, env, i64, i64) -DEF_HELPER_2(neon_abdl_u16, i64, i32, i32) -DEF_HELPER_2(neon_abdl_s16, i64, i32, i32) -DEF_HELPER_2(neon_abdl_u32, i64, i32, i32) -DEF_HELPER_2(neon_abdl_s32, i64, i32, i32) -DEF_HELPER_2(neon_abdl_u64, i64, i32, i32) -DEF_HELPER_2(neon_abdl_s64, i64, i32, i32) -DEF_HELPER_2(neon_mull_u8, i64, i32, i32) -DEF_HELPER_2(neon_mull_s8, i64, i32, i32) -DEF_HELPER_2(neon_mull_u16, i64, i32, i32) -DEF_HELPER_2(neon_mull_s16, i64, i32, i32) - -DEF_HELPER_1(neon_negl_u16, i64, i64) -DEF_HELPER_1(neon_negl_u32, i64, i64) - -DEF_HELPER_FLAGS_2(neon_qabs_s8, TCG_CALL_NO_RWG, i32, env, i32) -DEF_HELPER_FLAGS_2(neon_qabs_s16, TCG_CALL_NO_RWG, i32, env, i32) -DEF_HELPER_FLAGS_2(neon_qabs_s32, TCG_CALL_NO_RWG, i32, env, i32) -DEF_HELPER_FLAGS_2(neon_qabs_s64, TCG_CALL_NO_RWG, i64, env, i64) -DEF_HELPER_FLAGS_2(neon_qneg_s8, TCG_CALL_NO_RWG, i32, env, i32) -DEF_HELPER_FLAGS_2(neon_qneg_s16, TCG_CALL_NO_RWG, i32, env, i32) -DEF_HELPER_FLAGS_2(neon_qneg_s32, TCG_CALL_NO_RWG, i32, env, i32) -DEF_HELPER_FLAGS_2(neon_qneg_s64, TCG_CALL_NO_RWG, i64, env, i64) - -DEF_HELPER_3(neon_ceq_f32, i32, i32, i32, fpst) -DEF_HELPER_3(neon_cge_f32, i32, i32, i32, fpst) -DEF_HELPER_3(neon_cgt_f32, i32, i32, i32, fpst) -DEF_HELPER_3(neon_acge_f32, i32, i32, i32, fpst) -DEF_HELPER_3(neon_acgt_f32, i32, i32, i32, fpst) -DEF_HELPER_3(neon_acge_f64, i64, i64, i64, fpst) -DEF_HELPER_3(neon_acgt_f64, i64, i64, i64, fpst) - -/* iwmmxt_helper.c */ -DEF_HELPER_2(iwmmxt_maddsq, i64, i64, i64) -DEF_HELPER_2(iwmmxt_madduq, i64, i64, i64) -DEF_HELPER_2(iwmmxt_sadb, i64, i64, i64) -DEF_HELPER_2(iwmmxt_sadw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_mulslw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_mulshw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_mululw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_muluhw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_macsw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_macuw, i64, i64, i64) -DEF_HELPER_1(iwmmxt_setpsr_nz, i32, i64) - -#define DEF_IWMMXT_HELPER_SIZE_ENV(name) \ -DEF_HELPER_3(iwmmxt_##name##b, i64, env, i64, i64) \ -DEF_HELPER_3(iwmmxt_##name##w, i64, env, i64, i64) \ -DEF_HELPER_3(iwmmxt_##name##l, i64, env, i64, i64) \ - -DEF_IWMMXT_HELPER_SIZE_ENV(unpackl) -DEF_IWMMXT_HELPER_SIZE_ENV(unpackh) - -DEF_HELPER_2(iwmmxt_unpacklub, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackluw, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpacklul, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhub, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhuw, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhul, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpacklsb, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpacklsw, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpacklsl, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhsb, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhsw, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhsl, i64, env, i64) - -DEF_IWMMXT_HELPER_SIZE_ENV(cmpeq) -DEF_IWMMXT_HELPER_SIZE_ENV(cmpgtu) -DEF_IWMMXT_HELPER_SIZE_ENV(cmpgts) - -DEF_IWMMXT_HELPER_SIZE_ENV(mins) -DEF_IWMMXT_HELPER_SIZE_ENV(minu) -DEF_IWMMXT_HELPER_SIZE_ENV(maxs) -DEF_IWMMXT_HELPER_SIZE_ENV(maxu) - -DEF_IWMMXT_HELPER_SIZE_ENV(subn) -DEF_IWMMXT_HELPER_SIZE_ENV(addn) -DEF_IWMMXT_HELPER_SIZE_ENV(subu) -DEF_IWMMXT_HELPER_SIZE_ENV(addu) -DEF_IWMMXT_HELPER_SIZE_ENV(subs) -DEF_IWMMXT_HELPER_SIZE_ENV(adds) - -DEF_HELPER_3(iwmmxt_avgb0, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_avgb1, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_avgw0, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_avgw1, i64, env, i64, i64) - -DEF_HELPER_3(iwmmxt_align, i64, i64, i64, i32) -DEF_HELPER_4(iwmmxt_insr, i64, i64, i32, i32, i32) - -DEF_HELPER_1(iwmmxt_bcstb, i64, i32) -DEF_HELPER_1(iwmmxt_bcstw, i64, i32) -DEF_HELPER_1(iwmmxt_bcstl, i64, i32) - -DEF_HELPER_1(iwmmxt_addcb, i64, i64) -DEF_HELPER_1(iwmmxt_addcw, i64, i64) -DEF_HELPER_1(iwmmxt_addcl, i64, i64) - -DEF_HELPER_1(iwmmxt_msbb, i32, i64) -DEF_HELPER_1(iwmmxt_msbw, i32, i64) -DEF_HELPER_1(iwmmxt_msbl, i32, i64) - -DEF_HELPER_3(iwmmxt_srlw, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_srll, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_srlq, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_sllw, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_slll, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_sllq, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_sraw, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_sral, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_sraq, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_rorw, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_rorl, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_rorq, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_shufh, i64, env, i64, i32) - -DEF_HELPER_3(iwmmxt_packuw, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_packul, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_packuq, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_packsw, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_packsl, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_packsq, i64, env, i64, i64) - -DEF_HELPER_3(iwmmxt_muladdsl, i64, i64, i32, i32) -DEF_HELPER_3(iwmmxt_muladdsw, i64, i64, i32, i32) -DEF_HELPER_3(iwmmxt_muladdswl, i64, i64, i32, i32) - -DEF_HELPER_FLAGS_2(neon_unzip8, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_unzip16, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_qunzip8, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_qunzip16, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_qunzip32, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_zip8, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_zip16, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_qzip8, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_qzip16, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_qzip32, TCG_CALL_NO_RWG, void, ptr, ptr) - -DEF_HELPER_FLAGS_4(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_aesd, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(crypto_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(crypto_aesimc, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(crypto_sha1su0, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) -DEF_HELPER_FLAGS_4(crypto_sha1c, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_sha1p, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_sha1m, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(crypto_sha1h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(crypto_sha1su1, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(crypto_sha256h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) -DEF_HELPER_FLAGS_4(crypto_sha256h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, = i32) -DEF_HELPER_FLAGS_3(crypto_sha256su0, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_sha256su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr,= i32) - -DEF_HELPER_FLAGS_4(crypto_sha512h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) -DEF_HELPER_FLAGS_4(crypto_sha512h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, = i32) -DEF_HELPER_FLAGS_3(crypto_sha512su0, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_sha512su1, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(crypto_sm3tt1a, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) -DEF_HELPER_FLAGS_4(crypto_sm3tt1b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) -DEF_HELPER_FLAGS_4(crypto_sm3tt2a, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) -DEF_HELPER_FLAGS_4(crypto_sm3tt2b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) -DEF_HELPER_FLAGS_4(crypto_sm3partw1, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_sm3partw2, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(crypto_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) - -DEF_HELPER_FLAGS_4(crypto_rax1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) -DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) - -DEF_HELPER_FLAGS_5(gvec_qrdmlah_s16, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s16, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_qrdmlah_s32, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s32, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(sve2_sqrdmlah_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlah_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlah_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlah_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(gvec_sdot_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) -DEF_HELPER_FLAGS_5(gvec_udot_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) -DEF_HELPER_FLAGS_5(gvec_sdot_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) -DEF_HELPER_FLAGS_5(gvec_udot_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) -DEF_HELPER_FLAGS_5(gvec_usdot_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) - -DEF_HELPER_FLAGS_5(gvec_sdot_idx_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_udot_idx_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sdot_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_udot_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sudot_idx_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_usdot_idx_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(gvec_fcaddh, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fcadds, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fcaddd, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_6(gvec_fcmlah, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_6(gvec_fcmlah_idx, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_6(gvec_fcmlas, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_6(gvec_fcmlas_idx, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_6(gvec_fcmlad, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_4(gvec_sstoh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_sitos, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_ustoh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_uitos, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_tosszh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_tosizs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_touszh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_touizs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_4(gvec_vcvt_sf, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i3= 2) -DEF_HELPER_FLAGS_4(gvec_vcvt_uf, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i3= 2) -DEF_HELPER_FLAGS_4(gvec_vcvt_rz_fs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst,= i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_rz_fu, TCG_CALL_NO_RWG, void, ptr, ptr, fpst,= i32) - -DEF_HELPER_FLAGS_4(gvec_vcvt_sh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i3= 2) -DEF_HELPER_FLAGS_4(gvec_vcvt_uh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i3= 2) -DEF_HELPER_FLAGS_4(gvec_vcvt_rz_hs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst,= i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_rz_hu, TCG_CALL_NO_RWG, void, ptr, ptr, fpst,= i32) - -DEF_HELPER_FLAGS_4(gvec_vcvt_sd, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i3= 2) -DEF_HELPER_FLAGS_4(gvec_vcvt_ud, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i3= 2) -DEF_HELPER_FLAGS_4(gvec_vcvt_rz_ds, TCG_CALL_NO_RWG, void, ptr, ptr, fpst,= i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_rz_du, TCG_CALL_NO_RWG, void, ptr, ptr, fpst,= i32) - -DEF_HELPER_FLAGS_4(gvec_vcvt_rm_sd, TCG_CALL_NO_RWG, void, ptr, ptr, fpst,= i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_rm_ud, TCG_CALL_NO_RWG, void, ptr, ptr, fpst,= i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_rm_ss, TCG_CALL_NO_RWG, void, ptr, ptr, fpst,= i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_rm_us, TCG_CALL_NO_RWG, void, ptr, ptr, fpst,= i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_rm_sh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst,= i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_rm_uh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst,= i32) - -DEF_HELPER_FLAGS_4(gvec_vrint_rm_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst,= i32) -DEF_HELPER_FLAGS_4(gvec_vrint_rm_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst,= i32) - -DEF_HELPER_FLAGS_4(gvec_vrintx_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i= 32) -DEF_HELPER_FLAGS_4(gvec_vrintx_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i= 32) - -DEF_HELPER_FLAGS_4(gvec_frecpe_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i= 32) -DEF_HELPER_FLAGS_4(gvec_frecpe_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i= 32) -DEF_HELPER_FLAGS_4(gvec_frecpe_rpres_s, TCG_CALL_NO_RWG, void, ptr, ptr, f= pst, i32) -DEF_HELPER_FLAGS_4(gvec_frecpe_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i= 32) - -DEF_HELPER_FLAGS_4(gvec_frsqrte_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, = i32) -DEF_HELPER_FLAGS_4(gvec_frsqrte_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, = i32) -DEF_HELPER_FLAGS_4(gvec_frsqrte_rpres_s, TCG_CALL_NO_RWG, void, ptr, ptr, = fpst, i32) -DEF_HELPER_FLAGS_4(gvec_frsqrte_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, = i32) - -DEF_HELPER_FLAGS_4(gvec_fcgt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i3= 2) -DEF_HELPER_FLAGS_4(gvec_fcgt0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i3= 2) -DEF_HELPER_FLAGS_4(gvec_fcgt0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i3= 2) - -DEF_HELPER_FLAGS_4(gvec_fcge0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i3= 2) -DEF_HELPER_FLAGS_4(gvec_fcge0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i3= 2) -DEF_HELPER_FLAGS_4(gvec_fcge0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i3= 2) - -DEF_HELPER_FLAGS_4(gvec_fceq0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i3= 2) -DEF_HELPER_FLAGS_4(gvec_fceq0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i3= 2) -DEF_HELPER_FLAGS_4(gvec_fceq0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i3= 2) - -DEF_HELPER_FLAGS_4(gvec_fcle0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i3= 2) -DEF_HELPER_FLAGS_4(gvec_fcle0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i3= 2) -DEF_HELPER_FLAGS_4(gvec_fcle0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i3= 2) - -DEF_HELPER_FLAGS_4(gvec_fclt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i3= 2) -DEF_HELPER_FLAGS_4(gvec_fclt0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i3= 2) -DEF_HELPER_FLAGS_4(gvec_fclt0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i3= 2) - -DEF_HELPER_FLAGS_5(gvec_fadd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) -DEF_HELPER_FLAGS_5(gvec_fadd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) -DEF_HELPER_FLAGS_5(gvec_fadd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) - -DEF_HELPER_FLAGS_5(gvec_fsub_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) -DEF_HELPER_FLAGS_5(gvec_fsub_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) -DEF_HELPER_FLAGS_5(gvec_fsub_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) - -DEF_HELPER_FLAGS_5(gvec_fmul_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) -DEF_HELPER_FLAGS_5(gvec_fmul_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) -DEF_HELPER_FLAGS_5(gvec_fmul_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) - -DEF_HELPER_FLAGS_5(gvec_fabd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) -DEF_HELPER_FLAGS_5(gvec_fabd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) -DEF_HELPER_FLAGS_5(gvec_fabd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) - -DEF_HELPER_FLAGS_5(gvec_ah_fabd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, f= pst, i32) -DEF_HELPER_FLAGS_5(gvec_ah_fabd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, f= pst, i32) -DEF_HELPER_FLAGS_5(gvec_ah_fabd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, f= pst, i32) - -DEF_HELPER_FLAGS_5(gvec_fceq_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) -DEF_HELPER_FLAGS_5(gvec_fceq_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) -DEF_HELPER_FLAGS_5(gvec_fceq_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) - -DEF_HELPER_FLAGS_5(gvec_fcge_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) -DEF_HELPER_FLAGS_5(gvec_fcge_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) -DEF_HELPER_FLAGS_5(gvec_fcge_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) - -DEF_HELPER_FLAGS_5(gvec_fcgt_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) -DEF_HELPER_FLAGS_5(gvec_fcgt_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) -DEF_HELPER_FLAGS_5(gvec_fcgt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) - -DEF_HELPER_FLAGS_5(gvec_facge_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fps= t, i32) -DEF_HELPER_FLAGS_5(gvec_facge_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fps= t, i32) -DEF_HELPER_FLAGS_5(gvec_facge_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fps= t, i32) - -DEF_HELPER_FLAGS_5(gvec_facgt_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fps= t, i32) -DEF_HELPER_FLAGS_5(gvec_facgt_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fps= t, i32) -DEF_HELPER_FLAGS_5(gvec_facgt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fps= t, i32) - -DEF_HELPER_FLAGS_5(gvec_fmax_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) -DEF_HELPER_FLAGS_5(gvec_fmax_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) -DEF_HELPER_FLAGS_5(gvec_fmax_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) - -DEF_HELPER_FLAGS_5(gvec_fmin_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) -DEF_HELPER_FLAGS_5(gvec_fmin_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) -DEF_HELPER_FLAGS_5(gvec_fmin_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) - -DEF_HELPER_FLAGS_5(gvec_fmaxnum_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, f= pst, i32) -DEF_HELPER_FLAGS_5(gvec_fmaxnum_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, f= pst, i32) -DEF_HELPER_FLAGS_5(gvec_fmaxnum_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, f= pst, i32) - -DEF_HELPER_FLAGS_5(gvec_fminnum_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, f= pst, i32) -DEF_HELPER_FLAGS_5(gvec_fminnum_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, f= pst, i32) -DEF_HELPER_FLAGS_5(gvec_fminnum_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, f= pst, i32) - -DEF_HELPER_FLAGS_5(gvec_recps_nf_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, = fpst, i32) -DEF_HELPER_FLAGS_5(gvec_recps_nf_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, = fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_rsqrts_nf_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr,= fpst, i32) -DEF_HELPER_FLAGS_5(gvec_rsqrts_nf_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr,= fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fmla_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) -DEF_HELPER_FLAGS_5(gvec_fmla_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) - -DEF_HELPER_FLAGS_5(gvec_fmls_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) -DEF_HELPER_FLAGS_5(gvec_fmls_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) - -DEF_HELPER_FLAGS_5(gvec_vfma_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) -DEF_HELPER_FLAGS_5(gvec_vfma_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) -DEF_HELPER_FLAGS_5(gvec_vfma_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) - -DEF_HELPER_FLAGS_5(gvec_vfms_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) -DEF_HELPER_FLAGS_5(gvec_vfms_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) -DEF_HELPER_FLAGS_5(gvec_vfms_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst= , i32) - -DEF_HELPER_FLAGS_5(gvec_ah_vfms_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, f= pst, i32) -DEF_HELPER_FLAGS_5(gvec_ah_vfms_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, f= pst, i32) -DEF_HELPER_FLAGS_5(gvec_ah_vfms_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, f= pst, i32) - -DEF_HELPER_FLAGS_5(gvec_ftsmul_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_ftsmul_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_ftsmul_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fmul_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmul_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmul_idx_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fmla_nf_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmla_nf_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fmls_nf_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmls_nf_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_6(gvec_fmla_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_6(gvec_fmla_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_6(gvec_fmla_idx_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_6(gvec_fmls_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_6(gvec_fmls_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_6(gvec_fmls_idx_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_6(gvec_ah_fmls_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_6(gvec_ah_fmls_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_6(gvec_ah_fmls_idx_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_uqadd_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_uqadd_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_uqadd_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_uqadd_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sqadd_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sqadd_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sqadd_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sqadd_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_uqsub_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_uqsub_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_uqsub_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_uqsub_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sqsub_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sqsub_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sqsub_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sqsub_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_usqadd_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_usqadd_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_usqadd_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_usqadd_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_suqadd_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_suqadd_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_suqadd_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_suqadd_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(gvec_fmlal_a32, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(gvec_fmlal_a64, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a32, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a64, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, env, i32) - -DEF_HELPER_FLAGS_2(frint32_s, TCG_CALL_NO_RWG, f32, f32, fpst) -DEF_HELPER_FLAGS_2(frint64_s, TCG_CALL_NO_RWG, f32, f32, fpst) -DEF_HELPER_FLAGS_2(frint32_d, TCG_CALL_NO_RWG, f64, f64, fpst) -DEF_HELPER_FLAGS_2(frint64_d, TCG_CALL_NO_RWG, f64, f64, fpst) - -DEF_HELPER_FLAGS_3(gvec_ceq0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_ceq0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_clt0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_clt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_cle0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_cle0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_cgt0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_cgt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_cge0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_cge0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_smulh_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_smulh_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_smulh_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_smulh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_umulh_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_umulh_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_umulh_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_umulh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_sshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_sshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_ushl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_ushl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_pmul_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_pmull_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(neon_pmull_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_3(gvec_ssra_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_ssra_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_ssra_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_ssra_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_FLAGS_3(gvec_usra_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_usra_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_usra_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_usra_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_FLAGS_3(gvec_srshr_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_srshr_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_srshr_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_srshr_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_FLAGS_3(gvec_urshr_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_urshr_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_urshr_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_urshr_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_FLAGS_3(gvec_srsra_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_srsra_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_srsra_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_srsra_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_FLAGS_3(gvec_ursra_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_ursra_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_ursra_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_ursra_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_FLAGS_3(gvec_sri_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_sri_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_sri_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_sri_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_FLAGS_3(gvec_sli_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_sli_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_sli_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_sli_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_sabd_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_sabd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_sabd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_sabd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_uabd_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_uabd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_uabd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_uabd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_saba_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_saba_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_saba_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_saba_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_uaba_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_uaba_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_uaba_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_uaba_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_mul_idx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) -DEF_HELPER_FLAGS_4(gvec_mul_idx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) -DEF_HELPER_FLAGS_4(gvec_mul_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) - -DEF_HELPER_FLAGS_5(gvec_mla_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_mla_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_mla_idx_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(gvec_mls_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_mls_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_mls_idx_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(neon_sqdmulh_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(neon_sqdmulh_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(neon_sqrdmulh_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(neon_sqrdmulh_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(neon_sqdmulh_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(neon_sqdmulh_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(neon_sqrdmulh_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(neon_sqrdmulh_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(neon_sqrdmlah_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(neon_sqrdmlah_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(neon_sqrdmlsh_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(neon_sqrdmlsh_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(sve2_sqdmulh_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) -DEF_HELPER_FLAGS_4(sve2_sqdmulh_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) -DEF_HELPER_FLAGS_4(sve2_sqdmulh_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) -DEF_HELPER_FLAGS_4(sve2_sqdmulh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) - -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, = i32) -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, = i32) -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, = i32) -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, = i32) - -DEF_HELPER_FLAGS_4(sve2_sqdmulh_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqdmulh_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqdmulh_idx_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_idx_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_6(sve2_fmlal_zzzw_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_6(sve2_fmlal_zzxw_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, env, i32) - -DEF_HELPER_FLAGS_4(gvec_xar_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(gvec_smmla_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_ummla_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_usmmla_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_6(gvec_bfdot, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_6(gvec_bfdot_idx, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, env, i32) - -DEF_HELPER_FLAGS_6(gvec_bfmmla, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, env, i32) - -DEF_HELPER_FLAGS_6(gvec_bfmlal, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_6(gvec_bfmlal_idx, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_sclamp_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sclamp_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sclamp_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sclamp_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(gvec_uclamp_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_uclamp_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_uclamp_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(gvec_faddp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fps= t, i32) -DEF_HELPER_FLAGS_5(gvec_faddp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fps= t, i32) -DEF_HELPER_FLAGS_5(gvec_faddp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fps= t, i32) - -DEF_HELPER_FLAGS_5(gvec_fmaxp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fps= t, i32) -DEF_HELPER_FLAGS_5(gvec_fmaxp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fps= t, i32) -DEF_HELPER_FLAGS_5(gvec_fmaxp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fps= t, i32) - -DEF_HELPER_FLAGS_5(gvec_fminp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fps= t, i32) -DEF_HELPER_FLAGS_5(gvec_fminp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fps= t, i32) -DEF_HELPER_FLAGS_5(gvec_fminp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fps= t, i32) - -DEF_HELPER_FLAGS_5(gvec_fmaxnump_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, = fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmaxnump_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, = fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmaxnump_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, = fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fminnump_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, = fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fminnump_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, = fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fminnump_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, = fpst, i32) - -DEF_HELPER_FLAGS_4(gvec_addp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_addp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_addp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_addp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_smaxp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_smaxp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_smaxp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_sminp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_sminp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_sminp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_umaxp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_umaxp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_umaxp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_uminp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_uminp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_uminp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_3(gvec_urecpe_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_ursqrte_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +#include "tcg/helper.h" =20 #ifdef TARGET_AARCH64 #include "tcg/helper-a64.h" diff --git a/target/arm/helper.h b/target/arm/tcg/helper.h similarity index 99% copy from target/arm/helper.h copy to target/arm/tcg/helper.h index 0a4fc90fa8b..80db7c2c37a 100644 --- a/target/arm/helper.h +++ b/target/arm/tcg/helper.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + DEF_HELPER_FLAGS_1(sxtb16, TCG_CALL_NO_RWG_SE, i32, i32) DEF_HELPER_FLAGS_1(uxtb16, TCG_CALL_NO_RWG_SE, i32, i32) =20 @@ -1149,11 +1151,3 @@ DEF_HELPER_FLAGS_4(gvec_uminp_s, TCG_CALL_NO_RWG, vo= id, ptr, ptr, ptr, i32) =20 DEF_HELPER_FLAGS_3(gvec_urecpe_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) DEF_HELPER_FLAGS_3(gvec_ursqrte_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -#ifdef TARGET_AARCH64 -#include "tcg/helper-a64.h" -#include "tcg/helper-sve.h" -#include "tcg/helper-sme.h" -#endif - -#include "tcg/helper-mve.h" --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747305663; cv=none; d=zohomail.com; s=zohoarc; b=X/sTC4uSy97CxXKXh3vSbSjOTsz4720lD16RzUvMxxr/93qV16k749CgJ0X0vQS1t+lth5N+acPiTOREAl/PVgXaxAgL2Td94TjemeRjZkUbCYOcI+mwuFjUrHMR5MSEWiCZkdAaFonbESq279P4mQTAy0TC2/nrzYclLBSh1U8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747305663; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=2TzAtDDzJpSwPwlAZbZ50asH3mlBjtiOUxLHKYs7gC0=; b=Z1MvqZoeRGL4wtAwePMl2ax6DF/SD/lgqmNljMby2VmbagVwypxpM3tJFU++lq0CpluPfzy+swqzf+Bq7zJQlR5jayCRw2U8eFJ3waf+1QF7vgwy5ky/wwQbfXYjm0e9czOvACtHsi3yI3+ZdVr/V1kBpKNuFr1UrwH1Hv+qksY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747305663495813.7017210904992; Thu, 15 May 2025 03:41:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uFVol-0007Ax-C6; Thu, 15 May 2025 06:27:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uFVnG-0004xl-BD for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:26 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uFVnE-0008CC-KK for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:26 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-43ede096d73so5411785e9.2 for ; Thu, 15 May 2025 03:26:24 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442f396c3a4sm65657855e9.26.2025.05.15.03.26.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 03:26:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747304783; x=1747909583; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=2TzAtDDzJpSwPwlAZbZ50asH3mlBjtiOUxLHKYs7gC0=; b=l7dOSEqhlvT5HnE1Z6ClcCQBfu+naD82QwfwDAhaaISAjBxDyi0eeqfYzCnFo2Ktlb S2+qcFl1JReGquxv9oK18K95jVh2rQJeTnV4AG343uSa/FpUjNMazS6mXUAurVHYrpps 7HfGk0tqHpj/dJhBg1XLztHdjT0Jbfe9iriIQ+wl8NbR4HZSLOZsyR3vSSmiMBqMdyZ3 ZakPS2igM3U5gyeBAOIjJym0fYjoAaoOcJOR8geX1NgeLyi7vQsJ7cg9IDdtgI3Unmco atfEJzKqeoqcT6qaHefrtGQOlL9tuelRTcezcgiUJcNe6O5S7MJd+EwYcQVSvDJR4yF4 f+Zw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747304783; x=1747909583; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2TzAtDDzJpSwPwlAZbZ50asH3mlBjtiOUxLHKYs7gC0=; b=JHYj87n2+QAMkPPlUG3c4bHUZXx0GKbfmMpTle+c3+yAI0YYJP9O7Rq5P230j9UKL1 o3VMpmZVZg1K8nJbP529q4GUZ2y1jvuCulgRAF80QvedydxYNloijWChAU7jD0/nb0w4 3ej2M1HE/kmu9E/pSWjVyh2tdtDvCZsgk92Ix2VF1C9NWaBtvDNdNpOQs77R/CafLZ/i l3GPFLjP9B8gxl8k8Lu5ZR/Q2VR/jZVqDhXD1piv0eAr7pBhPvCZLODRHVf9FvPbOTq7 L4zApNye3S4vd2g4zdrSQoMqVFpERDDKqaWtHDzpqOkNuRD5UqppCSGwz+b1sfhlWPK9 EMzQ== X-Gm-Message-State: AOJu0YzUR0GNNUXI3JYpvgXSUJJ7pD90MxK8SM9hO3jlnWHaNlIe8Uu8 02teKIfV8jhboHVorkHSLGYbHLCBFc1IKV7aRsUm/vEKu901850BQ4+tmyxRdtEHlJLegHd9bNA 0wIQ= X-Gm-Gg: ASbGncvAYCNJekeY18QAztCZiQPyrENmcvUItD8pI5GLM+h/OdJ/4N554oVcJVsbiEL b9H5KqKTnbvTmEUTj959mCQxvyCSkO1QOTeV9sHDneBrmUSw/Kn4BUZrLOOO8r7anzNlXt4FTeS oqDaNQrh7gqBPvT28mon0kM0ISRhdDfPslGNnfHZT3Msji2ZlHX0BoHpCaUVxvT1KRyjZNfo/XR vgoEcAKNZxCL7twWNgVTFzRsoQ5G968py/xQwa4DffJisFB++ysli2Rt5ZKJLtSK/gH5hUSuzGc ezhxSx9Qa/c+cX6ACCHGZ0LdJ1i2VPkNsirjKRja3ioiM8/6XtG5+k5+9Q== X-Google-Smtp-Source: AGHT+IFOPI//ekFYMabXJ7a50nqbJVyH0Ry3nT67Vu1oeldTePkglPY1hO0wkVfm5TmgDIVTfCNMvw== X-Received: by 2002:a05:600c:3c85:b0:442:e03b:589d with SMTP id 5b1f17b1804b1-442f21610b5mr63347045e9.24.1747304783048; Thu, 15 May 2025 03:26:23 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/58] target/arm/debug_helper: only include common helpers Date: Thu, 15 May 2025 11:25:14 +0100 Message-ID: <20250515102546.2149601-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305664634116600 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Avoid pulling helper.h which contains TARGET_AARCH64. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-id: 20250512180502.2395029-17-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/debug_helper.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index de7999f6a94..cad0a5db707 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -11,10 +11,12 @@ #include "internals.h" #include "cpu-features.h" #include "cpregs.h" -#include "exec/helper-proto.h" #include "exec/watchpoint.h" #include "system/tcg.h" =20 +#define HELPER_H "tcg/helper.h" +#include "exec/helper-proto.h.inc" + #ifdef CONFIG_TCG /* Return the Exception Level targeted by debug exceptions. */ static int arm_debug_target_el(CPUARMState *env) --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747304923; cv=none; d=zohomail.com; s=zohoarc; b=Vjylea00rWK3TO0l7x9XMcSfz7ojZIPe43b98KsdR/5tBJz2RSSLH1lKw2xXEkcYxIWSbTOKCUtJuQTXl/32qNlFUWfQ2eVAWK5u8/CnDDdU75Zizxs14/BsIm3NDSyWCx4SbC5iZT32iE4ndzIKKxLIR/AmOFXvU2V9kP5mWIs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747304923; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Byp0Y4O5zheOoMWAZrB5mhT0UXR53h/CRs+fbHyD9ww=; b=Lxa87AfUwdopv0NwymevJ5lBg3AWotJF+GolJhJmX5r3eGpFNVF45Z7JkTPgT1Lv5A9xXkmatqz1Yt2RREw/xZYcqiMNm0aYXGHK6HWdE4Vqiu105B+GcC1j3TkkUv3+6PPPyOdfNMsmGs581OBWwj/ta87VTONON6atbfJNwPY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747304923879942.0331817569701; Thu, 15 May 2025 03:28:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uFVny-0005jU-Si; Thu, 15 May 2025 06:27:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uFVnH-0004zQ-LX for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:29 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uFVnF-0008CQ-NT for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:27 -0400 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-3a0b7fbdde7so669323f8f.2 for ; Thu, 15 May 2025 03:26:25 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Thu, 15 May 2025 03:26:23 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/58] target/arm/debug_helper: remove target_ulong Date: Thu, 15 May 2025 11:25:15 +0100 Message-ID: <20250515102546.2149601-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747304925872116600 From: Pierrick Bouvier Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Pierrick Bouvier Message-id: 20250512180502.2395029-18-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/debug_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index cad0a5db707..69fb1d0d9ff 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -380,7 +380,7 @@ bool arm_debug_check_breakpoint(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); 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Thu, 15 May 2025 03:26:25 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/58] target/arm/debug_helper: compile file twice (user, system) Date: Thu, 15 May 2025 11:25:16 +0100 Message-ID: <20250515102546.2149601-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305670793116600 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-id: 20250512180502.2395029-19-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/meson.build | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index de214fe5d56..48a6bf59353 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -1,7 +1,6 @@ arm_ss =3D ss.source_set() arm_common_ss =3D ss.source_set() arm_ss.add(files( - 'debug_helper.c', 'gdbstub.c', 'helper.c', 'vfp_fpscr.c', @@ -29,11 +28,18 @@ arm_system_ss.add(files( arm_user_ss =3D ss.source_set() arm_user_ss.add(files('cpu.c')) arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files( - 'cpu32-stubs.c')) + 'cpu32-stubs.c', +)) +arm_user_ss.add(files( + 'debug_helper.c', +)) =20 arm_common_system_ss.add(files('cpu.c'), capstone) arm_common_system_ss.add(when: 'TARGET_AARCH64', if_false: files( 'cpu32-stubs.c')) +arm_common_system_ss.add(files( + 'debug_helper.c', +)) =20 subdir('hvf') =20 --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 15 May 2025 03:26:26 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/58] target/arm/helper: restrict include to common helpers Date: Thu, 15 May 2025 11:25:17 +0100 Message-ID: <20250515102546.2149601-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305253166116600 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-id: 20250512180502.2395029-20-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 4a2d1ecbfee..3795dccd16b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12,7 +12,6 @@ #include "cpu.h" #include "internals.h" #include "cpu-features.h" -#include "exec/helper-proto.h" #include "exec/page-protection.h" #include "exec/mmap-lock.h" #include "qemu/main-loop.h" @@ -35,6 +34,9 @@ #include "cpregs.h" #include "target/arm/gtimer.h" =20 +#define HELPER_H "tcg/helper.h" +#include "exec/helper-proto.h.inc" + #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ =20 static void switch_mode(CPUARMState *env, int mode); --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 15 May 2025 03:26:27 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/58] target/arm/helper: replace target_ulong by vaddr Date: Thu, 15 May 2025 11:25:18 +0100 Message-ID: <20250515102546.2149601-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747304857265116600 From: Pierrick Bouvier Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Pierrick Bouvier Message-id: 20250512180502.2395029-21-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 3795dccd16b..d2607107eb9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10621,7 +10621,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *= cs) ARMCPU *cpu =3D ARM_CPU(cs); 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442f396c3a4sm65657855e9.26.2025.05.15.03.26.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 03:26:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747304789; x=1747909589; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=8OqIAv12cBzD5xPq0tKwoeVHDMUht+s84ge6JHo6zJM=; b=GQLXccCASQTBXz1236JTe38t4uPAcTU4hz3vnLZEWm5tbYDJaEzxstoS9v1CPl2M/h tIQ4wtHLAHkzPfZvVBn/rDAJAiJSUP//0gUidC/MzUM36SgFwwDlWZa3J4VMnW79RBCw GQR0c3T8vWR8o6DiPFAgyefUvlQ3nn0DwJyaxz+kCh+sd2vrGbgNGJyig4SPBp2YaLBc 5Pwf4JF/IPSAZ5RxndL0LwK7NyWE9DaVflVFmsO9vkrK8mgN12bSwqMuXfI7LXXgp0q6 0Bv7PNFBD9XHKITHDzWsrh+0nkRaoAnuObBhee9YMUa47X0ehOKzgEl//+4IitR+VhI5 Leag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747304789; x=1747909589; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8OqIAv12cBzD5xPq0tKwoeVHDMUht+s84ge6JHo6zJM=; b=gEM9OOFKaQgCWlJGZK1PxzPGkGtiUDo/BNry8RK6kjEVao1LPPCzpyvWiVqN5soCgK Vjx1HCDk5FIBM7Kvnx2YqCcLtj1VEBW9RBQuHOEh9Oi8jqukR2c5jIYhcIHdA/V8kPCr tu+oxXGekm8fwSUokTvVuhVFPbOOa6ej4QgnF080bD7pAR3JbR1XQIY2Yi7poamZ92IG mweOoV6bZ1YNHs7xPqXNSnBAgFJM7VbTTf7NeplTzMTK88YHCSvJCMYM3LGDoVX424tk Z7mNIUMM51mmiF7t3put2MfV7ft+5DVdjxe+ECZTnI6XtbnBgsSxhw9LoU3o5LnA5Swx cscA== X-Gm-Message-State: AOJu0YwRUrHg+nIQprWfv/QZAxuoWiwPyZd5z5EDQCJZNBim+SqxH4HI rPFp8q8UBBOYsre83ESSGRQ2gSPx+aUj+MuD5R4EjOw5DmKomxxC8xUht2IhtCoYBENljp3v7m4 pYOU= X-Gm-Gg: ASbGnctezxD1A8Qh01ZDu9cU1KUUEQVCNyNCfStSDmZUgcGwnjX91FaPP01AFonWdKJ Sj/EwgykoLjelitwt95khlKp7XK3CJZThDXfQw39WKwjqo3H+oOBbSzULcwh9OUhkRGNiE+j2HQ kqrdvAupZ7rR3Xl09FohLeiP4iacFjl5QHLi01nGKBEfDLwtsNwqwcnb934anjhpxlyjrlP9qLg M7pGHMEla0YSYIgJ2rIX3T93EPq+FieRsf85Ft2D2AZKMoUEk+9yX7/vjd3EYqMRilY70k1WxfD Za4WPBjmZxxJXIyKFAMFmoqqhc8AjLv1W1vkoDbmSwrPtJpwcOe+t+9/EA== X-Google-Smtp-Source: AGHT+IGniFgyKidmYnMdPWLKyU6MMEEXV1x0pcGRwM/vqXcAPbhh1jW17tzUbKFT2tz+rx88DepEpw== X-Received: by 2002:a05:600c:3f08:b0:43c:fd27:a216 with SMTP id 5b1f17b1804b1-442f970b20dmr15728895e9.23.1747304788800; Thu, 15 May 2025 03:26:28 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/58] target/arm/helper: expose aarch64 cpu registration Date: Thu, 15 May 2025 11:25:19 +0100 Message-ID: <20250515102546.2149601-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305418519116601 From: Pierrick Bouvier associated define_arm_cp_regs are guarded by "cpu_isar_feature(aa64_*)", so it's safe to expose that code for arm target (32 bit). Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Pierrick Bouvier Message-id: 20250512180502.2395029-22-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index d2607107eb9..92a975bbf78 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6590,7 +6590,6 @@ static const ARMCPRegInfo zcr_reginfo[] =3D { .writefn =3D zcr_write, .raw_writefn =3D raw_write }, }; =20 -#ifdef TARGET_AARCH64 static CPAccessResult access_tpidr2(CPUARMState *env, const ARMCPRegInfo *= ri, bool isread) { @@ -6824,7 +6823,6 @@ static const ARMCPRegInfo nmi_reginfo[] =3D { .writefn =3D aa64_allint_write, .readfn =3D aa64_allint_read, .resetfn =3D arm_cp_reset_ignore }, }; -#endif /* TARGET_AARCH64 */ =20 static void define_pmu_regs(ARMCPU *cpu) { @@ -7016,7 +7014,6 @@ static const ARMCPRegInfo lor_reginfo[] =3D { .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, }; =20 -#ifdef TARGET_AARCH64 static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *r= i, bool isread) { @@ -7509,8 +7506,6 @@ static const ARMCPRegInfo nv2_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.vncr_el2) }, }; =20 -#endif /* TARGET_AARCH64 */ - static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo = *ri, bool isread) { @@ -8951,7 +8946,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &hcrx_el2_reginfo); } =20 -#ifdef TARGET_AARCH64 if (cpu_isar_feature(aa64_sme, cpu)) { define_arm_cp_regs(cpu, sme_reginfo); } @@ -9012,7 +9006,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_nmi, cpu)) { define_arm_cp_regs(cpu, nmi_reginfo); } -#endif =20 if (cpu_isar_feature(any_predinv, cpu)) { define_arm_cp_regs(cpu, predinv_reginfo); --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747305416; cv=none; d=zohomail.com; s=zohoarc; b=jpHESXoZxYgZZ+/sZRWLsf5UJc/1N+ya+r9HdpK4N1YI/UiPa9zcy6Zs8SFF4Z+Fal1OXK474A+5Bgx16ijY4Z5vas/A6YRxAE+8MRwfGvXQSEj+cbuG8IPtmnjySxT8hn98dqdhdxS9M0i6TFf1rbX4L3jnpKwpgee6JSW7qro= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747305416; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=sFij1h3veGtKhSTyxyyf2bRq4SfQA6FXNfG9cnrUTkY=; b=RpEJIFG5/vEPll+6avKM+vaBE8WjpPngSa3Hqqk+rwwUeUPiOvGpQKC9yrsciTLrmhIOjpemTPympi5l2iPqCv3bZ5Oj2qtoMPk1WziwoeFFbok/JHdnqpAyMTjqaIfmG8TbsuKMybFQZJYbj+kMRe4bWD1i4Css5VRJrO+NZZw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747305416582869.94080677197; Thu, 15 May 2025 03:36:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uFVoO-0006QV-T9; Thu, 15 May 2025 06:27:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uFVnT-0005HX-E0 for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:44 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uFVnN-0008DQ-CV for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:38 -0400 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-3a0b7fbdde7so669572f8f.2 for ; Thu, 15 May 2025 03:26:31 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442f396c3a4sm65657855e9.26.2025.05.15.03.26.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 03:26:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747304790; x=1747909590; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=sFij1h3veGtKhSTyxyyf2bRq4SfQA6FXNfG9cnrUTkY=; b=K6+h+9Jskp2qOdvxZk97L7wBZB/LtXXZca0K84tqOYnsYbznuRFQFO8QYX2docrVaN ejl5DMVXgKSCMQ6Kdqc6f9IZ9P6O0JhJmmj9b1Fp0aovBu9eBS+GzqEII6159mThNZL4 DLfR1xGoNhmCHd53ggdcbvToDnC8ytK4rT2dX9ocSnZtvXmmDI12+K9Q4coGyo17DStN SxQ2FVzBdzu9YG5jb7+u5ifPVr+EukdqupNOpZOw+HS5mYBsfHGqvs0uK28s5eiHFm52 NrafIiNNIsrg9KmfjZ48JRay7okNnZ0h9UOsVlkqSvxc+BmQ9Up+a5iZCNrkCh/4ayGR 2BAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747304790; x=1747909590; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sFij1h3veGtKhSTyxyyf2bRq4SfQA6FXNfG9cnrUTkY=; b=O3sQcU+cWojHgN8PUXCix13wb7vmGWlPnzV3BKf+E12Zs4bJdVhqEHGU5pKRUSZMho ItjD+aq3HaQCn5SGtaPLCBtJQAxKi65KfFpz7ykITcLn3yRpKci8lImwoDvU7GHcVp9y jXdYBcTxCV7lhVcWqcEdb987lsbCci+EefDbZ5kJWntERXuD0DGEoWXdc9DFL3jLXTPh ui5CWdgINe3d8yB15RvUNZR07DE4Z8yWyAz3OQHWRmqqhX8fn4+lmiWHXvuFoK4QV0P9 d1LSAJKyGIVnMKVnO6GRguYHKUD1NjVyMaYrgzTVE4wqcBXEQrX1jXj7DJest/NtFYkZ aKdg== X-Gm-Message-State: AOJu0YxBqIC7sZLOZRbs/FOCXDq2+7B4YKNJicJM8MPUrF+yogFSO6nk fWC3Dcsah0i+Nfuhj1N2OuxTAHB2tfExY16I5FFqkYhCTRWaZxTei2aLEfI8GiGeK8ixHTsI2xs soh8= X-Gm-Gg: ASbGncvH7gIdvjmz36zff8cCaB+1FubfRlHXAECmAadIIwT2Oe2q7hKRqa/E4ggERqK CY841x/te1tDsx41NoKdIgAhLSbh9novvhzXS2QmK88Bx4mtgfao6+BOZVnSMv4T9j8BBw5JG+l cVFztKGzmbGTGJfJq4SWBWBB8SoyHjgisafCy4xpMPV34V2E0/HV1mhy3or+Sh9F1cu0TBen04n 9IDBhU853v3tTlpTTOBxtibKH4gdhVDn3mmxYqZfr1mgnMFcOxSK99jT99xYgHCSr51D7x0iFNG B0IeeJE5Ydrh4Wuh6ENTZuEAsL6ZhGArwFhhMAnhU7tUUJz1PrkSKDoo4w== X-Google-Smtp-Source: AGHT+IHRyXMSwYfDhHga5wPTdxeVIcP7wHyvoPOwzpUNT9kl1ISc5IUJPq6ZDfUHwoA4dsXfssgQnw== X-Received: by 2002:a05:6000:381:b0:3a2:229:2a4d with SMTP id ffacd0b85a97d-3a3496a49fdmr5513537f8f.22.1747304790042; Thu, 15 May 2025 03:26:30 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/58] target/arm/helper: remove remaining TARGET_AARCH64 Date: Thu, 15 May 2025 11:25:20 +0100 Message-ID: <20250515102546.2149601-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305418537116600 From: Pierrick Bouvier They were hiding aarch64_sve_narrow_vq and aarch64_sve_change_el, which we can expose safely. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20250512180502.2395029-23-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 92a975bbf78..aae8554e8f2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -29,6 +29,7 @@ #include "qemu/guest-random.h" #ifdef CONFIG_TCG #include "accel/tcg/probe.h" +#include "accel/tcg/getpc.h" #include "semihosting/common-semi.h" #endif #include "cpregs.h" @@ -6565,9 +6566,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, */ new_len =3D sve_vqm1_for_el(env, cur_el); if (new_len < old_len) { -#ifdef TARGET_AARCH64 aarch64_sve_narrow_vq(env, new_len + 1); -#endif } } =20 @@ -10625,9 +10624,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *= cs) * Note that new_el can never be 0. If cur_el is 0, then * el0_a64 is is_a64(), else el0_a64 is ignored. */ -#ifdef TARGET_AARCH64 aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); -#endif } =20 if (cur_el < new_el) { @@ -11418,7 +11415,6 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env) return arm_mmu_idx_el(env, arm_current_el(env)); } =20 -#ifdef TARGET_AARCH64 /* * The manual says that when SVE is enabled and VQ is widened the * implementation is allowed to zero the previously inaccessible @@ -11530,12 +11526,9 @@ void aarch64_sve_change_el(CPUARMState *env, int o= ld_el, =20 /* When changing vector length, clear inaccessible state. */ if (new_len < old_len) { -#ifdef TARGET_AARCH64 aarch64_sve_narrow_vq(env, new_len + 1); -#endif } } -#endif =20 #ifndef CONFIG_USER_ONLY ARMSecuritySpace arm_security_space(CPUARMState *env) --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747305136; cv=none; d=zohomail.com; s=zohoarc; b=nUy8laZa/2nFC4gcKzXIipVoyEUWM3MjkHQ9nQEMLGj8sLXZRVGmOMuOW2aWoONXsvivL8FXv70YbiJly8l1NyrRaKMKY6Hqskr5M87m/rOXUA/yOwofW6C/b2Dq+9qLk6m7Pd5ioHrKHYKtGYXia2kjMH9klPbumf18ggvNMWM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747305136; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=rwfPuBQXcGtWoJn9msWHbhqRij5/5zipndMnWAXWLc4=; b=fUAc0lyB6usNnNn34gSFTRScSNfi2RLdTMx9MKYDqDLzHpHTLq7jBCEQjQ2TYWqoeE5QI/oqVpdiOfmZKBFoRPVaTNP9wFb1LeqTtexpzEgTxE2o59W3I40R2g9HPOB998+7XbgWfV/2z4jAKIcueaQ7he+bVnS7xrB7rdeUmLQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747305136837127.21856407941914; Thu, 15 May 2025 03:32:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uFVoN-0006Mn-R7; Thu, 15 May 2025 06:27:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uFVnT-0005Hg-Fc for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:44 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uFVnP-0008Dg-3l for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:38 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-43d2d952eb1so5860955e9.1 for ; Thu, 15 May 2025 03:26:32 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Thu, 15 May 2025 03:26:31 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/58] target/arm/helper: compile file twice (user, system) Date: Thu, 15 May 2025 11:25:21 +0100 Message-ID: <20250515102546.2149601-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305138326116600 From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20250512180502.2395029-24-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/meson.build | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index 48a6bf59353..c8c80c3f969 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -2,7 +2,6 @@ arm_ss =3D ss.source_set() arm_common_ss =3D ss.source_set() arm_ss.add(files( 'gdbstub.c', - 'helper.c', 'vfp_fpscr.c', )) arm_ss.add(zlib) @@ -32,6 +31,7 @@ arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files( )) arm_user_ss.add(files( 'debug_helper.c', + 'helper.c', )) =20 arm_common_system_ss.add(files('cpu.c'), capstone) @@ -39,6 +39,7 @@ arm_common_system_ss.add(when: 'TARGET_AARCH64', if_false= : files( 'cpu32-stubs.c')) arm_common_system_ss.add(files( 'debug_helper.c', + 'helper.c', )) =20 subdir('hvf') --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 15 May 2025 03:26:33 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 34/58] target/arm/vfp_fpscr: compile file twice (user, system) Date: Thu, 15 May 2025 11:25:22 +0100 Message-ID: <20250515102546.2149601-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305664630116600 From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20250512180502.2395029-25-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/meson.build | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index c8c80c3f969..06d479570e2 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -2,7 +2,6 @@ arm_ss =3D ss.source_set() arm_common_ss =3D ss.source_set() arm_ss.add(files( 'gdbstub.c', - 'vfp_fpscr.c', )) arm_ss.add(zlib) =20 @@ -32,6 +31,7 @@ arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files( arm_user_ss.add(files( 'debug_helper.c', 'helper.c', + 'vfp_fpscr.c', )) =20 arm_common_system_ss.add(files('cpu.c'), capstone) @@ -40,6 +40,7 @@ arm_common_system_ss.add(when: 'TARGET_AARCH64', if_false= : files( arm_common_system_ss.add(files( 'debug_helper.c', 'helper.c', + 'vfp_fpscr.c', )) =20 subdir('hvf') --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 15 May 2025 03:26:34 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 35/58] target/arm/arch_dump: remove TARGET_AARCH64 conditionals Date: Thu, 15 May 2025 11:25:23 +0100 Message-ID: <20250515102546.2149601-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305091823116600 From: Pierrick Bouvier Associated code is protected by cpu_isar_feature(aa64*) Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Pierrick Bouvier Message-id: 20250512180502.2395029-26-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/arch_dump.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c index c40df4e7fd7..1dd79849c13 100644 --- a/target/arm/arch_dump.c +++ b/target/arm/arch_dump.c @@ -143,7 +143,6 @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFun= ction f, return 0; } =20 -#ifdef TARGET_AARCH64 static off_t sve_zreg_offset(uint32_t vq, int n) { off_t off =3D sizeof(struct aarch64_user_sve_header); @@ -231,7 +230,6 @@ static int aarch64_write_elf64_sve(WriteCoreDumpFunctio= n f, =20 return 0; } -#endif =20 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, int cpuid, DumpState *s) @@ -273,11 +271,9 @@ int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, = CPUState *cs, return ret; } =20 -#ifdef TARGET_AARCH64 if (cpu_isar_feature(aa64_sve, cpu)) { ret =3D aarch64_write_elf64_sve(f, env, cpuid, s); } -#endif =20 return ret; } @@ -451,11 +447,9 @@ ssize_t cpu_get_note_size(int class, int machine, int = nr_cpus) if (class =3D=3D ELFCLASS64) { note_size =3D AARCH64_PRSTATUS_NOTE_SIZE; note_size +=3D AARCH64_PRFPREG_NOTE_SIZE; -#ifdef TARGET_AARCH64 if (cpu_isar_feature(aa64_sve, cpu)) { note_size +=3D AARCH64_SVE_NOTE_SIZE(&cpu->env); } -#endif } else { note_size =3D ARM_PRSTATUS_NOTE_SIZE; if (cpu_isar_feature(aa32_vfp_simd, cpu)) { --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 15 May 2025 03:26:35 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 36/58] target/arm/arch_dump: compile file once (system) Date: Thu, 15 May 2025 11:25:24 +0100 Message-ID: <20250515102546.2149601-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305130086116600 From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20250512180502.2395029-27-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index 06d479570e2..95a2b077dd6 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -15,7 +15,6 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( arm_system_ss =3D ss.source_set() arm_common_system_ss =3D ss.source_set() arm_system_ss.add(files( - 'arch_dump.c', 'arm-powerctl.c', 'arm-qmp-cmds.c', 'cortex-regs.c', @@ -38,6 +37,7 @@ arm_common_system_ss.add(files('cpu.c'), capstone) arm_common_system_ss.add(when: 'TARGET_AARCH64', if_false: files( 'cpu32-stubs.c')) arm_common_system_ss.add(files( + 'arch_dump.c', 'debug_helper.c', 'helper.c', 'vfp_fpscr.c', --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 15 May 2025 03:26:36 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 37/58] target/arm/arm-powerctl: compile file once (system) Date: Thu, 15 May 2025 11:25:25 +0100 Message-ID: <20250515102546.2149601-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305418519116600 From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20250512180502.2395029-28-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index 95a2b077dd6..7db573f4a97 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -15,7 +15,6 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( arm_system_ss =3D ss.source_set() arm_common_system_ss =3D ss.source_set() arm_system_ss.add(files( - 'arm-powerctl.c', 'arm-qmp-cmds.c', 'cortex-regs.c', 'machine.c', @@ -38,6 +37,7 @@ arm_common_system_ss.add(when: 'TARGET_AARCH64', if_false= : files( 'cpu32-stubs.c')) arm_common_system_ss.add(files( 'arch_dump.c', + 'arm-powerctl.c', 'debug_helper.c', 'helper.c', 'vfp_fpscr.c', --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 15 May 2025 03:26:37 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 38/58] target/arm/cortex-regs: compile file once (system) Date: Thu, 15 May 2025 11:25:26 +0100 Message-ID: <20250515102546.2149601-39-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305138346116600 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-id: 20250512180502.2395029-29-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index 7db573f4a97..6e0327b6f5b 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -16,7 +16,6 @@ arm_system_ss =3D ss.source_set() arm_common_system_ss =3D ss.source_set() arm_system_ss.add(files( 'arm-qmp-cmds.c', - 'cortex-regs.c', 'machine.c', 'ptw.c', )) @@ -38,6 +37,7 @@ arm_common_system_ss.add(when: 'TARGET_AARCH64', if_false= : files( arm_common_system_ss.add(files( 'arch_dump.c', 'arm-powerctl.c', + 'cortex-regs.c', 'debug_helper.c', 'helper.c', 'vfp_fpscr.c', --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442f396c3a4sm65657855e9.26.2025.05.15.03.26.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 03:26:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747304799; x=1747909599; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=VzUYeVehWBpH/+74MDsuZXiS92S2Pkyo2cNDX9duuiI=; b=J6qYBCN2jpHNjf6A2qYlIowzteap/W8apVEM02YKaAA6beXwlV8CXBbJS8GcWi8IuD xY3Tyz/s0nVz6YZlHL0TlFmXNgPYfd5fPCQmkBYIf2JI+rMWIT9uvo4bF3weu6NcHK9+ EY5XA8SkUZFMDJ0fjYVBK51j4rMREl7Ln2Z4rVIAOqRJaSO0Ej/6DqZ5NBJz3uLomXRW JN4yBtGYKDg5DE5kRElFZ5CAwk9nnkB0quA2twSWNLtG2nEli3UkTBjHI9Pts1zTPaW2 2Ia52GzOZVmjELnL5ofGA5ZCKi1ZcAqYB+BU5F9JQ8A0Y6NsMdG0G4T7/zeQKZ4ks92o 6lOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747304799; x=1747909599; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VzUYeVehWBpH/+74MDsuZXiS92S2Pkyo2cNDX9duuiI=; b=cqRZ+Ti6IRD5Sf69XIcDJ/MC1usjzdIOts0HISnTuxncD9sIvATBmcfygPT4y4Xfze 40GWBA61+OgY9ED73hcnzEEZnO6fpzTtOjwoDM9F3EXSZXlox+z+X2Z9rvIpyy1YSzps AXalFwcIKmjFFx4a+WkwczDIrQeWbAM8mD97KykY94QxaNuglK3TtxSIgPZl7btIBPTC cHWwRf9NtVSOQFFQX3PN/3adNLJCkWc3SIbZpskyg2OQIp5rygWeSxTolxbp1LscuQtn Li3M8ZUIz8ah2MDFsYaLgjCQy7jQjiLyuSM+n3znAku7sG6KP1wl61v6ctcGJd5aev2J luTw== X-Gm-Message-State: AOJu0Yzhl2EOen4JCYOLJvyDwWa7hv5swqBa1MJUsI4vqjdjsWvXS7lt aT2ZpdDqo4bukjLkoFU1YNEhoBlJec2I1txh3y8zY0O7hOD26mT4euXw1dATyCkFQ72RR1snt79 7w98= X-Gm-Gg: ASbGncs924lGvKxd2NKNLQoe/jgaLNBBoccuhDFnFHEvDN+75qZJ5slwHysssM9kIWL QvRfpbMTxJx5FHSCMuste9ow2eLdJ16bzIHsMtm2ETUyaII5xk1axKJGy3WDGr4kREK54gkRq/w hvNq7m/tML58X8TN9kEa7Y48bsGrY5HZA2PU85ug95NcckVv5u6Myw8fim9SNFcMKZ2BUTigtsZ M9HXSuGh+Zj80InF3OE1LFaaH2GUY1qJDo8W9bpfmfDPz/YaAf1rd4Wc9exgTsSgpQ7+7d8QwnK LDsTJipvkac7cuLRn5x5mDrVArxMB0Vz+0KDyek47rEAaXhTa2JhVCLxkw== X-Google-Smtp-Source: AGHT+IHj86quehy7uUCSTP1drMRgGpqVxcQYPmv2Q14xcvUbXJnPftSLe9d+r7XYMYph7DWngbDXag== X-Received: by 2002:a05:600c:8411:b0:43c:ef55:f1e8 with SMTP id 5b1f17b1804b1-442f20e93eemr68286735e9.13.1747304798681; Thu, 15 May 2025 03:26:38 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 39/58] target/arm/ptw: replace target_ulong with int64_t Date: Thu, 15 May 2025 11:25:27 +0100 Message-ID: <20250515102546.2149601-40-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305061375116600 From: Pierrick Bouvier sextract64 returns a signed value. Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Pierrick Bouvier Message-id: 20250512180502.2395029-30-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/ptw.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 89979c07e5a..68ec3f5e755 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1660,7 +1660,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, uint64_t ttbr; hwaddr descaddr, indexmask, indexmask_grainsize; uint32_t tableattrs; - target_ulong page_size; + uint64_t page_size; uint64_t attrs; int32_t stride; int addrsize, inputsize, outputsize; @@ -1733,7 +1733,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, * validation to do here. */ if (inputsize < addrsize) { - target_ulong top_bits =3D sextract64(address, inputsize, + uint64_t top_bits =3D sextract64(address, inputsize, addrsize - inputsize); if (-top_bits !=3D param.select) { /* The gap between the two regions is a Translation fault */ --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747305366; cv=none; d=zohomail.com; s=zohoarc; b=dIIhMsiiHxH7JGTeT4qDFaknuo/3gAnHLi4dZy5jcWgdBGaeSCzh+JRdY9JzoBB4OqoIokEjlHS0fdH+xWE0GXRdeiA+vVc8jxoyzkbY0SYyWmU9WwdqczdoJI+bTCxo3dsqxm6sW65EPcNsD/CzM5dA1KjPskcb0NM78GqVG64= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747305366; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=M4wis+oyI42kUUV62F9CkVaRrtKVkEpqI4xQo+H0IZg=; b=OopLkVsXpB8bBN4hP3GuuKo74KoFhVVfdFVAzTwaR7/gaxhOaLsKqB+9rNHu8yoe3DPJ5qIFSiygRAB4STSfuthSdfZ9BzRU4FkwkjmQTHN3LL+Q6wbVL8BzOVRZvo+93Fi0PoSpNQJjX94FnAmJHUHMPAePsDu03YlhUDGIymo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747305366925644.9146391419781; Thu, 15 May 2025 03:36:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uFVoO-0006NR-CQ; Thu, 15 May 2025 06:27:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uFVnc-0005NJ-DV for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:49 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uFVnV-0008Fl-9d for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:44 -0400 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-43cf06eabdaso7149225e9.2 for ; Thu, 15 May 2025 03:26:40 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442f396c3a4sm65657855e9.26.2025.05.15.03.26.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 03:26:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747304800; x=1747909600; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=M4wis+oyI42kUUV62F9CkVaRrtKVkEpqI4xQo+H0IZg=; b=tnHJQNA1GFqHW6c5plNcxqIZGLgppruWW5wt+JWdI95RrebGnV24LGqrw4PY87Fl7z i87J0O0iwfzNZkmarl3U6sDqmx803CVBqpoD/XO1bp2BAQKW0Kl+B3CTvDIJqMHs0Bd8 2FC46hSsiWfFbv4tHDvxGzmHNUBr/FATwvQQYkv84p0irFTasw14cgdGELAfNrZwnzlu V2K09ZSl6Y3Spo+VQwm6lmMKoRJA/R+Aj9Gy1o2v/qYEIoNXK+d54J5vtSm2wRHbA0iR 6HV7nF4EVb6R7N4iCoUSLg11syN0AAn/wNf6pLCuczjRMYnDHKkcDppLKEPlzm5f7c/r jN0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747304800; x=1747909600; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=M4wis+oyI42kUUV62F9CkVaRrtKVkEpqI4xQo+H0IZg=; b=l7Yfl350sf/63PHKn/cIciPtW7K8RPKv7n8oSpCHXuT3cvShKuy9nryY83YdGFwLEO 1EiohXrNKfy5fAS94NUsebzKmuJyIhWD/PFgz/POQI6pNRj5b7/m238kkMleXH/NIPgR oRTfEigujAY/sROOIXvWfDBlh37GtQyGGs7crHwhwqODMuIr4woUC6mD27tRUICM/TB6 +wfidRfc7NRXRTjc88dpdnmXutNOWs5dqtk7dnBAkb+jAUJyzgejxC28P/k49MNY4rwg I6R+xTmVqMJQ8nyKcFFWgp0xLstSTQDxwdybs+CFzJ5gTjPQnAeZAL9RbaGqTeROXf0m hp7g== X-Gm-Message-State: AOJu0Yz9Nr874oY0wSHhZnM6OYHUdGbABtD2gPO45aTlpaV25yuYTJ2u +ncNSDnjen1I/esqf2AIUQEtcWXgIencCml4g9pjVXIampJNHQQjbTwQ6S4A0MFgD7XfgN6n6/5 anJE= X-Gm-Gg: ASbGnctMjpuozQgcQzmRFAKNdLZDBNIYqj7geMLjg16JTuU/EXw5oXCvvje/gzZNL1V Hi5jBotlb2IbdOcf958/bqkH5jRDqRon3c6aM412a16qcG7kbwKi5Hys7oK9c+wTAX+jA5U1saH LS9fPyiWkW1pM5d1Xz4/Enzev60NTRa8FyZemH2TVuSbDr9urrLwkgvPWwhNzpyB60OJ+rk+WuI EIQoj4lycsxA2KjywWtFlsckUCv8nZmyjwRDuxYdohQq6642qe5kc34UL7oVP8gZ+32/g+k/jZa dIUsgA8HFahkadrH7iH3+VnGmGVSdZ8ZeGqZgYFz42CIHc1dhW7fHwUOLQ== X-Google-Smtp-Source: AGHT+IG3Vj/Ca8Oyuo/RAc7izkJhAKUzIiMozfQh21LGed+zkzi0rFkSu0v9Kdnq6DxkYHJqpTFjPQ== X-Received: by 2002:a05:600c:4e09:b0:43d:1b74:e89a with SMTP id 5b1f17b1804b1-442f96e8949mr19607585e9.9.1747304799641; Thu, 15 May 2025 03:26:39 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 40/58] target/arm/ptw: replace TARGET_AARCH64 by CONFIG_ATOMIC64 from arm_casq_ptw Date: Thu, 15 May 2025 11:25:28 +0100 Message-ID: <20250515102546.2149601-41-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305368128116600 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier This function needs 64 bit compare exchange, so we hide implementation for hosts not supporting it (some 32 bit target, which don't run 64 bit guests anyway). Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-id: 20250512180502.2395029-31-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/ptw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 68ec3f5e755..44170d831cc 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -737,7 +737,7 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t= old_val, uint64_t new_val, S1Translate *ptw, ARMMMUFaultInfo *fi) { -#if defined(TARGET_AARCH64) && defined(CONFIG_TCG) +#if defined(CONFIG_ATOMIC64) && defined(CONFIG_TCG) uint64_t cur_val; void *host =3D ptw->out_host; =20 --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747305488; cv=none; d=zohomail.com; s=zohoarc; b=L/AvDH8yBaPt4F9PCHvtUE74u2OqVUBs1tkqwtT+rAQj959MIDPYTr/+tuHWlrQLKcRfpvb6otvYEfUYylsPhMS+IPj27qhlcErsbViu18kgdPh5+4DhhpuyQODhr9GQfPIBDukUkjRfQEvfDL2kHkt86P+Qi58qkYX1G6weqHs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747305488; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Ab5pp6BZoHOVPbJgDowtlvgwNNGVrCIgmepaEE9nqb0=; b=SSziGV4SyJWiAUqafx2m3Ixd0YzOiEfpcpzd2yb6LtZPJ5nkNqE3+2JeoRXW2H0t66fA9+mpnuToJELJ7rMG4stfwjcB0xXtWU4O66dYbxOHfN/c30ULgP/9roPiSTWyQYwSbs1YeOqRQEqWuYdoYxKvsCVqA1/cMS25TL86S20= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747305488531772.285250692207; Thu, 15 May 2025 03:38:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uFVq6-00026s-1f; Thu, 15 May 2025 06:29:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uFVne-0005PF-Eb for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:50 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uFVnW-0008Fy-Uy for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:45 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-43d0618746bso5770015e9.2 for ; Thu, 15 May 2025 03:26:41 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Thu, 15 May 2025 03:26:40 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 41/58] target/arm/ptw: compile file once (system) Date: Thu, 15 May 2025 11:25:29 +0100 Message-ID: <20250515102546.2149601-42-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305489222116600 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-id: 20250512180502.2395029-32-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index 6e0327b6f5b..151184da71c 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -17,7 +17,6 @@ arm_common_system_ss =3D ss.source_set() arm_system_ss.add(files( 'arm-qmp-cmds.c', 'machine.c', - 'ptw.c', )) =20 arm_user_ss =3D ss.source_set() @@ -40,6 +39,7 @@ arm_common_system_ss.add(files( 'cortex-regs.c', 'debug_helper.c', 'helper.c', + 'ptw.c', 'vfp_fpscr.c', )) =20 --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 15 May 2025 03:26:41 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 42/58] target/arm/meson: accelerator files are not needed in user mode Date: Thu, 15 May 2025 11:25:30 +0100 Message-ID: <20250515102546.2149601-43-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305376245116600 From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20250512180502.2395029-33-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/meson.build | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index 151184da71c..29a36fb3c5e 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -5,9 +5,6 @@ arm_ss.add(files( )) arm_ss.add(zlib) =20 -arm_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm.c'), i= f_false: files('kvm-stub.c')) -arm_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c')) - arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'cpu64.c', 'gdbstub64.c')) @@ -18,6 +15,8 @@ arm_system_ss.add(files( 'arm-qmp-cmds.c', 'machine.c', )) +arm_system_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm= .c'), if_false: files('kvm-stub.c')) +arm_system_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c')) =20 arm_user_ss =3D ss.source_set() arm_user_ss.add(files('cpu.c')) --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 15 May 2025 03:26:42 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 43/58] target/arm/kvm-stub: compile file once (system) Date: Thu, 15 May 2025 11:25:31 +0100 Message-ID: <20250515102546.2149601-44-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747304923909116600 From: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-id: 20250512180502.2395029-34-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/meson.build | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index 29a36fb3c5e..bb1c09676d5 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -15,7 +15,7 @@ arm_system_ss.add(files( 'arm-qmp-cmds.c', 'machine.c', )) -arm_system_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm= .c'), if_false: files('kvm-stub.c')) +arm_system_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm= .c')) arm_system_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c')) =20 arm_user_ss =3D ss.source_set() @@ -32,6 +32,7 @@ arm_user_ss.add(files( arm_common_system_ss.add(files('cpu.c'), capstone) arm_common_system_ss.add(when: 'TARGET_AARCH64', if_false: files( 'cpu32-stubs.c')) +arm_common_system_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c')) arm_common_system_ss.add(files( 'arch_dump.c', 'arm-powerctl.c', --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 15 May 2025 03:26:43 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 44/58] target/arm/machine: reduce migration include to avoid target specific definitions Date: Thu, 15 May 2025 11:25:32 +0100 Message-ID: <20250515102546.2149601-45-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305358032116600 From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20250512180502.2395029-35-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/machine.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/machine.c b/target/arm/machine.c index 978249fb71b..f7956898fa1 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -6,7 +6,8 @@ #include "kvm_arm.h" #include "internals.h" #include "cpu-features.h" -#include "migration/cpu.h" +#include "migration/qemu-file-types.h" +#include "migration/vmstate.h" #include "target/arm/gtimer.h" =20 static bool vfp_needed(void *opaque) --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442f396c3a4sm65657855e9.26.2025.05.15.03.26.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 03:26:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747304804; x=1747909604; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=DMmPrEBzw/pNSwsYU/O6mEpqFCBPIG8Om9+uShyE0Pg=; b=SEkh6iQ5GCvPSEjRi+F31miNfrNTXZ4ivcEK+IfwWUDPf6BOOVO5X1ar+31vkPSVUb Wr7rL/iPAkNU46k+WtmkYU0xTDTLyEQ0NEK/K5L6wWC9If/aZAOtScdTO8LSOfkwB9NG hmRtVDAM/fRbyAvyIeFzISGkYUdctGU/Mu+JUf9WYB4SB9N+LDrjh83bdq7yMPNVTUz7 T0Yw8KL0tkZDn3EQ3f8UyJXLPwex9Fra19yhf3xzPMUB/1qGaAy4MFECcEjsrB9NsOMy s5Y6Y0EvOr20x7kQ24zgV9MPuFyoAFjxdFuLws5ltvWfnYrKRzydMk6eUbnLbQuqDDK7 CNhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747304804; x=1747909604; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DMmPrEBzw/pNSwsYU/O6mEpqFCBPIG8Om9+uShyE0Pg=; b=qq00hjWbyVOALTNWTSCx611cMHQ85gLlIWRTkK/wue3dCJD+rNsEQW5Qrcky80aUHs ou9fwTfymW9+linBOgTSQxUANc8rDEIeg8ZshDG8bbePrf+AHh4v7XtxTZQNXpOus2lh 8/e5JA9PONHdp0Vpu04IcYpgbLatQnf+r3oj/G1h7Q5nA2dYGOLEKN6XlSfSyW8HRZ1H jTeVXVdSk3cTNGLUgwEUqjeThWCwhW2i5P7WoRokDT8utJ0eXtJhArwjKgD58OY09TAO 9EvwxOT2k4vi5zNljS1s756XzfCfsVl+n7XEAGPbvuLxrhoRKzYtMWpCqrPm/2ZrhI7N Bb5A== X-Gm-Message-State: AOJu0Yw9CZ0UAmXUeW0D752THQnx4/7JPWxeL/QT0aFFM0Ixz3SGf37A UrS8YTwZ1yE6+nZAs3f3UrZQ0SO6gl7dZH+WgW/w2V/v1DrYjUJ3+2mLxkrQZ1Ov68VDThQ+rpC wxoc= X-Gm-Gg: ASbGncsZk6igvdQLZzFaeLVfM0CAJYo2+/XWuxj3aGrdEGi+/BZGO24t5FYxovqq9Nt ABtDr9TmA5y17D/tjqIFWsqMIZaeduOnp1IrQYGKN4G3+IhBKkqoYoZU8v7qCpNF/ZU2xl5Wnr3 14Ej27HX5NP/uqVICkCnk2B3mbkMmvGCrXX1Ctq9HXGQa8AE1VJm+EXqOTj588LdCJ8MCCHEupo a+QHZEqpN61xrZKHTYUsxzzIW7IG2fkFDZ/TzxBknC3FkTqEp479ZmbKdZpUPtdmEc11HFpbg2P 2IXG+WTRxDgdZU8KiFAGGaMKXdAVeSt6DLq/cviS/UkwMysuFuKVjSLlNA== X-Google-Smtp-Source: AGHT+IEV3TY8Y0GlDESxjmWa5J9Mc/1iI/bgx8PjdHRDNrLvAIPiQla2YFPY+4vWZWK1aCbVWTGWZw== X-Received: by 2002:a05:600c:3e86:b0:43c:eeee:b706 with SMTP id 5b1f17b1804b1-442f9706006mr18251145e9.24.1747304804361; Thu, 15 May 2025 03:26:44 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 45/58] target/arm/machine: remove TARGET_AARCH64 from migration state Date: Thu, 15 May 2025 11:25:33 +0100 Message-ID: <20250515102546.2149601-46-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305378222116600 From: Pierrick Bouvier This exposes two new subsections for arm: vmstate_sve and vmstate_za. Those sections have a ".needed" callback, which already allow to skip them when not needed. vmstate_sve .needed is checking cpu_isar_feature(aa64_sve, cpu). vmstate_za .needed is checking ZA flag in cpu->env.svcr. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20250512180502.2395029-36-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/machine.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/target/arm/machine.c b/target/arm/machine.c index f7956898fa1..868246a98c0 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -241,7 +241,6 @@ static const VMStateDescription vmstate_iwmmxt =3D { } }; =20 -#ifdef TARGET_AARCH64 /* The expression ARM_MAX_VQ - 2 is 0 for pure AArch32 build, * and ARMPredicateReg is actively empty. This triggers errors * in the expansion of the VMSTATE macros. @@ -321,7 +320,6 @@ static const VMStateDescription vmstate_za =3D { VMSTATE_END_OF_LIST() } }; -#endif /* AARCH64 */ =20 static bool serror_needed(void *opaque) { @@ -1102,10 +1100,8 @@ const VMStateDescription vmstate_arm_cpu =3D { &vmstate_pmsav7, &vmstate_pmsav8, &vmstate_m_security, -#ifdef TARGET_AARCH64 &vmstate_sve, &vmstate_za, -#endif &vmstate_serror, &vmstate_irq_line_state, &vmstate_wfxt_timer, --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747305303; cv=none; d=zohomail.com; s=zohoarc; b=FgjN4ASAAxSKTByU5lkpSV1ZSVvwC+2S8vYBSx2ADQzATt2MZB+1G87N3ph9JHJHxkBrIb3rHYclykImiEV+4MhztB7Hz7JmX+NTh+Gt58zjqiTkvL3CTZwMyhH3MMpWKis5Y9cmE/qBZyQ0YqDLOuLb/xYXqTxetvl2sLd+H8E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747305303; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=JgvcooGso6hgHoCAG9dIwH2FprpPy71bhrSzgHgqriY=; b=VxbWpxNsc3bv1FO/nTVks4thKurq2X/em/Tk3lzWB1hOlt+IzM0ko74M1qrvMRbLDrgoye6pu+0/XIqitG3slTuu8SlEU1Xtn21M7pM6etde0OgGFPpKbLtoC/3QwQmlQxNzhC+QtyGTZGrileqWs7Un9RG3/VNxzIVJq/kpzQA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747305303173633.9976167553416; Thu, 15 May 2025 03:35:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uFVp0-0000Nf-HA; Thu, 15 May 2025 06:28:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uFVnh-0005Va-5Q for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:53 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uFVne-0008Gl-Ao for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:52 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-440685d6afcso8448285e9.0 for ; Thu, 15 May 2025 03:26:46 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Thu, 15 May 2025 03:26:45 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 46/58] target/arm/machine: move cpu_post_load kvm bits to kvm_arm_cpu_post_load function Date: Thu, 15 May 2025 11:25:34 +0100 Message-ID: <20250515102546.2149601-47-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305303626116600 From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20250512180502.2395029-37-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 4 +++- target/arm/kvm.c | 13 ++++++++++++- target/arm/machine.c | 8 +------- 3 files changed, 16 insertions(+), 9 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index b638e09a687..c4178d1327c 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -83,8 +83,10 @@ void kvm_arm_cpu_pre_save(ARMCPU *cpu); * @cpu: ARMCPU * * Called from cpu_post_load() to update KVM CPU state from the cpreg list. + * + * Returns: true on success, or false if write_list_to_kvmstate failed. */ -void kvm_arm_cpu_post_load(ARMCPU *cpu); +bool kvm_arm_cpu_post_load(ARMCPU *cpu); =20 /** * kvm_arm_reset_vcpu: diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 82668d64385..a2791aa866f 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -938,13 +938,24 @@ void kvm_arm_cpu_pre_save(ARMCPU *cpu) } } =20 -void kvm_arm_cpu_post_load(ARMCPU *cpu) +bool kvm_arm_cpu_post_load(ARMCPU *cpu) { + if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) { + return false; + } + /* Note that it's OK for the TCG side not to know about + * every register in the list; KVM is authoritative if + * we're using it. + */ + write_list_to_cpustate(cpu); + /* KVM virtual time adjustment */ if (cpu->kvm_adjvtime) { cpu->kvm_vtime =3D *kvm_arm_get_cpreg_ptr(cpu, KVM_REG_ARM_TIMER_C= NT); cpu->kvm_vtime_dirty =3D true; } + + return true; } =20 void kvm_arm_reset_vcpu(ARMCPU *cpu) diff --git a/target/arm/machine.c b/target/arm/machine.c index 868246a98c0..e442d485241 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -976,15 +976,9 @@ static int cpu_post_load(void *opaque, int version_id) } =20 if (kvm_enabled()) { - if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) { + if (!kvm_arm_cpu_post_load(cpu)) { return -1; } - /* Note that it's OK for the TCG side not to know about - * every register in the list; KVM is authoritative if - * we're using it. - */ - write_list_to_cpustate(cpu); - kvm_arm_cpu_post_load(cpu); } else { if (!write_list_to_cpustate(cpu)) { return -1; --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442f396c3a4sm65657855e9.26.2025.05.15.03.26.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 03:26:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747304806; x=1747909606; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=wVaw38IJB5ualjLwd7Gyd/Z0jgsIF8bEQZE81xv9lGk=; b=wIedFG8FnRpySf74J+7lZkgwsH3sg407tKaUpBKQZiOysBsgzlpOZMTZnJZu0lMVRY y1oeut6FJNfskC+slw/mZ8V+0N3U/sQoCVlLCvptGAn7RBEqIpSn6OBSBikx4d6ivEXB +LQvuUiGlwpd7iQn8A5ogE74We75o5ngp6iHZ2Oy4u2y1q7C6+fABKh3XZbAfc4RWepV N9RJQM1ALIBIqPOhAP+HfqK5DCUewEucM6YiKoT2bgtopiIMhsJdT0loL2g0EeZLvqDm vwHSqYVpMq2siMUiFXbygfSnkIkHPXNpM8GHTN/AJ6VF4aVRGIVJp1tb+xExQeMAfTv1 bwyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747304806; x=1747909606; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wVaw38IJB5ualjLwd7Gyd/Z0jgsIF8bEQZE81xv9lGk=; b=bB1gzBqdQR2xrIlBpe37xkXEtnnn3ZV+yWb7z4MEGIdYEiUBHD2p1705i+ijuLnQ1f gfIwEGrMiaFbytcl/qn9D9DBO7Iqy1FlvoDhiGZF76KgUoWZ33P8/ZO9GBfr7Q4t/Ku7 iqdDMjdcHzQJn/GtB3a8AZC2fBD1houlb9HY4xLz6F5F//iDdNG/K2MeumQHGOjEgPHo Je77LZ+nWI/if/zO51rZF0Xb4iFnsyrGf0qvEp8yT9iD2fIDyF5Zj5wQkRO+xBN/mtnJ +lcXzSQ+uTop8ug7GDMSIIiQ7zV/qLozXSjKt7q0PSDPwd6V0+klwjdgKFycaXkb6a1w pCLQ== X-Gm-Message-State: AOJu0YxDSJFbzAaf7VnLq7CMVf5J7/9iYAo/ZPI2yEgYCEpFqe4ZrOmd keC0wPDGWQzX3sm2VZBeVZPA+/MT7fEZ7YtVO50EteMZGq2IHSLlkkpsiD2ljG0KYFaARtDqxnm J5rE= X-Gm-Gg: ASbGncslff9yRHyjKkwky1tClIr/UtwHLJ5cFODkqZmV/FKufIsT75y1ZoJrF+eR0h2 0LHzv6UMq0hZqAP8nykwdxlU1bR80xRuwkAh7cXli7n1eRMjF2i+ADXzRXJa/bf/khGaY3YY2km BqrpoZHYcBEnF9fo4xcrb7Hytdm8y/7vUIpWW7Ymv5j3MEdWJhuIOzYNL7rB+S267O49vFxIL5y vWCFyjRR6VFbfP+tAmk2uwG+OJp/OoQfMUVqZNi8eP887PHkv2swUryOUmrL212Phbx6x4Hamd/ lKPks7N/SG+BDejP3hifLTxOWxvescAY5u1ti4Kzz6dYenfIAyOZHuHa1A== X-Google-Smtp-Source: AGHT+IF+cCMpy12TCa/I+9WlChg2mA9SwNPAAsnbILCA21D+OVYIAgibPv9Sjn57dPgYLPCTt0gkeg== X-Received: by 2002:a05:600c:5286:b0:43d:5ec:b2f4 with SMTP id 5b1f17b1804b1-442f20e9008mr82841465e9.10.1747304806229; Thu, 15 May 2025 03:26:46 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 47/58] target/arm/kvm-stub: add missing stubs Date: Thu, 15 May 2025 11:25:35 +0100 Message-ID: <20250515102546.2149601-48-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305622398116600 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Those become needed once kvm_enabled can't be known at compile time. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-id: 20250512180502.2395029-38-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm-stub.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c index 4806365cdc5..34e57fab011 100644 --- a/target/arm/kvm-stub.c +++ b/target/arm/kvm-stub.c @@ -109,3 +109,13 @@ void arm_cpu_kvm_set_irq(void *arm_cpu, int irq, int l= evel) { g_assert_not_reached(); } + +void kvm_arm_cpu_pre_save(ARMCPU *cpu) +{ + g_assert_not_reached(); +} + +bool kvm_arm_cpu_post_load(ARMCPU *cpu) +{ + g_assert_not_reached(); +} --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747305584; cv=none; d=zohomail.com; s=zohoarc; b=f15c5nRqHMG9Gr6gzjMz2ekdEjf3NOvJZtFNCkZ7Tk5d9+1d+RwcHb9E/9QJmDLuuue3R7nlKL7XZlRjFlBxe6MuqgoJ7AbqP9RFcGfEz9z5c+xPRIX7IcVp0HmQc2LCwjO3R6LGCyvbpJFoWLYMqu/yeEO3B7YKw6/icyqIKQQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747305584; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=/5UHyMTmrHQ5mwQcvuo9BiQqIMdODzOxHwcQCEhq1rs=; b=VA4cgF5H5cK3943bPapSJeRlyFfjahirSIHZkoIvlbnvWc4tYp9Yjueu1BwgKVNdbG9u4g9OXgido4Uh/J3h+ktqX7/qEaH75UGUDoo2Og1g2xb/zF+x5MhZ0DKM7mjUV/HwNL/T8x9LbqyIsZmzlhV5stRWcNbJ29K79i9qCrg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747305584857333.9713876640152; Thu, 15 May 2025 03:39:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uFVp1-0000OL-59; Thu, 15 May 2025 06:28:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uFVnk-0005Yn-Du for qemu-devel@nongnu.org; Thu, 15 May 2025 06:27:00 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uFVne-0008H2-Jc for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:56 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-43cfe63c592so8059485e9.2 for ; Thu, 15 May 2025 03:26:48 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Thu, 15 May 2025 03:26:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 48/58] target/arm/machine: compile file once (system) Date: Thu, 15 May 2025 11:25:36 +0100 Message-ID: <20250515102546.2149601-49-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305585958116600 From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20250512180502.2395029-39-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index bb1c09676d5..b404fa54863 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -13,7 +13,6 @@ arm_system_ss =3D ss.source_set() arm_common_system_ss =3D ss.source_set() arm_system_ss.add(files( 'arm-qmp-cmds.c', - 'machine.c', )) arm_system_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm= .c')) arm_system_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c')) @@ -39,6 +38,7 @@ arm_common_system_ss.add(files( 'cortex-regs.c', 'debug_helper.c', 'helper.c', + 'machine.c', 'ptw.c', 'vfp_fpscr.c', )) --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-id: 20250512180502.2395029-40-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/vec_internal.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/arm/tcg/vec_internal.h b/target/arm/tcg/vec_internal.h index 6b93b5aeb94..c02f9c37f83 100644 --- a/target/arm/tcg/vec_internal.h +++ b/target/arm/tcg/vec_internal.h @@ -22,6 +22,8 @@ =20 #include "fpu/softfloat.h" =20 +typedef struct CPUArchState CPUARMState; + /* * Note that vector data is stored in host-endian 64-bit chunks, * so addressing units smaller than that needs a host-endian fixup. --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747305633; cv=none; d=zohomail.com; s=zohoarc; b=A5zfrr+hc8I297OFpRnTX6T/9Tj45jhRAVHWxi0yAHutLS6WSRF17hEyGnPsiIO//oLhOBOGz2cUtgNfNpQmsiGUbJA96LJQh1PS3ckzS/a19c8ngLrexIdWrAuZS5dWRNVXkIGEcIwp0rbuiQ0p0vEQ5uUTgzYjDrPkq3hDa1A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747305633; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=LWZityl3Dx64taRs5l4r1AoYIXbjRwWByF1wfRUq6sU=; b=PkISNouYFYClTFGq93rU8JXCyQC1g01ENlPFLvdBGFq7sw3wUarPUdtUcLtKYCHGyg0q65G2u/TqQjTb4/2Fc6qkkuaIgVNzd3MsMuEVraQhnQfmnHFOZhdccbDo5X6AeQtIq4NMlrioY8KeMAmZ11bEFUf99vwmZlSB70kdVWw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747305633468350.4287435758936; Thu, 15 May 2025 03:40:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uFVpP-0001Ma-A7; Thu, 15 May 2025 06:28:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uFVnh-0005X7-SO for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:54 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uFVnf-0008HN-4w for qemu-devel@nongnu.org; Thu, 15 May 2025 06:26:53 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-442f5b3c710so6071725e9.1 for ; Thu, 15 May 2025 03:26:50 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Thu, 15 May 2025 03:26:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 50/58] target/arm/tcg/crypto_helper: compile file once Date: Thu, 15 May 2025 11:25:38 +0100 Message-ID: <20250515102546.2149601-51-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_SPACE_RATIO=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305634427116600 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-id: 20250512180502.2395029-41-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/crypto_helper.c | 6 ++++-- target/arm/tcg/meson.build | 5 ++++- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/target/arm/tcg/crypto_helper.c b/target/arm/tcg/crypto_helper.c index 7cadd61e124..3428bd1bf0b 100644 --- a/target/arm/tcg/crypto_helper.c +++ b/target/arm/tcg/crypto_helper.c @@ -10,14 +10,16 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/bitops.h" =20 -#include "cpu.h" -#include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" #include "crypto/aes-round.h" #include "crypto/sm4.h" #include "vec_internal.h" =20 +#define HELPER_H "tcg/helper.h" +#include "exec/helper-proto.h.inc" + union CRYPTO_STATE { uint8_t bytes[16]; uint32_t words[4]; diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index dd12ccedb18..2f73eefe383 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -30,7 +30,6 @@ arm_ss.add(files( 'translate-mve.c', 'translate-neon.c', 'translate-vfp.c', - 'crypto_helper.c', 'hflags.c', 'iwmmxt_helper.c', 'm_helper.c', @@ -63,3 +62,7 @@ arm_system_ss.add(files( =20 arm_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c')) arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files('cpu-v7m.c')) + +arm_common_ss.add(files( + 'crypto_helper.c', +)) --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 15 May 2025 03:26:50 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 51/58] target/arm/tcg/hflags: compile file twice (system, user) Date: Thu, 15 May 2025 11:25:39 +0100 Message-ID: <20250515102546.2149601-52-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305537526116600 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-id: 20250512180502.2395029-42-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/hflags.c | 4 +++- target/arm/tcg/meson.build | 8 +++++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index fd407a7b28e..1ccec63bbd4 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -9,11 +9,13 @@ #include "cpu.h" #include "internals.h" #include "cpu-features.h" -#include "exec/helper-proto.h" #include "exec/translation-block.h" #include "accel/tcg/cpu-ops.h" #include "cpregs.h" =20 +#define HELPER_H "tcg/helper.h" +#include "exec/helper-proto.h.inc" + static inline bool fgt_svc(CPUARMState *env, int el) { /* diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 2f73eefe383..cee00b24cda 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -30,7 +30,6 @@ arm_ss.add(files( 'translate-mve.c', 'translate-neon.c', 'translate-vfp.c', - 'hflags.c', 'iwmmxt_helper.c', 'm_helper.c', 'mve_helper.c', @@ -66,3 +65,10 @@ arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files(= 'cpu-v7m.c')) arm_common_ss.add(files( 'crypto_helper.c', )) + +arm_common_system_ss.add(files( + 'hflags.c', +)) +arm_user_ss.add(files( + 'hflags.c', +)) --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 15 May 2025 03:26:51 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 52/58] target/arm/tcg/iwmmxt_helper: compile file twice (system, user) Date: Thu, 15 May 2025 11:25:40 +0100 Message-ID: <20250515102546.2149601-53-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305329747116600 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-id: 20250512180502.2395029-43-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/iwmmxt_helper.c | 4 +++- target/arm/tcg/meson.build | 3 ++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/iwmmxt_helper.c b/target/arm/tcg/iwmmxt_helper.c index 610b1b2103e..ba054b6b4db 100644 --- a/target/arm/tcg/iwmmxt_helper.c +++ b/target/arm/tcg/iwmmxt_helper.c @@ -22,7 +22,9 @@ #include "qemu/osdep.h" =20 #include "cpu.h" -#include "exec/helper-proto.h" + +#define HELPER_H "tcg/helper.h" +#include "exec/helper-proto.h.inc" =20 /* iwMMXt macros extracted from GNU gdb. */ =20 diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index cee00b24cda..02dfe768c5d 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -30,7 +30,6 @@ arm_ss.add(files( 'translate-mve.c', 'translate-neon.c', 'translate-vfp.c', - 'iwmmxt_helper.c', 'm_helper.c', 'mve_helper.c', 'neon_helper.c', @@ -68,7 +67,9 @@ arm_common_ss.add(files( =20 arm_common_system_ss.add(files( 'hflags.c', + 'iwmmxt_helper.c', )) arm_user_ss.add(files( 'hflags.c', + 'iwmmxt_helper.c', )) --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 15 May 2025 03:26:52 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 53/58] target/arm/tcg/neon_helper: compile file twice (system, user) Date: Thu, 15 May 2025 11:25:41 +0100 Message-ID: <20250515102546.2149601-54-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305670804116600 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-id: 20250512180502.2395029-44-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/neon_helper.c | 4 +++- target/arm/tcg/meson.build | 3 ++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/neon_helper.c b/target/arm/tcg/neon_helper.c index e2cc7cf4ee6..2cc8241f1e4 100644 --- a/target/arm/tcg/neon_helper.c +++ b/target/arm/tcg/neon_helper.c @@ -9,11 +9,13 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" #include "vec_internal.h" =20 +#define HELPER_H "tcg/helper.h" +#include "exec/helper-proto.h.inc" + #define SIGNBIT (uint32_t)0x80000000 #define SIGNBIT64 ((uint64_t)1 << 63) =20 diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 02dfe768c5d..af786196d2f 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -32,7 +32,6 @@ arm_ss.add(files( 'translate-vfp.c', 'm_helper.c', 'mve_helper.c', - 'neon_helper.c', 'op_helper.c', 'tlb_helper.c', 'vec_helper.c', @@ -68,8 +67,10 @@ arm_common_ss.add(files( arm_common_system_ss.add(files( 'hflags.c', 'iwmmxt_helper.c', + 'neon_helper.c', )) arm_user_ss.add(files( 'hflags.c', 'iwmmxt_helper.c', + 'neon_helper.c', )) --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 15 May 2025 03:26:53 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 54/58] target/arm/tcg/tlb_helper: compile file twice (system, user) Date: Thu, 15 May 2025 11:25:42 +0100 Message-ID: <20250515102546.2149601-55-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305485129116600 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-id: 20250512180502.2395029-45-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/tlb_helper.c | 3 ++- target/arm/tcg/meson.build | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index d9e6c827d43..23c72a99f5c 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -9,8 +9,9 @@ #include "cpu.h" #include "internals.h" #include "cpu-features.h" -#include "exec/helper-proto.h" =20 +#define HELPER_H "tcg/helper.h" +#include "exec/helper-proto.h.inc" =20 /* * Returns true if the stage 1 translation regime is using LPAE format page diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index af786196d2f..49c8f4390a1 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -33,7 +33,6 @@ arm_ss.add(files( 'm_helper.c', 'mve_helper.c', 'op_helper.c', - 'tlb_helper.c', 'vec_helper.c', 'tlb-insns.c', 'arith_helper.c', @@ -68,9 +67,11 @@ arm_common_system_ss.add(files( 'hflags.c', 'iwmmxt_helper.c', 'neon_helper.c', + 'tlb_helper.c', )) arm_user_ss.add(files( 'hflags.c', 'iwmmxt_helper.c', 'neon_helper.c', + 'tlb_helper.c', )) --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442f396c3a4sm65657855e9.26.2025.05.15.03.26.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 03:26:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747304815; x=1747909615; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=oDX/L4H6LWozpQuVjGq8Fpv0Kh4dC814yG6ylUtKBIs=; b=FO/RMRwkmWYAIBMyTBz1HVHgAjRZ7HjN2Q6IYjoEin7T12oj5fs0P2EVLwcA7uKyE0 LKJBc9591ScqmjkH+sna6bIiXAoNdRBzmpFeTMbgfOtU2unj4M/E2yodb0C22WyD0a0R omntObEVL57PEo/mWcGzIcV5TkCFgReGW0rE7IfIOvYsklQiBu+97fjPdkuQW0Sk3Ww7 wADIkj7Fq8MTHBQsZO9zHN3RxyBADd5kxLA1sepgqZcXO/p0MSaXFf9bIbn95j+tlL6M sblNuUvOmTDGzJuYR8/Pgx94+dVWNoR0xnl/fG5GJpVNYf3hQuYYv4zXE2B5PMQN5Cyq x4zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747304815; x=1747909615; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oDX/L4H6LWozpQuVjGq8Fpv0Kh4dC814yG6ylUtKBIs=; b=gIW2Bsldw/AqXDoK6fKXsICq2XB5RMcZsIguO4NSIj37mIRSCBlwn8X44d9cKK/82N lDYLGwVX10HL6xhAvqnYKwAFmN5OYHn5GeKDfwk/3pa10L4SvC64g6j2CckQMKuhVZVi cxmfVRbSLfRUEvQs8L5RrbjKkBNz5J12eqNC04njB00ADn/zy4saLRubUe4waG5DkFyH xLOSRQXr1MvdMwbo2THUWiIlLrhrhkzXHoJrA0HM7tNF7i8R7LcK4K2aZhs2Zzo458bF 8EUiWg4BiD+08phz7TFMCB2TAZ7kW24M2BViLdKF4eszAUVqF2IUQn9PqGo2vpeG4J3Z oecA== X-Gm-Message-State: AOJu0YyMO1dgYkfFsm545GuMKl46ba3cNIwclP/B/miJT3wXTW0jvKP9 NdHpjnl2OY6yb9giraAPzZ5JLBPMfL9xHub+axG5Kjwb9+Qu+T2Y8Zvb7xv9jjqSGrAIbboOGX7 FGIY= X-Gm-Gg: ASbGncu+KSa5A8Esg2y4DbtlfXPCaAI+EjmVaPY2uW2KF1TA32p3kWxAWc+0ozXCUza 5uI7HbVXMmczKu505rl7+NA9Nml1SCpR6yV+1tcaPOtHpT669OeZVZKK6P4Z1UaG51QrcwA3u7p PwTLzApGiAqkIlgRn4y0bxYcYh3M/Nss98fftestut3a5ax6KZw1EY6zPqWQ8UEm+Qy4SvJAnHL gEQTIfNyj9pkqV4UCLYhlRYrI3mlFGJ1vX1Mt+jRLd2qHdt9x46anlyh83Gs8qVh2ZwosUzLY+i fkPjJagDwhDAbJBrOBu/d7++M6z7G3o7/vJWCnY4JJ1FXOO1cB1mU07Stw== X-Google-Smtp-Source: AGHT+IF818A/TT2fkzT527nvJH1q4Zfehv+cptKqxGIcMm5XEI/wTfUq/KRAcF3+a3xfRenipHKOVw== X-Received: by 2002:a05:600c:8414:b0:441:b3eb:574e with SMTP id 5b1f17b1804b1-442f96e497amr20146555e9.5.1747304814868; Thu, 15 May 2025 03:26:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 55/58] target/arm/helper: restrict define_tlb_insn_regs to system target Date: Thu, 15 May 2025 11:25:43 +0100 Message-ID: <20250515102546.2149601-56-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305061367116600 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Allows to include target/arm/tcg/tlb-insns.c only for system targets. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-id: 20250512180502.2395029-46-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index aae8554e8f2..76312102879 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7764,7 +7764,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, not_v8_cp_reginfo); } =20 +#ifndef CONFIG_USER_ONLY define_tlb_insn_regs(cpu); +#endif =20 if (arm_feature(env, ARM_FEATURE_V6)) { /* The ID registers all have impdef reset values */ --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747305662; cv=none; d=zohomail.com; s=zohoarc; b=gxOiU5NDjqe99rLKvWPCZ+5vsbozAQ9clvVBxgoSRi55IqAgcE1u4+N+kKLxAVNmBWVxkyDd2ux7I4fKm41wTm3qfTQXY/SQDJfQ4TF2gilcEzhiisQqgRZpIAU3sW26bViPWybXSofFot2VyfnvgFOy+ZpoJU8PYbRSks4RmtA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747305662; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=uHg4ycwbPf3C1Edy5OlGts+9E0FlfMfrBWAhEu26MCU=; b=Im3OemVHFOjbHwH9c/RJiHm5itbHz/9WBalRBOJXGIxASOWrK5IZRm+91vwEyptTlZKUGQ8fPF8W8DnOBdJEk1CdrjvjOdMNKM/emFLdICXtWjunFCcKX6VFbsjWMNn7E7UU7p1pJpLQLazCQEYTTso0GQny3Bp2J3o/ZYPeIQ0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747305662264438.3806025310532; Thu, 15 May 2025 03:41:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uFVqP-0002BB-EG; Thu, 15 May 2025 06:29:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uFVns-0005i3-Ua for qemu-devel@nongnu.org; Thu, 15 May 2025 06:27:06 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uFVnr-0008JC-2D for qemu-devel@nongnu.org; Thu, 15 May 2025 06:27:04 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-442ec3ce724so6131835e9.0 for ; Thu, 15 May 2025 03:26:57 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442f396c3a4sm65657855e9.26.2025.05.15.03.26.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 03:26:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747304816; x=1747909616; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=uHg4ycwbPf3C1Edy5OlGts+9E0FlfMfrBWAhEu26MCU=; b=wRWdeD4yrNAZm409NdYr9UHWwVR9LbyZ5UpcpNSW/naqeQ8l7SlmhkOiok5d+oGi5R K1F6E37pDfbX1s/Nb97dWrUgbnnsY6RK+suk/U8pSEdD82YT98I7gMJ2uzG8nUFPf0rl R/62kzoXlhFwv5G/Dw2c3kNndj8BAQ97xri7qlQ/oGjkHCD6nf6K8ak9pimkmCpeVezP 0Rfh08LK3H7MYxS3gfwh6nNxjW95Yf7XVvwU/LzIglDI5Ppsom0oNX8CkUNoFEX2aPbq PEcDPp9QamATMpg55+/HOSxTG1U0gVXyUvoN5zjcTzdn5UsS0LGBBxuiibl4kuhJOllb rNCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747304816; x=1747909616; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uHg4ycwbPf3C1Edy5OlGts+9E0FlfMfrBWAhEu26MCU=; b=e+rZSmGitVRoOs6JUCh+uGQ5eiGTQT2WebvTtFARUnxNNbXPkw7Tjd+cIO5dYSQMJn ixeacJMw4AN4ihvihDKsP2YfKxwsPvb0MfQeWhxpaOZQ6WBTEdszofO/Fbt40Nhi2vou d6DAgosIYg+lsWT3vrujxujSSFjCJckMF8J1GbXZPy2wJh9dn1Ww+ut+/TFfdSxW6VYD W7h79ROeCi5X5ceTgi+pXRtlo8seqdyjahPJWkT8E98IguBGnbFKmJQT+ELoSTEzOrlj /hDVtjwF5DJoWDK6/fVOlTdDlprwBrD6K/eRzeNhP5Csjc47sfvOaAd+uiMQdVJIIJyX F6nQ== X-Gm-Message-State: AOJu0YyL1txJzk+gt5Q0q6jCf/gC2OgyeVIuwggHGBxIc/GSoPIZN/EQ Lu2ZluFmwulVyr2t7zofNHUWmfCDnlzhoD33goBGjYekv/7CAwBLufguAcD2ZYDTOTbBxzjyo2E zn8g= X-Gm-Gg: ASbGncsJI10ANkaD2zKl6u4+s6p01RqQnofqfa10ivJltMq5PGr+QAWbmKlDFbD0fiq /fmn727wl5n1X/mBKrJ9FpPXm9CrbPU+1YSwLgnt2RNekAGN7XohhsOABXvqOFdyMZtAXWfo+3d J30AZ+l9S27j3bPc4H7uZLIGT0RaNc1Gpm1ji+1ttnZgg3Y52xX3omhwe0WX4jQt6TZKdCWgig4 9qB9go08f9lLcx7Ls9E607rh6NqpZNVOD307mOePDxHCnIEH7kO63V1BNqYaBk19BlkAaEeexnc eTcjHtTYdYmXEjYzcXi/XEU0lnjinstbC5uTwBDUn7LgETyjIFlEQgBy+g== X-Google-Smtp-Source: AGHT+IHphXRO6E7WetKpMoSy5DAY8mFhrOwUbXKNOdQsU4mKfXn6p1POMAcLKHj0A3INkdvjetUNsQ== X-Received: by 2002:a05:600c:c1c8:10b0:442:f989:3dfb with SMTP id 5b1f17b1804b1-442f9893f2dmr7997995e9.1.1747304815772; Thu, 15 May 2025 03:26:55 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 56/58] target/arm/tcg/tlb-insns: compile file once (system) Date: Thu, 15 May 2025 11:25:44 +0100 Message-ID: <20250515102546.2149601-57-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305662780116600 From: Pierrick Bouvier aarch64 specific code is guarded by cpu_isar_feature(aa64*), so it's safe to expose it. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20250512180502.2395029-47-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/tlb-insns.c | 7 ------- target/arm/tcg/meson.build | 2 +- 2 files changed, 1 insertion(+), 8 deletions(-) diff --git a/target/arm/tcg/tlb-insns.c b/target/arm/tcg/tlb-insns.c index 0407ad5542d..95c26c6d463 100644 --- a/target/arm/tcg/tlb-insns.c +++ b/target/arm/tcg/tlb-insns.c @@ -35,7 +35,6 @@ static CPAccessResult access_ttlbis(CPUARMState *env, con= st ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 -#ifdef TARGET_AARCH64 /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBOS. */ static CPAccessResult access_ttlbos(CPUARMState *env, const ARMCPRegInfo *= ri, bool isread) @@ -46,7 +45,6 @@ static CPAccessResult access_ttlbos(CPUARMState *env, con= st ARMCPRegInfo *ri, } return CP_ACCESS_OK; } -#endif =20 /* IS variants of TLB operations must affect all cores */ static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -802,7 +800,6 @@ static const ARMCPRegInfo tlbi_el3_cp_reginfo[] =3D { .writefn =3D tlbi_aa64_vae3_write }, }; =20 -#ifdef TARGET_AARCH64 typedef struct { uint64_t base; uint64_t length; @@ -1270,8 +1267,6 @@ static const ARMCPRegInfo tlbi_rme_reginfo[] =3D { .writefn =3D tlbi_aa64_paallos_write }, }; =20 -#endif - void define_tlb_insn_regs(ARMCPU *cpu) { CPUARMState *env =3D &cpu->env; @@ -1299,7 +1294,6 @@ void define_tlb_insn_regs(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_EL3)) { define_arm_cp_regs(cpu, tlbi_el3_cp_reginfo); } -#ifdef TARGET_AARCH64 if (cpu_isar_feature(aa64_tlbirange, cpu)) { define_arm_cp_regs(cpu, tlbirange_reginfo); } @@ -1309,5 +1303,4 @@ void define_tlb_insn_regs(ARMCPU *cpu) if (cpu_isar_feature(aa64_rme, cpu)) { define_arm_cp_regs(cpu, tlbi_rme_reginfo); } -#endif } diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 49c8f4390a1..5d326585401 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -34,7 +34,6 @@ arm_ss.add(files( 'mve_helper.c', 'op_helper.c', 'vec_helper.c', - 'tlb-insns.c', 'arith_helper.c', 'vfp_helper.c', )) @@ -68,6 +67,7 @@ arm_common_system_ss.add(files( 'iwmmxt_helper.c', 'neon_helper.c', 'tlb_helper.c', + 'tlb-insns.c', )) arm_user_ss.add(files( 'hflags.c', --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747305320; cv=none; d=zohomail.com; s=zohoarc; b=QaQp5w3rR6YaCJdGNhuTzf0pxXW9DsgNpxysxSy0kN+rYJh/+YH/sv5lRTKtRkrd2W7Nlur4aT7lU7aw7bkQXd8QzPZOl8VElyS96qgmfllqKGD0xDcCCFSMCk9w2NdTFOET5Ov+5FLqHWsg7O7DhczccVTtWSlZMQLcJ6zvOZw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747305320; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=97ZZBvdmNF0X3lx5ZR5EO55LMqvaqGIqAUiNymsGAhM=; b=aFO34EQLmQj9rMH1HcUExjG1GIebxpVzNWMlaZnGB4o6m7mn2EykKZQNhFU9srzCxcckj/ufmXAGeigeDfmXpwYN+M/0BqbHWVz+FppeDJ/tQLWrOSnOET1gVxrpbkOl04YPITRbeHafssMl391tXsrY3kwjD9vqcmWl2tPMRIw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747305320113361.8327649832246; Thu, 15 May 2025 03:35:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uFVoi-0006yr-Ge; Thu, 15 May 2025 06:27:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uFVns-0005hn-SN for qemu-devel@nongnu.org; Thu, 15 May 2025 06:27:05 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uFVnr-0008JM-1v for qemu-devel@nongnu.org; Thu, 15 May 2025 06:27:04 -0400 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-3a1f5d2d91eso427581f8f.1 for ; Thu, 15 May 2025 03:26:57 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442f396c3a4sm65657855e9.26.2025.05.15.03.26.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 03:26:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747304817; x=1747909617; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=97ZZBvdmNF0X3lx5ZR5EO55LMqvaqGIqAUiNymsGAhM=; b=huGK8PV/zX+/eL+mAatduOl88RQCK/wH65GEOTJ5QU8Ynb0iUhb8mkfBt6QZMpkFcx s2d2dVyYVE/n3M6lffVvY1fiRf/Gnv5nRx65Ie5rrnVseNa1kt2LkaphcO4BQnLF1VTz rhrOvR99g5t2Lmb6QP8Ssl+LohegTHFKYRGYMi0n480Whm9WoNESGoz058j2if4M1R7w zqNyo02Te9DMsPdhGKaPAHVQGsPWpMZCKUXGtOPPFCrEPI5ZO0JvaoCOJYGr9CJq21Cs EQNfxWDp0aYJz56VEjrlNtR/audtUqLH23e+i8p+3eA5kuA8u1xEDnOEE1xzF13i6pXG ZZ+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747304817; x=1747909617; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=97ZZBvdmNF0X3lx5ZR5EO55LMqvaqGIqAUiNymsGAhM=; b=Z7rOae9LhgFxXSA/TGGGuo/hI4Lw0QB75xdQL3A7P3+nhLTgvae2UKfJN2q7xRZ7wF 2BjnUree23z2FTBaRdZUPvl3gwPTfNfmIuL5q/qxZ2V/X8xpRLIybRfet+q1USrTVPl1 umgYhoabhQq+2gxIEzHymj8ds4tO5FnhFO/WaYyUdpxLsmIJTnh/KB0TMQybUpwm4zWe loD4Vbdtplhth1lrIuIu4I9Douc9b3IdGY2EQD3R5DuAFpjg8e8WKW6iB5encoJYRsA6 +CcZxpxg6ni0THaNg++HHpmqS8mYwzTNZSOPMrpGqJOTlsyxkkU10Q4gDPh9P21jDiPD alrQ== X-Gm-Message-State: AOJu0YyFTEXjtpDwpRd/wiDPIXm0U5S6dZgIhjwdePRrHbLnzhMeTzx8 MnI79XdX+VJGRkNUU+mHQYQ6yfBqbPIRqrGqWs7QEDGOsR3ZpzV6ibwRzUKnpB/7pPQOMgQMssh MzE0= X-Gm-Gg: ASbGncvcUJwXB0ba5qoU10xDuPjMBRF/cHhUYNg2B3Y29CMdJInTPaSzEV9TcvjacT7 nq7zMj1312A/+pe7ZPna0wsCbqjuBiC7QRZrwgErM5zEUZ2bNbWQ/lBnLaRIXImEKanl4bB2RmN bFIrSiUBi4k79eAPYm/1A1TSplWZ/tMnzglGEWDrzQKqwowCNcNy2t8F480rdWiSHh/8nau5oZh IJcR1XsR1zmQXDQVic7ORcfNCPnoADobEsDvoCN1YJNVuYqeeKSFOFpvumtn05o8qeLLVISuIi/ dmwo0OvQtsZ2HfZrLnDtJma3n/mfjOCymZrGjjfyzdlbl+474Uh+b+YGog== X-Google-Smtp-Source: AGHT+IElbrCTemBYe6bJToe/SAe9fFH/bdWOmt5RLPqUURuYg84icWQnI3bjpPa4HHwHbGYjrKw0SA== X-Received: by 2002:a05:6000:1864:b0:391:4873:7940 with SMTP id ffacd0b85a97d-3a34994d99amr5866627f8f.54.1747304816781; Thu, 15 May 2025 03:26:56 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 57/58] target/arm/tcg/arith_helper: compile file once Date: Thu, 15 May 2025 11:25:45 +0100 Message-ID: <20250515102546.2149601-58-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305321653116600 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-id: 20250512180502.2395029-48-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/arith_helper.c | 5 +++-- target/arm/tcg/meson.build | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/target/arm/tcg/arith_helper.c b/target/arm/tcg/arith_helper.c index 9a555c7966c..670139819df 100644 --- a/target/arm/tcg/arith_helper.c +++ b/target/arm/tcg/arith_helper.c @@ -6,11 +6,12 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ #include "qemu/osdep.h" -#include "cpu.h" -#include "exec/helper-proto.h" #include "qemu/crc32c.h" #include /* for crc32 */ =20 +#define HELPER_H "tcg/helper.h" +#include "exec/helper-proto.h.inc" + /* * Note that signed overflow is undefined in C. The following routines are * careful to use unsigned types where modulo arithmetic is required. diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 5d326585401..7502c5cded6 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -34,7 +34,6 @@ arm_ss.add(files( 'mve_helper.c', 'op_helper.c', 'vec_helper.c', - 'arith_helper.c', 'vfp_helper.c', )) =20 @@ -59,6 +58,7 @@ arm_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files(= 'cpu-v7m.c')) arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files('cpu-v7m.c')) =20 arm_common_ss.add(files( + 'arith_helper.c', 'crypto_helper.c', )) =20 --=20 2.43.0 From nobody Fri Dec 19 17:37:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747305416; cv=none; d=zohomail.com; s=zohoarc; b=DzTkSokitmCaErEyOizUwk0jlDffWoekgK1vX3HgJ51h5wyC3WnTJ7qRPGF+nOCzBfcx91HTbMtlZDbsL0ujAZ6qk7+0TyUMPw0a0SkqCNu7ByfYFdVB5wl6zk/OHgji00Y5L2QjMfqQARlBs1wEi4bjyjvx+k1PX7bmu/GNWcU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747305416; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=xSiXRwtDMWDeTq5UrKQY9rIDpqHmH/9swQvH3M4K+Hg=; b=CIwoXEIgT2CCwJn01E1gLm/08b1RawxJI8XgdB/NiNg+VAh60khMs/GvcuYLaYXPlOZoMEWlRo8TfbvdSDpzZLIWbl8rMsUyT81TeOoSTIA5vSLvf4O4GuAUgPAcfxDTDByAm5Y8DBVj92ka+j1Yo4LhcDtqVAMtUUc1k1l4yiU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174730541645843.08652036195963; Thu, 15 May 2025 03:36:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uFVqW-0002JH-1S; Thu, 15 May 2025 06:29:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uFVnu-0005k3-Q8 for qemu-devel@nongnu.org; Thu, 15 May 2025 06:27:09 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uFVnr-0008JS-38 for qemu-devel@nongnu.org; Thu, 15 May 2025 06:27:06 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-43ce71582e9so5935915e9.1 for ; Thu, 15 May 2025 03:26:58 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Thu, 15 May 2025 03:26:57 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 58/58] target/arm/tcg/vfp_helper: compile file twice (system, user) Date: Thu, 15 May 2025 11:25:46 +0100 Message-ID: <20250515102546.2149601-59-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515102546.2149601-1-peter.maydell@linaro.org> References: <20250515102546.2149601-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747305418516116600 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-id: 20250512180502.2395029-49-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/vfp_helper.c | 4 +++- target/arm/tcg/meson.build | 3 ++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/vfp_helper.c b/target/arm/tcg/vfp_helper.c index b32e2f4e27c..b1324c5c0a6 100644 --- a/target/arm/tcg/vfp_helper.c +++ b/target/arm/tcg/vfp_helper.c @@ -19,12 +19,14 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/helper-proto.h" #include "internals.h" #include "cpu-features.h" #include "fpu/softfloat.h" #include "qemu/log.h" =20 +#define HELPER_H "tcg/helper.h" +#include "exec/helper-proto.h.inc" + /* * Set the float_status behaviour to match the Arm defaults: * * tininess-before-rounding diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 7502c5cded6..2d1502ba882 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -34,7 +34,6 @@ arm_ss.add(files( 'mve_helper.c', 'op_helper.c', 'vec_helper.c', - 'vfp_helper.c', )) =20 arm_ss.add(when: 'TARGET_AARCH64', if_true: files( @@ -68,10 +67,12 @@ arm_common_system_ss.add(files( 'neon_helper.c', 'tlb_helper.c', 'tlb-insns.c', + 'vfp_helper.c', )) arm_user_ss.add(files( 'hflags.c', 'iwmmxt_helper.c', 'neon_helper.c', 'tlb_helper.c', + 'vfp_helper.c', )) --=20 2.43.0