From nobody Fri Dec 19 17:53:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1747297146; cv=none; d=zohomail.com; s=zohoarc; b=RJ45uukbwc3exhLLfz19zxpMifZGTFYHqNrcnl9631acDOlC/fHKeVnhxlkzU1/9UNil2AYwa5XdpMR+cTIaAMEOGQc9Km0wHdZ580kXijW8V83vSYiu0XtlWBzo7HqAnmeBm3l08GbmNWpoeq/qziRv97m1PneRKB8MgpYRkyE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747297146; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=Lnlq3RjLKLFTuWuOMe8dMqpfqfEsVy3vqTEY1zWz9Us=; b=VphwlDu4/LxWngYeC6/UPzO9WL5/gl+TF0Sc9tqRn48Rtgcgt2UVHcSMit4WcIyYUa3Jjkmjbsj65ZLh7oRl9dYA4L397XfOsQtpiCaN4AlcoEOfYuQPI6bMX/AQMNWunK2BYo/TlhWjw9cGShBKCLqF0G3GTvRVmtFvc7bM1mY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747297146817326.88711576759704; Thu, 15 May 2025 01:19:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uFTiB-0004Mr-4n; Thu, 15 May 2025 04:13:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uFTgQ-0004dU-0R; Thu, 15 May 2025 04:11:14 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uFTgM-00011Y-Ln; Thu, 15 May 2025 04:11:13 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 15 May 2025 16:10:12 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 15 May 2025 16:10:12 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v3 12/28] hw/misc/aspeed_hace: Move register size to instance class and dynamically allocate regs Date: Thu, 15 May 2025 16:09:44 +0800 Message-ID: <20250515081008.583578-13-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515081008.583578-1-jamin_lin@aspeedtech.com> References: <20250515081008.583578-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1747297148513116600 Content-Type: text/plain; charset="utf-8" Dynamically allocate the register array by removing the hardcoded ASPEED_HACE_NR_REGS macro. To support different register sizes across SoC variants, introduce a new "nr_regs" class attribute and replace the static "regs" array with dynamica= lly allocated memory. Add a new "aspeed_hace_unrealize" function to properly free the allocated "= regs" memory during device cleanup. Remove the bounds checking in the MMIO read/write handlers since the MemoryRegion size now matches the (register array size << 2). This commit updates the VMState fields accordingly. The VMState version was already bumped in a previous patch of this series, so no further version ch= ange is needed. Signed-off-by: Jamin Lin --- include/hw/misc/aspeed_hace.h | 5 +++-- hw/misc/aspeed_hace.c | 36 ++++++++++++++++++----------------- 2 files changed, 22 insertions(+), 19 deletions(-) diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h index b69a038d35..f30d606559 100644 --- a/include/hw/misc/aspeed_hace.h +++ b/include/hw/misc/aspeed_hace.h @@ -22,7 +22,6 @@ =20 OBJECT_DECLARE_TYPE(AspeedHACEState, AspeedHACEClass, ASPEED_HACE) =20 -#define ASPEED_HACE_NR_REGS (0x64 >> 2) #define ASPEED_HACE_MAX_SG 256 /* max number of entries */ =20 struct AspeedHACEState { @@ -31,7 +30,7 @@ struct AspeedHACEState { MemoryRegion iomem; qemu_irq irq; =20 - uint32_t regs[ASPEED_HACE_NR_REGS]; + uint32_t *regs; uint32_t total_req_len; =20 MemoryRegion *dram_mr; @@ -44,10 +43,12 @@ struct AspeedHACEState { struct AspeedHACEClass { SysBusDeviceClass parent_class; =20 + const MemoryRegionOps *reg_ops; uint32_t src_mask; uint32_t dest_mask; uint32_t key_mask; uint32_t hash_mask; + uint64_t nr_regs; bool raise_crypt_interrupt_workaround; }; =20 diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index 049f732f99..fef63eb488 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -386,13 +386,6 @@ static uint64_t aspeed_hace_read(void *opaque, hwaddr = addr, unsigned int size) =20 addr >>=3D 2; =20 - if (addr >=3D ASPEED_HACE_NR_REGS) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "= \n", - __func__, addr << 2); - return 0; - } - return s->regs[addr]; } =20 @@ -404,13 +397,6 @@ static void aspeed_hace_write(void *opaque, hwaddr add= r, uint64_t data, =20 addr >>=3D 2; =20 - if (addr >=3D ASPEED_HACE_NR_REGS) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx = "\n", - __func__, addr << 2); - return; - } - switch (addr) { case R_STATUS: if (data & HASH_IRQ) { @@ -507,13 +493,14 @@ static const MemoryRegionOps aspeed_hace_ops =3D { static void aspeed_hace_reset(DeviceState *dev) { struct AspeedHACEState *s =3D ASPEED_HACE(dev); + AspeedHACEClass *ahc =3D ASPEED_HACE_GET_CLASS(s); =20 if (s->hash_ctx !=3D NULL) { qcrypto_hash_free(s->hash_ctx); s->hash_ctx =3D NULL; } =20 - memset(s->regs, 0, sizeof(s->regs)); + memset(s->regs, 0, ahc->nr_regs << 2); s->total_req_len =3D 0; } =20 @@ -521,11 +508,13 @@ static void aspeed_hace_realize(DeviceState *dev, Err= or **errp) { AspeedHACEState *s =3D ASPEED_HACE(dev); SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + AspeedHACEClass *ahc =3D ASPEED_HACE_GET_CLASS(s); =20 sysbus_init_irq(sbd, &s->irq); =20 + s->regs =3D g_new(uint32_t, ahc->nr_regs); memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_hace_ops, s, - TYPE_ASPEED_HACE, 0x1000); + TYPE_ASPEED_HACE, ahc->nr_regs << 2); =20 if (!s->dram_mr) { error_setg(errp, TYPE_ASPEED_HACE ": 'dram' link not set"); @@ -548,17 +537,25 @@ static const VMStateDescription vmstate_aspeed_hace = =3D { .version_id =3D 2, .minimum_version_id =3D 2, .fields =3D (const VMStateField[]) { - VMSTATE_UINT32_ARRAY(regs, AspeedHACEState, ASPEED_HACE_NR_REGS), VMSTATE_UINT32(total_req_len, AspeedHACEState), VMSTATE_END_OF_LIST(), } }; =20 +static void aspeed_hace_unrealize(DeviceState *dev) +{ + AspeedHACEState *s =3D ASPEED_HACE(dev); + + g_free(s->regs); + s->regs =3D NULL; +} + static void aspeed_hace_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->realize =3D aspeed_hace_realize; + dc->unrealize =3D aspeed_hace_unrealize; device_class_set_legacy_reset(dc, aspeed_hace_reset); device_class_set_props(dc, aspeed_hace_properties); dc->vmsd =3D &vmstate_aspeed_hace; @@ -579,6 +576,7 @@ static void aspeed_ast2400_hace_class_init(ObjectClass = *klass, const void *data) =20 dc->desc =3D "AST2400 Hash and Crypto Engine"; =20 + ahc->nr_regs =3D 0x64 >> 2; ahc->src_mask =3D 0x0FFFFFFF; ahc->dest_mask =3D 0x0FFFFFF8; ahc->key_mask =3D 0x0FFFFFC0; @@ -598,6 +596,7 @@ static void aspeed_ast2500_hace_class_init(ObjectClass = *klass, const void *data) =20 dc->desc =3D "AST2500 Hash and Crypto Engine"; =20 + ahc->nr_regs =3D 0x64 >> 2; ahc->src_mask =3D 0x3fffffff; ahc->dest_mask =3D 0x3ffffff8; ahc->key_mask =3D 0x3FFFFFC0; @@ -617,6 +616,7 @@ static void aspeed_ast2600_hace_class_init(ObjectClass = *klass, const void *data) =20 dc->desc =3D "AST2600 Hash and Crypto Engine"; =20 + ahc->nr_regs =3D 0x64 >> 2; ahc->src_mask =3D 0x7FFFFFFF; ahc->dest_mask =3D 0x7FFFFFF8; ahc->key_mask =3D 0x7FFFFFF8; @@ -636,6 +636,7 @@ static void aspeed_ast1030_hace_class_init(ObjectClass = *klass, const void *data) =20 dc->desc =3D "AST1030 Hash and Crypto Engine"; =20 + ahc->nr_regs =3D 0x64 >> 2; ahc->src_mask =3D 0x7FFFFFFF; ahc->dest_mask =3D 0x7FFFFFF8; ahc->key_mask =3D 0x7FFFFFF8; @@ -655,6 +656,7 @@ static void aspeed_ast2700_hace_class_init(ObjectClass = *klass, const void *data) =20 dc->desc =3D "AST2700 Hash and Crypto Engine"; =20 + ahc->nr_regs =3D 0x64 >> 2; ahc->src_mask =3D 0x7FFFFFFF; ahc->dest_mask =3D 0x7FFFFFF8; ahc->key_mask =3D 0x7FFFFFF8; --=20 2.43.0