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Tue, 13 May 2025 10:39:35 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Richard Henderson , Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 01/19] target/arm/tcg-stubs: compile file once (system) Date: Tue, 13 May 2025 18:39:10 +0100 Message-ID: <20250513173928.77376-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250513173928.77376-1-philmd@linaro.org> References: <20250513173928.77376-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747158545748116600 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- target/arm/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index b404fa54863..e568dfb706a 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -48,7 +48,7 @@ subdir('hvf') if 'CONFIG_TCG' in config_all_accel subdir('tcg') else - arm_ss.add(files('tcg-stubs.c')) + arm_common_system_ss.add(files('tcg-stubs.c')) endif =20 target_arch +=3D {'arm': arm_ss} --=20 2.47.1 From nobody Sat Nov 15 20:49:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- MAINTAINERS | 1 + target/arm/hvf_arm.h | 16 ---------------- target/arm/hvf-stub.c | 20 ++++++++++++++++++++ target/arm/meson.build | 1 + 4 files changed, 22 insertions(+), 16 deletions(-) create mode 100644 target/arm/hvf-stub.c diff --git a/MAINTAINERS b/MAINTAINERS index 6dacd6d004d..7431f88b5d9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -509,6 +509,7 @@ Apple Silicon HVF CPUs M: Alexander Graf S: Maintained F: target/arm/hvf/ +F: target/arm/hvf-stub.c =20 X86 HVF CPUs M: Cameron Esfahani diff --git a/target/arm/hvf_arm.h b/target/arm/hvf_arm.h index 26c717b3826..7a44e092620 100644 --- a/target/arm/hvf_arm.h +++ b/target/arm/hvf_arm.h @@ -22,23 +22,7 @@ void hvf_arm_init_debug(void); =20 void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu); =20 -#ifdef CONFIG_HVF - uint32_t hvf_arm_get_default_ipa_bit_size(void); uint32_t hvf_arm_get_max_ipa_bit_size(void); =20 -#else - -static inline uint32_t hvf_arm_get_default_ipa_bit_size(void) -{ - return 0; -} - -static inline uint32_t hvf_arm_get_max_ipa_bit_size(void) -{ - return 0; -} - -#endif - #endif diff --git a/target/arm/hvf-stub.c b/target/arm/hvf-stub.c new file mode 100644 index 00000000000..ff137267a03 --- /dev/null +++ b/target/arm/hvf-stub.c @@ -0,0 +1,20 @@ +/* + * QEMU Hypervisor.framework (HVF) stubs for ARM + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hvf_arm.h" + +uint32_t hvf_arm_get_default_ipa_bit_size(void) +{ + g_assert_not_reached(); +} + +uint32_t hvf_arm_get_max_ipa_bit_size(void) +{ + g_assert_not_reached(); +} diff --git a/target/arm/meson.build b/target/arm/meson.build index e568dfb706a..2747f4b404c 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -32,6 +32,7 @@ arm_common_system_ss.add(files('cpu.c'), capstone) arm_common_system_ss.add(when: 'TARGET_AARCH64', if_false: files( 'cpu32-stubs.c')) arm_common_system_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c')) +arm_common_system_ss.add(when: 'CONFIG_HVF', if_false: files('hvf-stub.c')) arm_common_system_ss.add(files( 'arch_dump.c', 'arm-powerctl.c', --=20 2.47.1 From nobody Sat Nov 15 20:49:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747158492; cv=none; d=zohomail.com; s=zohoarc; b=UlKGuH8IDCZ3r+4G1U7ONKgvehInySQyeMSQV8igzDiuFGiCTj0hoR10S+xcnicxxZkPugSjCh3uSgEflqORt5iyv75ZFgxGexOtaBua4JcZc/paqNIpc9OsfRGZQPwF0XIkVrDC4BJRRvFxuOnXRYstqU/xoA9JFCm8HGsh0Go= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747158492; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=YZUjAMI61frHwsGBUl1u718eVkak4wUh6JhRLUE3SNU=; b=P4vzJoGeo8to11XmGzWNedQjc+/OQtHK7qMTjlcWBB04z5ORmLVIJHoGw7L2NKyucMpotBxctMjQJzlZRQqs4ufQiwl/WNVIb9QiGmwoG3jdOANOU+hJe6EWxMtr3NO+OePoVCZm8Mgg/34r/emQ3wtBARCqnRddURIT0hZ+DG4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747158492866578.225866243997; Tue, 13 May 2025 10:48:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uEtgt-0005FG-Fu; Tue, 13 May 2025 13:45:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEtbZ-0008EA-I3 for qemu-devel@nongnu.org; Tue, 13 May 2025 13:39:49 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uEtbX-00038Y-Ts for qemu-devel@nongnu.org; Tue, 13 May 2025 13:39:49 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-442ec3ce724so7384895e9.0 for ; Tue, 13 May 2025 10:39:47 -0700 (PDT) Received: from localhost.localdomain (110.8.30.213.rev.vodafone.pt. [213.30.8.110]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442cd32f331sm221365035e9.13.2025.05.13.10.39.45 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 13 May 2025 10:39:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747157986; x=1747762786; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YZUjAMI61frHwsGBUl1u718eVkak4wUh6JhRLUE3SNU=; b=LjFKgDxeOXmbcmlYajA9+glyROi11ehKDqpeIV1Hyh2FutMmIGiDhD1LP86hej9dlN 0spvGxCtMGD1xpU/B7RCWu0f8DJBP/EMOTBjqhMNxXsNJJtQXFYuorZz5n377w20ah+4 l/+Uh2MU0Z/pWrAfzIh0xf4NybB4QWZtYXqle3cfPEUdmMN4h5rcB20WEhEQAV9Lf9+H mB7VirJ5rqRL3aHevfTv1FIZ7n1ocEuuAjul8aGHwL2iKdJvbauVX5P5vWZqXiNfC3L6 2D/G/ehZVCXJyWndczz+MekXeUfDFaStGQ0Q0fD7uzFGsQXq5ope0h8L+fuXyYEGN3XG enAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747157986; x=1747762786; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YZUjAMI61frHwsGBUl1u718eVkak4wUh6JhRLUE3SNU=; b=TXk2AcQbLzUkPrfVfweUtj/aawNWtoIXV3LHt9Hs33KiXC6kNK3jIppDp/4HAH1VKF WkQ909xNy1KUXTzJhKwChYQEK79B63fQlvAhp2akrsr8somQZpFc+Arp+87Hqil7WB8H y3EPjjnv+r4DnWwk5ZgMotB01tqX+iJkbKvT47Wx0FUYl6sBo5LivbCc41drE1gRLTW8 Pm0PGqx9pLogKm9NXv38LyL5odMFzvRBa+CvltdhuBrwEDgsdRJzVRSzkLGBlrDT7hh8 4q1splycFn3n7tTA0AjpBFvovE4kfqvc97kGyuXdgtzYagsfQDkIUPBpwg8KyqdTQPXN cB5g== X-Gm-Message-State: AOJu0YxTz0K8Itfbm6HVPP47oldyoJbeLM1u0Uo46DMYHz7gXg98rLIU 0bWISJkAwoXXl9C8RCJA4F11DKs7yfQEBbWYseiUY4/rEhAw2lk5C6JDkQgx5GoF03WEUDRLV7C MpHw= X-Gm-Gg: ASbGncsDk5jlm8KaDvwPlI01tbu6amvM1QyBgPkYSDgJnq4RhRbMlki4RIVO2m63x7F l/LHYo7fW/HQH3NV2PI/HP2HA8DZzuHBuZhY5B+DN3eJPWo1ouXNFYlCLaquZuCbpUj1HdPNoKo WFtH4AHc2wuIJpUFaeLJ3z4KcP57JRYwVZXbCI1j/5xON49D8ARI23qswgl0f0zbFAYnlK1eG5c kGJ5JnKg/pszDf8rIvEKwBwl2mom1Lf6WQD2M5tNxXOXPZfRFw6+kAkb6MKzVQqjpCyq8jbCVpN mVcB6u59+h5thodXz/l62F/NSoBOX1sQAcr+TiUAPK7uxM8phrrxrtRgEUvlJfo2li3AQlf29NB MQzzsxnLw9O7Y0W5iTlgnSpsDf0te X-Google-Smtp-Source: AGHT+IGpdJ04lqoDlMvqxaaMQbtzwJyZqp9yNJ2Q0v10AbgjVoG9l+UbH8ogYhI4L+i7SMICme1Pcw== X-Received: by 2002:a05:600c:1e89:b0:43c:fa24:8721 with SMTP id 5b1f17b1804b1-442f210fa5emr2720075e9.17.1747157985932; Tue, 13 May 2025 10:39:45 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Richard Henderson , Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 03/19] target/arm: Only link with zlib when TCG is enabled Date: Tue, 13 May 2025 18:39:12 +0100 Message-ID: <20250513173928.77376-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250513173928.77376-1-philmd@linaro.org> References: <20250513173928.77376-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747158493256116600 Since commit 538b764d341 ("target/arm: Move minor arithmetic helpers out of helper.c") we only use the zlib helpers under TCG. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/arm/meson.build | 1 - target/arm/tcg/meson.build | 2 ++ 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index 2747f4b404c..dcba4ef3792 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -3,7 +3,6 @@ arm_common_ss =3D ss.source_set() arm_ss.add(files( 'gdbstub.c', )) -arm_ss.add(zlib) =20 arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'cpu64.c', diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 2d1502ba882..c59f0f03a1b 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -56,6 +56,8 @@ arm_system_ss.add(files( arm_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c')) arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files('cpu-v7m.c')) =20 +arm_common_ss.add(zlib) + arm_common_ss.add(files( 'arith_helper.c', 'crypto_helper.c', --=20 2.47.1 From nobody Sat Nov 15 20:49:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747158526; cv=none; d=zohomail.com; s=zohoarc; b=TVE3T/TqSj6Uqz19JvlXxBiR2ma9o2/LWC9XlBgA4m4CjLKnj+BGCI5MMxSm9odlKvfng1gISk3OiJyRRvFawfL34H4sNNVJxChhZONKemhcctlEwcnDkPa8I8Nmm90yh4cIcYHkRZXanN2gjzjF2/z5xygmPOg4E+B703mOM7c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747158526; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=fZ+iRFzlsz++4RFD9fl5KNYh6wELAyZ06jqDq2TXAd8=; b=G2eECA0mKylqMuu2Z9kzwM59dYrk5wBE/xyFn5SgIcNKWn6Hf9dKv8528CqJRXohnK8Bwqz8MPUwQF9Ka6ommVv6uA6qqeJ7zLSHAnmJbdTpUhkzyVdH3Pxrdxe5dJvbiM19uXZWjP7pPnck2LQJyXBk1ezkST0knUBcnB4+/W4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747158526596773.3313948524158; Tue, 13 May 2025 10:48:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uEtjY-0007nt-U5; Tue, 13 May 2025 13:48:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEtbe-0008ML-25 for qemu-devel@nongnu.org; Tue, 13 May 2025 13:39:59 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uEtbc-000399-Kv for qemu-devel@nongnu.org; Tue, 13 May 2025 13:39:53 -0400 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-3a0b6aa08e5so39435f8f.1 for ; Tue, 13 May 2025 10:39:52 -0700 (PDT) Received: from localhost.localdomain (110.8.30.213.rev.vodafone.pt. [213.30.8.110]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a1f58f2ab2sm16803819f8f.46.2025.05.13.10.39.49 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 13 May 2025 10:39:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747157991; x=1747762791; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fZ+iRFzlsz++4RFD9fl5KNYh6wELAyZ06jqDq2TXAd8=; b=lxDLEpMId/WwWYWmtwN0ALnWCGjktA76umZDnrHyiO9iauuztAjA1/rGgw/FMICDTc 1Vjm0fcu2jRmt0LFE0FfpytqlfG3MY6r2MSx9S7X/75exOLCOnsr/73mbyeltuEPKYKL UvARxRrUnNcV/VGhXsTYj+4S2u3Nd16OdYdT8zZGHzBYOJFqrwXdpyMVYpdTnXb9DwxY 1UTXvnaB0VZ6NLsfmZQdZByLC3ObdMOykqZOP0dH9YLY1TR12eAE7KfnL//+UNEuM3jw Q7T78g51MY8E+REOWmcKAF6EQ8oZpl3O9xuG9aB+ls7AzLzNaXImOxhqYXuj+baMiFp6 R5MA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747157991; x=1747762791; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fZ+iRFzlsz++4RFD9fl5KNYh6wELAyZ06jqDq2TXAd8=; b=uk/ftjrBsD/hww53tz+p25G2ncmeTp3guH84Jr8g9KoW93QoBufdq5UZXvSb7MLZ9T y7N3UsZc87lBA1qw7z0tnRAr8FIVpltdTdOiim12rt5wS4EpuN1bcNSt5w1NN3gvRJfA He/ufB7fZz8lSbJ1oFfwxL+t/6/7uylj1G/3if7ccnrV+wsYrGQ8R1wAk1k0OpS/57WQ FOv3Z0MWauatYNQiLIcmbKbxA6X4PePk5HygV0ofIjryjz+OUb33PYb/0tqF7hti62Pm kYjzer8M93YZ5A2TjrSUOjS5DGZlAEobP5Uvr1mj8qqf3R7AJ8V9j0R/Sngl28u0r/n8 gsAw== X-Gm-Message-State: AOJu0Yy0z7A3eEBL1PULzfOL+ydELY3XuPaF7YHAkuLli6lwRvs6EwMl lKl6jnj+3w7tCjk6ykW1MvJv+09K5I4V4T0ePiknLXcaztcJhuOMYG+aTa0dXS3Hqul4Gmg3gtT czlM= X-Gm-Gg: ASbGncujjkAKybeaOSvTYzciCB/2WPi6MgEXhJOc7zc2vyAH4pUysOmVIz+zR+5oIOW PHxlLF6DFFa81jtYRy7h/hoTMD33wHqTROV5qavb+gdocNwNCuV9inkgND368KLPfLt3qNnWujT oxGQZ/T9n2kKOeIndC/vBTKu+Awdg7SVnzVVage1iQ54TRnCFXnXLC5APkUnjri0VxvMw1KdmXe mrgC+QcEwjr23h+OxD5fUnABuSqsH4nJKoyb/V84RDtEm/WX0P0u2Sf6S+xiqUqDxCqZf+Tjd3Q gDxuG9qXVhGRHe+2MP2hzqOz3Q145/HKUMuFG1Czj4u2r5f4DEfUENldp3WLDaRBECaFYoaqS55 OzX9+JFU9GPqWfK50HU6t/jKu8AiO X-Google-Smtp-Source: AGHT+IHEX8qyR6nyxz3lFuciGpSkSB6FW0Yqx0MS2RyNHPDGPv4kGeF39UI6qKSPpb5Y7/5f1OzFZg== X-Received: by 2002:a05:6000:4283:b0:3a0:8524:b480 with SMTP id ffacd0b85a97d-3a340d15a00mr3980462f8f.2.1747157990807; Tue, 13 May 2025 10:39:50 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Richard Henderson , Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 04/19] target/arm/cpregs: Include missing 'target/arm/cpu.h' header Date: Tue, 13 May 2025 18:39:13 +0100 Message-ID: <20250513173928.77376-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250513173928.77376-1-philmd@linaro.org> References: <20250513173928.77376-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747158528227019000 CPReadFn type definitions use the CPUARMState type, itself declared in "cpu.h". Include this file in order to avoid when refactoring headers: ../target/arm/cpregs.h:241:27: error: unknown type name 'CPUARMState' typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); ^ Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpregs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 2183de8eda6..c1a7ae37356 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -23,6 +23,7 @@ =20 #include "hw/registerfields.h" #include "target/arm/kvm-consts.h" +#include "cpu.h" =20 /* * ARMCPRegInfo type field bits: --=20 2.47.1 From nobody Sat Nov 15 20:49:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747158584; cv=none; d=zohomail.com; s=zohoarc; b=IqvDLhOZ3Rf3r+anO5tM5tmD8qhkmlQQxCaJs3/LBwdorHcEV/FqK6QmZ1msGq9ZLtBw4UQArJcoCvWlWCsYm28jkPSRtu+5nK4z3UGEhmxETFWA638+GruUPSjuSxqoxseXTsZRYmvkTXvdzuFRpxlEuiwVvxHmjJWdnnuczFM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747158584; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=FlgmqWinD7NQwKFSRiJub8ZlgVYRN5tlN02/pnlcz3E=; b=U4uZf7djIozHfFjjCV+KiOueCK9lchOnVs8vE2Ub3hsqF3rb28y2EdnZ8YQ0M3fUXTCwgZDplcaiU4q1lkF75Uq/4NDxOrKI95NbCdaV2v9GhWQTcLnP/Akr371TYYRZYPA/VvnQuaa4Z/k5aqbfkCQYTbhBJybk4d3QKA71+PU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747158584780714.3310060975316; Tue, 13 May 2025 10:49:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uEtkh-00043x-LJ; Tue, 13 May 2025 13:49:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEtbk-0008Pf-JU for qemu-devel@nongnu.org; Tue, 13 May 2025 13:40:00 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uEtbi-00039Y-WB for qemu-devel@nongnu.org; Tue, 13 May 2025 13:40:00 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-43ede096d73so41384235e9.2 for ; Tue, 13 May 2025 10:39:56 -0700 (PDT) Received: from localhost.localdomain (110.8.30.213.rev.vodafone.pt. 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Include this header in order to avoid when refactoring headers: ../hw/arm/boot.c:281:5: error: implicit declaration of function 'address_= space_stl_notdirty' is invalid in C99 [-Werror,-Wimplicit-function-declarat= ion] address_space_stl_notdirty(as, info->smp_bootreg_addr, ^ Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/boot.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index f94b940bc31..79afb51b8a5 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -19,6 +19,7 @@ #include "system/kvm.h" #include "system/tcg.h" #include "system/system.h" +#include "system/memory.h" #include "system/numa.h" #include "hw/boards.h" #include "system/reset.h" --=20 2.47.1 From nobody Sat Nov 15 20:49:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747158299; cv=none; d=zohomail.com; s=zohoarc; b=jrCta+hfesvW44zTQ719wdekr6AxcuRs+sgRdw4egNia7UaSj3m6BT/B9Rkd6D0hO6bXQPgn45Az3yvp3uzNXPnST1XnDY52ygRJaZktmLB7dOhLPMIWz4DlaTrVPqSjgtEpT0h7UjZn9StKyYx6R0+p6RvLW3gTBinSn6VxmEo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747158299; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=1DnV5Hp0tmpiDlfH4Mi6kMgDb46uwa+8Kt5FmKdT51M=; b=hKZCTR97NF9elz5aKXfNRGDwS1X89mgLnZbZTTfpIi5jHrMDtdUdFChIrdnV3JNXTCfX67h5k9o2EzjVcDZt25hG89HKGhuf6NAR5FFSuMPD9zt3CJPwwmReWyEzaEr45vS+Xb9xh0djfKHaJiTP3FPqeFujXe3kyvEQz0oMCfk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747158299308493.0565571247449; Tue, 13 May 2025 10:44:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uEtft-0003Ub-Am; Tue, 13 May 2025 13:44:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEtbp-0008UM-0q for qemu-devel@nongnu.org; Tue, 13 May 2025 13:40:05 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uEtbm-0003A5-Hv for qemu-devel@nongnu.org; Tue, 13 May 2025 13:40:04 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-440685d6afcso65667055e9.0 for ; Tue, 13 May 2025 10:40:01 -0700 (PDT) Received: from localhost.localdomain (110.8.30.213.rev.vodafone.pt. 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Include the latter to avoid when refactoring unrelated headers: In file included from target/arm/internals.h:33: target/arm/cpu-features.h:45:54: error: unknown type name 'ARMISARegister= s' 45 | static inline bool isar_feature_aa32_thumb_div(const ARMISARegist= ers *id) | ^ target/arm/cpu-features.h:47:12: error: use of undeclared identifier 'R_I= D_ISAR0_DIVIDE_SHIFT' 47 | return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) !=3D 0; | ^ Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/arm/cpu-features.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 525e4cee12f..4452e7c21e3 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -22,6 +22,7 @@ =20 #include "hw/registerfields.h" #include "qemu/host-utils.h" +#include "cpu.h" =20 /* * Naming convention for isar_feature functions: --=20 2.47.1 From nobody Sat Nov 15 20:49:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747158535; cv=none; d=zohomail.com; s=zohoarc; b=X/up2IC3JXlWexXFTiYPTFVogPmeiGnXcueTumAQ1vUO1Cn5vFeJEL/n18eX13E/vV0netQaz85DQSOO4IfJwMEJmmydlmNBFari9B19yg/DQrMMrDRySSoiUJfx9x1qNW21xA/+FJGbGMpC8ZW8v4ut1mQocmnAhm6FXyQ8pDc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747158535; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=j/lGVjd8P+mmHimB41hBIfndruizKSfZ7N3NnHpeffY=; b=lpXFtGd/XE0XwrLZvIm19FG6MO0KFZbPRwNjTwTXFZdhWh7LrboRiR3khaBkrwuDAHGZIVPgIzMEEV+F+zzFd52ywyAJwN8b6i4ufJkV6VCwgxjPAYhDOZwrry6IAKUxrvxQJ73Jn5J6FIT6eSHw8WzoHoTROdUHCTFNap3bvlI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747158535636547.0703307191735; Tue, 13 May 2025 10:48:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uEtfu-0003WR-Ok; Tue, 13 May 2025 13:44:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEtbt-0000B5-3T for qemu-devel@nongnu.org; Tue, 13 May 2025 13:40:09 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uEtbr-0003MG-2m for qemu-devel@nongnu.org; Tue, 13 May 2025 13:40:08 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-3a108684f90so3622659f8f.1 for ; Tue, 13 May 2025 10:40:06 -0700 (PDT) Received: from localhost.localdomain (110.8.30.213.rev.vodafone.pt. [213.30.8.110]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a1f57ee95asm17105644f8f.11.2025.05.13.10.40.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 13 May 2025 10:40:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747158005; x=1747762805; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=j/lGVjd8P+mmHimB41hBIfndruizKSfZ7N3NnHpeffY=; b=njWLMuxO+4sD9GurbFKevQDfEvqow/KgyTXQdILXrVE8P2mLN7E+57M6cGQGUVPT6K ddRSxijVudA/l4jXCfO+Uz7173r5h1Z+kWEAgEV53JLd93bTfUwCpnkwSM4U9Z0Fkm4n 3ePAVI7gSILFr3qLJybp/1sNbwJRijWatJgNEn7LQWAROukNr4x2tlfZnLAgchQPMyMR 3teQwyxRg7nkIfKIRsV+iVKQTsFnDNJyOh24FHh2i2T1tGD51XyeAxHWu56kc5KvwtsK 7+3v4LU2fUjzJeX3Fi9vOK5XTE0aZ7550kqAY/6RCZNdLgD6okEG4UhAfXK9LAqZWoth HWFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747158005; x=1747762805; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=j/lGVjd8P+mmHimB41hBIfndruizKSfZ7N3NnHpeffY=; b=XDYhIyzoBozNSAjZVlfR7pZr9+zh1xTIdiNzdOfql80QxjH7aGO6yrujPbQW5WQONY 8dqNRxDI61UpNGr0Qv3z6JvfqkwhFV9+ISGLtSoEC7DJL1YNbr9ITyzWv/Cyv4JdrOxn r6442pq3LSDSMxX5b0YB5SYYPc8v3HXhZqYurCmb0C1r0gEhwuXwNOo01LvTZ02kH1s+ XaQPc7oCHxema+pO2Rx5ZqfP1tqoxzUjsAmMYqBY6B/6uHcnVnP4HZj+06h6EXrlwSVB bAYZCKFb/qokmRxtvlnn4dSPBUUzecxvWuFyJm2RgnyV3EZkoh89ZXlygqZ6DoW/sROq pQdA== X-Gm-Message-State: AOJu0Yx4Iaam3ZADWjatkiuSgFq6mbtk71jSpqRECf66GEnjXo8f2xR5 9gIJNL45y4VS43cxQ5MixNLBDBYcqgIwIolHSeeVIXQ1k3DwUPMGaC9oeKcw64qZdlfxILHfxwb erOw= X-Gm-Gg: ASbGncuiKgOeoANy8DVf/TpdfRB6qLHwDplbD8FCLCcDxOIHg7z5sEZwP3NZ/Zlj0M/ e8dGesO/Cnxvx263tZizhgKm6cMZa/mFKwFSKN/uPAciuebL+YMacfP9hyXJMhk7af6DNHCxpqX CDHDY+V1Dmk0lHqlmGv1zJneQ2pv9KgxQyA+3Vbme++6Dc+GMTGwZPewmV7mibBQs6ZQJ7/YZ75 pW7dyWkr7ffj3SnRZKWPMPXDwlLgtSNM5z4XnGlByifssP3giqnFM5/lflCLOjdthKhlcq+gEJO DmQey/X7pJpVQhhBHDiVGhCULaesmd1MVT3ged5669xHFwb5v2R8Qi0tizU+5u8lh17gJEV2WYy yBzQV7oRklM+y8+LaDKTjsaHHEKg/ X-Google-Smtp-Source: AGHT+IG9y8FnZ4DTIwP5cv7o0bemgUVC+qrov40VGxMdsOYpK3LQnzpYsbkjEf5uY/e+8hZJ3o9UwQ== X-Received: by 2002:a5d:59ae:0:b0:3a0:8495:cb75 with SMTP id ffacd0b85a97d-3a3496997d7mr196089f8f.9.1747158005233; Tue, 13 May 2025 10:40:05 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Richard Henderson , Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 07/19] target/arm/qmp: Include missing 'cpu.h' header Date: Tue, 13 May 2025 18:39:16 +0100 Message-ID: <20250513173928.77376-8-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250513173928.77376-1-philmd@linaro.org> References: <20250513173928.77376-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747158536482019000 arm-qmp-cmds.c uses ARM_MAX_VQ, which is defined in "cpu.h". Include the latter to avoid when refactoring unrelated headers: target/arm/arm-qmp-cmds.c:83:19: error: use of undeclared identifier 'ARM= _MAX_VQ' 83 | QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16); | ^ Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/arm/arm-qmp-cmds.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/arm-qmp-cmds.c b/target/arm/arm-qmp-cmds.c index a1a944adb43..930ec37413d 100644 --- a/target/arm/arm-qmp-cmds.c +++ b/target/arm/arm-qmp-cmds.c @@ -30,6 +30,7 @@ #include "qapi/qapi-commands-misc-target.h" #include "qobject/qdict.h" #include "qom/qom-qobject.h" +#include "cpu.h" =20 static GICCapability *gic_cap_new(int version) { --=20 2.47.1 From nobody Sat Nov 15 20:49:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747158723; cv=none; d=zohomail.com; s=zohoarc; b=ZimvstKKp0Rp8+d6qFP2L+QdHhj53vl3SyRj9RTbZmdd+tnt8nv5SXR91gc8VgZe0y0NIrnwu+JiIFvByEMrg5W31yVNbh7S4am0tu2D+c5oC782UhLLKkT2t97QfHQOOohdtWlS90owYcBw9rhEX6wPSkmjNMoVZN3L8jXM6EY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747158723; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=4Yt1id2RxlQ9HmFh2CVejYPkAilxVPKGmzO8+uGHOl0=; b=TjSkb9Dnehhcufbk097Czg0eGa30cK74q2u3xnMmP1Vm7NPETbMfLpx/oldeMuOU+G6EUZMM3Tcy/bzLoBfAbtD2vN/650bUAFUOjB/TUzqUIXslV32DVxHxWqtkulEy5VSZf1zlJRYs8+dxewdkCttzSyBYyrIUTr3ane8Orrs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747158723784318.2645055886727; Tue, 13 May 2025 10:52:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uEtnD-0007qL-P1; Tue, 13 May 2025 13:51:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEtc0-0000GX-3L for qemu-devel@nongnu.org; Tue, 13 May 2025 13:40:22 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uEtbw-0003N3-Ak for qemu-devel@nongnu.org; Tue, 13 May 2025 13:40:14 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-442ed8a275fso7593625e9.2 for ; Tue, 13 May 2025 10:40:11 -0700 (PDT) Received: from localhost.localdomain (110.8.30.213.rev.vodafone.pt. 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Include it in order to avoid when refactoring unrelated headers: target/arm/kvm_arm.h:54:29: error: unknown type name 'ARMCPU' 54 | bool write_list_to_kvmstate(ARMCPU *cpu, int level); | ^ Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/arm/kvm_arm.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index c4178d1327c..7dc83caed5c 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -12,6 +12,7 @@ #define QEMU_KVM_ARM_H =20 #include "system/kvm.h" +#include "target/arm/cpu-qom.h" =20 #define KVM_ARM_VGIC_V2 (1 << 0) #define KVM_ARM_VGIC_V3 (1 << 1) --=20 2.47.1 From nobody Sat Nov 15 20:49:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747158784; cv=none; d=zohomail.com; s=zohoarc; b=mtOy9RvhBc/Zuvg9YeXfRtAiM8Cg8CLiPVVlVPhN6sk9NB03ZWvnBPXi+ZZ0/8kw9Vk9v1Aj2kTRG02eOMbAg+R04ssJ/ACTyDZhuOPF55+H+Ac1SBJSmb+45gGUHUt8CNB1n6OdRMxuGHqMHi1+Sjup3qwigsX+6qDtZY15HmI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747158784; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=jo0KGiOqZWbyCmUkMPNRmBmFE7abFdGaEV66vf3nIzs=; b=FPUVGdCKht8fX1c/X4jLcn2X4SY1K+sP22G/Yx2vOoL0DK5DG63kiKaKEuan9J8KhNqH5ycpUPUd+dTud0vfKR7t0IZHHLXBfcWmpghlQlbYKq/jYNJLRz9+PGJTbe+wif7o9FoAMagjGX87ck0I1DoY52IWqDh5hOMro0ZJidA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747158784664891.5275140918236; Tue, 13 May 2025 10:53:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uEtnU-00009M-Ss; Tue, 13 May 2025 13:52:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEtc3-0000IM-Kw for qemu-devel@nongnu.org; Tue, 13 May 2025 13:40:24 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uEtc1-0003Nc-Ao for qemu-devel@nongnu.org; Tue, 13 May 2025 13:40:19 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-441d437cfaaso36470115e9.1 for ; Tue, 13 May 2025 10:40:16 -0700 (PDT) Received: from localhost.localdomain (110.8.30.213.rev.vodafone.pt. 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Include it in order to avoid when refactoring unrelated headers: target/arm/hvf_arm.h:23:41: error: unknown type name 'ARMCPU' 23 | void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu); | ^ Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/arm/hvf_arm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/hvf_arm.h b/target/arm/hvf_arm.h index 7a44e092620..ea82f2691df 100644 --- a/target/arm/hvf_arm.h +++ b/target/arm/hvf_arm.h @@ -11,7 +11,7 @@ #ifndef QEMU_HVF_ARM_H #define QEMU_HVF_ARM_H =20 -#include "cpu.h" +#include "target/arm/cpu-qom.h" =20 /** * hvf_arm_init_debug() - initialize guest debug capabilities --=20 2.47.1 From nobody Sat Nov 15 20:49:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747158762; cv=none; d=zohomail.com; s=zohoarc; b=OmJhuid1NpmLbXZYxgJHbb0B6riDJ4r+jYRRlITBSFrXXB1/kjGg0LKeisyExlsegnJSo/vFlpe8YXaTm+KoQ9ZpDtJnqQrUw9vwlAiqUHKwwi+Mwp0CIWUgL1/iE1zj7rQGMtbpZJsPpTBvOl0yhUT+VCo8EBUhs0BKgFOQQBk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747158762; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=q8SAO3KJ++XWvDWuMU/h8ZGGLKmYxZ6lrHNEHZshFbA=; b=Zm0pp9d7sxpKMVw3oDdCkFUNftIvVdYrFlpaqJMWDfMpSA/8czSIUJcjfF7EoMabz3ZtFxN7kbzViQmLIO+OOrWKkRAA2So/SCYpw/ZsBZQPG6kk52LzpscaXCfDz7g4wqKZl6PBxmdIs/95hC/N2Sfz+VKqGzarmwA1/cmoH1M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747158762176868.5179280053243; Tue, 13 May 2025 10:52:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uEtnb-0000Ve-MJ; Tue, 13 May 2025 13:52:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEtc7-0000KL-S4 for qemu-devel@nongnu.org; Tue, 13 May 2025 13:40:27 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uEtc5-0003OG-Rl for qemu-devel@nongnu.org; Tue, 13 May 2025 13:40:23 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-43cec5cd73bso40319495e9.3 for ; Tue, 13 May 2025 10:40:21 -0700 (PDT) Received: from localhost.localdomain (110.8.30.213.rev.vodafone.pt. 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Tue, 13 May 2025 10:40:19 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Richard Henderson , Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 10/19] hw/arm: Remove unnecessary 'cpu.h' header Date: Tue, 13 May 2025 18:39:19 +0100 Message-ID: <20250513173928.77376-11-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250513173928.77376-1-philmd@linaro.org> References: <20250513173928.77376-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747158763886116600 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- hw/arm/exynos4210.c | 1 - hw/arm/highbank.c | 1 - hw/arm/mps3r.c | 1 - hw/arm/smmuv3.c | 1 - 4 files changed, 4 deletions(-) diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 76001ff0dfc..56267ec2bd2 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -24,7 +24,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "exec/tswap.h" -#include "cpu.h" #include "hw/cpu/a9mpcore.h" #include "hw/irq.h" #include "system/blockdev.h" diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index 3ae26ebebdc..5b2719555af 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -35,7 +35,6 @@ #include "hw/cpu/a15mpcore.h" #include "qemu/log.h" #include "qom/object.h" -#include "cpu.h" #include "target/arm/cpu-qom.h" =20 #define SMP_BOOT_ADDR 0x100 diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c index 48c73acc62e..889d291401e 100644 --- a/hw/arm/mps3r.c +++ b/hw/arm/mps3r.c @@ -29,7 +29,6 @@ #include "qapi/error.h" #include "qobject/qlist.h" #include "system/address-spaces.h" -#include "cpu.h" #include "system/system.h" #include "hw/boards.h" #include "hw/or-irq.h" diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index ab679723533..37b39c9f84f 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -24,7 +24,6 @@ #include "hw/qdev-properties.h" #include "hw/qdev-core.h" #include "hw/pci/pci.h" -#include "cpu.h" #include "exec/target_page.h" #include "trace.h" #include "qemu/log.h" --=20 2.47.1 From nobody Sat Nov 15 20:49:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/arm/cpu.h | 1 - target/arm/cpu.c | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6ed6409cb7a..33ac0c9f818 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -30,7 +30,6 @@ #include "exec/gdbstub.h" #include "exec/page-protection.h" #include "qapi/qapi-types-common.h" -#include "target/arm/multiprocessing.h" #include "target/arm/gtimer.h" =20 #define EXCP_UDEF 1 /* undefined instruction */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a604e4ccac8..8c9d161f2ef 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -52,6 +52,7 @@ #include "cpregs.h" #include "target/arm/cpu-qom.h" #include "target/arm/gtimer.h" +#include "target/arm/multiprocessing.h" =20 static void arm_cpu_set_pc(CPUState *cs, vaddr value) { --=20 2.47.1 From nobody Sat Nov 15 20:49:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747158772; cv=none; d=zohomail.com; s=zohoarc; b=Vl1YGkHdo8g4dPbtPLh6ey6DGyYK949U4VwY2hrP40NBTv1EEdmdYYGq2xmHz45i25QNs6+7qBWnk6chWexJi0m0wWyHK/cgWHClOoCgd4zs7SKZtqvkqGJwms23gz55v1g07qWcy6sFJFvESKJ77dkbgxTVT5UD4Ab1Zyafusw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747158772; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=mOQr33THEcq0t4i2qfK/BB9LCYbfrT4uaAwTHlVrFMs=; b=SaYc3IO1mfj8DP0j9A2j1mNfBlzbhMOsOxQFz7H5UMfm7YkrC1GWs9NVRFpDHetDEtpZLDc7zwfElBzkcSwrr/N4lPcpxOwX7O7pMqiWtsiUWe04+9lnsk9fdSxVI1Yq4w+3yNP4exGWQhIuf1IQtACbfhPDYFFCFbdM7f39UtA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747158772394494.85785927775134; Tue, 13 May 2025 10:52:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uEtnj-00015N-3k; Tue, 13 May 2025 13:52:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEtcI-0000PF-CY for qemu-devel@nongnu.org; Tue, 13 May 2025 13:40:36 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uEtcG-0003Pa-CR for qemu-devel@nongnu.org; Tue, 13 May 2025 13:40:34 -0400 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-3a1fa0d8884so2782556f8f.3 for ; Tue, 13 May 2025 10:40:31 -0700 (PDT) Received: from localhost.localdomain (110.8.30.213.rev.vodafone.pt. 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Move them to "multiprocessing.h", including this header when necessary. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/arm/cpu.h | 17 ----------------- target/arm/multiprocessing.h | 18 ++++++++++++++++++ hw/arm/aspeed_ast2600.c | 1 + hw/arm/aspeed_ast27x0.c | 1 + hw/arm/exynos4210.c | 1 + hw/arm/npcm8xx.c | 1 + hw/arm/sbsa-ref.c | 1 + hw/vmapple/vmapple.c | 1 + target/arm/kvm.c | 1 + 9 files changed, 25 insertions(+), 17 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 33ac0c9f818..b70c7a3ecd2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1155,23 +1155,6 @@ void gt_rme_post_el_change(ARMCPU *cpu, void *opaque= ); =20 void arm_cpu_post_init(Object *obj); =20 -#define ARM_AFF0_SHIFT 0 -#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) -#define ARM_AFF1_SHIFT 8 -#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) -#define ARM_AFF2_SHIFT 16 -#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) -#define ARM_AFF3_SHIFT 32 -#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) -#define ARM_DEFAULT_CPUS_PER_CLUSTER 8 - -#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK) -#define ARM64_AFFINITY_MASK \ - (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK | ARM_AFF3_MASK) -#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) - -uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz); - #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_arm_cpu; =20 diff --git a/target/arm/multiprocessing.h b/target/arm/multiprocessing.h index 81715d345c2..8eec79b11d8 100644 --- a/target/arm/multiprocessing.h +++ b/target/arm/multiprocessing.h @@ -11,6 +11,24 @@ =20 #include "target/arm/cpu-qom.h" =20 +#define ARM_AFF0_SHIFT 0 +#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) +#define ARM_AFF1_SHIFT 8 +#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) +#define ARM_AFF2_SHIFT 16 +#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) +#define ARM_AFF3_SHIFT 32 +#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) +#define ARM_DEFAULT_CPUS_PER_CLUSTER 8 + +#define ARM32_AFFINITY_MASK \ + (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK) +#define ARM64_AFFINITY_MASK \ + (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK) +#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) + +uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz); + uint64_t arm_cpu_mp_affinity(ARMCPU *cpu); =20 #endif diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index d12707f0abe..62a9200dac6 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -17,6 +17,7 @@ #include "net/net.h" #include "system/system.h" #include "target/arm/cpu-qom.h" +#include "target/arm/multiprocessing.h" =20 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 #define ASPEED_SOC_DPMCU_SIZE 0x00040000 diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 1974a257660..a38c2a19751 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -22,6 +22,7 @@ #include "hw/intc/arm_gicv3.h" #include "qobject/qlist.h" #include "qemu/log.h" +#include "target/arm/multiprocessing.h" =20 #define AST2700_SOC_IO_SIZE 0x01000000 #define AST2700_SOC_IOMEM_SIZE 0x01000000 diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 56267ec2bd2..e83a88d3369 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -36,6 +36,7 @@ #include "hw/sd/sdhci.h" #include "hw/usb/hcd-ehci.h" #include "target/arm/cpu-qom.h" +#include "target/arm/multiprocessing.h" =20 #define EXYNOS4210_CHIPID_ADDR 0x10000000 =20 diff --git a/hw/arm/npcm8xx.c b/hw/arm/npcm8xx.c index d7ee306de7a..e6c16537eef 100644 --- a/hw/arm/npcm8xx.c +++ b/hw/arm/npcm8xx.c @@ -29,6 +29,7 @@ #include "qapi/error.h" #include "qemu/units.h" #include "system/system.h" +#include "target/arm/multiprocessing.h" =20 /* * This covers the whole MMIO space. We'll use this to catch any MMIO acce= sses diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index deae5cf9861..25ffb029ff4 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -52,6 +52,7 @@ #include "qom/object.h" #include "target/arm/cpu-qom.h" #include "target/arm/gtimer.h" +#include "target/arm/multiprocessing.h" =20 #define RAMLIMIT_GB 8192 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) diff --git a/hw/vmapple/vmapple.c b/hw/vmapple/vmapple.c index 16e6110b68f..47f23b6e2c0 100644 --- a/hw/vmapple/vmapple.c +++ b/hw/vmapple/vmapple.c @@ -51,6 +51,7 @@ #include "system/reset.h" #include "system/runstate.h" #include "system/system.h" +#include "target/arm/multiprocessing.h" =20 struct VMAppleMachineState { MachineState parent; diff --git a/target/arm/kvm.c b/target/arm/kvm.c index a08a269ad61..5969249b579 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -39,6 +39,7 @@ #include "hw/acpi/acpi.h" #include "hw/acpi/ghes.h" #include "target/arm/gtimer.h" +#include "target/arm/multiprocessing.h" #include "migration/blocker.h" =20 const KVMCapabilityInfo kvm_arch_required_capabilities[] =3D { --=20 2.47.1 From nobody Sat Nov 15 20:49:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747158808; cv=none; d=zohomail.com; s=zohoarc; b=Qo5mpw/BU/k8txjn37zGoiW06zF+rKI0cxzaAzQSqH3AwNeWXG2Qg71c2VSDKmfpjLp1kfwjUFc1stEpJuUd76nGeTDT3gRBKsq1jPep3OaQ+be97m/Di6cp48dHIy7CRA30AsRg267NtF67GAFg8JqqGqDWOrilr7JOBNreGQ0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747158808; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=rbZkU9N2W70mmJR5tu1c9TOXd68jr3evYSE4eI0rwy4=; b=j7PCLa4j3DIfcKEsiroFzVqLl39gMVDQDKIjjTEOTGCnHXwKPyiQ5YrO5IEe/i8SUIL6F9lcXhORU3jjyW/ss1i9A63iBkbb+t2cEKlBGJQa6j1nDf+BxdDHkbQp5offtsgdHCGqFZyBGYpbEXS6kX1ngMrJ+BanCHthib/gdW4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174715880800414.926031648994922; Tue, 13 May 2025 10:53:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uEto6-0001b3-8B; Tue, 13 May 2025 13:52:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEtcN-0000V1-54 for qemu-devel@nongnu.org; Tue, 13 May 2025 13:40:40 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uEtcL-0003Pw-8T for qemu-devel@nongnu.org; Tue, 13 May 2025 13:40:38 -0400 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-43edecbfb94so60863045e9.1 for ; Tue, 13 May 2025 10:40:36 -0700 (PDT) Received: from localhost.localdomain (110.8.30.213.rev.vodafone.pt. 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Tue, 13 May 2025 10:40:35 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Richard Henderson , Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 13/19] hw/arm: Include missing 'target/arm/gtimer.h' header Date: Tue, 13 May 2025 18:39:22 +0100 Message-ID: <20250513173928.77376-14-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250513173928.77376-1-philmd@linaro.org> References: <20250513173928.77376-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747158809258019000 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- hw/arm/aspeed_ast27x0.c | 1 + hw/arm/bcm2838.c | 1 + hw/arm/exynos4210.c | 1 + hw/arm/fsl-imx8mp.c | 1 + hw/arm/mps3r.c | 1 + hw/arm/npcm8xx.c | 1 + hw/vmapple/vmapple.c | 1 + target/arm/tcg/op_helper.c | 1 + 8 files changed, 8 insertions(+) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index a38c2a19751..ad017237f3f 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -22,6 +22,7 @@ #include "hw/intc/arm_gicv3.h" #include "qobject/qlist.h" #include "qemu/log.h" +#include "target/arm/gtimer.h" #include "target/arm/multiprocessing.h" =20 #define AST2700_SOC_IO_SIZE 0x01000000 diff --git a/hw/arm/bcm2838.c b/hw/arm/bcm2838.c index 22aa754613c..20709bf19e8 100644 --- a/hw/arm/bcm2838.c +++ b/hw/arm/bcm2838.c @@ -12,6 +12,7 @@ #include "hw/arm/raspi_platform.h" #include "hw/sysbus.h" #include "hw/arm/bcm2838.h" +#include "target/arm/gtimer.h" #include "trace.h" =20 #define GIC400_MAINTENANCE_IRQ 9 diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index e83a88d3369..24b3c0b5d29 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -36,6 +36,7 @@ #include "hw/sd/sdhci.h" #include "hw/usb/hcd-ehci.h" #include "target/arm/cpu-qom.h" +#include "target/arm/gtimer.h" #include "target/arm/multiprocessing.h" =20 #define EXYNOS4210_CHIPID_ADDR 0x10000000 diff --git a/hw/arm/fsl-imx8mp.c b/hw/arm/fsl-imx8mp.c index 23e662c16ca..3528adb90f1 100644 --- a/hw/arm/fsl-imx8mp.c +++ b/hw/arm/fsl-imx8mp.c @@ -17,6 +17,7 @@ #include "hw/boards.h" #include "system/system.h" #include "target/arm/cpu-qom.h" +#include "target/arm/gtimer.h" #include "qapi/error.h" #include "qobject/qlist.h" =20 diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c index 889d291401e..8c743be3cb5 100644 --- a/hw/arm/mps3r.c +++ b/hw/arm/mps3r.c @@ -47,6 +47,7 @@ #include "hw/ssi/pl022.h" #include "hw/timer/cmsdk-apb-dualtimer.h" #include "hw/watchdog/cmsdk-apb-watchdog.h" +#include "target/arm/gtimer.h" =20 /* Define the layout of RAM and ROM in a board */ typedef struct RAMInfo { diff --git a/hw/arm/npcm8xx.c b/hw/arm/npcm8xx.c index e6c16537eef..7802768c384 100644 --- a/hw/arm/npcm8xx.c +++ b/hw/arm/npcm8xx.c @@ -29,6 +29,7 @@ #include "qapi/error.h" #include "qemu/units.h" #include "system/system.h" +#include "target/arm/gtimer.h" #include "target/arm/multiprocessing.h" =20 /* diff --git a/hw/vmapple/vmapple.c b/hw/vmapple/vmapple.c index 47f23b6e2c0..2dc5e15e791 100644 --- a/hw/vmapple/vmapple.c +++ b/hw/vmapple/vmapple.c @@ -51,6 +51,7 @@ #include "system/reset.h" #include "system/runstate.h" #include "system/system.h" +#include "target/arm/gtimer.h" #include "target/arm/multiprocessing.h" =20 struct VMAppleMachineState { diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 575e566280b..073a8319fa5 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -25,6 +25,7 @@ #include "cpu-features.h" #include "accel/tcg/cpu-ldst.h" #include "accel/tcg/probe.h" +#include "target/arm/gtimer.h" #include "cpregs.h" =20 #define SIGNBIT (uint32_t)0x80000000 --=20 2.47.1 From nobody Sat Nov 15 20:49:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- include/hw/arm/boot.h | 3 ++- target/arm/cpu.h | 7 ++----- target/arm/psci.h | 18 ++++++++++++++++++ hw/arm/bananapi_m2u.c | 1 + hw/arm/boot.c | 1 + hw/arm/highbank.c | 1 + hw/arm/imx8mp-evk.c | 1 + hw/arm/mcimx6ul-evk.c | 1 + hw/arm/mcimx7d-sabre.c | 1 + hw/arm/orangepi.c | 1 + hw/arm/sbsa-ref.c | 1 + hw/arm/virt-acpi-build.c | 1 + hw/arm/virt.c | 1 + hw/arm/xlnx-versal-virt.c | 1 + hw/arm/xlnx-zcu102.c | 1 + hw/vmapple/vmapple.c | 1 + target/arm/helper.c | 1 + target/arm/hvf/hvf.c | 1 + target/arm/tcg/op_helper.c | 1 + target/arm/tcg/psci.c | 1 + 20 files changed, 39 insertions(+), 6 deletions(-) create mode 100644 target/arm/psci.h diff --git a/include/hw/arm/boot.h b/include/hw/arm/boot.h index b12bf61ca81..648fdb88862 100644 --- a/include/hw/arm/boot.h +++ b/include/hw/arm/boot.h @@ -12,6 +12,7 @@ #define HW_ARM_BOOT_H =20 #include "target/arm/cpu-qom.h" +//#include "target/arm/psci.h" #include "qemu/notify.h" =20 typedef enum { @@ -100,7 +101,7 @@ struct arm_boot_info { * as the conduit specifies calls should go to (eg guest firmware boot= ed * to EL3) then PSCI will not be enabled. */ - int psci_conduit; + int psci_conduit;// /* Used internally by arm_boot.c */ int is_linux; hwaddr initrd_start; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b70c7a3ecd2..116745975fa 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3098,11 +3098,8 @@ static inline bool bswap_code(bool sctlr_b) #endif } =20 -enum { - QEMU_PSCI_CONDUIT_DISABLED =3D 0, - QEMU_PSCI_CONDUIT_SMC =3D 1, - QEMU_PSCI_CONDUIT_HVC =3D 2, -}; +void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags); =20 #ifndef CONFIG_USER_ONLY /* Return the address space index to use for a memory access */ diff --git a/target/arm/psci.h b/target/arm/psci.h new file mode 100644 index 00000000000..8b868dfbb91 --- /dev/null +++ b/target/arm/psci.h @@ -0,0 +1,18 @@ +/* + * ARM Power State Coordination Interface (PSCI) definitions + * + * Copyright (c) 2003 Fabrice Bellard + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef TARGET_ARM_PSCI_H +#define TARGET_ARM_PSCI_H + +enum { + QEMU_PSCI_CONDUIT_DISABLED =3D 0, + QEMU_PSCI_CONDUIT_SMC =3D 1, + QEMU_PSCI_CONDUIT_HVC =3D 2, +}; + +#endif diff --git a/hw/arm/bananapi_m2u.c b/hw/arm/bananapi_m2u.c index b750a575f72..61e01a38099 100644 --- a/hw/arm/bananapi_m2u.c +++ b/hw/arm/bananapi_m2u.c @@ -27,6 +27,7 @@ #include "hw/qdev-properties.h" #include "hw/arm/allwinner-r40.h" #include "hw/arm/boot.h" +#include "target/arm/psci.h" =20 static struct arm_boot_info bpim2u_binfo; =20 diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 79afb51b8a5..b81a850819b 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -29,6 +29,7 @@ #include "qemu/config-file.h" #include "qemu/option.h" #include "qemu/units.h" +#include "target/arm/psci.h" =20 /* Kernel boot protocol is specified in the kernel docs * Documentation/arm/Booting and Documentation/arm64/booting.txt diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index 5b2719555af..0ce39877822 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -36,6 +36,7 @@ #include "qemu/log.h" #include "qom/object.h" #include "target/arm/cpu-qom.h" +#include "target/arm/psci.h" =20 #define SMP_BOOT_ADDR 0x100 #define SMP_BOOT_REG 0x40 diff --git a/hw/arm/imx8mp-evk.c b/hw/arm/imx8mp-evk.c index b3082fa60d8..81fe0361ea7 100644 --- a/hw/arm/imx8mp-evk.c +++ b/hw/arm/imx8mp-evk.c @@ -15,6 +15,7 @@ #include "system/qtest.h" #include "qemu/error-report.h" #include "qapi/error.h" +#include "target/arm/psci.h" #include =20 static void imx8mp_evk_modify_dtb(const struct arm_boot_info *info, void *= fdt) diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c index 86982cb0772..be5e50abf17 100644 --- a/hw/arm/mcimx6ul-evk.c +++ b/hw/arm/mcimx6ul-evk.c @@ -18,6 +18,7 @@ #include "hw/qdev-properties.h" #include "qemu/error-report.h" #include "system/qtest.h" +#include "target/arm/psci.h" =20 static void mcimx6ul_evk_init(MachineState *machine) { diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c index 33119610113..e0f25b92594 100644 --- a/hw/arm/mcimx7d-sabre.c +++ b/hw/arm/mcimx7d-sabre.c @@ -20,6 +20,7 @@ #include "hw/qdev-properties.h" #include "qemu/error-report.h" #include "system/qtest.h" +#include "target/arm/psci.h" =20 static void mcimx7d_sabre_init(MachineState *machine) { diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c index e0956880d11..99037a09a36 100644 --- a/hw/arm/orangepi.c +++ b/hw/arm/orangepi.c @@ -26,6 +26,7 @@ #include "hw/qdev-properties.h" #include "hw/arm/allwinner-h3.h" #include "hw/arm/boot.h" +#include "target/arm/psci.h" =20 static struct arm_boot_info orangepi_binfo; =20 diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 25ffb029ff4..d5ce15b688f 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -53,6 +53,7 @@ #include "target/arm/cpu-qom.h" #include "target/arm/gtimer.h" #include "target/arm/multiprocessing.h" +#include "target/arm/psci.h" =20 #define RAMLIMIT_GB 8192 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 7e8e0f0298d..20dc93fbc54 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -59,6 +59,7 @@ #include "hw/acpi/viot.h" #include "hw/virtio/virtio-acpi.h" #include "target/arm/multiprocessing.h" +#include "target/arm/psci.h" =20 #define ARM_SPI_BASE 32 =20 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 9a6cd085a37..d110cb07943 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -79,6 +79,7 @@ #include "target/arm/internals.h" #include "target/arm/multiprocessing.h" #include "target/arm/gtimer.h" +#include "target/arm/psci.h" #include "hw/mem/pc-dimm.h" #include "hw/mem/nvdimm.h" #include "hw/acpi/generic_event_device.h" diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index adadbb72902..7e1b93b782d 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -21,6 +21,7 @@ #include "hw/arm/xlnx-versal.h" #include "hw/arm/boot.h" #include "target/arm/multiprocessing.h" +#include "target/arm/psci.h" #include "qom/object.h" =20 #define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt") diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index 14b6641a713..c46bf11ce24 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -26,6 +26,7 @@ #include "qom/object.h" #include "net/can_emu.h" #include "audio/audio.h" +#include "target/arm/psci.h" =20 struct XlnxZCU102 { MachineState parent_obj; diff --git a/hw/vmapple/vmapple.c b/hw/vmapple/vmapple.c index 2dc5e15e791..b61f5ea51a4 100644 --- a/hw/vmapple/vmapple.c +++ b/hw/vmapple/vmapple.c @@ -53,6 +53,7 @@ #include "system/system.h" #include "target/arm/gtimer.h" #include "target/arm/multiprocessing.h" +#include "target/arm/psci.h" =20 struct VMAppleMachineState { MachineState parent; diff --git a/target/arm/helper.c b/target/arm/helper.c index 76312102879..7859729c39f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -34,6 +34,7 @@ #endif #include "cpregs.h" #include "target/arm/gtimer.h" +#include "target/arm/psci.h" =20 #define HELPER_H "tcg/helper.h" #include "exec/helper-proto.h.inc" diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 42258cc2d88..8fbd4c4be59 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -33,6 +33,7 @@ #include "target/arm/internals.h" #include "target/arm/multiprocessing.h" #include "target/arm/gtimer.h" +#include "target/arm/psci.h" #include "trace.h" #include "migration/vmstate.h" =20 diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 073a8319fa5..e0f9c91450a 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -26,6 +26,7 @@ #include "accel/tcg/cpu-ldst.h" #include "accel/tcg/probe.h" #include "target/arm/gtimer.h" +#include "target/arm/psci.h" #include "cpregs.h" =20 #define SIGNBIT (uint32_t)0x80000000 diff --git a/target/arm/tcg/psci.c b/target/arm/tcg/psci.c index cabed43e8a8..0313cdd6ba2 100644 --- a/target/arm/tcg/psci.c +++ b/target/arm/tcg/psci.c @@ -25,6 +25,7 @@ #include "internals.h" #include "arm-powerctl.h" #include "target/arm/multiprocessing.h" +#include "target/arm/psci.h" =20 bool arm_is_psci_call(ARMCPU *cpu, int excp_type) { --=20 2.47.1 From nobody Sat Nov 15 20:49:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 13 May 2025 10:40:44 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Richard Henderson , Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 15/19] target/arm: Extract feature definitions to 'cpu_has_feature.h' header Date: Tue, 13 May 2025 18:39:24 +0100 Message-ID: <20250513173928.77376-16-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250513173928.77376-1-philmd@linaro.org> References: <20250513173928.77376-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747158545876116600 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/arm/cpu.h | 54 +----------------------------- target/arm/cpu_has_feature.h | 65 ++++++++++++++++++++++++++++++++++++ 2 files changed, 66 insertions(+), 53 deletions(-) create mode 100644 target/arm/cpu_has_feature.h diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 116745975fa..cf3ff21965c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -30,6 +30,7 @@ #include "exec/gdbstub.h" #include "exec/page-protection.h" #include "qapi/qapi-types-common.h" +#include "target/arm/cpu_has_feature.h" #include "target/arm/gtimer.h" =20 #define EXCP_UDEF 1 /* undefined instruction */ @@ -2376,59 +2377,6 @@ FIELD(MFAR, NS, 63, 1) =20 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <=3D R_V7M_CSSELR_INDE= X_MASK); =20 -/* If adding a feature bit which corresponds to a Linux ELF - * HWCAP bit, remember to update the feature-bit-to-hwcap - * mapping in linux-user/elfload.c:get_elf_hwcap(). - */ -enum arm_features { - ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ - ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ - ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ - ARM_FEATURE_V6, - ARM_FEATURE_V6K, - ARM_FEATURE_V7, - ARM_FEATURE_THUMB2, - ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ - ARM_FEATURE_NEON, - ARM_FEATURE_M, /* Microcontroller profile. */ - ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ - ARM_FEATURE_THUMB2EE, - ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ - ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ - ARM_FEATURE_V4T, - ARM_FEATURE_V5, - ARM_FEATURE_STRONGARM, - ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ - ARM_FEATURE_GENERIC_TIMER, - ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ - ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=3D15 */ - ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ - ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register = */ - ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ - ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ - ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ - ARM_FEATURE_V8, - ARM_FEATURE_AARCH64, /* supports 64 bit mode */ - ARM_FEATURE_CBAR, /* has cp15 CBAR */ - ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ - ARM_FEATURE_EL2, /* has EL2 Virtualization support */ - ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ - ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ - ARM_FEATURE_PMU, /* has PMU support */ - ARM_FEATURE_VBAR, /* has cp15 VBAR */ - ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ - ARM_FEATURE_M_MAIN, /* M profile Main Extension */ - ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ - /* - * ARM_FEATURE_BACKCOMPAT_CNTFRQ makes the CPU default cntfrq be 62.5M= Hz - * if the board doesn't set a value, instead of 1GHz. It is for backwa= rds - * compatibility and used only with CPU definitions that were already - * in QEMU before we changed the default. It should not be set on any - * CPU types added in future. - */ - ARM_FEATURE_BACKCOMPAT_CNTFRQ, /* 62.5MHz timer default */ -}; - static inline int arm_feature(CPUARMState *env, int feature) { return (env->features & (1ULL << feature)) !=3D 0; diff --git a/target/arm/cpu_has_feature.h b/target/arm/cpu_has_feature.h new file mode 100644 index 00000000000..2adfccd9208 --- /dev/null +++ b/target/arm/cpu_has_feature.h @@ -0,0 +1,65 @@ +/* + * Helper to check ARM CPU has features + * + * Copyright (c) 2003 Fabrice Bellard + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ +#ifndef TARGET_ARM_CPU_HAS_FEATURE_H +#define TARGET_ARM_CPU_HAS_FEATURE_H + +/* + * If adding a feature bit which corresponds to a Linux ELF + * HWCAP bit, remember to update the feature-bit-to-hwcap + * mapping in linux-user/elfload.c:get_elf_hwcap(). + */ +typedef enum arm_features { + ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ + ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ + ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ + ARM_FEATURE_V6, + ARM_FEATURE_V6K, + ARM_FEATURE_V7, + ARM_FEATURE_THUMB2, + ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ + ARM_FEATURE_NEON, + ARM_FEATURE_M, /* Microcontroller profile. */ + ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ + ARM_FEATURE_THUMB2EE, + ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ + ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ + ARM_FEATURE_V4T, + ARM_FEATURE_V5, + ARM_FEATURE_STRONGARM, + ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ + ARM_FEATURE_GENERIC_TIMER, + ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ + ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=3D15 */ + ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ + ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register = */ + ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ + ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ + ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ + ARM_FEATURE_V8, + ARM_FEATURE_AARCH64, /* supports 64 bit mode */ + ARM_FEATURE_CBAR, /* has cp15 CBAR */ + ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ + ARM_FEATURE_EL2, /* has EL2 Virtualization support */ + ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ + ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ + ARM_FEATURE_PMU, /* has PMU support */ + ARM_FEATURE_VBAR, /* has cp15 VBAR */ + ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ + ARM_FEATURE_M_MAIN, /* M profile Main Extension */ + ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ + /* + * ARM_FEATURE_BACKCOMPAT_CNTFRQ makes the CPU default cntfrq be 62.5M= Hz + * if the board doesn't set a value, instead of 1GHz. It is for backwa= rds + * compatibility and used only with CPU definitions that were already + * in QEMU before we changed the default. It should not be set on any + * CPU types added in future. + */ + ARM_FEATURE_BACKCOMPAT_CNTFRQ, /* 62.5MHz timer default */ +} ArmCpuFeature; + +#endif --=20 2.47.1 From nobody Sat Nov 15 20:49:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747158322; cv=none; d=zohomail.com; s=zohoarc; b=UeYcFc+hTmwhpz0Lvg9R1IukkOPOf4PR0hEgH63xZst+f2DSO2UXMfWjAMlvnslrS7RjxEbR9iATot77UnRt5KVfrr+n8higYxalBjEaLrt7PVZNbw3eYu4Mk3/gZAqonLRIuoaI2xwfP2yYKAT8rzx13iPVhQlc7lwJjEJ8AkE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747158322; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=qVIjgN7PqQ1InviEgK5iLvt5f8f9YeJbM0wSldGeGyk=; b=kIeDd3a2OH0sq7386a+sOS6GddvKw8i35aGloOl52ei6EYvSlb1FxzZgjvI+I4FFL5SK0Keb/ongDyii7FKFxNvBCWtsJA5G5mL78bMymevjwTOU3Y6XOA0YaaLw8dQAjP73wlZX/k4Kds9hqVwb1Svg4BfOC3CGj2fnEqadUCs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747158322704559.9833311553342; Tue, 13 May 2025 10:45:22 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uEtfx-0003al-QK; Tue, 13 May 2025 13:44:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEtcm-0000tm-E1 for qemu-devel@nongnu.org; Tue, 13 May 2025 13:41:10 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uEtcZ-0003RN-FV for qemu-devel@nongnu.org; Tue, 13 May 2025 13:41:03 -0400 Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-3a0b9e2d640so5409887f8f.2 for ; Tue, 13 May 2025 10:40:51 -0700 (PDT) Received: from localhost.localdomain (110.8.30.213.rev.vodafone.pt. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/arm/cpu_has_feature.h | 2 ++ target/arm/cpu.c | 7 +++++++ 2 files changed, 9 insertions(+) diff --git a/target/arm/cpu_has_feature.h b/target/arm/cpu_has_feature.h index 2adfccd9208..352f9d75bed 100644 --- a/target/arm/cpu_has_feature.h +++ b/target/arm/cpu_has_feature.h @@ -62,4 +62,6 @@ typedef enum arm_features { ARM_FEATURE_BACKCOMPAT_CNTFRQ, /* 62.5MHz timer default */ } ArmCpuFeature; =20 +bool arm_cpu_has_feature(ARMCPU *cpu, ArmCpuFeature feature); + #endif diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8c9d161f2ef..759636a3b0e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -54,6 +54,13 @@ #include "target/arm/gtimer.h" #include "target/arm/multiprocessing.h" =20 +bool arm_cpu_has_feature(ARMCPU *cpu, ArmCpuFeature feature) +{ + CPUARMState *env =3D &cpu->env; + + return arm_feature(env, feature); +} + static void arm_cpu_set_pc(CPUState *cs, vaddr value) { ARMCPU *cpu =3D ARM_CPU(cs); --=20 2.47.1 From nobody Sat Nov 15 20:49:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747158580; cv=none; d=zohomail.com; s=zohoarc; b=gBihRGEPDtYwZi92CbnK/3GmJ8AQ7BEZvxG6eFu35PVLvI84XXVtwYYPT26eQWQSSVt9LKz/yim/RNcAWM3p1Klg2Bf8gNKNMzASh1d+kQUjx3o3T6exDTbStolYJSHYOjrSd0EYggh+kpDUg5wzRA/Tnga0A75Bo1nSG1q94pk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747158580; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Mc5S9P/50U+uOhuImq7ntWk/pRQZs10UmelyfyrMZ/I=; b=My7NnWEs7+I0O3WhZEujzErZqWiZCY8SgMu43/p7OvuQ9RYOszTIsQEyzh38aAmMYL/xJvXXTcBQJAaLdqgQ12hLJ6AgZPlnZshiFwmH7R8qWpUMyS1G05zCwQcaNz/zoasA/vjmSYwQeCLwqguUn/JZd5cQHENwD0juWNTBLoU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747158578780443.9624702385754; Tue, 13 May 2025 10:49:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uEtkR-0002ho-AM; Tue, 13 May 2025 13:48:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEtcp-0000uB-AO for qemu-devel@nongnu.org; Tue, 13 May 2025 13:41:12 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uEtcl-0003Rb-2p for qemu-devel@nongnu.org; Tue, 13 May 2025 13:41:05 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-43d0618746bso45440485e9.2 for ; Tue, 13 May 2025 10:40:56 -0700 (PDT) Received: from localhost.localdomain (110.8.30.213.rev.vodafone.pt. [213.30.8.110]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442d67d7795sm181970525e9.8.2025.05.13.10.40.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 13 May 2025 10:40:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747158055; x=1747762855; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Mc5S9P/50U+uOhuImq7ntWk/pRQZs10UmelyfyrMZ/I=; b=XtMiMzbiW37jSEUA7c/VQb+J1gZozMwDIkBcgt5URMFBmPyzIdkkmhlQzPA8P4buWm 1b/BTe7GSaLNACC9+haMtbu5paHvtEa2yRuDTUC6lTX2Uhh7fuVBC4r/p87PCINFZBP0 sLm252opMS9OVXy+0kCMT+VTBkZ2MBZt9JOwIJsTJtpg1b4H0Fauh2S0Ih7xp+DfSr/+ OUrZb1A8otzlgKN0M3DKoV5xR4wATJw0MG46n0usKHrHB2HaKEIl4ZiE2RzUT9etVOXj f62VbZ7L5RaJHP2ZO2lhaLgHiz0FdA2nYrrSewiTLobYVm9xLRyj2rfHLhjZVuyVmy+X 5f3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747158055; x=1747762855; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Mc5S9P/50U+uOhuImq7ntWk/pRQZs10UmelyfyrMZ/I=; b=Nsembdd6fmMHLFO+cKcWjwg2o4fEqfQHr87H1VK7FtZ3i95loiIMRGKczGJaOPt7IT SaMsjAmGrXYcffs+kLRCPkek0o4CLpQC3kXjWxyQPJjYvqgCHSHdWzGvULwlD4Ze3J3S 5wrKF8NyaVKRX2TcZy8rNXfOELTNXP0OBTpQczrndyyWlbNf4YSbNb5qsvMG/9eufbuk 7+8SPm4UvxwaznhFtaG8faMkgKY90ogj+HruLdkAYHBBM4vc6M/EwEU14UrFqHtWIMBf nYCE7X1Mx358hkwJqjf6CRUxcUV65rAKXOzBHJFUxdn7aouo9apy5c/DKyfBLkEvE+QI E2vQ== X-Gm-Message-State: AOJu0Yy3a+U9wdWQPIfJ2L5q1rmMJ9Dk9YzROsTD0KJ/MFjjd93SWHh+ WNAhD9QWvNbYElSiZ/lzAjJch0saArY52tJxnMK18zOU5pd+3xFc3yNSSF3Iswl5E4hdBUsOk03 6Q8U= X-Gm-Gg: ASbGnctJCEvZiiHfPCz9zwmUehbFKUJ9pNS3tBeLqHGbdZO63U5BqIsbwb3+sWv59+w Y13/s1Q7vzDW/c0xe+7fHAG8MwpqA9kQVMG3KMWQUZZN7gM/BD0fvv2bO+2QZ1Bz/cIyroxnTRL s2AK4XiHG8zbF3LC5ylUD/j5v4K+rSSw3/NgKsgdXzepkuwIf1bzOSppl4ura4rLGjC1ADcSTzi e9vJ1dfWmcZD6srMN1aeDtxpChZhgzqL+Z9q4SCyK5cdXFH/cdQDgPjjmDKyGgLWtXnyZROqy2j /tYua/TNAg8FpIsJ98UY/FFrRGvn7+qaU/wCMU4E07vphSDy+GwcaOvxCvQugjVLGn11OAd8oUv qd6P5UdcTsHyLSNnA+5xmbJjwPUgU X-Google-Smtp-Source: AGHT+IFLkgkIv806lDoC0d/3pkBhRsCUuWsFWcI2Ig5dVmkTiEYxRrQWCewkvd7DKokGo8OSpMKw7A== X-Received: by 2002:a05:600c:6308:b0:441:b3f0:e5f6 with SMTP id 5b1f17b1804b1-442f215dcc7mr1737495e9.25.1747158054951; Tue, 13 May 2025 10:40:54 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Richard Henderson , Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 17/19] hw/arm/realview: Replace arm_feature() -> arm_cpu_has_feature() Date: Tue, 13 May 2025 18:39:26 +0100 Message-ID: <20250513173928.77376-18-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250513173928.77376-1-philmd@linaro.org> References: <20250513173928.77376-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747158582508019000 By using arm_cpu_has_feature() instead of arm_feature() we don't need to include "cpu.h" anymore. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- hw/arm/realview.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 5c9050490b4..4c0a8b42709 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -9,7 +9,6 @@ =20 #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "hw/sysbus.h" #include "hw/arm/boot.h" #include "hw/arm/primecell.h" @@ -31,6 +30,7 @@ #include "hw/sd/sd.h" #include "audio/audio.h" #include "target/arm/cpu-qom.h" +#include "target/arm/cpu_has_feature.h" =20 #define SMP_BOOT_ADDR 0xe0000000 #define SMP_BOOTREG_ADDR 0x10000030 @@ -77,7 +77,6 @@ static void realview_init(MachineState *machine, enum realview_board_type board_type) { ARMCPU *cpu =3D NULL; - CPUARMState *env; MemoryRegion *sysmem =3D get_system_memory(); MemoryRegion *ram_lo; MemoryRegion *ram_hi =3D g_new(MemoryRegion, 1); @@ -138,16 +137,15 @@ static void realview_init(MachineState *machine, cpu_irq[n] =3D qdev_get_gpio_in(DEVICE(cpuobj), ARM_CPU_IRQ); } cpu =3D ARM_CPU(first_cpu); - env =3D &cpu->env; - if (arm_feature(env, ARM_FEATURE_V7)) { + if (arm_cpu_has_feature(cpu, ARM_FEATURE_V7)) { if (is_mpcore) { proc_id =3D 0x0c000000; } else { proc_id =3D 0x0e000000; } - } else if (arm_feature(env, ARM_FEATURE_V6K)) { + } else if (arm_cpu_has_feature(cpu, ARM_FEATURE_V6K)) { proc_id =3D 0x06000000; - } else if (arm_feature(env, ARM_FEATURE_V6)) { + } else if (arm_cpu_has_feature(cpu, ARM_FEATURE_V6)) { proc_id =3D 0x04000000; } else { proc_id =3D 0x02000000; --=20 2.47.1 From nobody Sat Nov 15 20:49:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1747158638; cv=none; d=zohomail.com; s=zohoarc; b=ExHjFBL7Yyp2esJrF3uotWhhjLqPS+IO2iTLV0U1qc6NtoTdsujD36yqwx+mO2ck/QfSrnVHCRxT1qlYxl2GZ6jLN7WMNkmrnjxKNv4p8E+GLDMqK5SDevJXRvMRiS8HzSFRr2RwzNHzwcIkjlamM73T2/LolMa1SvQ1ffXTho0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747158638; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=AdJyj/3YunQPgnoavXNfU5+nphnaMTFTvEkxD36KHXw=; b=eRi69xNyak8RVXfLCrfh9/OD/0UkWUNTgPErMJTqj0TIsnBo6MXLma3YL0Qn8mpiTdzdXng+UqQnwJtmm/tppFcvw5gIjXFsH+6qHho5oN87GJPx7qmG3gfRJo8EZjzt6/gNUOBJz8kMPZ1S55R+GqoCUmME7w9BW2RxdNOWG5Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747158638874615.9789438471981; Tue, 13 May 2025 10:50:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uEtka-0003YX-TA; Tue, 13 May 2025 13:49:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEtcp-0000uA-9x for qemu-devel@nongnu.org; Tue, 13 May 2025 13:41:12 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uEtcl-0003S6-T2 for qemu-devel@nongnu.org; Tue, 13 May 2025 13:41:05 -0400 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-43ce70f9afbso60988285e9.0 for ; Tue, 13 May 2025 10:41:02 -0700 (PDT) Received: from localhost.localdomain (110.8.30.213.rev.vodafone.pt. [213.30.8.110]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442cd32f194sm221374605e9.10.2025.05.13.10.40.58 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 13 May 2025 10:41:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747158061; x=1747762861; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AdJyj/3YunQPgnoavXNfU5+nphnaMTFTvEkxD36KHXw=; b=WosqhyHuTW9SZYrhIMsj2t/V8Ky42HEyYP5a0EAvkvBeiibBd4434yZvC+O9mJtCgu 8Uj+kui23PYh2By/90bOgN90II4s5nJU1GKQ0guJ7Z2WnG8NRmVZ1MPDKcYd4m0dv+2C WOPo/FDLi6i5Y3dgkyokVFbGEhJ+Kfw11s7luwCwA+VREuJGZLlcGcbaKUY/FKayZ18q 9V9b2OruUozHSOJXN1GBbQwwRjUvijOU8jBYJZOnaQw3g0bhioiaRp9/WMJq0gAP+wdO cd3PqLdajaSJaWhr7dOjqfOoLiRicexGcKHfHrqev2l9r2gRjaZy+EzgyQJrOKNgK8ip dK+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747158061; x=1747762861; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AdJyj/3YunQPgnoavXNfU5+nphnaMTFTvEkxD36KHXw=; b=UwY5CViVhjOVpsnqZEkoE13o77noCRxfjVGR8pK96a3x92s35Eihlp0voKu6VQ+N8t LoY4pWaLkgcRKz/1n9nSoDlH/oJ6QzVrZpLIS3d8BUNalQWcGuYnqDtnyIxN6H+8evMe 4hIYHivlakB3xdPInhnrMchO3J8fbD/v7AKdNr20AGzDsg+Yk5eTXUhQoBIP3RsQJaXL PypPgN/KSO4pTY1S8781LuckEf8LATcStUG5QSXA4xXU4mi3SVTil6mtbc0NDPxGFGah P/Wpt1Ch/uncWraYzYKpirmCoSCdiXMksV5RAHaJTabnOlQv5Rytwf4lKqjzj5BWJsH2 /4kQ== X-Gm-Message-State: AOJu0Yz6ft79ar7GP7MufIa5q0iQ8Nc9cOsXupjJVXI2ruEr/812WFa9 sKSUfW5sFwRINLCIps+mN9p8ETMAhP9ms5XL2tRdIBvn+yygBfSQYsQWqXKlofyHhwGK3qjOjJK q/OE= X-Gm-Gg: ASbGncuPEu3UDDydtEKUTAaqBl9xOd8j6AVFHa0aOPAYQ5rAaKt89xsiXrQ6s8OdsAf 3u+B0tBVHE6/rDNRwJ3pwH8Nt652YSkGu8cY11ia+XA9MkpcA8DgChKkU1UGsfoun3iNzIXVZEq 5ExtbcPtoMJn+Z0PClxesNm2Fs1c1E5pP/Cy4NoPdvlO8TcRlY4qfDX0tfse/FflJbeNXWAN/hZ S3ozpvSMe6WBialZTdyENhxj/YxYM4UA/ykkuoKjXTATg47XYyB3L24FQRC98XT7fqf7mOm17Tp ssWutFvI6NAD3DU+hSRp/+yrjLi5Uysfh0XIPNsAjIdj87Lu5DDyugCA+6JtQr4K37Dc6pBZDVC iyqLw6PtuW2OF2ixTUemFbIfUm4xD X-Google-Smtp-Source: AGHT+IGEzemtm9ZAf3kgDUxZQyorMNRiLrCOhn6uwaOpHEYSRqzAYgiot/jxOdmcJblrNksBE/Z87g== X-Received: by 2002:a05:600c:524c:b0:43c:f597:d582 with SMTP id 5b1f17b1804b1-442f20ba9f0mr1823085e9.1.1747158060572; Tue, 13 May 2025 10:41:00 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Richard Henderson , Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 18/19] hw/arm/virt-acpi: Replace arm_feature() -> arm_cpu_has_feature() Date: Tue, 13 May 2025 18:39:27 +0100 Message-ID: <20250513173928.77376-19-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250513173928.77376-1-philmd@linaro.org> References: <20250513173928.77376-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747158640756019000 Using arm_cpu_has_feature() instead of arm_feature() remove a dependency on (the indirectly included) "cpu.h" header. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- hw/arm/virt-acpi-build.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 20dc93fbc54..cc4ec7ad465 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -58,6 +58,7 @@ #include "hw/acpi/ghes.h" #include "hw/acpi/viot.h" #include "hw/virtio/virtio-acpi.h" +#include "target/arm/cpu_has_feature.h" #include "target/arm/multiprocessing.h" #include "target/arm/psci.h" =20 @@ -693,7 +694,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(i)); uint64_t physical_base_address =3D 0, gich =3D 0, gicv =3D 0; uint32_t vgic_interrupt =3D vms->virt ? ARCH_GIC_MAINT_IRQ : 0; - uint32_t pmu_interrupt =3D arm_feature(&armcpu->env, ARM_FEATURE_P= MU) ? + uint32_t pmu_interrupt =3D arm_cpu_has_feature(armcpu, ARM_FEATURE= _PMU) ? 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Unify by using the latter which is more explicit. Suggested-by: Pierrick Bouvier Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/arm/cpregs.h | 2 +- target/arm/cpu-features.h | 2 +- target/arm/tcg/translate.h | 2 +- target/arm/arch_dump.c | 2 +- target/arm/arm-powerctl.c | 2 +- target/arm/arm-qmp-cmds.c | 2 +- target/arm/cortex-regs.c | 2 +- target/arm/cpu.c | 2 +- target/arm/cpu64.c | 2 +- target/arm/debug_helper.c | 2 +- target/arm/gdbstub.c | 2 +- target/arm/gdbstub64.c | 2 +- target/arm/helper.c | 2 +- target/arm/hyp_gdbstub.c | 2 +- target/arm/kvm-stub.c | 2 +- target/arm/kvm.c | 2 +- target/arm/machine.c | 2 +- target/arm/ptw.c | 2 +- target/arm/tcg-stubs.c | 2 +- target/arm/tcg/cpu-v7m.c | 2 +- target/arm/tcg/cpu32.c | 2 +- target/arm/tcg/cpu64.c | 2 +- target/arm/tcg/helper-a64.c | 2 +- target/arm/tcg/hflags.c | 2 +- target/arm/tcg/iwmmxt_helper.c | 2 +- target/arm/tcg/m_helper.c | 2 +- target/arm/tcg/mte_helper.c | 2 +- target/arm/tcg/mve_helper.c | 2 +- target/arm/tcg/neon_helper.c | 2 +- target/arm/tcg/op_helper.c | 2 +- target/arm/tcg/pauth_helper.c | 2 +- target/arm/tcg/psci.c | 2 +- target/arm/tcg/sme_helper.c | 2 +- target/arm/tcg/sve_helper.c | 2 +- target/arm/tcg/tlb-insns.c | 2 +- target/arm/tcg/tlb_helper.c | 2 +- target/arm/tcg/vec_helper.c | 2 +- target/arm/tcg/vfp_helper.c | 2 +- target/arm/vfp_fpscr.c | 2 +- 39 files changed, 39 insertions(+), 39 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index c1a7ae37356..25a7c2928ba 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -23,7 +23,7 @@ =20 #include "hw/registerfields.h" #include "target/arm/kvm-consts.h" -#include "cpu.h" +#include "target/arm/cpu.h" =20 /* * ARMCPRegInfo type field bits: diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 4452e7c21e3..90c5efd6eac 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -22,7 +22,7 @@ =20 #include "hw/registerfields.h" #include "qemu/host-utils.h" -#include "cpu.h" +#include "target/arm/cpu.h" =20 /* * Naming convention for isar_feature functions: diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 1bfdb0fb9bb..f8eb0d4a5a8 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -1,7 +1,7 @@ #ifndef TARGET_ARM_TRANSLATE_H #define TARGET_ARM_TRANSLATE_H =20 -#include "cpu.h" +#include "target/arm/cpu.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" #include "exec/translator.h" diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c index 1dd79849c13..9c90430d1b6 100644 --- a/target/arm/arch_dump.c +++ b/target/arm/arch_dump.c @@ -19,7 +19,7 @@ */ =20 #include "qemu/osdep.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "elf.h" #include "system/dump.h" #include "cpu-features.h" diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c index 20c70c7d6bb..4cffe557e37 100644 --- a/target/arm/arm-powerctl.c +++ b/target/arm/arm-powerctl.c @@ -9,7 +9,7 @@ */ =20 #include "qemu/osdep.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "cpu-qom.h" #include "internals.h" #include "arm-powerctl.h" diff --git a/target/arm/arm-qmp-cmds.c b/target/arm/arm-qmp-cmds.c index 930ec37413d..392887d3b48 100644 --- a/target/arm/arm-qmp-cmds.c +++ b/target/arm/arm-qmp-cmds.c @@ -30,7 +30,7 @@ #include "qapi/qapi-commands-misc-target.h" #include "qobject/qdict.h" #include "qom/qom-qobject.h" -#include "cpu.h" +#include "target/arm/cpu.h" =20 static GICCapability *gic_cap_new(int version) { diff --git a/target/arm/cortex-regs.c b/target/arm/cortex-regs.c index ae817b08ddf..2caa8855f02 100644 --- a/target/arm/cortex-regs.c +++ b/target/arm/cortex-regs.c @@ -7,7 +7,7 @@ */ =20 #include "qemu/osdep.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "cpregs.h" =20 =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 759636a3b0e..00f06916e62 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -27,7 +27,7 @@ #include "target/arm/idau.h" #include "qemu/module.h" #include "qapi/error.h" -#include "cpu.h" +#include "target/arm/cpu.h" #ifdef CONFIG_TCG #include "exec/translation-block.h" #include "accel/tcg/cpu-ops.h" diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 00629a5d1d1..34f43094da9 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -20,7 +20,7 @@ =20 #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "cpregs.h" #include "qemu/module.h" #include "qemu/units.h" diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 69fb1d0d9ff..a6199a73740 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -7,7 +7,7 @@ */ #include "qemu/osdep.h" #include "qemu/log.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "internals.h" #include "cpu-features.h" #include "cpregs.h" diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index ce4497ad7c3..d148d8434f1 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -18,7 +18,7 @@ * License along with this library; if not, see . */ #include "qemu/osdep.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "exec/gdbstub.h" #include "gdbstub/helpers.h" #include "gdbstub/commands.h" diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 64ee9b3b567..b6033f431d8 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -18,7 +18,7 @@ */ #include "qemu/osdep.h" #include "qemu/log.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "internals.h" #include "gdbstub/helpers.h" #include "gdbstub/commands.h" diff --git a/target/arm/helper.c b/target/arm/helper.c index 7859729c39f..05a50c5c750 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9,7 +9,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "trace.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "internals.h" #include "cpu-features.h" #include "exec/page-protection.h" diff --git a/target/arm/hyp_gdbstub.c b/target/arm/hyp_gdbstub.c index bb5969720ce..73c9a9a8333 100644 --- a/target/arm/hyp_gdbstub.c +++ b/target/arm/hyp_gdbstub.c @@ -10,7 +10,7 @@ */ =20 #include "qemu/osdep.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "internals.h" #include "gdbstub/enums.h" =20 diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c index 34e57fab011..532018b745e 100644 --- a/target/arm/kvm-stub.c +++ b/target/arm/kvm-stub.c @@ -10,7 +10,7 @@ * */ #include "qemu/osdep.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "kvm_arm.h" =20 bool write_kvmstate_to_list(ARMCPU *cpu) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 5969249b579..d280d08a63e 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -25,7 +25,7 @@ #include "system/kvm.h" #include "system/kvm_int.h" #include "kvm_arm.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "trace.h" #include "internals.h" #include "hw/pci/pci.h" diff --git a/target/arm/machine.c b/target/arm/machine.c index e442d485241..f0524615fe1 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -1,5 +1,5 @@ #include "qemu/osdep.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "qemu/error-report.h" #include "system/kvm.h" #include "system/tcg.h" diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 44170d831cc..03047d10d87 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -14,7 +14,7 @@ #include "exec/target_page.h" #include "exec/tlb-flags.h" #include "accel/tcg/probe.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "internals.h" #include "cpu-features.h" #include "idau.h" diff --git a/target/arm/tcg-stubs.c b/target/arm/tcg-stubs.c index 5e5166c0490..672b5b01db0 100644 --- a/target/arm/tcg-stubs.c +++ b/target/arm/tcg-stubs.c @@ -8,7 +8,7 @@ */ =20 #include "qemu/osdep.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "internals.h" =20 void write_v7m_exception(CPUARMState *env, uint32_t new_exc) diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 95b23d9b55d..9b7108d9678 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -9,7 +9,7 @@ */ =20 #include "qemu/osdep.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "accel/tcg/cpu-ops.h" #include "internals.h" =20 diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 2c45b7eddda..5bf78d9240a 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -9,7 +9,7 @@ */ =20 #include "qemu/osdep.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "accel/tcg/cpu-ops.h" #include "internals.h" #include "target/arm/idau.h" diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 29ab0ac79da..c95036df2a5 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -20,7 +20,7 @@ =20 #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "qemu/module.h" #include "qapi/visitor.h" #include "hw/qdev-properties.h" diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 4f618ae390e..1713348a55d 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -19,7 +19,7 @@ =20 #include "qemu/osdep.h" #include "qemu/units.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "gdbstub/helpers.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index 1ccec63bbd4..d77eacb7338 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -6,7 +6,7 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ #include "qemu/osdep.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "internals.h" #include "cpu-features.h" #include "exec/translation-block.h" diff --git a/target/arm/tcg/iwmmxt_helper.c b/target/arm/tcg/iwmmxt_helper.c index ba054b6b4db..3489f6d01c3 100644 --- a/target/arm/tcg/iwmmxt_helper.c +++ b/target/arm/tcg/iwmmxt_helper.c @@ -21,7 +21,7 @@ =20 #include "qemu/osdep.h" =20 -#include "cpu.h" +#include "target/arm/cpu.h" =20 #define HELPER_H "tcg/helper.h" #include "exec/helper-proto.h.inc" diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index 6614719832e..5d657f5c753 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -7,7 +7,7 @@ */ =20 #include "qemu/osdep.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "internals.h" #include "cpu-features.h" #include "gdbstub/helpers.h" diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 0efc18a181e..66e90b03520 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -19,7 +19,7 @@ =20 #include "qemu/osdep.h" #include "qemu/log.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "internals.h" #include "exec/page-protection.h" #ifdef CONFIG_USER_ONLY diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c index 506d1c34757..105fc0a4b9d 100644 --- a/target/arm/tcg/mve_helper.c +++ b/target/arm/tcg/mve_helper.c @@ -18,7 +18,7 @@ */ =20 #include "qemu/osdep.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "internals.h" #include "vec_internal.h" #include "exec/helper-proto.h" diff --git a/target/arm/tcg/neon_helper.c b/target/arm/tcg/neon_helper.c index 2cc8241f1e4..44f1aafd17d 100644 --- a/target/arm/tcg/neon_helper.c +++ b/target/arm/tcg/neon_helper.c @@ -8,7 +8,7 @@ */ =20 #include "qemu/osdep.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" #include "vec_internal.h" diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index e0f9c91450a..3a4a76e999e 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -18,7 +18,7 @@ */ #include "qemu/osdep.h" #include "qemu/main-loop.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "exec/helper-proto.h" #include "exec/target_page.h" #include "internals.h" diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index c591c3052c3..0ae329710ac 100644 --- a/target/arm/tcg/pauth_helper.c +++ b/target/arm/tcg/pauth_helper.c @@ -18,7 +18,7 @@ */ =20 #include "qemu/osdep.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "internals.h" #include "cpu-features.h" #include "accel/tcg/cpu-ldst.h" diff --git a/target/arm/tcg/psci.c b/target/arm/tcg/psci.c index 0313cdd6ba2..05ecd647c9f 100644 --- a/target/arm/tcg/psci.c +++ b/target/arm/tcg/psci.c @@ -17,7 +17,7 @@ */ =20 #include "qemu/osdep.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "exec/helper-proto.h" #include "kvm-consts.h" #include "qemu/main-loop.h" diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index de0c6e54d4b..a2104b4751d 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -18,7 +18,7 @@ */ =20 #include "qemu/osdep.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "internals.h" #include "tcg/tcg-gvec-desc.h" #include "exec/helper-proto.h" diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index a2c363a4e17..afd110431cd 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -18,7 +18,7 @@ */ =20 #include "qemu/osdep.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "internals.h" #include "exec/page-protection.h" #include "exec/helper-proto.h" diff --git a/target/arm/tcg/tlb-insns.c b/target/arm/tcg/tlb-insns.c index 95c26c6d463..bc8353cdbb5 100644 --- a/target/arm/tcg/tlb-insns.c +++ b/target/arm/tcg/tlb-insns.c @@ -9,7 +9,7 @@ #include "qemu/log.h" #include "exec/cputlb.h" #include "exec/target_page.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "internals.h" #include "cpu-features.h" #include "cpregs.h" diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 23c72a99f5c..ea7d0c74c88 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -6,7 +6,7 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ #include "qemu/osdep.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "internals.h" #include "cpu-features.h" =20 diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index 986eaf8ffa4..9e2715e34de 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -18,7 +18,7 @@ */ =20 #include "qemu/osdep.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" diff --git a/target/arm/tcg/vfp_helper.c b/target/arm/tcg/vfp_helper.c index b1324c5c0a6..ac532ef8511 100644 --- a/target/arm/tcg/vfp_helper.c +++ b/target/arm/tcg/vfp_helper.c @@ -18,7 +18,7 @@ */ =20 #include "qemu/osdep.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "internals.h" #include "cpu-features.h" #include "fpu/softfloat.h" diff --git a/target/arm/vfp_fpscr.c b/target/arm/vfp_fpscr.c index 92ea60ebbf2..a196bcfa803 100644 --- a/target/arm/vfp_fpscr.c +++ b/target/arm/vfp_fpscr.c @@ -18,7 +18,7 @@ */ =20 #include "qemu/osdep.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "internals.h" #include "cpu-features.h" =20 --=20 2.47.1