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[81.250.175.67]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442cd3b7e7fsm213438805e9.39.2025.05.13.07.15.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 May 2025 07:15:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=adacore.com; s=google; t=1747145739; x=1747750539; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=e3t/nIVRg+2jwmgdqscl/THpDb4n/5JCjlQr5Qe7fL8=; b=Sry6ZYwpleV+byZK1JOUxOmixbn7WeItJOsf/MgVP1MRFwv9Srr0um2UUnQEmh614I JnqYmMWS8cT1i3SVl+3EJOWYQnFjkEk7RC2VRUjIa/OuQlhVLTVycOgsrrsXZFm5fpps lgwTjoemvd9W533qecwSkJjyh22jE7GuQ61Us1yO2DzHJdqKr+IbK8K4RLDOzrtOml4M 1B+qjyEZWohJ37HeBIFmEjTX6PsI01L9aoAsgqAMjYdOBK0DNPMXmwkbWWTq99+zafCQ jUDOGn3VdBjiZQACagWgpuvoP6GAy9p757TFCu25oQwDbWjFhUfKuXTDRYT94GT75mx1 XaAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747145739; x=1747750539; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=e3t/nIVRg+2jwmgdqscl/THpDb4n/5JCjlQr5Qe7fL8=; b=hEHOxJUJBreT2yBESSuTymHuzt483aWeRhA6yb6wRQ4FUIwpkQH1sE/Qi09/779qf8 SOZL727F2fyaVtRI64sbrGOGP14V4cv9dUw0Y9o49vMGHBsBfKrabmZrxomVcebAR6H8 n6fJ8t2koeGqPy+XB7CfKWXOs8skCck2Hj8Y2R4MeoRMEQ1rbGFM8q7sk3cxV8BqXikF BtGGZIg70w9o7i4bNkf25D7BjNGWcGOo31XK8DZYzBYZjOdK9puLrT+IIaTVhGQws3zM NC0OBNdMD3FTEpHUQRQAmWQOGEloxR45+VfC2wdvJSu4GQ1xl1Rkk7XEShd9bSa0yXtc EMig== X-Gm-Message-State: AOJu0Yw8Ez9kd+kTJxT8yqC8tI7bH+ZHCsvwqCnQSvJdTnJljillbiXJ KhLpZ6cSSbmF0gb8MCIWBFO32YNMBU2BjGJbEfqqKHI1WCDYSLPa+n1d39QE8Cb/AgxS7S/KOus = X-Gm-Gg: ASbGnctiH082ahRN8eQ3eeOB6IJmS5F55dyJLzx9mGdxp/1VpsW9kakqXbDS0Qrao/m L/CF/yuAiLiEy59iUr3gHnU8eEh0v0rE6RpZiSRDLJjTbBjwoOItdeXEBWGE+O4yp7rHw/i9EVa Wbr6aA1iIYICsAu7wvLsQP8+e84botaAOAEPAmtKgoEwDi2IF3sz4mw692X84c5NWBsHjfT8BFz SgfuSEIpUAd0dG6PWEqApVp5r9NP4oefMB7E/JS6hHhnm1+HCUFvLkInSwMrhlkPZDDLYkhAbRp iKT1p/MX9s0vNjHVb8zdZ/ArR4YMf04llxMoXnO6EzrK49uFHyeo09fw8ok+DVgy2O5At4+yGsc apiEV9GGxZidd8XGPNnzG6gbCkRv8QaPyKNlkIP2fyLiyHlWQ X-Google-Smtp-Source: AGHT+IHWSajJZ6WfViJEDnRWZO/QuobAgMzhlzMwcfuSCWNFAgIueY2VXPgfH7lHFDKOYZEmFhrX9Q== X-Received: by 2002:a05:600c:3d14:b0:43c:fd27:a216 with SMTP id 5b1f17b1804b1-442d6dd21demr135625765e9.23.1747145739335; Tue, 13 May 2025 07:15:39 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20Chigot?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, edgar.iglesias@gmail.com, alistair@alistair23.me, Frederic Konrad , =?UTF-8?q?Cl=C3=A9ment=20Chigot?= Subject: [PATCH 3/4] hw/arm/xlnx-zynqmp: wire a second GIC for the Cortex-R5 Date: Tue, 13 May 2025 16:14:47 +0200 Message-Id: <20250513141448.297946-4-chigot@adacore.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250513141448.297946-1-chigot@adacore.com> References: <20250513141448.297946-1-chigot@adacore.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=chigot@adacore.com; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @adacore.com) X-ZM-MESSAGEID: 1747145895299116600 From: Frederic Konrad This wires a second GIC for the Cortex-R5, all the IRQs are split when there is an RPU instanciated. Signed-off-by: Cl=C3=A9ment Chigot --- hw/arm/xlnx-zynqmp.c | 88 +++++++++++++++++++++++++++++++++--- include/hw/arm/xlnx-zynqmp.h | 6 +++ 2 files changed, 87 insertions(+), 7 deletions(-) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index ec96a46eec..be33669f87 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -26,8 +26,6 @@ #include "target/arm/cpu-qom.h" #include "target/arm/gtimer.h" =20 -#define GIC_NUM_SPI_INTR 160 - #define ARM_PHYS_TIMER_PPI 30 #define ARM_VIRT_TIMER_PPI 27 #define ARM_HYP_TIMER_PPI 26 @@ -206,7 +204,7 @@ static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_region= s[] =3D { =20 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) { - return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; + return XLXN_ZYNQMP_GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_inde= x; } =20 static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s, @@ -377,6 +375,8 @@ static void xlnx_zynqmp_init(Object *obj) XlnxZynqMPState *s =3D XLNX_ZYNQMP(obj); int i; int num_apus =3D MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); + int num_rpus =3D MIN((int)(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS), + XLNX_ZYNQMP_NUM_RPU_CPUS); =20 object_initialize_child(obj, "apu-cluster", &s->apu_cluster, TYPE_CPU_CLUSTER); @@ -390,6 +390,12 @@ static void xlnx_zynqmp_init(Object *obj) =20 object_initialize_child(obj, "gic", &s->gic, gic_class_name()); =20 + if (num_rpus > 0) { + /* Do not create the rpu_gic in case we don't have rpus.. */ + object_initialize_child(obj, "rpu_gic", &s->rpu_gic, + gic_class_name()); + } + for (i =3D 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { object_initialize_child(obj, "gem[*]", &s->gem[i], TYPE_CADENCE_GE= M); object_initialize_child(obj, "gem-irq-orgate[*]", @@ -439,6 +445,13 @@ static void xlnx_zynqmp_init(Object *obj) object_initialize_child(obj, "qspi-irq-orgate", &s->qspi_irq_orgate, TYPE_OR_IRQ); =20 + for (i =3D 0; i < ARRAY_SIZE(s->splitter); i++) { + g_autofree char *name =3D g_strdup_printf("irq-splitter%d", i); + object_initialize_child(obj, name, &s->splitter[i], TYPE_SPLIT_IRQ= ); + } + + + for (i =3D 0; i < XLNX_ZYNQMP_NUM_USB; i++) { object_initialize_child(obj, "usb[*]", &s->usb[i], TYPE_USB_DWC3); } @@ -452,10 +465,13 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Err= or **errp) uint8_t i; uint64_t ram_size; int num_apus =3D MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); + int num_rpus =3D MIN((int)(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS), + XLNX_ZYNQMP_NUM_RPU_CPUS); const char *boot_cpu =3D s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; ram_addr_t ddr_low_size, ddr_high_size; - qemu_irq gic_spi[GIC_NUM_SPI_INTR]; + qemu_irq gic_spi[XLXN_ZYNQMP_GIC_NUM_SPI_INTR]; Error *err =3D NULL; + DeviceState *splitter; =20 ram_size =3D memory_region_size(s->ddr_ram); =20 @@ -502,13 +518,21 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Err= or **errp) g_free(ocm_name); } =20 - qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32= ); + qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", XLXN_ZYNQMP_GIC_NUM_S= PI_INTR + 32); qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus); qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secur= e); qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", s->virt); =20 + if (num_rpus > 0) { + qdev_prop_set_uint32(DEVICE(&s->rpu_gic), "num-irq", + XLXN_ZYNQMP_GIC_NUM_SPI_INTR + 32); + qdev_prop_set_uint32(DEVICE(&s->rpu_gic), "revision", 1); + qdev_prop_set_uint32(DEVICE(&s->rpu_gic), "num-cpu", num_rpus); + qdev_prop_set_uint32(DEVICE(&s->rpu_gic), "first-cpu-index", 4); + } + qdev_realize(DEVICE(&s->apu_cluster), NULL, &error_fatal); =20 /* Realize APUs before realizing the GIC. KVM requires this. */ @@ -608,13 +632,63 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Err= or **errp) return; } =20 + if (num_rpus > 0) { + if (!sysbus_realize(SYS_BUS_DEVICE(&s->rpu_gic), errp)) { + return; + } + + for (i =3D 0; i < num_rpus; i++) { + qemu_irq irq; + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->rpu_gic), i + 1, + GIC_BASE_ADDR + i * 0x1000); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rpu_gic), i, + qdev_get_gpio_in(DEVICE(&s->rpu_cpu[i]), + ARM_CPU_IRQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rpu_gic), i + num_rpus, + qdev_get_gpio_in(DEVICE(&s->rpu_cpu[i]), + ARM_CPU_FIQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rpu_gic), i + num_rpus *= 2, + qdev_get_gpio_in(DEVICE(&s->rpu_cpu[i]), + ARM_CPU_VIRQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rpu_gic), i + num_rpus *= 3, + qdev_get_gpio_in(DEVICE(&s->rpu_cpu[i]), + ARM_CPU_VFIQ)); + irq =3D qdev_get_gpio_in(DEVICE(&s->rpu_gic), + arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI= )); + qdev_connect_gpio_out(DEVICE(&s->rpu_cpu[i]), GTIMER_PHYS, irq= ); + irq =3D qdev_get_gpio_in(DEVICE(&s->rpu_gic), + arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI= )); + qdev_connect_gpio_out(DEVICE(&s->rpu_cpu[i]), GTIMER_VIRT, irq= ); + irq =3D qdev_get_gpio_in(DEVICE(&s->rpu_gic), + arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI)= ); + qdev_connect_gpio_out(DEVICE(&s->rpu_cpu[i]), GTIMER_HYP, irq); + irq =3D qdev_get_gpio_in(DEVICE(&s->rpu_gic), + arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI)= ); + qdev_connect_gpio_out(DEVICE(&s->rpu_cpu[i]), GTIMER_SEC, irq); + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->rpu_gic), 0, GIC_BASE_ADDR); + } + if (!s->boot_cpu_ptr) { error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu); return; } =20 - for (i =3D 0; i < GIC_NUM_SPI_INTR; i++) { - gic_spi[i] =3D qdev_get_gpio_in(DEVICE(&s->gic), i); + for (i =3D 0; i < XLXN_ZYNQMP_GIC_NUM_SPI_INTR; i++) { + splitter =3D DEVICE(&s->splitter[i]); + qdev_prop_set_uint16(splitter, "num-lines", 2); + qdev_realize(splitter, NULL, &error_abort); + if (num_rpus > 0) { + gic_spi[i] =3D qdev_get_gpio_in(splitter, 0); + qdev_connect_gpio_out(splitter, 0, + qdev_get_gpio_in(DEVICE(&s->gic), i)); + qdev_connect_gpio_out(splitter, 1, + qdev_get_gpio_in(DEVICE(&s->rpu_gic), i)= ); + } else { + gic_spi[i] =3D qdev_get_gpio_in(DEVICE(&s->gic), i); + } } =20 for (i =3D 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index c137ac59e8..a69953650d 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -42,6 +42,7 @@ #include "hw/misc/xlnx-zynqmp-crf.h" #include "hw/timer/cadence_ttc.h" #include "hw/usb/hcd-dwc3.h" +#include "hw/core/split-irq.h" =20 #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp" OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) @@ -87,12 +88,14 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE) =20 #define XLNX_ZYNQMP_NUM_TTC 4 +#define XLXN_ZYNQMP_GIC_NUM_SPI_INTR 160 =20 /* * Unimplemented mmio regions needed to boot some images. */ #define XLNX_ZYNQMP_NUM_UNIMP_AREAS 1 =20 + struct XlnxZynqMPState { /*< private >*/ DeviceState parent_obj; @@ -105,6 +108,9 @@ struct XlnxZynqMPState { GICState gic; MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES]; =20 + GICState rpu_gic; + SplitIRQ splitter[XLXN_ZYNQMP_GIC_NUM_SPI_INTR]; + MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS]; =20 MemoryRegion *ddr_ram; --=20 2.34.1