From nobody Sat Nov 15 22:24:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1747118090; cv=none; d=zohomail.com; s=zohoarc; b=KW7aZbVF1AxD2Poo3CFHwT6FLYXAwh+97CRQrDFD1r+KtEhgUmfQs3BPXamt3d/UR0yyMfGusDaAZQnslkOIBJAmfj/1aRp31jLAKDR8rRO55fqiQ6XpI09qxjThjagKN2C7dqh+xL6VSMRvE2VwUuZQZRrYuNFttTwXAtPQLx0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747118090; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=zmoo5LT15sNlU06Q/xiUbE3juWp1BOggyogv3w3tLDE=; b=dk/+PtPEZvW2mngVXzUyHKmQiCjenVdHUH8Jayd+Oo3xm7aHt818qaR1mqGMb5xMxeiGXauHef0KHkvlWSK1KyzyYcSqAM6t9tlf5sTOBZm2jWcm7HP88Uy6wG4opkQNe7G8zVsUHFbLcC64+TWKeNK5XFb3MUoV/ZklPp4O8fM= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747118090217407.9564106644168; Mon, 12 May 2025 23:34:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uEj9u-00041B-LG; Tue, 13 May 2025 02:30:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEj9d-0003Zr-D4; Tue, 13 May 2025 02:30:20 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEj9Y-0001oe-Vf; Tue, 13 May 2025 02:30:15 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 13 May 2025 14:29:04 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 13 May 2025 14:29:04 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v2 06/25] hw/misc/aspeed_hace: Introduce 64-bit hash source address helper function Date: Tue, 13 May 2025 14:28:36 +0800 Message-ID: <20250513062901.2256865-7-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> References: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1747118092706116600 Content-Type: text/plain; charset="utf-8" The AST2700 CPU, based on the Cortex-A35, is a 64-bit processor, and its DR= AM address space is also 64-bit. To support future AST2700 updates, the source hash buffer address data type is being updated to 64-bit. Introduces the "hash_get_source_addr()" helper function to extract the sour= ce hash buffer address. Signed-off-by: Jamin Lin --- hw/misc/aspeed_hace.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index eb513ba00f..5f3c8190ef 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -142,21 +142,30 @@ static bool has_padding(AspeedHACEState *s, struct io= vec *iov, return false; } =20 +static uint64_t hash_get_source_addr(AspeedHACEState *s) +{ + uint64_t src_addr =3D 0; + + src_addr =3D deposit64(src_addr, 0, 32, s->regs[R_HASH_SRC]); + + return src_addr; +} + static int hash_prepare_direct_iov(AspeedHACEState *s, struct iovec *iov) { - uint32_t src; + uint64_t src; void *haddr; hwaddr plen; int iov_idx; =20 plen =3D s->regs[R_HASH_SRC_LEN]; - src =3D s->regs[R_HASH_SRC]; + src =3D hash_get_source_addr(s); haddr =3D address_space_map(&s->dram_as, src, &plen, false, MEMTXATTRS_UNSPECIFIED); if (haddr =3D=3D NULL) { qemu_log_mask(LOG_GUEST_ERROR, - "%s: Unable to map address, addr=3D0x%x, " - "plen=3D0x%" HWADDR_PRIx "\n", + "%s: Unable to map address, addr=3D0x%" HWADDR_PRIx + " ,plen=3D0x%" HWADDR_PRIx "\n", __func__, src, plen); return -1; } @@ -175,11 +184,12 @@ static int hash_prepare_sg_iov(AspeedHACEState *s, st= ruct iovec *iov, uint32_t pad_offset; uint32_t len =3D 0; uint32_t sg_addr; - uint32_t src; + uint64_t src; int iov_idx; hwaddr plen; void *haddr; =20 + src =3D hash_get_source_addr(s); for (iov_idx =3D 0; !(len & SG_LIST_LEN_LAST); iov_idx++) { if (iov_idx =3D=3D ASPEED_HACE_MAX_SG) { qemu_log_mask(LOG_GUEST_ERROR, @@ -188,8 +198,6 @@ static int hash_prepare_sg_iov(AspeedHACEState *s, stru= ct iovec *iov, return -1; } =20 - src =3D s->regs[R_HASH_SRC] + (iov_idx * SG_LIST_ENTRY_SIZE); - len =3D address_space_ldl_le(&s->dram_as, src, MEMTXATTRS_UNSPECIFIED, NULL); sg_addr =3D address_space_ldl_le(&s->dram_as, src + SG_LIST_LEN_SI= ZE, @@ -208,6 +216,8 @@ static int hash_prepare_sg_iov(AspeedHACEState *s, stru= ct iovec *iov, return -1; } =20 + src +=3D SG_LIST_ENTRY_SIZE; + iov[iov_idx].iov_base =3D haddr; if (acc_mode) { s->total_req_len +=3D plen; --=20 2.43.0