From nobody Sat Nov 15 22:24:40 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1747118261; cv=none; d=zohomail.com; s=zohoarc; b=e2kff1QziuDGAgf4Wh5euC0uvJBluJ6jcKq6079dJLsgxYYqwdrBhuXYuV3mNvHP4X3gTIoUTowFM6Nhvrv9vcQ0Dr5ee2CZM8moOIP0j7H3cry7KrsuQke1PLwCrX0EQyo//wNBqn9YBGgVfKNPnTpfqGb6/HyhhYNr7iaZwKI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747118261; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=QHrvzQaJMy/BoR2zBPOSAEQXBKAGEDHzfe82lQK3yH4=; b=TT1WwG1OQnysiauRS6+g7uKN7DWaGB+xOb6dQXiv6ALkr/qSj8zzz7tvh1JcMPKE2PcINDySa72yqIuM1iB2zb2NuQ57lh9svCvdY0svYfvtc+2ORxF28vm5vm8vmcLcInBAW4Byn9MhKBQNQL0o6k0tJrMNugKB9n4JgCGLoqw= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747118261624665.3220878536059; Mon, 12 May 2025 23:37:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uEjEI-0002U6-1G; Tue, 13 May 2025 02:35:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEjB5-0005YF-BS; Tue, 13 May 2025 02:31:52 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEjB2-00026a-1p; Tue, 13 May 2025 02:31:45 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 13 May 2025 14:29:08 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 13 May 2025 14:29:08 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v2 17/25] test/qtest/hace: Adjust test address range for AST1030 due to SRAM limitations Date: Tue, 13 May 2025 14:28:47 +0800 Message-ID: <20250513062901.2256865-18-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> References: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1747118261894116600 Content-Type: text/plain; charset="utf-8" The digest_addr is set to "src_addr + 0x1000000", where src_addr is the DRAM base address. However, the value 0x1000000 (16MB) is too large because the AST1030 does not support DRAM, and its SRAM size is only 768KB. A range size of 0x10000 (64KB) is sufficient for HACE test cases, as the te= st vector size does not exceed 64KB. Updates: 1. Direct Access Mode Update digest_addr to "src_addr + 0x10000" in the following functions: aspeed_test_md5 aspeed_test_sha256 aspeed_test_sha512 2. Scatter-Gather (SG) Mode Update source address for different SG buffer addresses in the following functions: src_addr1 =3D src_addr + 0x10000 src_addr2 =3D src_addr + 0x20000 src_addr3 =3D src_addr + 0x30000 digest_addr =3D src_addr + 0x40000 aspeed_test_sha256_sg aspeed_test_sha512_sg 3. ACC Mode Update Update the SG List start address: src_addr + 0x10000 Update the SG List buffer size to 0x30000 (192KB). buffer_addr =3D src_addr + 0x10000 digest_addr =3D src_addr + 0x40000 Signed-off-by: Jamin Lin --- tests/qtest/aspeed-hace-utils.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/tests/qtest/aspeed-hace-utils.c b/tests/qtest/aspeed-hace-util= s.c index 777fa5b986..539d06e4f8 100644 --- a/tests/qtest/aspeed-hace-utils.c +++ b/tests/qtest/aspeed-hace-utils.c @@ -132,7 +132,7 @@ void aspeed_test_md5(const char *machine, const uint32_= t base, { QTestState *s =3D qtest_init(machine); =20 - uint32_t digest_addr =3D src_addr + 0x01000000; + uint32_t digest_addr =3D src_addr + 0x010000; uint8_t digest[16] =3D {0}; =20 /* Check engine is idle, no busy or irq bits set */ @@ -166,7 +166,7 @@ void aspeed_test_sha256(const char *machine, const uint= 32_t base, { QTestState *s =3D qtest_init(machine); =20 - const uint32_t digest_addr =3D src_addr + 0x1000000; + const uint32_t digest_addr =3D src_addr + 0x10000; uint8_t digest[32] =3D {0}; =20 /* Check engine is idle, no busy or irq bits set */ @@ -200,7 +200,7 @@ void aspeed_test_sha512(const char *machine, const uint= 32_t base, { QTestState *s =3D qtest_init(machine); =20 - const uint32_t digest_addr =3D src_addr + 0x1000000; + const uint32_t digest_addr =3D src_addr + 0x10000; uint8_t digest[64] =3D {0}; =20 /* Check engine is idle, no busy or irq bits set */ @@ -234,10 +234,10 @@ void aspeed_test_sha256_sg(const char *machine, const= uint32_t base, { QTestState *s =3D qtest_init(machine); =20 - const uint32_t src_addr_1 =3D src_addr + 0x1000000; - const uint32_t src_addr_2 =3D src_addr + 0x2000000; - const uint32_t src_addr_3 =3D src_addr + 0x3000000; - const uint32_t digest_addr =3D src_addr + 0x4000000; + const uint32_t src_addr_1 =3D src_addr + 0x10000; + const uint32_t src_addr_2 =3D src_addr + 0x20000; + const uint32_t src_addr_3 =3D src_addr + 0x30000; + const uint32_t digest_addr =3D src_addr + 0x40000; uint8_t digest[32] =3D {0}; struct AspeedSgList array[] =3D { { cpu_to_le32(sizeof(test_vector_sg1)), @@ -285,10 +285,10 @@ void aspeed_test_sha512_sg(const char *machine, const= uint32_t base, { QTestState *s =3D qtest_init(machine); =20 - const uint32_t src_addr_1 =3D src_addr + 0x1000000; - const uint32_t src_addr_2 =3D src_addr + 0x2000000; - const uint32_t src_addr_3 =3D src_addr + 0x3000000; - const uint32_t digest_addr =3D src_addr + 0x4000000; + const uint32_t src_addr_1 =3D src_addr + 0x10000; + const uint32_t src_addr_2 =3D src_addr + 0x20000; + const uint32_t src_addr_3 =3D src_addr + 0x30000; + const uint32_t digest_addr =3D src_addr + 0x40000; uint8_t digest[64] =3D {0}; struct AspeedSgList array[] =3D { { cpu_to_le32(sizeof(test_vector_sg1)), @@ -336,8 +336,8 @@ void aspeed_test_sha256_accum(const char *machine, cons= t uint32_t base, { QTestState *s =3D qtest_init(machine); =20 - const uint32_t buffer_addr =3D src_addr + 0x1000000; - const uint32_t digest_addr =3D src_addr + 0x4000000; + const uint32_t buffer_addr =3D src_addr + 0x10000; + const uint32_t digest_addr =3D src_addr + 0x40000; uint8_t digest[32] =3D {0}; struct AspeedSgList array[] =3D { { cpu_to_le32(sizeof(test_vector_accum_256) | SG_LIST_LEN_LAST), @@ -377,8 +377,8 @@ void aspeed_test_sha512_accum(const char *machine, cons= t uint32_t base, { QTestState *s =3D qtest_init(machine); =20 - const uint32_t buffer_addr =3D src_addr + 0x1000000; - const uint32_t digest_addr =3D src_addr + 0x4000000; + const uint32_t buffer_addr =3D src_addr + 0x10000; + const uint32_t digest_addr =3D src_addr + 0x40000; uint8_t digest[64] =3D {0}; struct AspeedSgList array[] =3D { { cpu_to_le32(sizeof(test_vector_accum_512) | SG_LIST_LEN_LAST), --=20 2.43.0