From nobody Sat Nov 15 22:24:45 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1747118103; cv=none; d=zohomail.com; s=zohoarc; b=SllILYTVMLS/Bd+4Fw0O+do2ofIqqQOea/8lSa/uAbIut79J3hOWVKXY9JSOR93/400QWrbFTHSY862+KFkEOdUSwStl4kbniqMO9YNz99oGFC4N9+VERW9wDlZ0EVcpa+ysBpguuDTlb2+ipxUS43938yYaPQyxp4ZNihK15I8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747118103; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=waKNQ7ICAWhVDlBDI6d9nYBltdk2/ze4UI9TF2xNq7k=; b=YeaAv7uuJWcB353MdxXeK6ZY0w8tZJl4xHQ7X/cm5GDyljKCaVLtUPhOIfM9+7Nt6Ka3C2qKSLSa1+ReZ6FKhWn3ODK2HIZ04b1UGWAUinZULPGeZiTj+5xLM3GwgBy6AVrTt+vJvXLRAV7vs1ffdPV4Ugje9i4dscu3NNJlxOk= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747118103573684.4211535544493; Mon, 12 May 2025 23:35:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uEjCW-0006kW-Fw; Tue, 13 May 2025 02:33:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEjAe-0005Fn-0F; Tue, 13 May 2025 02:31:23 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEjAb-00026a-73; Tue, 13 May 2025 02:31:18 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 13 May 2025 14:29:06 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 13 May 2025 14:29:06 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v2 12/25] hw/misc/aspeed_hace: Add trace-events for better debugging Date: Tue, 13 May 2025 14:28:42 +0800 Message-ID: <20250513062901.2256865-13-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> References: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1747118104393116600 Content-Type: text/plain; charset="utf-8" Introduced "trace_aspeed_hace_hash_addr", "trace_aspeed_hace_hash_sg", "trace_aspeed_hace_read", "trace_aspeed_hace_hash_execute_acc_mode", and "trace_aspeed_hace_write" trace events. Signed-off-by: Jamin Lin --- hw/misc/aspeed_hace.c | 11 +++++++++++ hw/misc/trace-events | 7 +++++++ 2 files changed, 18 insertions(+) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index 5454f51aa6..1ffec029dc 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -18,6 +18,7 @@ #include "crypto/hash.h" #include "hw/qdev-properties.h" #include "hw/irq.h" +#include "trace.h" =20 #define R_CRYPT_CMD (0x10 / 4) =20 @@ -170,6 +171,7 @@ static int hash_prepare_direct_iov(AspeedHACEState *s, = struct iovec *iov, =20 plen =3D s->regs[R_HASH_SRC_LEN]; src =3D hash_get_source_addr(s); + trace_aspeed_hace_hash_addr("src", src); haddr =3D address_space_map(&s->dram_as, src, &plen, false, MEMTXATTRS_UNSPECIFIED); if (haddr =3D=3D NULL) { @@ -214,6 +216,7 @@ static int hash_prepare_sg_iov(AspeedHACEState *s, stru= ct iovec *iov, void *haddr; =20 src =3D hash_get_source_addr(s); + trace_aspeed_hace_hash_addr("src", src); for (iov_idx =3D 0; !(len & SG_LIST_LEN_LAST); iov_idx++) { if (iov_idx =3D=3D ASPEED_HACE_MAX_SG) { qemu_log_mask(LOG_GUEST_ERROR, @@ -227,6 +230,7 @@ static int hash_prepare_sg_iov(AspeedHACEState *s, stru= ct iovec *iov, sg_addr =3D address_space_ldl_le(&s->dram_as, src + SG_LIST_LEN_SI= ZE, MEMTXATTRS_UNSPECIFIED, NULL); sg_addr &=3D SG_LIST_ADDR_MASK; + trace_aspeed_hace_hash_sg(iov_idx, sg_addr, len); /* * To maintain compatibility with older SoCs such as the AST2600, * the AST2700 HW automatically set bit 34 of the 64-bit sg_addr. @@ -290,6 +294,7 @@ static void hash_write_digest_and_unmap_iov(AspeedHACES= tate *s, uint64_t digest_addr =3D 0; =20 digest_addr =3D hash_get_digest_addr(s); + trace_aspeed_hace_hash_addr("digest", digest_addr); if (address_space_write(&s->dram_as, digest_addr, MEMTXATTRS_UNSPECIFIED, digest_buf, digest_len)) { @@ -332,6 +337,8 @@ static void hash_execute_acc_mode(AspeedHACEState *s, i= nt algo, Error *local_err =3D NULL; size_t digest_len; =20 + trace_aspeed_hace_hash_execute_acc_mode(final_request); + if (s->hash_ctx =3D=3D NULL) { s->hash_ctx =3D qcrypto_hash_new(algo, &local_err); if (s->hash_ctx =3D=3D NULL) { @@ -403,6 +410,8 @@ static uint64_t aspeed_hace_read(void *opaque, hwaddr a= ddr, unsigned int size) =20 addr >>=3D 2; =20 + trace_aspeed_hace_read(addr << 2, s->regs[addr]); + return s->regs[addr]; } =20 @@ -414,6 +423,8 @@ static void aspeed_hace_write(void *opaque, hwaddr addr= , uint64_t data, =20 addr >>=3D 2; =20 + trace_aspeed_hace_write(addr << 2, data); + switch (addr) { case R_STATUS: if (data & HASH_IRQ) { diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 4383808d7a..b2587c37d7 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -302,6 +302,13 @@ aspeed_peci_read(uint64_t offset, uint64_t data) "offs= et 0x%" PRIx64 " data 0x%" aspeed_peci_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " da= ta 0x%" PRIx64 aspeed_peci_raise_interrupt(uint32_t ctrl, uint32_t status) "ctrl 0x%" PRI= x32 " status 0x%" PRIx32 =20 +# aspeed_hace.c +aspeed_hace_read(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " dat= a 0x%" PRIx64 +aspeed_hace_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " da= ta 0x%" PRIx64 +aspeed_hace_hash_sg(int index, uint64_t addr, uint32_t len) "%d: addr 0x%"= PRIx64 " len 0x%" PRIx32 +aspeed_hace_hash_addr(const char *s, uint64_t addr) "%s: 0x%" PRIx64 +aspeed_hace_hash_execute_acc_mode(bool final_request) "final request: %d" + # bcm2835_property.c bcm2835_mbox_property(uint32_t tag, uint32_t bufsize, size_t resplen) "mbo= x property tag:0x%08x in_sz:%u out_sz:%zu" =20 --=20 2.43.0