From nobody Sat Nov 15 20:52:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1747117797; cv=none; d=zohomail.com; s=zohoarc; b=XdJ347KHkEX9pskPx7QzEFz3O5L8XdcpVPHdRY7qHz3B2rhegyLmDJLLmN0/G9Je7X8BApDVgnQiVAahsuMI//Y+8f9889Resb2L0QALSCWyaCBxLkFXClqiCPl5rPF7YOo+n8VdO/aC2sYvvR5E16JDYFWBrHbSTiabBzDJkJk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747117797; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=7Zjm+kQUTbB5ZAbooGrzD9Iv37runvOr2Sv/yhiToVA=; b=mR89S4AqY6sXrueImY+bdgfR11Y9wog4HgIdals2JlE4qJShY75TtO6SDAIfL8yYMYEvIrE6wR4cu5u8vivWUmBoB7F5jFOgVrgr1dXRLWJw4fAH2YPbZvwGtDkDvi8EFb+92ZNdSnzer+oHljmHMpOJ0E0XeyNkFZnq4MWNSxQ= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747117797556188.34556269411303; Mon, 12 May 2025 23:29:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uEj92-0002G0-ST; Tue, 13 May 2025 02:29:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEj8t-0002E3-Dh; Tue, 13 May 2025 02:29:31 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEj8q-0001kC-ER; Tue, 13 May 2025 02:29:31 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 13 May 2025 14:29:02 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 13 May 2025 14:29:02 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v2 01/25] hw/misc/aspeed_hace: Remove unused code for better readability Date: Tue, 13 May 2025 14:28:31 +0800 Message-ID: <20250513062901.2256865-2-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> References: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1747117801118116600 In the previous design of the hash framework, accumulative hashing was not supported. To work around this limitation, commit 5cd7d85 introduced an iov_cache array to store all the hash data from firmware. Once the ASPEED HACE model collected all the data, it passed the iov_cache = to the hash API to calculate the final digest. However, with commit e3c0752, the hash framework now supports accumulative hashing. This allows us to refactor the ASPEED HACE model, removing redunda= nt logic and simplifying the implementation for better readability and maintainability. As a result, the iov_count variable is no longer needed=E2=80=94it was prev= iously used to track how many cached entries were used for hashing. To maintain VMSTATE compatibility after removing this field, the VMSTATE_VE= RSION is bumped to 2 This cleanup follows significant changes in commit 4c1d0af4a28d, making the model more readable. - Deleted "iov_cache" and "iov_count" from "AspeedHACEState". - Removed "reconstruct_iov" function and related logic. - Simplified "do_hash_operation" by eliminating redundant checks. Signed-off-by: Jamin Lin --- include/hw/misc/aspeed_hace.h | 2 -- hw/misc/aspeed_hace.c | 39 ++--------------------------------- 2 files changed, 2 insertions(+), 39 deletions(-) diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h index 5d4aa19cfe..b69a038d35 100644 --- a/include/hw/misc/aspeed_hace.h +++ b/include/hw/misc/aspeed_hace.h @@ -31,10 +31,8 @@ struct AspeedHACEState { MemoryRegion iomem; qemu_irq irq; =20 - struct iovec iov_cache[ASPEED_HACE_MAX_SG]; uint32_t regs[ASPEED_HACE_NR_REGS]; uint32_t total_req_len; - uint32_t iov_count; =20 MemoryRegion *dram_mr; AddressSpace dram_as; diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index f4bff32a00..9263739ea6 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -142,25 +142,6 @@ static bool has_padding(AspeedHACEState *s, struct iov= ec *iov, return false; } =20 -static int reconstruct_iov(AspeedHACEState *s, struct iovec *iov, int id, - uint32_t *pad_offset) -{ - int i, iov_count; - if (*pad_offset !=3D 0) { - s->iov_cache[s->iov_count].iov_base =3D iov[id].iov_base; - s->iov_cache[s->iov_count].iov_len =3D *pad_offset; - ++s->iov_count; - } - for (i =3D 0; i < s->iov_count; i++) { - iov[i].iov_base =3D s->iov_cache[i].iov_base; - iov[i].iov_len =3D s->iov_cache[i].iov_len; - } - iov_count =3D s->iov_count; - s->iov_count =3D 0; - s->total_req_len =3D 0; - return iov_count; -} - static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode, bool acc_mode) { @@ -242,19 +223,6 @@ static void do_hash_operation(AspeedHACEState *s, int = algo, bool sg_mode, iov[0].iov_base =3D haddr; iov[0].iov_len =3D len; i =3D 1; - - if (s->iov_count) { - /* - * In aspeed sdk kernel driver, sg_mode is disabled in hash_fi= nal(). - * Thus if we received a request with sg_mode disabled, it is - * required to check whether cache is empty. If no, we should - * combine cached iov and the current iov. - */ - s->total_req_len +=3D len; - if (has_padding(s, iov, len, &total_msg_len, &pad_offset)) { - i =3D reconstruct_iov(s, iov, 0, &pad_offset); - } - } } =20 if (acc_mode) { @@ -278,7 +246,6 @@ static void do_hash_operation(AspeedHACEState *s, int a= lgo, bool sg_mode, qcrypto_hash_free(s->hash_ctx); =20 s->hash_ctx =3D NULL; - s->iov_count =3D 0; s->total_req_len =3D 0; } } else if (qcrypto_hash_bytesv(algo, iov, i, &digest_buf, @@ -437,7 +404,6 @@ static void aspeed_hace_reset(DeviceState *dev) } =20 memset(s->regs, 0, sizeof(s->regs)); - s->iov_count =3D 0; s->total_req_len =3D 0; } =20 @@ -469,12 +435,11 @@ static const Property aspeed_hace_properties[] =3D { =20 static const VMStateDescription vmstate_aspeed_hace =3D { .name =3D TYPE_ASPEED_HACE, - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .fields =3D (const VMStateField[]) { VMSTATE_UINT32_ARRAY(regs, AspeedHACEState, ASPEED_HACE_NR_REGS), VMSTATE_UINT32(total_req_len, AspeedHACEState), - VMSTATE_UINT32(iov_count, AspeedHACEState), VMSTATE_END_OF_LIST(), } }; --=20 2.43.0 From nobody Sat Nov 15 20:52:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1747117798; cv=none; d=zohomail.com; s=zohoarc; b=m8Ip+8iBTdDDR5Bsrj5zVDvU1idr7dnXdO16vKzEoBxro0SanBuJ20FsVQpzFcpB2BhB03fq42znRbph8d7fWzxGlKUIdDilgNwNEsfpAY7jEukaQjmbXU82iqOLAErlCnAG9P2Dtl/ZuD45NvUrnmrm4UoVqER1J4Yy/uJ00Ic= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747117798; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=4kPGix99Im5Hg5H8aZ8wIu5iNL/zHTNeuHO/5gWksKU=; b=ZeGVhP/dD4muBNkMr00xuSHR4cVhwj2XI8evS8ORgbZuDnUJvdc0CNr1SU24IydEgEzE4yNTFoijz4dYwuABAKVNGbpZ1l1ReLOyrwmmGIddvhHf11Qy2GynTXvlpvRv/xGYLhqtQHkiK9PEO3vvL1t+kD7jprVx9KJ6yTslViA= ARC-Authentication-Results: i=1; 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Tue, 13 May 2025 14:29:02 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 13 May 2025 14:29:02 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v2 02/25] hw/misc/aspeed_hace: Improve readability and consistency in variable naming Date: Tue, 13 May 2025 14:28:32 +0800 Message-ID: <20250513062901.2256865-3-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> References: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1747117801130116600 Content-Type: text/plain; charset="utf-8" Currently, users define multiple local variables within different if-statem= ents. To improve readability and maintain consistency in variable naming, rename = the variables accordingly. Introduced "sg_addr" to clearly indicate the scatter-gather mode buffer add= ress. Signed-off-by: Jamin Lin --- hw/misc/aspeed_hace.c | 67 +++++++++++++++++++++---------------------- 1 file changed, 33 insertions(+), 34 deletions(-) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index 9263739ea6..6be94963bc 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -145,15 +145,19 @@ static bool has_padding(AspeedHACEState *s, struct io= vec *iov, static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode, bool acc_mode) { + g_autofree uint8_t *digest_buf =3D NULL; struct iovec iov[ASPEED_HACE_MAX_SG]; + bool acc_final_request =3D false; + Error *local_err =3D NULL; uint32_t total_msg_len; - uint32_t pad_offset; - g_autofree uint8_t *digest_buf =3D NULL; size_t digest_len =3D 0; - bool sg_acc_mode_final_request =3D false; - int i; + uint32_t sg_addr =3D 0; + uint32_t pad_offset; + int iov_idx =3D 0; + uint32_t len =3D 0; + uint32_t src =3D 0; void *haddr; - Error *local_err =3D NULL; + hwaddr plen; =20 if (acc_mode && s->hash_ctx =3D=3D NULL) { s->hash_ctx =3D qcrypto_hash_new(algo, &local_err); @@ -166,74 +170,69 @@ static void do_hash_operation(AspeedHACEState *s, int= algo, bool sg_mode, } =20 if (sg_mode) { - uint32_t len =3D 0; - - for (i =3D 0; !(len & SG_LIST_LEN_LAST); i++) { - uint32_t addr, src; - hwaddr plen; - - if (i =3D=3D ASPEED_HACE_MAX_SG) { + for (iov_idx =3D 0; !(len & SG_LIST_LEN_LAST); iov_idx++) { + if (iov_idx =3D=3D ASPEED_HACE_MAX_SG) { qemu_log_mask(LOG_GUEST_ERROR, "aspeed_hace: guest failed to set end of sg list m= arker\n"); break; } =20 - src =3D s->regs[R_HASH_SRC] + (i * SG_LIST_ENTRY_SIZE); + src =3D s->regs[R_HASH_SRC] + (iov_idx * SG_LIST_ENTRY_SIZE); =20 len =3D address_space_ldl_le(&s->dram_as, src, MEMTXATTRS_UNSPECIFIED, NULL); =20 - addr =3D address_space_ldl_le(&s->dram_as, src + SG_LIST_LEN_S= IZE, - MEMTXATTRS_UNSPECIFIED, NULL); - addr &=3D SG_LIST_ADDR_MASK; + sg_addr =3D address_space_ldl_le(&s->dram_as, src + SG_LIST_LE= N_SIZE, + MEMTXATTRS_UNSPECIFIED, NULL); + sg_addr &=3D SG_LIST_ADDR_MASK; =20 plen =3D len & SG_LIST_LEN_MASK; - haddr =3D address_space_map(&s->dram_as, addr, &plen, false, + haddr =3D address_space_map(&s->dram_as, sg_addr, &plen, false, MEMTXATTRS_UNSPECIFIED); if (haddr =3D=3D NULL) { qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func__); return; } - iov[i].iov_base =3D haddr; + iov[iov_idx].iov_base =3D haddr; if (acc_mode) { s->total_req_len +=3D plen; =20 - if (has_padding(s, &iov[i], plen, &total_msg_len, + if (has_padding(s, &iov[iov_idx], plen, &total_msg_len, &pad_offset)) { /* Padding being present indicates the final request */ - sg_acc_mode_final_request =3D true; - iov[i].iov_len =3D pad_offset; + acc_final_request =3D true; + iov[iov_idx].iov_len =3D pad_offset; } else { - iov[i].iov_len =3D plen; + iov[iov_idx].iov_len =3D plen; } } else { - iov[i].iov_len =3D plen; + iov[iov_idx].iov_len =3D plen; } } } else { - hwaddr len =3D s->regs[R_HASH_SRC_LEN]; + plen =3D s->regs[R_HASH_SRC_LEN]; =20 haddr =3D address_space_map(&s->dram_as, s->regs[R_HASH_SRC], - &len, false, MEMTXATTRS_UNSPECIFIED); + &plen, false, MEMTXATTRS_UNSPECIFIED); if (haddr =3D=3D NULL) { qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func_= _); return; } iov[0].iov_base =3D haddr; - iov[0].iov_len =3D len; - i =3D 1; + iov[0].iov_len =3D plen; + iov_idx =3D 1; } =20 if (acc_mode) { - if (qcrypto_hash_updatev(s->hash_ctx, iov, i, &local_err) < 0) { + if (qcrypto_hash_updatev(s->hash_ctx, iov, iov_idx, &local_err) < = 0) { qemu_log_mask(LOG_GUEST_ERROR, "qcrypto hash update failed : %= s", error_get_pretty(local_err)); error_free(local_err); return; } =20 - if (sg_acc_mode_final_request) { + if (acc_final_request) { if (qcrypto_hash_finalize_bytes(s->hash_ctx, &digest_buf, &digest_len, &local_err)) { qemu_log_mask(LOG_GUEST_ERROR, @@ -248,7 +247,7 @@ static void do_hash_operation(AspeedHACEState *s, int a= lgo, bool sg_mode, s->hash_ctx =3D NULL; s->total_req_len =3D 0; } - } else if (qcrypto_hash_bytesv(algo, iov, i, &digest_buf, + } else if (qcrypto_hash_bytesv(algo, iov, iov_idx, &digest_buf, &digest_len, &local_err) < 0) { qemu_log_mask(LOG_GUEST_ERROR, "qcrypto hash bytesv failed : %s", error_get_pretty(local_err)); @@ -263,10 +262,10 @@ static void do_hash_operation(AspeedHACEState *s, int= algo, bool sg_mode, "aspeed_hace: address space write failed\n"); } =20 - for (; i > 0; i--) { - address_space_unmap(&s->dram_as, iov[i - 1].iov_base, - iov[i - 1].iov_len, false, - iov[i - 1].iov_len); + for (; iov_idx > 0; iov_idx--) { + address_space_unmap(&s->dram_as, iov[iov_idx - 1].iov_base, + iov[iov_idx - 1].iov_len, false, + iov[iov_idx - 1].iov_len); } =20 /* --=20 2.43.0 From nobody Sat Nov 15 20:52:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1747117892; cv=none; d=zohomail.com; s=zohoarc; b=DJXFwwjfnVnpaSIkNef7tyqGG7i9Ef/5IM4GIhrCqTNvPQWtuaUIJGsxilJktSn5VvFFDbBqGD1nksh7udQzyNvbNrR36vP3oaZNFJstCPMg1qwWSi0iCgvLmZ9TXvmHTMH65tNFNHzDjGjLHBOxALj0LWXtBt9gX9S+ArrfVQk= ARC-Message-Signature: i=1; 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Tue, 13 May 2025 02:29:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEj98-0002S1-3A; Tue, 13 May 2025 02:29:46 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEj96-0001lo-Ad; Tue, 13 May 2025 02:29:45 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 13 May 2025 14:29:03 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 13 May 2025 14:29:03 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v2 03/25] hw/misc/aspeed_hace: Ensure HASH_IRQ is always set to prevent firmware hang Date: Tue, 13 May 2025 14:28:33 +0800 Message-ID: <20250513062901.2256865-4-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> References: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1747117896937116600 Content-Type: text/plain; charset="utf-8" Currently, if the program encounters an unsupported algorithm, it does not = set the HASH_IRQ bit in the status register and send an interrupt to indicate command completion. As a result, the FW gets stuck waiting for a completion signal from the HACE module. Additionally, in do_hash_operation, if an error occurs within the condition= al statement, the HASH_IRQ bit is not set in the status register. This causes = the firmware to continuously send HASH commands, as it is unaware that the HACE model has completed processing the command. To fix this, the HASH_IRQ bit in the status register must always be set to ensure that the firmware receives an interrupt from the HACE module, preven= ting it from getting stuck or repeatedly sending HASH commands. Signed-off-by: Jamin Lin Fixes: c5475b3 ("hw: Model ASPEED's Hash and Crypto Engine") --- hw/misc/aspeed_hace.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index 6be94963bc..1256926d22 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -267,12 +267,6 @@ static void do_hash_operation(AspeedHACEState *s, int = algo, bool sg_mode, iov[iov_idx - 1].iov_len, false, iov[iov_idx - 1].iov_len); } - - /* - * Set status bits to indicate completion. Testing shows hardware sets - * these irrespective of HASH_IRQ_EN. - */ - s->regs[R_STATUS] |=3D HASH_IRQ; } =20 static uint64_t aspeed_hace_read(void *opaque, hwaddr addr, unsigned int s= ize) @@ -356,10 +350,16 @@ static void aspeed_hace_write(void *opaque, hwaddr ad= dr, uint64_t data, qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid hash algorithm selection 0x%"PRIx64"\= n", __func__, data & ahc->hash_mask); - break; + } else { + do_hash_operation(s, algo, data & HASH_SG_EN, + ((data & HASH_HMAC_MASK) =3D=3D HASH_DIGEST_ACCUM)); } - do_hash_operation(s, algo, data & HASH_SG_EN, - ((data & HASH_HMAC_MASK) =3D=3D HASH_DIGEST_ACCUM)); + + /* + * Set status bits to indicate completion. Testing shows hardware = sets + * these irrespective of HASH_IRQ_EN. + */ + s->regs[R_STATUS] |=3D HASH_IRQ; =20 if (data & HASH_IRQ_EN) { qemu_irq_raise(s->irq); --=20 2.43.0 From nobody Sat Nov 15 20:52:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1747117839; cv=none; d=zohomail.com; s=zohoarc; b=m86G/YvQtPCMNbPEA+6Hur1rC0FfD5YARGaabXzNDnokSGP5bSM16EAzysk/SEkVHmJ7l13hASJsPZEVJXB8Y/o15zTtHVXTapWOhOAlxPO2EfS9JVnOWt3ZUJnaSQV91EDv34VIzanvOCdPy0cxIL7wr70UEA1MVdZBTI1xVY0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747117839; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=CFg1lY5UmgzSfDhHpCIrqkRb/0g/8tb+bSiMXdtO//U=; b=WcmZPDxWZy6Ag9xC13aynGdJABmAa6vQxGIZwyFG18Iy2uEkv+Ss+q3k1YPbe4wQpsN7EoplkXe5vqL7m0DjkuKBoj4lBMv/JTb5xMFIaoPTKc4lX6T6iRbWj7BiwIH2InJt0lO1u8Yc4cwXPvlwlZv1rU+IfxvgGQVNOBYeoK4= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17471178389562.088626104388709; Mon, 12 May 2025 23:30:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uEj9H-0002yK-U7; Tue, 13 May 2025 02:29:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEj9G-0002vS-9B; Tue, 13 May 2025 02:29:54 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEj9E-0001me-Bt; Tue, 13 May 2025 02:29:53 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 13 May 2025 14:29:03 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 13 May 2025 14:29:03 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v2 04/25] hw/misc/aspeed_hace: Refactor hash buffer setup into helper functions for clarity Date: Tue, 13 May 2025 14:28:34 +0800 Message-ID: <20250513062901.2256865-5-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> References: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1747117841617019000 Content-Type: text/plain; charset="utf-8" To improve code readability and maintainability, this commit refactors the = hash buffer preparation logic from "do_hash_operation()" into two helper functio= ns: - "hash_prepare_direct_iov()": handles non-scatter-gather (direct) mode. - "hash_prepare_sg_iov()": handles scatter-gather mode with accumulation and padding detection support No functional changes are introduced. Signed-off-by: Jamin Lin --- hw/misc/aspeed_hace.c | 153 ++++++++++++++++++++++++++---------------- 1 file changed, 95 insertions(+), 58 deletions(-) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index 1256926d22..22eea62693 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -142,6 +142,92 @@ static bool has_padding(AspeedHACEState *s, struct iov= ec *iov, return false; } =20 +static int hash_prepare_direct_iov(AspeedHACEState *s, struct iovec *iov) +{ + uint32_t src; + void *haddr; + hwaddr plen; + int iov_idx; + + plen =3D s->regs[R_HASH_SRC_LEN]; + src =3D s->regs[R_HASH_SRC]; + haddr =3D address_space_map(&s->dram_as, src, &plen, false, + MEMTXATTRS_UNSPECIFIED); + if (haddr =3D=3D NULL) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Unable to map address, addr=3D0x%x, " + "plen=3D0x%" HWADDR_PRIx "\n", + __func__, src, plen); + return -1; + } + + iov[0].iov_base =3D haddr; + iov[0].iov_len =3D plen; + iov_idx =3D 1; + + return iov_idx; +} + +static int hash_prepare_sg_iov(AspeedHACEState *s, struct iovec *iov, + bool acc_mode, bool *acc_final_request) +{ + uint32_t total_msg_len; + uint32_t pad_offset; + uint32_t len =3D 0; + uint32_t sg_addr; + uint32_t src; + int iov_idx; + hwaddr plen; + void *haddr; + + for (iov_idx =3D 0; !(len & SG_LIST_LEN_LAST); iov_idx++) { + if (iov_idx =3D=3D ASPEED_HACE_MAX_SG) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Failed to set end of sg list marker\n", + __func__); + return -1; + } + + src =3D s->regs[R_HASH_SRC] + (iov_idx * SG_LIST_ENTRY_SIZE); + + len =3D address_space_ldl_le(&s->dram_as, src, + MEMTXATTRS_UNSPECIFIED, NULL); + sg_addr =3D address_space_ldl_le(&s->dram_as, src + SG_LIST_LEN_SI= ZE, + MEMTXATTRS_UNSPECIFIED, NULL); + sg_addr &=3D SG_LIST_ADDR_MASK; + + plen =3D len & SG_LIST_LEN_MASK; + haddr =3D address_space_map(&s->dram_as, sg_addr, &plen, false, + MEMTXATTRS_UNSPECIFIED); + + if (haddr =3D=3D NULL) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Unable to map address, sg_addr=3D0x%x, " + "plen=3D0x%" HWADDR_PRIx "\n", + __func__, sg_addr, plen); + return -1; + } + + iov[iov_idx].iov_base =3D haddr; + if (acc_mode) { + s->total_req_len +=3D plen; + + if (has_padding(s, &iov[iov_idx], plen, &total_msg_len, + &pad_offset)) { + /* Padding being present indicates the final request */ + *acc_final_request =3D true; + iov[iov_idx].iov_len =3D pad_offset; + } else { + iov[iov_idx].iov_len =3D plen; + } + } else { + iov[iov_idx].iov_len =3D plen; + } + } + + return iov_idx; +} + static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode, bool acc_mode) { @@ -149,15 +235,8 @@ static void do_hash_operation(AspeedHACEState *s, int = algo, bool sg_mode, struct iovec iov[ASPEED_HACE_MAX_SG]; bool acc_final_request =3D false; Error *local_err =3D NULL; - uint32_t total_msg_len; size_t digest_len =3D 0; - uint32_t sg_addr =3D 0; - uint32_t pad_offset; - int iov_idx =3D 0; - uint32_t len =3D 0; - uint32_t src =3D 0; - void *haddr; - hwaddr plen; + int iov_idx =3D -1; =20 if (acc_mode && s->hash_ctx =3D=3D NULL) { s->hash_ctx =3D qcrypto_hash_new(algo, &local_err); @@ -169,59 +248,17 @@ static void do_hash_operation(AspeedHACEState *s, int= algo, bool sg_mode, } } =20 + /* Prepares the iov for hashing operations based on the selected mode = */ if (sg_mode) { - for (iov_idx =3D 0; !(len & SG_LIST_LEN_LAST); iov_idx++) { - if (iov_idx =3D=3D ASPEED_HACE_MAX_SG) { - qemu_log_mask(LOG_GUEST_ERROR, - "aspeed_hace: guest failed to set end of sg list m= arker\n"); - break; - } - - src =3D s->regs[R_HASH_SRC] + (iov_idx * SG_LIST_ENTRY_SIZE); - - len =3D address_space_ldl_le(&s->dram_as, src, - MEMTXATTRS_UNSPECIFIED, NULL); - - sg_addr =3D address_space_ldl_le(&s->dram_as, src + SG_LIST_LE= N_SIZE, - MEMTXATTRS_UNSPECIFIED, NULL); - sg_addr &=3D SG_LIST_ADDR_MASK; - - plen =3D len & SG_LIST_LEN_MASK; - haddr =3D address_space_map(&s->dram_as, sg_addr, &plen, false, - MEMTXATTRS_UNSPECIFIED); - if (haddr =3D=3D NULL) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: qcrypto failed\n", __func__); - return; - } - iov[iov_idx].iov_base =3D haddr; - if (acc_mode) { - s->total_req_len +=3D plen; - - if (has_padding(s, &iov[iov_idx], plen, &total_msg_len, - &pad_offset)) { - /* Padding being present indicates the final request */ - acc_final_request =3D true; - iov[iov_idx].iov_len =3D pad_offset; - } else { - iov[iov_idx].iov_len =3D plen; - } - } else { - iov[iov_idx].iov_len =3D plen; - } - } + iov_idx =3D hash_prepare_sg_iov(s, iov, acc_mode, &acc_final_reque= st); } else { - plen =3D s->regs[R_HASH_SRC_LEN]; + iov_idx =3D hash_prepare_direct_iov(s, iov); + } =20 - haddr =3D address_space_map(&s->dram_as, s->regs[R_HASH_SRC], - &plen, false, MEMTXATTRS_UNSPECIFIED); - if (haddr =3D=3D NULL) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func_= _); - return; - } - iov[0].iov_base =3D haddr; - iov[0].iov_len =3D plen; - iov_idx =3D 1; + if (iov_idx <=3D 0) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Failed to prepare iov\n", __func__); + return; } =20 if (acc_mode) { --=20 2.43.0 From nobody Sat Nov 15 20:52:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174711809009052.40136249762634; Mon, 12 May 2025 23:34:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uEj9R-0003Ef-R9; Tue, 13 May 2025 02:30:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEj9M-0003AY-F5; Tue, 13 May 2025 02:30:00 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEj9K-0001nN-M4; Tue, 13 May 2025 02:30:00 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 13 May 2025 14:29:03 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 13 May 2025 14:29:03 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v2 05/25] hw/misc/aspeed_hace: Split hash execution into helper functions for clarity Date: Tue, 13 May 2025 14:28:35 +0800 Message-ID: <20250513062901.2256865-6-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> References: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1747118092802116600 Content-Type: text/plain; charset="utf-8" Refactor "do_hash_operation()" by extracting hash execution and result hand= ling into dedicated helper functions: - "hash_write_digest_and_unmap_iov()": Writes the digest result to memory a= nd unmaps IOVs after processing. - "hash_execute_non_acc_mode()": Handles one-shot (non-accumulated) hash operations. - "hash_execute_acc_mode()": Handles accumulated hashing, including update = and finalize logic. No functional changes introduced. Signed-off-by: Jamin Lin --- hw/misc/aspeed_hace.c | 133 ++++++++++++++++++++++++++---------------- 1 file changed, 83 insertions(+), 50 deletions(-) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index 22eea62693..eb513ba00f 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -228,26 +228,96 @@ static int hash_prepare_sg_iov(AspeedHACEState *s, st= ruct iovec *iov, return iov_idx; } =20 -static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode, - bool acc_mode) +static void hash_write_digest_and_unmap_iov(AspeedHACEState *s, + struct iovec *iov, + int iov_idx, + uint8_t *digest_buf, + size_t digest_len) +{ + if (address_space_write(&s->dram_as, s->regs[R_HASH_DEST], + MEMTXATTRS_UNSPECIFIED, digest_buf, digest_len= )) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Failed to write digest to 0x%x\n", + __func__, s->regs[R_HASH_DEST]); + } + + for (; iov_idx > 0; iov_idx--) { + address_space_unmap(&s->dram_as, iov[iov_idx - 1].iov_base, + iov[iov_idx - 1].iov_len, false, + iov[iov_idx - 1].iov_len); + } +} + +static void hash_execute_non_acc_mode(AspeedHACEState *s, int algo, + struct iovec *iov, int iov_idx) { g_autofree uint8_t *digest_buf =3D NULL; - struct iovec iov[ASPEED_HACE_MAX_SG]; - bool acc_final_request =3D false; Error *local_err =3D NULL; - size_t digest_len =3D 0; - int iov_idx =3D -1; + size_t digest_len; + + if (qcrypto_hash_bytesv(algo, iov, iov_idx, &digest_buf, + &digest_len, &local_err) < 0) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: qcrypto hash bytesv failed : %s", + __func__, error_get_pretty(local_err)); + error_free(local_err); + return; + } + + hash_write_digest_and_unmap_iov(s, iov, iov_idx, digest_buf, digest_le= n); +} + +static void hash_execute_acc_mode(AspeedHACEState *s, int algo, + struct iovec *iov, int iov_idx, + bool final_request) +{ + g_autofree uint8_t *digest_buf =3D NULL; + Error *local_err =3D NULL; + size_t digest_len; =20 - if (acc_mode && s->hash_ctx =3D=3D NULL) { + if (s->hash_ctx =3D=3D NULL) { s->hash_ctx =3D qcrypto_hash_new(algo, &local_err); if (s->hash_ctx =3D=3D NULL) { - qemu_log_mask(LOG_GUEST_ERROR, "qcrypto hash failed : %s", - error_get_pretty(local_err)); + qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto hash new failed : = %s", + __func__, error_get_pretty(local_err)); error_free(local_err); return; } } =20 + if (qcrypto_hash_updatev(s->hash_ctx, iov, iov_idx, &local_err) < 0) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto hash updatev failed : = %s", + __func__, error_get_pretty(local_err)); + error_free(local_err); + return; + } + + if (final_request) { + if (qcrypto_hash_finalize_bytes(s->hash_ctx, &digest_buf, + &digest_len, &local_err)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: qcrypto hash finalize bytes failed : %s", + __func__, error_get_pretty(local_err)); + error_free(local_err); + local_err =3D NULL; + } + + qcrypto_hash_free(s->hash_ctx); + + s->hash_ctx =3D NULL; + s->total_req_len =3D 0; + } + + hash_write_digest_and_unmap_iov(s, iov, iov_idx, digest_buf, digest_le= n); +} + +static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode, + bool acc_mode) +{ + struct iovec iov[ASPEED_HACE_MAX_SG]; + bool acc_final_request =3D false; + int iov_idx =3D -1; + /* Prepares the iov for hashing operations based on the selected mode = */ if (sg_mode) { iov_idx =3D hash_prepare_sg_iov(s, iov, acc_mode, &acc_final_reque= st); @@ -261,48 +331,11 @@ static void do_hash_operation(AspeedHACEState *s, int= algo, bool sg_mode, return; } =20 + /* Executes the hash operation */ if (acc_mode) { - if (qcrypto_hash_updatev(s->hash_ctx, iov, iov_idx, &local_err) < = 0) { - qemu_log_mask(LOG_GUEST_ERROR, "qcrypto hash update failed : %= s", - error_get_pretty(local_err)); - error_free(local_err); - return; - } - - if (acc_final_request) { - if (qcrypto_hash_finalize_bytes(s->hash_ctx, &digest_buf, - &digest_len, &local_err)) { - qemu_log_mask(LOG_GUEST_ERROR, - "qcrypto hash finalize failed : %s", - error_get_pretty(local_err)); - error_free(local_err); - local_err =3D NULL; - } - - qcrypto_hash_free(s->hash_ctx); - - s->hash_ctx =3D NULL; - s->total_req_len =3D 0; - } - } else if (qcrypto_hash_bytesv(algo, iov, iov_idx, &digest_buf, - &digest_len, &local_err) < 0) { - qemu_log_mask(LOG_GUEST_ERROR, "qcrypto hash bytesv failed : %s", - error_get_pretty(local_err)); - error_free(local_err); - return; - } - - if (address_space_write(&s->dram_as, s->regs[R_HASH_DEST], - MEMTXATTRS_UNSPECIFIED, - digest_buf, digest_len)) { - qemu_log_mask(LOG_GUEST_ERROR, - "aspeed_hace: address space write failed\n"); - } - - for (; iov_idx > 0; iov_idx--) { - address_space_unmap(&s->dram_as, iov[iov_idx - 1].iov_base, - iov[iov_idx - 1].iov_len, false, - iov[iov_idx - 1].iov_len); + hash_execute_acc_mode(s, algo, iov, iov_idx, acc_final_request); + } else { + hash_execute_non_acc_mode(s, algo, iov, iov_idx); } } =20 --=20 2.43.0 From nobody Sat Nov 15 20:52:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1747118090; cv=none; d=zohomail.com; s=zohoarc; b=KW7aZbVF1AxD2Poo3CFHwT6FLYXAwh+97CRQrDFD1r+KtEhgUmfQs3BPXamt3d/UR0yyMfGusDaAZQnslkOIBJAmfj/1aRp31jLAKDR8rRO55fqiQ6XpI09qxjThjagKN2C7dqh+xL6VSMRvE2VwUuZQZRrYuNFttTwXAtPQLx0= ARC-Message-Signature: i=1; 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Tue, 13 May 2025 02:30:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEj9d-0003Zr-D4; Tue, 13 May 2025 02:30:20 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEj9Y-0001oe-Vf; Tue, 13 May 2025 02:30:15 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 13 May 2025 14:29:04 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 13 May 2025 14:29:04 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v2 06/25] hw/misc/aspeed_hace: Introduce 64-bit hash source address helper function Date: Tue, 13 May 2025 14:28:36 +0800 Message-ID: <20250513062901.2256865-7-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> References: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1747118092706116600 Content-Type: text/plain; charset="utf-8" The AST2700 CPU, based on the Cortex-A35, is a 64-bit processor, and its DR= AM address space is also 64-bit. To support future AST2700 updates, the source hash buffer address data type is being updated to 64-bit. Introduces the "hash_get_source_addr()" helper function to extract the sour= ce hash buffer address. Signed-off-by: Jamin Lin --- hw/misc/aspeed_hace.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index eb513ba00f..5f3c8190ef 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -142,21 +142,30 @@ static bool has_padding(AspeedHACEState *s, struct io= vec *iov, return false; } =20 +static uint64_t hash_get_source_addr(AspeedHACEState *s) +{ + uint64_t src_addr =3D 0; + + src_addr =3D deposit64(src_addr, 0, 32, s->regs[R_HASH_SRC]); + + return src_addr; +} + static int hash_prepare_direct_iov(AspeedHACEState *s, struct iovec *iov) { - uint32_t src; + uint64_t src; void *haddr; hwaddr plen; int iov_idx; =20 plen =3D s->regs[R_HASH_SRC_LEN]; - src =3D s->regs[R_HASH_SRC]; + src =3D hash_get_source_addr(s); haddr =3D address_space_map(&s->dram_as, src, &plen, false, MEMTXATTRS_UNSPECIFIED); if (haddr =3D=3D NULL) { qemu_log_mask(LOG_GUEST_ERROR, - "%s: Unable to map address, addr=3D0x%x, " - "plen=3D0x%" HWADDR_PRIx "\n", + "%s: Unable to map address, addr=3D0x%" HWADDR_PRIx + " ,plen=3D0x%" HWADDR_PRIx "\n", __func__, src, plen); return -1; } @@ -175,11 +184,12 @@ static int hash_prepare_sg_iov(AspeedHACEState *s, st= ruct iovec *iov, uint32_t pad_offset; uint32_t len =3D 0; uint32_t sg_addr; - uint32_t src; + uint64_t src; int iov_idx; hwaddr plen; void *haddr; =20 + src =3D hash_get_source_addr(s); for (iov_idx =3D 0; !(len & SG_LIST_LEN_LAST); iov_idx++) { if (iov_idx =3D=3D ASPEED_HACE_MAX_SG) { qemu_log_mask(LOG_GUEST_ERROR, @@ -188,8 +198,6 @@ static int hash_prepare_sg_iov(AspeedHACEState *s, stru= ct iovec *iov, return -1; } =20 - src =3D s->regs[R_HASH_SRC] + (iov_idx * SG_LIST_ENTRY_SIZE); - len =3D address_space_ldl_le(&s->dram_as, src, MEMTXATTRS_UNSPECIFIED, NULL); sg_addr =3D address_space_ldl_le(&s->dram_as, src + SG_LIST_LEN_SI= ZE, @@ -208,6 +216,8 @@ static int hash_prepare_sg_iov(AspeedHACEState *s, stru= ct iovec *iov, return -1; } =20 + src +=3D SG_LIST_ENTRY_SIZE; + iov[iov_idx].iov_base =3D haddr; if (acc_mode) { s->total_req_len +=3D plen; --=20 2.43.0 From nobody Sat Nov 15 20:52:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 13 May 2025 14:29:04 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 13 May 2025 14:29:04 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v2 07/25] hw/misc/aspeed_hace: Rename R_HASH_DEST to R_HASH_DIGEST and introduce 64-bit hash digest address helper Date: Tue, 13 May 2025 14:28:37 +0800 Message-ID: <20250513062901.2256865-8-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> References: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1747117936229019000 Content-Type: text/plain; charset="utf-8" Renaming R_HASH_DEST to R_HASH_DIGEST for better semantic clarity. The AST2700 CPU, based on the Cortex-A35, features a 64-bit DRAM address sp= ace. To prepare for future AST2700 support, this change introduces a new helper function hash_get_digest_addr() to encapsulate digest address extraction lo= gic and improve code readability. Signed-off-by: Jamin Lin --- hw/misc/aspeed_hace.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index 5f3c8190ef..c5ddc1c99a 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -27,7 +27,7 @@ #define TAG_IRQ BIT(15) =20 #define R_HASH_SRC (0x20 / 4) -#define R_HASH_DEST (0x24 / 4) +#define R_HASH_DIGEST (0x24 / 4) #define R_HASH_KEY_BUFF (0x28 / 4) #define R_HASH_SRC_LEN (0x2c / 4) =20 @@ -238,17 +238,30 @@ static int hash_prepare_sg_iov(AspeedHACEState *s, st= ruct iovec *iov, return iov_idx; } =20 +static uint64_t hash_get_digest_addr(AspeedHACEState *s) +{ + uint64_t digest_addr =3D 0; + + digest_addr =3D deposit64(digest_addr, 0, 32, s->regs[R_HASH_DIGEST]); + + return digest_addr; +} + static void hash_write_digest_and_unmap_iov(AspeedHACEState *s, struct iovec *iov, int iov_idx, uint8_t *digest_buf, size_t digest_len) { - if (address_space_write(&s->dram_as, s->regs[R_HASH_DEST], - MEMTXATTRS_UNSPECIFIED, digest_buf, digest_len= )) { + uint64_t digest_addr =3D 0; + + digest_addr =3D hash_get_digest_addr(s); + if (address_space_write(&s->dram_as, digest_addr, + MEMTXATTRS_UNSPECIFIED, + digest_buf, digest_len)) { qemu_log_mask(LOG_GUEST_ERROR, - "%s: Failed to write digest to 0x%x\n", - __func__, s->regs[R_HASH_DEST]); + "%s: Failed to write digest to 0x%" HWADDR_PRIx "\n", + __func__, digest_addr); } =20 for (; iov_idx > 0; iov_idx--) { @@ -402,7 +415,7 @@ static void aspeed_hace_write(void *opaque, hwaddr addr= , uint64_t data, case R_HASH_SRC: data &=3D ahc->src_mask; break; - case R_HASH_DEST: + case R_HASH_DIGEST: data &=3D ahc->dest_mask; break; case R_HASH_KEY_BUFF: --=20 2.43.0 From nobody Sat Nov 15 20:52:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1747118031; cv=none; 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Tue, 13 May 2025 14:29:05 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v2 08/25] hw/misc/aspeed_hace: Support accumulative mode for direct access mode Date: Tue, 13 May 2025 14:28:38 +0800 Message-ID: <20250513062901.2256865-9-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> References: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1747118032673019000 Content-Type: text/plain; charset="utf-8" Enable accumulative mode for direct access mode operations. In direct access mode, only a single source buffer is used, so the "iovec" count is set to 1. If "acc_mode" is enabled: 1. Accumulate "total_req_len" with the current request length ("plen"). 2. Check for padding and determine whether this is the final request. Signed-off-by: Jamin Lin --- hw/misc/aspeed_hace.c | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index c5ddc1c99a..ef777bb594 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -151,8 +151,11 @@ static uint64_t hash_get_source_addr(AspeedHACEState *= s) return src_addr; } =20 -static int hash_prepare_direct_iov(AspeedHACEState *s, struct iovec *iov) +static int hash_prepare_direct_iov(AspeedHACEState *s, struct iovec *iov, + bool acc_mode, bool *acc_final_request) { + uint32_t total_msg_len; + uint32_t pad_offset; uint64_t src; void *haddr; hwaddr plen; @@ -171,9 +174,23 @@ static int hash_prepare_direct_iov(AspeedHACEState *s,= struct iovec *iov) } =20 iov[0].iov_base =3D haddr; - iov[0].iov_len =3D plen; iov_idx =3D 1; =20 + if (acc_mode) { + s->total_req_len +=3D plen; + + if (has_padding(s, &iov[0], plen, &total_msg_len, + &pad_offset)) { + /* Padding being present indicates the final request */ + *acc_final_request =3D true; + iov[0].iov_len =3D pad_offset; + } else { + iov[0].iov_len =3D plen; + } + } else { + iov[0].iov_len =3D plen; + } + return iov_idx; } =20 @@ -345,7 +362,8 @@ static void do_hash_operation(AspeedHACEState *s, int a= lgo, bool sg_mode, if (sg_mode) { iov_idx =3D hash_prepare_sg_iov(s, iov, acc_mode, &acc_final_reque= st); } else { - iov_idx =3D hash_prepare_direct_iov(s, iov); + iov_idx =3D hash_prepare_direct_iov(s, iov, acc_mode, + &acc_final_request); } =20 if (iov_idx <=3D 0) { --=20 2.43.0 From nobody Sat Nov 15 20:52:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1747118031; cv=none; d=zohomail.com; s=zohoarc; b=b//mBfm3e+UUlJjgYXZQmJfrxBMSmwmT/azCjgZs8Pt0qYALZYTzm/AwdEcoj3QKx2QufJLZU2XSouIrx2kyCF4Rsym5XC0DYK+zR8uf/Cqpqa6FYSKHCBh410FZvS4rzoOf7yZehykjqQxCSKx6NTouLVnhW1OZEfG/0DSCPm8= ARC-Message-Signature: i=1; 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Tue, 13 May 2025 02:33:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEjAR-00053K-2v; Tue, 13 May 2025 02:31:10 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEjAL-000252-Bl; Tue, 13 May 2025 02:31:03 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 13 May 2025 14:29:05 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 13 May 2025 14:29:05 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v2 09/25] hw/misc/aspeed_hace: Move register size to instance class and dynamically allocate regs Date: Tue, 13 May 2025 14:28:39 +0800 Message-ID: <20250513062901.2256865-10-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> References: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1747118032754019000 Content-Type: text/plain; charset="utf-8" Dynamically allocate the register array by removing the hardcoded ASPEED_HACE_NR_REGS macro. To support different register sizes across SoC variants, introduce a new "nr_regs" class attribute and replace the static "regs" array with dynamica= lly allocated memory. Add a new "aspeed_hace_unrealize" function to properly free the allocated "= regs" memory during device cleanup. Remove the bounds checking in the MMIO read/write handlers since the MemoryRegion size now matches the (register array size << 2). This commit updates the VMState fields accordingly. The VMState version was already bumped in a previous patch of this series, so no further version ch= ange is needed. Signed-off-by: Jamin Lin --- include/hw/misc/aspeed_hace.h | 5 +++-- hw/misc/aspeed_hace.c | 36 ++++++++++++++++++----------------- 2 files changed, 22 insertions(+), 19 deletions(-) diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h index b69a038d35..f30d606559 100644 --- a/include/hw/misc/aspeed_hace.h +++ b/include/hw/misc/aspeed_hace.h @@ -22,7 +22,6 @@ =20 OBJECT_DECLARE_TYPE(AspeedHACEState, AspeedHACEClass, ASPEED_HACE) =20 -#define ASPEED_HACE_NR_REGS (0x64 >> 2) #define ASPEED_HACE_MAX_SG 256 /* max number of entries */ =20 struct AspeedHACEState { @@ -31,7 +30,7 @@ struct AspeedHACEState { MemoryRegion iomem; qemu_irq irq; =20 - uint32_t regs[ASPEED_HACE_NR_REGS]; + uint32_t *regs; uint32_t total_req_len; =20 MemoryRegion *dram_mr; @@ -44,10 +43,12 @@ struct AspeedHACEState { struct AspeedHACEClass { SysBusDeviceClass parent_class; =20 + const MemoryRegionOps *reg_ops; uint32_t src_mask; uint32_t dest_mask; uint32_t key_mask; uint32_t hash_mask; + uint64_t nr_regs; bool raise_crypt_interrupt_workaround; }; =20 diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index ef777bb594..63404a76f7 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -386,13 +386,6 @@ static uint64_t aspeed_hace_read(void *opaque, hwaddr = addr, unsigned int size) =20 addr >>=3D 2; =20 - if (addr >=3D ASPEED_HACE_NR_REGS) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "= \n", - __func__, addr << 2); - return 0; - } - return s->regs[addr]; } =20 @@ -404,13 +397,6 @@ static void aspeed_hace_write(void *opaque, hwaddr add= r, uint64_t data, =20 addr >>=3D 2; =20 - if (addr >=3D ASPEED_HACE_NR_REGS) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx = "\n", - __func__, addr << 2); - return; - } - switch (addr) { case R_STATUS: if (data & HASH_IRQ) { @@ -507,13 +493,14 @@ static const MemoryRegionOps aspeed_hace_ops =3D { static void aspeed_hace_reset(DeviceState *dev) { struct AspeedHACEState *s =3D ASPEED_HACE(dev); + AspeedHACEClass *ahc =3D ASPEED_HACE_GET_CLASS(s); =20 if (s->hash_ctx !=3D NULL) { qcrypto_hash_free(s->hash_ctx); s->hash_ctx =3D NULL; } =20 - memset(s->regs, 0, sizeof(s->regs)); + memset(s->regs, 0, ahc->nr_regs << 2); s->total_req_len =3D 0; } =20 @@ -521,11 +508,13 @@ static void aspeed_hace_realize(DeviceState *dev, Err= or **errp) { AspeedHACEState *s =3D ASPEED_HACE(dev); SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + AspeedHACEClass *ahc =3D ASPEED_HACE_GET_CLASS(s); =20 sysbus_init_irq(sbd, &s->irq); =20 + s->regs =3D g_new(uint32_t, ahc->nr_regs); memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_hace_ops, s, - TYPE_ASPEED_HACE, 0x1000); + TYPE_ASPEED_HACE, ahc->nr_regs << 2); =20 if (!s->dram_mr) { error_setg(errp, TYPE_ASPEED_HACE ": 'dram' link not set"); @@ -548,17 +537,25 @@ static const VMStateDescription vmstate_aspeed_hace = =3D { .version_id =3D 2, .minimum_version_id =3D 2, .fields =3D (const VMStateField[]) { - VMSTATE_UINT32_ARRAY(regs, AspeedHACEState, ASPEED_HACE_NR_REGS), VMSTATE_UINT32(total_req_len, AspeedHACEState), VMSTATE_END_OF_LIST(), } }; =20 +static void aspeed_hace_unrealize(DeviceState *dev) +{ + AspeedHACEState *s =3D ASPEED_HACE(dev); + + g_free(s->regs); + s->regs =3D NULL; +} + static void aspeed_hace_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->realize =3D aspeed_hace_realize; + dc->unrealize =3D aspeed_hace_unrealize; device_class_set_legacy_reset(dc, aspeed_hace_reset); device_class_set_props(dc, aspeed_hace_properties); dc->vmsd =3D &vmstate_aspeed_hace; @@ -579,6 +576,7 @@ static void aspeed_ast2400_hace_class_init(ObjectClass = *klass, const void *data) =20 dc->desc =3D "AST2400 Hash and Crypto Engine"; =20 + ahc->nr_regs =3D 0x64 >> 2; ahc->src_mask =3D 0x0FFFFFFF; ahc->dest_mask =3D 0x0FFFFFF8; ahc->key_mask =3D 0x0FFFFFC0; @@ -598,6 +596,7 @@ static void aspeed_ast2500_hace_class_init(ObjectClass = *klass, const void *data) =20 dc->desc =3D "AST2500 Hash and Crypto Engine"; =20 + ahc->nr_regs =3D 0x64 >> 2; ahc->src_mask =3D 0x3fffffff; ahc->dest_mask =3D 0x3ffffff8; ahc->key_mask =3D 0x3FFFFFC0; @@ -617,6 +616,7 @@ static void aspeed_ast2600_hace_class_init(ObjectClass = *klass, const void *data) =20 dc->desc =3D "AST2600 Hash and Crypto Engine"; =20 + ahc->nr_regs =3D 0x64 >> 2; ahc->src_mask =3D 0x7FFFFFFF; ahc->dest_mask =3D 0x7FFFFFF8; ahc->key_mask =3D 0x7FFFFFF8; @@ -636,6 +636,7 @@ static void aspeed_ast1030_hace_class_init(ObjectClass = *klass, const void *data) =20 dc->desc =3D "AST1030 Hash and Crypto Engine"; =20 + ahc->nr_regs =3D 0x64 >> 2; ahc->src_mask =3D 0x7FFFFFFF; ahc->dest_mask =3D 0x7FFFFFF8; ahc->key_mask =3D 0x7FFFFFF8; @@ -655,6 +656,7 @@ static void aspeed_ast2700_hace_class_init(ObjectClass = *klass, const void *data) =20 dc->desc =3D "AST2700 Hash and Crypto Engine"; =20 + ahc->nr_regs =3D 0x64 >> 2; ahc->src_mask =3D 0x7FFFFFFF; ahc->dest_mask =3D 0x7FFFFFF8; ahc->key_mask =3D 0x7FFFFFF8; --=20 2.43.0 From nobody Sat Nov 15 20:52:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747118198808545.207926928694; Mon, 12 May 2025 23:36:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uEjCR-0006TJ-Us; Tue, 13 May 2025 02:33:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEjAW-00057w-EH; Tue, 13 May 2025 02:31:16 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEjAU-00026a-AK; Tue, 13 May 2025 02:31:12 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 13 May 2025 14:29:05 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 13 May 2025 14:29:05 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v2 10/25] hw/misc/aspeed_hace: Add support for source, digest, key buffer 64 bit addresses Date: Tue, 13 May 2025 14:28:40 +0800 Message-ID: <20250513062901.2256865-11-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> References: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1747118200780019000 Content-Type: text/plain; charset="utf-8" According to the AST2700 design, the data source address is 64-bit, with R_HASH_SRC_HI storing bits [63:32] and R_HASH_SRC storing bits [31:0]. Similarly, the digest address is 64-bit, with R_HASH_DIGEST_HI storing bits [63:32] and R_HASH_DIGEST storing bits [31:0]. The HMAC key buffer address = is also 64-bit, with R_HASH_KEY_BUFF_HI storing bits [63:32] and R_HASH_KEY_BUFF st= oring bits [31:0]. The AST2700 supports a maximum DRAM size of 8 GB, with a DRAM addressable r= ange from 0x0_0000_0000 to 0x1_FFFF_FFFF. Since this range fits within 34 bits, = only bits [33:0] are needed to store the DRAM offset. To optimize address storag= e, the high physical address bits [1:0] of the source, digest and key buffer addresses are stored as dram_offset bits [33:32]. To achieve this, a src_hi_mask with a mask value of 0x3 is introduced, ensu= ring that src_addr_hi consists of bits [1:0]. The final src_addr is computed as (src_addr_hi[1:0] << 32) | src_addr[31:0], representing the DRAM offset wit= hin bits [33:0]. Similarly, a dest_hi_mask with a mask value of 0x3 is introduced to ensure = that dest_addr_hi consists of bits [1:0]. The final dest_addr is calculated as (dest_addr_hi[1:0] << 32) | dest_addr[31:0], representing the DRAM offset w= ithin bits [33:0]. Additionally, a key_hi_mask with a mask value of 0x3 is introduced to ensure that key_buf_addr_hi consists of bits [1:0]. The final key_buf_addr is determined as (key_buf_addr_hi[1:0] << 32) | key_buf_addr[31:0], representi= ng the DRAM offset within bits [33:0]. This approach eliminates the need to reduce the high part of the DRAM physi= cal address for DMA operations. Previously, this was calculated as (high physical address bits [7:0] - 4), since the DRAM start address is 0x4_00000000, making the high part address [7:0] - 4. Signed-off-by: Jamin Lin --- include/hw/misc/aspeed_hace.h | 3 +++ hw/misc/aspeed_hace.c | 31 ++++++++++++++++++++++++++++++- 2 files changed, 33 insertions(+), 1 deletion(-) diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h index f30d606559..9945b61863 100644 --- a/include/hw/misc/aspeed_hace.h +++ b/include/hw/misc/aspeed_hace.h @@ -50,6 +50,9 @@ struct AspeedHACEClass { uint32_t hash_mask; uint64_t nr_regs; bool raise_crypt_interrupt_workaround; + uint32_t src_hi_mask; + uint32_t dest_hi_mask; + uint32_t key_hi_mask; }; =20 #endif /* ASPEED_HACE_H */ diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index 63404a76f7..0fd8a167a2 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -30,6 +30,9 @@ #define R_HASH_DIGEST (0x24 / 4) #define R_HASH_KEY_BUFF (0x28 / 4) #define R_HASH_SRC_LEN (0x2c / 4) +#define R_HASH_SRC_HI (0x90 / 4) +#define R_HASH_DIGEST_HI (0x94 / 4) +#define R_HASH_KEY_BUFF_HI (0x98 / 4) =20 #define R_HASH_CMD (0x30 / 4) /* Hash algorithm selection */ @@ -473,6 +476,15 @@ static void aspeed_hace_write(void *opaque, hwaddr add= r, uint64_t data, } } break; + case R_HASH_SRC_HI: + data &=3D ahc->src_hi_mask; + break; + case R_HASH_DIGEST_HI: + data &=3D ahc->dest_hi_mask; + break; + case R_HASH_KEY_BUFF_HI: + data &=3D ahc->key_hi_mask; + break; default: break; } @@ -656,12 +668,29 @@ static void aspeed_ast2700_hace_class_init(ObjectClas= s *klass, const void *data) =20 dc->desc =3D "AST2700 Hash and Crypto Engine"; =20 - ahc->nr_regs =3D 0x64 >> 2; + ahc->nr_regs =3D 0x9C >> 2; ahc->src_mask =3D 0x7FFFFFFF; ahc->dest_mask =3D 0x7FFFFFF8; ahc->key_mask =3D 0x7FFFFFF8; ahc->hash_mask =3D 0x00147FFF; =20 + /* + * The AST2700 supports a maximum DRAM size of 8 GB, with a DRAM + * addressable range from 0x0_0000_0000 to 0x1_FFFF_FFFF. Since this r= ange + * fits within 34 bits, only bits [33:0] are needed to store the DRAM + * offset. To optimize address storage, the high physical address bits + * [1:0] of the source, digest and key buffer addresses are stored as + * dram_offset bits [33:32]. + * + * This approach eliminates the need to reduce the high part of the DR= AM + * physical address for DMA operations. Previously, this was calculate= d as + * (high physical address bits [7:0] - 4), since the DRAM start addres= s is + * 0x4_00000000, making the high part address [7:0] - 4. + */ + ahc->src_hi_mask =3D 0x00000003; + ahc->dest_hi_mask =3D 0x00000003; + ahc->key_hi_mask =3D 0x00000003; + /* * Currently, it does not support the CRYPT command. Instead, it only * sends an interrupt to notify the firmware that the crypt command --=20 2.43.0 From nobody Sat Nov 15 20:52:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1747118103; cv=none; d=zohomail.com; s=zohoarc; b=QqsM2Tx0ruAfkfLsjOX+yB9SwHk7niGcC4tiOuXYLcaPTAA+c3Ly0itjYlAgYIxE4JsYskaQWaANvMiVSMery45n5vO6qWIU6px56yZcQoyIBunjgbYs+O30nKk3EheoKw2HED5l9jrMHXV+CPxuiwPgZe+DHPSFgbTmySKxIcg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747118103; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=eJFyrCNoeuEvfrsU/RDm6+Tez1El8zxSnycihYdMiow=; b=AMc4N+glAh2fLe8lH13chueBsnm0+Yp7luqRpu5UXqdecAH7CfqFC8Rd3yEgRhr16zBelgzKrIcg12LSKMqfRKQnjscB1pkCfUATB6numehxuNUb7o48Q4TZ4qLUF2x7yaFxbFfsLp9xF8UQ+sn1JN02SQfdhKibnHzfjEcKazU= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174711810393844.360402141088; Mon, 12 May 2025 23:35:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uEjDl-0000Zo-Sx; Tue, 13 May 2025 02:34:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEjAa-00059v-2e; Tue, 13 May 2025 02:31:22 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEjAX-00026a-FY; Tue, 13 May 2025 02:31:15 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 13 May 2025 14:29:06 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 13 May 2025 14:29:06 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v2 11/25] hw/misc/aspeed_hace: Support DMA 64 bits dram address Date: Tue, 13 May 2025 14:28:41 +0800 Message-ID: <20250513062901.2256865-12-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> References: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1747118104377116600 Content-Type: text/plain; charset="utf-8" According to the AST2700 design, the data source address is 64-bit, with R_HASH_SRC_HI storing bits [63:32] and R_HASH_SRC storing bits [31:0]. Similarly, the digest address is 64-bit, with R_HASH_DEST_HI storing bits [63:32] and R_HASH_DEST storing bits [31:0]. To maintain compatibility with older SoCs such as the AST2600, the AST2700 = HW automatically set bit 34 of the 64-bit sg_addr. As a result, the firmware only needs to provide a 32-bit sg_addr containing bits [31:0]. This is sufficient for the AST2700, as it uses a DRAM offset rather than a DRAM address. Introduce a has_dma64 class attribute and set it to true for the AST2700. Signed-off-by: Jamin Lin --- include/hw/misc/aspeed_hace.h | 1 + hw/misc/aspeed_hace.c | 17 ++++++++++++++++- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h index 9945b61863..d5d07c6c02 100644 --- a/include/hw/misc/aspeed_hace.h +++ b/include/hw/misc/aspeed_hace.h @@ -53,6 +53,7 @@ struct AspeedHACEClass { uint32_t src_hi_mask; uint32_t dest_hi_mask; uint32_t key_hi_mask; + bool has_dma64; }; =20 #endif /* ASPEED_HACE_H */ diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index 0fd8a167a2..5454f51aa6 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -147,9 +147,13 @@ static bool has_padding(AspeedHACEState *s, struct iov= ec *iov, =20 static uint64_t hash_get_source_addr(AspeedHACEState *s) { + AspeedHACEClass *ahc =3D ASPEED_HACE_GET_CLASS(s); uint64_t src_addr =3D 0; =20 src_addr =3D deposit64(src_addr, 0, 32, s->regs[R_HASH_SRC]); + if (ahc->has_dma64) { + src_addr =3D deposit64(src_addr, 32, 32, s->regs[R_HASH_SRC_HI]); + } =20 return src_addr; } @@ -223,7 +227,13 @@ static int hash_prepare_sg_iov(AspeedHACEState *s, str= uct iovec *iov, sg_addr =3D address_space_ldl_le(&s->dram_as, src + SG_LIST_LEN_SI= ZE, MEMTXATTRS_UNSPECIFIED, NULL); sg_addr &=3D SG_LIST_ADDR_MASK; - + /* + * To maintain compatibility with older SoCs such as the AST2600, + * the AST2700 HW automatically set bit 34 of the 64-bit sg_addr. + * As a result, the firmware only needs to provide a 32-bit sg_addr + * containing bits [31:0]. This is sufficient for the AST2700, as + * it uses a DRAM offset rather than a DRAM address. + */ plen =3D len & SG_LIST_LEN_MASK; haddr =3D address_space_map(&s->dram_as, sg_addr, &plen, false, MEMTXATTRS_UNSPECIFIED); @@ -260,9 +270,13 @@ static int hash_prepare_sg_iov(AspeedHACEState *s, str= uct iovec *iov, =20 static uint64_t hash_get_digest_addr(AspeedHACEState *s) { + AspeedHACEClass *ahc =3D ASPEED_HACE_GET_CLASS(s); uint64_t digest_addr =3D 0; =20 digest_addr =3D deposit64(digest_addr, 0, 32, s->regs[R_HASH_DIGEST]); + if (ahc->has_dma64) { + digest_addr =3D deposit64(digest_addr, 32, 32, s->regs[R_HASH_DIGE= ST_HI]); + } =20 return digest_addr; } @@ -697,6 +711,7 @@ static void aspeed_ast2700_hace_class_init(ObjectClass = *klass, const void *data) * has completed. It is a temporary workaround. */ ahc->raise_crypt_interrupt_workaround =3D true; + ahc->has_dma64 =3D true; } =20 static const TypeInfo aspeed_ast2700_hace_info =3D { --=20 2.43.0 From nobody Sat Nov 15 20:52:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1747118103; cv=none; d=zohomail.com; s=zohoarc; b=SllILYTVMLS/Bd+4Fw0O+do2ofIqqQOea/8lSa/uAbIut79J3hOWVKXY9JSOR93/400QWrbFTHSY862+KFkEOdUSwStl4kbniqMO9YNz99oGFC4N9+VERW9wDlZ0EVcpa+ysBpguuDTlb2+ipxUS43938yYaPQyxp4ZNihK15I8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747118103; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=waKNQ7ICAWhVDlBDI6d9nYBltdk2/ze4UI9TF2xNq7k=; b=YeaAv7uuJWcB353MdxXeK6ZY0w8tZJl4xHQ7X/cm5GDyljKCaVLtUPhOIfM9+7Nt6Ka3C2qKSLSa1+ReZ6FKhWn3ODK2HIZ04b1UGWAUinZULPGeZiTj+5xLM3GwgBy6AVrTt+vJvXLRAV7vs1ffdPV4Ugje9i4dscu3NNJlxOk= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747118103573684.4211535544493; Mon, 12 May 2025 23:35:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uEjCW-0006kW-Fw; Tue, 13 May 2025 02:33:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEjAe-0005Fn-0F; Tue, 13 May 2025 02:31:23 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEjAb-00026a-73; Tue, 13 May 2025 02:31:18 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 13 May 2025 14:29:06 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 13 May 2025 14:29:06 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v2 12/25] hw/misc/aspeed_hace: Add trace-events for better debugging Date: Tue, 13 May 2025 14:28:42 +0800 Message-ID: <20250513062901.2256865-13-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> References: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1747118104393116600 Content-Type: text/plain; charset="utf-8" Introduced "trace_aspeed_hace_hash_addr", "trace_aspeed_hace_hash_sg", "trace_aspeed_hace_read", "trace_aspeed_hace_hash_execute_acc_mode", and "trace_aspeed_hace_write" trace events. Signed-off-by: Jamin Lin --- hw/misc/aspeed_hace.c | 11 +++++++++++ hw/misc/trace-events | 7 +++++++ 2 files changed, 18 insertions(+) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index 5454f51aa6..1ffec029dc 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -18,6 +18,7 @@ #include "crypto/hash.h" #include "hw/qdev-properties.h" #include "hw/irq.h" +#include "trace.h" =20 #define R_CRYPT_CMD (0x10 / 4) =20 @@ -170,6 +171,7 @@ static int hash_prepare_direct_iov(AspeedHACEState *s, = struct iovec *iov, =20 plen =3D s->regs[R_HASH_SRC_LEN]; src =3D hash_get_source_addr(s); + trace_aspeed_hace_hash_addr("src", src); haddr =3D address_space_map(&s->dram_as, src, &plen, false, MEMTXATTRS_UNSPECIFIED); if (haddr =3D=3D NULL) { @@ -214,6 +216,7 @@ static int hash_prepare_sg_iov(AspeedHACEState *s, stru= ct iovec *iov, void *haddr; =20 src =3D hash_get_source_addr(s); + trace_aspeed_hace_hash_addr("src", src); for (iov_idx =3D 0; !(len & SG_LIST_LEN_LAST); iov_idx++) { if (iov_idx =3D=3D ASPEED_HACE_MAX_SG) { qemu_log_mask(LOG_GUEST_ERROR, @@ -227,6 +230,7 @@ static int hash_prepare_sg_iov(AspeedHACEState *s, stru= ct iovec *iov, sg_addr =3D address_space_ldl_le(&s->dram_as, src + SG_LIST_LEN_SI= ZE, MEMTXATTRS_UNSPECIFIED, NULL); sg_addr &=3D SG_LIST_ADDR_MASK; + trace_aspeed_hace_hash_sg(iov_idx, sg_addr, len); /* * To maintain compatibility with older SoCs such as the AST2600, * the AST2700 HW automatically set bit 34 of the 64-bit sg_addr. @@ -290,6 +294,7 @@ static void hash_write_digest_and_unmap_iov(AspeedHACES= tate *s, uint64_t digest_addr =3D 0; =20 digest_addr =3D hash_get_digest_addr(s); + trace_aspeed_hace_hash_addr("digest", digest_addr); if (address_space_write(&s->dram_as, digest_addr, MEMTXATTRS_UNSPECIFIED, digest_buf, digest_len)) { @@ -332,6 +337,8 @@ static void hash_execute_acc_mode(AspeedHACEState *s, i= nt algo, Error *local_err =3D NULL; size_t digest_len; =20 + trace_aspeed_hace_hash_execute_acc_mode(final_request); + if (s->hash_ctx =3D=3D NULL) { s->hash_ctx =3D qcrypto_hash_new(algo, &local_err); if (s->hash_ctx =3D=3D NULL) { @@ -403,6 +410,8 @@ static uint64_t aspeed_hace_read(void *opaque, hwaddr a= ddr, unsigned int size) =20 addr >>=3D 2; =20 + trace_aspeed_hace_read(addr << 2, s->regs[addr]); + return s->regs[addr]; } =20 @@ -414,6 +423,8 @@ static void aspeed_hace_write(void *opaque, hwaddr addr= , uint64_t data, =20 addr >>=3D 2; =20 + trace_aspeed_hace_write(addr << 2, data); + switch (addr) { case R_STATUS: if (data & HASH_IRQ) { diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 4383808d7a..b2587c37d7 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -302,6 +302,13 @@ aspeed_peci_read(uint64_t offset, uint64_t data) "offs= et 0x%" PRIx64 " data 0x%" aspeed_peci_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " da= ta 0x%" PRIx64 aspeed_peci_raise_interrupt(uint32_t ctrl, uint32_t status) "ctrl 0x%" PRI= x32 " status 0x%" PRIx32 =20 +# aspeed_hace.c +aspeed_hace_read(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " dat= a 0x%" PRIx64 +aspeed_hace_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " da= ta 0x%" PRIx64 +aspeed_hace_hash_sg(int index, uint64_t addr, uint32_t len) "%d: addr 0x%"= PRIx64 " len 0x%" PRIx32 +aspeed_hace_hash_addr(const char *s, uint64_t addr) "%s: 0x%" PRIx64 +aspeed_hace_hash_execute_acc_mode(bool final_request) "final request: %d" + # bcm2835_property.c bcm2835_mbox_property(uint32_t tag, uint32_t bufsize, size_t resplen) "mbo= x property tag:0x%08x in_sz:%u out_sz:%zu" =20 --=20 2.43.0 From nobody Sat Nov 15 20:52:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1747118160749019000 Content-Type: text/plain; charset="utf-8" 1. Added "hace_hexdump()" to dump a contiguous buffer using qemu_hexdump. 2. Added "hace_iov_hexdump()" to flatten and dump scatter-gather source vec= tors. 3. Introduced a new trace event: "aspeed_hace_hexdump". Signed-off-by: Jamin Lin --- hw/misc/aspeed_hace.c | 46 +++++++++++++++++++++++++++++++++++++++++++ hw/misc/trace-events | 1 + 2 files changed, 47 insertions(+) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index 1ffec029dc..50607d2cfa 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -10,8 +10,10 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/cutils.h" #include "qemu/log.h" #include "qemu/error-report.h" +#include "qemu/iov.h" #include "hw/misc/aspeed_hace.h" #include "qapi/error.h" #include "migration/vmstate.h" @@ -88,6 +90,42 @@ static const struct { QCRYPTO_HASH_ALGO_SHA256 }, }; =20 +static void hace_hexdump(const char *desc, const char *buf, size_t size) +{ + g_autoptr(GString) str =3D g_string_sized_new(64); + size_t len; + size_t i; + + for (i =3D 0; i < size; i +=3D len) { + len =3D MIN(16, size - i); + g_string_truncate(str, 0); + qemu_hexdump_line(str, buf + i, len, 1, 4); + trace_aspeed_hace_hexdump(desc, i, str->str); + } +} + +static void hace_iov_hexdump(const char *desc, const struct iovec *iov, + const unsigned int iov_cnt) +{ + size_t size =3D 0; + char *buf; + int i; + + for (i =3D 0; i < iov_cnt; i++) { + size +=3D iov[i].iov_len; + } + + buf =3D g_malloc(size); + + if (!buf) { + return; + } + + iov_to_buf(iov, iov_cnt, 0, buf, size); + hace_hexdump(desc, buf, size); + g_free(buf); +} + static int hash_algo_lookup(uint32_t reg) { int i; @@ -303,6 +341,10 @@ static void hash_write_digest_and_unmap_iov(AspeedHACE= State *s, __func__, digest_addr); } =20 + if (trace_event_get_state_backends(TRACE_ASPEED_HACE_HEXDUMP)) { + hace_hexdump("digest", (char *)digest_buf, digest_len); + } + for (; iov_idx > 0; iov_idx--) { address_space_unmap(&s->dram_as, iov[iov_idx - 1].iov_base, iov[iov_idx - 1].iov_len, false, @@ -396,6 +438,10 @@ static void do_hash_operation(AspeedHACEState *s, int = algo, bool sg_mode, return; } =20 + if (trace_event_get_state_backends(TRACE_ASPEED_HACE_HEXDUMP)) { + hace_iov_hexdump("plaintext", iov, iov_idx); + } + /* Executes the hash operation */ if (acc_mode) { hash_execute_acc_mode(s, algo, iov, iov_idx, acc_final_request); diff --git a/hw/misc/trace-events b/hw/misc/trace-events index b2587c37d7..70ca1bd85d 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -308,6 +308,7 @@ aspeed_hace_write(uint64_t offset, uint64_t data) "offs= et 0x%" PRIx64 " data 0x% aspeed_hace_hash_sg(int index, uint64_t addr, uint32_t len) "%d: addr 0x%"= PRIx64 " len 0x%" PRIx32 aspeed_hace_hash_addr(const char *s, uint64_t addr) "%s: 0x%" PRIx64 aspeed_hace_hash_execute_acc_mode(bool final_request) "final request: %d" +aspeed_hace_hexdump(const char *desc, uint32_t offset, char *s) "%s: 0x%08= x: %s" =20 # bcm2835_property.c bcm2835_mbox_property(uint32_t tag, uint32_t bufsize, size_t resplen) "mbo= x property tag:0x%08x in_sz:%u out_sz:%zu" --=20 2.43.0 From nobody Sat Nov 15 20:52:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tue, 13 May 2025 14:29:07 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 13 May 2025 14:29:07 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v2 14/25] tests/qtest: Reorder aspeed test list Date: Tue, 13 May 2025 14:28:44 +0800 Message-ID: <20250513062901.2256865-15-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> References: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1747118060253116600 Content-Type: text/plain; charset="utf-8" Reordered the aspeed test list to keep the alphabetical order. No functional changes in test behavior. Signed-off-by: Jamin Lin --- tests/qtest/meson.build | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 3136d15e0f..6b5161a643 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -211,9 +211,9 @@ qtests_npcm7xx =3D \ 'npcm_gmac-test'] + \ (slirp.found() ? ['npcm7xx_emc-test'] : []) qtests_aspeed =3D \ - ['aspeed_hace-test', - 'aspeed_smc-test', - 'aspeed_gpio-test'] + ['aspeed_gpio-test', + 'aspeed_hace-test', + 'aspeed_smc-test'] qtests_aspeed64 =3D \ ['ast2700-gpio-test', 'ast2700-smc-test'] @@ -360,6 +360,8 @@ if gnutls.found() endif =20 qtests =3D { + 'aspeed_smc-test': files('aspeed-smc-utils.c', 'aspeed_smc-test.c'), + 'ast2700-smc-test': files('aspeed-smc-utils.c', 'ast2700-smc-test.c'), 'bios-tables-test': [io, 'boot-sector.c', 'acpi-utils.c', 'tpm-emu.c'], 'cdrom-test': files('boot-sector.c'), 'dbus-vmstate-test': files('migration/migration-qmp.c', @@ -381,8 +383,6 @@ qtests =3D { 'virtio-net-failover': migration_files, 'vmgenid-test': files('boot-sector.c', 'acpi-utils.c'), 'netdev-socket': files('netdev-socket.c', '../unit/socket-helpers.c'), - 'aspeed_smc-test': files('aspeed-smc-utils.c', 'aspeed_smc-test.c'), - 'ast2700-smc-test': files('aspeed-smc-utils.c', 'ast2700-smc-test.c'), } =20 if vnc.found() --=20 2.43.0 From nobody Sat Nov 15 20:52:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 13 May 2025 14:29:07 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 13 May 2025 14:29:07 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v2 15/25] test/qtest: Introduce a new aspeed-hace-utils.c to place common testcases Date: Tue, 13 May 2025 14:28:45 +0800 Message-ID: <20250513062901.2256865-16-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> References: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1747118193342116600 The test cases for the ASPEED HACE model were originally placed in aspeed_hace-test.c. However, this test file only supports ARM32. To enable compatibility with all ASPEED SoCs, including the AST2700, which uses the AArch64 architecture, this update introduces a new source file, aspeed-hace-utils.c. All common APIs and test cases have been moved from aspeed_hace-test.c to aspeed-hace-utils.c to facilitate reuse across different ASPEED SoCs. As a result, these test cases can now be reused for AST2700 and future ASPE= ED SoC testing. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- tests/qtest/aspeed-hace-utils.h | 71 +++++ tests/qtest/aspeed-hace-utils.c | 455 ++++++++++++++++++++++++++++ tests/qtest/aspeed_hace-test.c | 515 ++------------------------------ tests/qtest/meson.build | 1 + 4 files changed, 547 insertions(+), 495 deletions(-) create mode 100644 tests/qtest/aspeed-hace-utils.h create mode 100644 tests/qtest/aspeed-hace-utils.c diff --git a/tests/qtest/aspeed-hace-utils.h b/tests/qtest/aspeed-hace-util= s.h new file mode 100644 index 0000000000..598577c69b --- /dev/null +++ b/tests/qtest/aspeed-hace-utils.h @@ -0,0 +1,71 @@ +/* + * QTest testcase for the ASPEED Hash and Crypto Engine + * + * SPDX-License-Identifier: GPL-2.0-or-later + * Copyright 2021 IBM Corp. + */ + +#ifndef TESTS_ASPEED_HACE_UTILS_H +#define TESTS_ASPEED_HACE_UTILS_H + +#include "qemu/osdep.h" +#include "libqtest.h" +#include "qemu/bitops.h" + +#define HACE_CMD 0x10 +#define HACE_SHA_BE_EN BIT(3) +#define HACE_MD5_LE_EN BIT(2) +#define HACE_ALGO_MD5 0 +#define HACE_ALGO_SHA1 BIT(5) +#define HACE_ALGO_SHA224 BIT(6) +#define HACE_ALGO_SHA256 (BIT(4) | BIT(6)) +#define HACE_ALGO_SHA512 (BIT(5) | BIT(6)) +#define HACE_ALGO_SHA384 (BIT(5) | BIT(6) | BIT(10)) +#define HACE_SG_EN BIT(18) +#define HACE_ACCUM_EN BIT(8) + +#define HACE_STS 0x1c +#define HACE_RSA_ISR BIT(13) +#define HACE_CRYPTO_ISR BIT(12) +#define HACE_HASH_ISR BIT(9) +#define HACE_RSA_BUSY BIT(2) +#define HACE_CRYPTO_BUSY BIT(1) +#define HACE_HASH_BUSY BIT(0) +#define HACE_HASH_SRC 0x20 +#define HACE_HASH_DIGEST 0x24 +#define HACE_HASH_KEY_BUFF 0x28 +#define HACE_HASH_DATA_LEN 0x2c +#define HACE_HASH_CMD 0x30 + +/* Scatter-Gather Hash */ +#define SG_LIST_LEN_LAST BIT(31) +struct AspeedSgList { + uint32_t len; + uint32_t addr; +} __attribute__ ((__packed__)); + +struct AspeedMasks { + uint32_t src; + uint32_t dest; + uint32_t len; +}; + +void aspeed_test_md5(const char *machine, const uint32_t base, + const uint32_t src_addr); +void aspeed_test_sha256(const char *machine, const uint32_t base, + const uint32_t src_addr); +void aspeed_test_sha512(const char *machine, const uint32_t base, + const uint32_t src_addr); +void aspeed_test_sha256_sg(const char *machine, const uint32_t base, + const uint32_t src_addr); +void aspeed_test_sha512_sg(const char *machine, const uint32_t base, + const uint32_t src_addr); +void aspeed_test_sha256_accum(const char *machine, const uint32_t base, + const uint32_t src_addr); +void aspeed_test_sha512_accum(const char *machine, const uint32_t base, + const uint32_t src_addr); +void aspeed_test_addresses(const char *machine, const uint32_t base, + const struct AspeedMasks *expected); + +#endif /* TESTS_ASPEED_HACE_UTILS_H */ + diff --git a/tests/qtest/aspeed-hace-utils.c b/tests/qtest/aspeed-hace-util= s.c new file mode 100644 index 0000000000..8582847945 --- /dev/null +++ b/tests/qtest/aspeed-hace-utils.c @@ -0,0 +1,455 @@ +/* + * QTest testcase for the ASPEED Hash and Crypto Engine + * + * SPDX-License-Identifier: GPL-2.0-or-later + * Copyright 2021 IBM Corp. + */ + +#include "qemu/osdep.h" +#include "libqtest.h" +#include "qemu/bitops.h" +#include "aspeed-hace-utils.h" + +/* + * Test vector is the ascii "abc" + * + * Expected results were generated using command line utitiles: + * + * echo -n -e 'abc' | dd of=3D/tmp/test + * for hash in sha512sum sha256sum md5sum; do $hash /tmp/test; done + * + */ +static const uint8_t test_vector[] =3D {0x61, 0x62, 0x63}; + +static const uint8_t test_result_sha512[] =3D { + 0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba, 0xcc, 0x41, 0x73, 0x49, + 0xae, 0x20, 0x41, 0x31, 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2, + 0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a, 0x21, 0x92, 0x99, 0x2a, + 0x27, 0x4f, 0xc1, 0xa8, 0x36, 0xba, 0x3c, 0x23, 0xa3, 0xfe, 0xeb, 0xbd, + 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, 0x2a, 0x9a, 0xc9, 0x4f, + 0xa5, 0x4c, 0xa4, 0x9f}; + +static const uint8_t test_result_sha256[] =3D { + 0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea, 0x41, 0x41, 0x40, 0xde, + 0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c, + 0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad}; + +static const uint8_t test_result_md5[] =3D { + 0x90, 0x01, 0x50, 0x98, 0x3c, 0xd2, 0x4f, 0xb0, 0xd6, 0x96, 0x3f, 0x7d, + 0x28, 0xe1, 0x7f, 0x72}; + +/* + * The Scatter-Gather Test vector is the ascii "abc" "def" "ghi", broken + * into blocks of 3 characters as shown + * + * Expected results were generated using command line utitiles: + * + * echo -n -e 'abcdefghijkl' | dd of=3D/tmp/test + * for hash in sha512sum sha256sum; do $hash /tmp/test; done + * + */ +static const uint8_t test_vector_sg1[] =3D {0x61, 0x62, 0x63, 0x64, 0x65, = 0x66}; +static const uint8_t test_vector_sg2[] =3D {0x67, 0x68, 0x69}; +static const uint8_t test_vector_sg3[] =3D {0x6a, 0x6b, 0x6c}; + +static const uint8_t test_result_sg_sha512[] =3D { + 0x17, 0x80, 0x7c, 0x72, 0x8e, 0xe3, 0xba, 0x35, 0xe7, 0xcf, 0x7a, 0xf8, + 0x23, 0x11, 0x6d, 0x26, 0xe4, 0x1e, 0x5d, 0x4d, 0x6c, 0x2f, 0xf1, 0xf3, + 0x72, 0x0d, 0x3d, 0x96, 0xaa, 0xcb, 0x6f, 0x69, 0xde, 0x64, 0x2e, 0x63, + 0xd5, 0xb7, 0x3f, 0xc3, 0x96, 0xc1, 0x2b, 0xe3, 0x8b, 0x2b, 0xd5, 0xd8, + 0x84, 0x25, 0x7c, 0x32, 0xc8, 0xf6, 0xd0, 0x85, 0x4a, 0xe6, 0xb5, 0x40, + 0xf8, 0x6d, 0xda, 0x2e}; + +static const uint8_t test_result_sg_sha256[] =3D { + 0xd6, 0x82, 0xed, 0x4c, 0xa4, 0xd9, 0x89, 0xc1, 0x34, 0xec, 0x94, 0xf1, + 0x55, 0x1e, 0x1e, 0xc5, 0x80, 0xdd, 0x6d, 0x5a, 0x6e, 0xcd, 0xe9, 0xf3, + 0xd3, 0x5e, 0x6e, 0x4a, 0x71, 0x7f, 0xbd, 0xe4}; + +/* + * The accumulative mode requires firmware to provide internal initial sta= te + * and message padding (including length L at the end of padding). + * + * This test vector is a ascii text "abc" with padding message. + * + * Expected results were generated using command line utitiles: + * + * echo -n -e 'abc' | dd of=3D/tmp/test + * for hash in sha512sum sha256sum; do $hash /tmp/test; done + */ +static const uint8_t test_vector_accum_512[] =3D { + 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18}; + +static const uint8_t test_vector_accum_256[] =3D { + 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18}; + +static const uint8_t test_result_accum_sha512[] =3D { + 0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba, 0xcc, 0x41, 0x73, 0x49, + 0xae, 0x20, 0x41, 0x31, 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2, + 0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a, 0x21, 0x92, 0x99, 0x2a, + 0x27, 0x4f, 0xc1, 0xa8, 0x36, 0xba, 0x3c, 0x23, 0xa3, 0xfe, 0xeb, 0xbd, + 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, 0x2a, 0x9a, 0xc9, 0x4f, + 0xa5, 0x4c, 0xa4, 0x9f}; + +static const uint8_t test_result_accum_sha256[] =3D { + 0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea, 0x41, 0x41, 0x40, 0xde, + 0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c, + 0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad}; + +static void write_regs(QTestState *s, uint32_t base, uint32_t src, + uint32_t length, uint32_t out, uint32_t method) +{ + qtest_writel(s, base + HACE_HASH_SRC, src); + qtest_writel(s, base + HACE_HASH_DIGEST, out); + qtest_writel(s, base + HACE_HASH_DATA_LEN, length); + qtest_writel(s, base + HACE_HASH_CMD, HACE_SHA_BE_EN | method); +} + +void aspeed_test_md5(const char *machine, const uint32_t base, + const uint32_t src_addr) + +{ + QTestState *s =3D qtest_init(machine); + + uint32_t digest_addr =3D src_addr + 0x01000000; + uint8_t digest[16] =3D {0}; + + /* Check engine is idle, no busy or irq bits set */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Write test vector into memory */ + qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector)); + + write_regs(s, base, src_addr, sizeof(test_vector), + digest_addr, HACE_ALGO_MD5); + + /* Check hash IRQ status is asserted */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); + + /* Clear IRQ status and check status is deasserted */ + qtest_writel(s, base + HACE_STS, 0x00000200); + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Read computed digest from memory */ + qtest_memread(s, digest_addr, digest, sizeof(digest)); + + /* Check result of computation */ + g_assert_cmpmem(digest, sizeof(digest), + test_result_md5, sizeof(digest)); + + qtest_quit(s); +} + +void aspeed_test_sha256(const char *machine, const uint32_t base, + const uint32_t src_addr) +{ + QTestState *s =3D qtest_init(machine); + + const uint32_t digest_addr =3D src_addr + 0x1000000; + uint8_t digest[32] =3D {0}; + + /* Check engine is idle, no busy or irq bits set */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Write test vector into memory */ + qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector)); + + write_regs(s, base, src_addr, sizeof(test_vector), digest_addr, + HACE_ALGO_SHA256); + + /* Check hash IRQ status is asserted */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); + + /* Clear IRQ status and check status is deasserted */ + qtest_writel(s, base + HACE_STS, 0x00000200); + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Read computed digest from memory */ + qtest_memread(s, digest_addr, digest, sizeof(digest)); + + /* Check result of computation */ + g_assert_cmpmem(digest, sizeof(digest), + test_result_sha256, sizeof(digest)); + + qtest_quit(s); +} + +void aspeed_test_sha512(const char *machine, const uint32_t base, + const uint32_t src_addr) +{ + QTestState *s =3D qtest_init(machine); + + const uint32_t digest_addr =3D src_addr + 0x1000000; + uint8_t digest[64] =3D {0}; + + /* Check engine is idle, no busy or irq bits set */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Write test vector into memory */ + qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector)); + + write_regs(s, base, src_addr, sizeof(test_vector), digest_addr, + HACE_ALGO_SHA512); + + /* Check hash IRQ status is asserted */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); + + /* Clear IRQ status and check status is deasserted */ + qtest_writel(s, base + HACE_STS, 0x00000200); + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Read computed digest from memory */ + qtest_memread(s, digest_addr, digest, sizeof(digest)); + + /* Check result of computation */ + g_assert_cmpmem(digest, sizeof(digest), + test_result_sha512, sizeof(digest)); + + qtest_quit(s); +} + +void aspeed_test_sha256_sg(const char *machine, const uint32_t base, + const uint32_t src_addr) +{ + QTestState *s =3D qtest_init(machine); + + const uint32_t src_addr_1 =3D src_addr + 0x1000000; + const uint32_t src_addr_2 =3D src_addr + 0x2000000; + const uint32_t src_addr_3 =3D src_addr + 0x3000000; + const uint32_t digest_addr =3D src_addr + 0x4000000; + uint8_t digest[32] =3D {0}; + struct AspeedSgList array[] =3D { + { cpu_to_le32(sizeof(test_vector_sg1)), + cpu_to_le32(src_addr_1) }, + { cpu_to_le32(sizeof(test_vector_sg2)), + cpu_to_le32(src_addr_2) }, + { cpu_to_le32(sizeof(test_vector_sg3) | SG_LIST_LEN_LAST), + cpu_to_le32(src_addr_3) }, + }; + + /* Check engine is idle, no busy or irq bits set */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Write test vector into memory */ + qtest_memwrite(s, src_addr_1, test_vector_sg1, sizeof(test_vector_sg1)= ); + qtest_memwrite(s, src_addr_2, test_vector_sg2, sizeof(test_vector_sg2)= ); + qtest_memwrite(s, src_addr_3, test_vector_sg3, sizeof(test_vector_sg3)= ); + qtest_memwrite(s, src_addr, array, sizeof(array)); + + write_regs(s, base, src_addr, + (sizeof(test_vector_sg1) + + sizeof(test_vector_sg2) + + sizeof(test_vector_sg3)), + digest_addr, HACE_ALGO_SHA256 | HACE_SG_EN); + + /* Check hash IRQ status is asserted */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); + + /* Clear IRQ status and check status is deasserted */ + qtest_writel(s, base + HACE_STS, 0x00000200); + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Read computed digest from memory */ + qtest_memread(s, digest_addr, digest, sizeof(digest)); + + /* Check result of computation */ + g_assert_cmpmem(digest, sizeof(digest), + test_result_sg_sha256, sizeof(digest)); + + qtest_quit(s); +} + +void aspeed_test_sha512_sg(const char *machine, const uint32_t base, + const uint32_t src_addr) +{ + QTestState *s =3D qtest_init(machine); + + const uint32_t src_addr_1 =3D src_addr + 0x1000000; + const uint32_t src_addr_2 =3D src_addr + 0x2000000; + const uint32_t src_addr_3 =3D src_addr + 0x3000000; + const uint32_t digest_addr =3D src_addr + 0x4000000; + uint8_t digest[64] =3D {0}; + struct AspeedSgList array[] =3D { + { cpu_to_le32(sizeof(test_vector_sg1)), + cpu_to_le32(src_addr_1) }, + { cpu_to_le32(sizeof(test_vector_sg2)), + cpu_to_le32(src_addr_2) }, + { cpu_to_le32(sizeof(test_vector_sg3) | SG_LIST_LEN_LAST), + cpu_to_le32(src_addr_3) }, + }; + + /* Check engine is idle, no busy or irq bits set */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Write test vector into memory */ + qtest_memwrite(s, src_addr_1, test_vector_sg1, sizeof(test_vector_sg1)= ); + qtest_memwrite(s, src_addr_2, test_vector_sg2, sizeof(test_vector_sg2)= ); + qtest_memwrite(s, src_addr_3, test_vector_sg3, sizeof(test_vector_sg3)= ); + qtest_memwrite(s, src_addr, array, sizeof(array)); + + write_regs(s, base, src_addr, + (sizeof(test_vector_sg1) + + sizeof(test_vector_sg2) + + sizeof(test_vector_sg3)), + digest_addr, HACE_ALGO_SHA512 | HACE_SG_EN); + + /* Check hash IRQ status is asserted */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); + + /* Clear IRQ status and check status is deasserted */ + qtest_writel(s, base + HACE_STS, 0x00000200); + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Read computed digest from memory */ + qtest_memread(s, digest_addr, digest, sizeof(digest)); + + /* Check result of computation */ + g_assert_cmpmem(digest, sizeof(digest), + test_result_sg_sha512, sizeof(digest)); + + qtest_quit(s); +} + +void aspeed_test_sha256_accum(const char *machine, const uint32_t base, + const uint32_t src_addr) +{ + QTestState *s =3D qtest_init(machine); + + const uint32_t buffer_addr =3D src_addr + 0x1000000; + const uint32_t digest_addr =3D src_addr + 0x4000000; + uint8_t digest[32] =3D {0}; + struct AspeedSgList array[] =3D { + { cpu_to_le32(sizeof(test_vector_accum_256) | SG_LIST_LEN_LAST), + cpu_to_le32(buffer_addr) }, + }; + + /* Check engine is idle, no busy or irq bits set */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Write test vector into memory */ + qtest_memwrite(s, buffer_addr, test_vector_accum_256, + sizeof(test_vector_accum_256)); + qtest_memwrite(s, src_addr, array, sizeof(array)); + + write_regs(s, base, src_addr, sizeof(test_vector_accum_256), + digest_addr, HACE_ALGO_SHA256 | HACE_SG_EN | HACE_ACCUM_EN); + + /* Check hash IRQ status is asserted */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); + + /* Clear IRQ status and check status is deasserted */ + qtest_writel(s, base + HACE_STS, 0x00000200); + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Read computed digest from memory */ + qtest_memread(s, digest_addr, digest, sizeof(digest)); + + /* Check result of computation */ + g_assert_cmpmem(digest, sizeof(digest), + test_result_accum_sha256, sizeof(digest)); + + qtest_quit(s); +} + +void aspeed_test_sha512_accum(const char *machine, const uint32_t base, + const uint32_t src_addr) +{ + QTestState *s =3D qtest_init(machine); + + const uint32_t buffer_addr =3D src_addr + 0x1000000; + const uint32_t digest_addr =3D src_addr + 0x4000000; + uint8_t digest[64] =3D {0}; + struct AspeedSgList array[] =3D { + { cpu_to_le32(sizeof(test_vector_accum_512) | SG_LIST_LEN_LAST), + cpu_to_le32(buffer_addr) }, + }; + + /* Check engine is idle, no busy or irq bits set */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Write test vector into memory */ + qtest_memwrite(s, buffer_addr, test_vector_accum_512, + sizeof(test_vector_accum_512)); + qtest_memwrite(s, src_addr, array, sizeof(array)); + + write_regs(s, base, src_addr, sizeof(test_vector_accum_512), + digest_addr, HACE_ALGO_SHA512 | HACE_SG_EN | HACE_ACCUM_EN); + + /* Check hash IRQ status is asserted */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); + + /* Clear IRQ status and check status is deasserted */ + qtest_writel(s, base + HACE_STS, 0x00000200); + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Read computed digest from memory */ + qtest_memread(s, digest_addr, digest, sizeof(digest)); + + /* Check result of computation */ + g_assert_cmpmem(digest, sizeof(digest), + test_result_accum_sha512, sizeof(digest)); + + qtest_quit(s); +} + +void aspeed_test_addresses(const char *machine, const uint32_t base, + const struct AspeedMasks *expected) +{ + QTestState *s =3D qtest_init(machine); + + /* + * Check command mode is zero, meaning engine is in direct access mode, + * as this affects the masking behavior of the HASH_SRC register. + */ + g_assert_cmphex(qtest_readl(s, base + HACE_CMD), =3D=3D, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), =3D=3D, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), =3D=3D, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), =3D=3D, 0); + + + /* Check that the address masking is correct */ + qtest_writel(s, base + HACE_HASH_SRC, 0xffffffff); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), =3D=3D, expected= ->src); + + qtest_writel(s, base + HACE_HASH_DIGEST, 0xffffffff); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), =3D=3D, + expected->dest); + + qtest_writel(s, base + HACE_HASH_DATA_LEN, 0xffffffff); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), =3D=3D, + expected->len); + + /* Reset to zero */ + qtest_writel(s, base + HACE_HASH_SRC, 0); + qtest_writel(s, base + HACE_HASH_DIGEST, 0); + qtest_writel(s, base + HACE_HASH_DATA_LEN, 0); + + /* Check that all bits are now zero */ + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), =3D=3D, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), =3D=3D, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), =3D=3D, 0); + + qtest_quit(s); +} + diff --git a/tests/qtest/aspeed_hace-test.c b/tests/qtest/aspeed_hace-test.c index ce86a44672..42a306af2a 100644 --- a/tests/qtest/aspeed_hace-test.c +++ b/tests/qtest/aspeed_hace-test.c @@ -6,584 +6,109 @@ */ =20 #include "qemu/osdep.h" - #include "libqtest.h" #include "qemu/bitops.h" +#include "aspeed-hace-utils.h" =20 -#define HACE_CMD 0x10 -#define HACE_SHA_BE_EN BIT(3) -#define HACE_MD5_LE_EN BIT(2) -#define HACE_ALGO_MD5 0 -#define HACE_ALGO_SHA1 BIT(5) -#define HACE_ALGO_SHA224 BIT(6) -#define HACE_ALGO_SHA256 (BIT(4) | BIT(6)) -#define HACE_ALGO_SHA512 (BIT(5) | BIT(6)) -#define HACE_ALGO_SHA384 (BIT(5) | BIT(6) | BIT(10)) -#define HACE_SG_EN BIT(18) -#define HACE_ACCUM_EN BIT(8) - -#define HACE_STS 0x1c -#define HACE_RSA_ISR BIT(13) -#define HACE_CRYPTO_ISR BIT(12) -#define HACE_HASH_ISR BIT(9) -#define HACE_RSA_BUSY BIT(2) -#define HACE_CRYPTO_BUSY BIT(1) -#define HACE_HASH_BUSY BIT(0) -#define HACE_HASH_SRC 0x20 -#define HACE_HASH_DIGEST 0x24 -#define HACE_HASH_KEY_BUFF 0x28 -#define HACE_HASH_DATA_LEN 0x2c -#define HACE_HASH_CMD 0x30 -/* Scatter-Gather Hash */ -#define SG_LIST_LEN_LAST BIT(31) -struct AspeedSgList { - uint32_t len; - uint32_t addr; -} __attribute__ ((__packed__)); - -/* - * Test vector is the ascii "abc" - * - * Expected results were generated using command line utitiles: - * - * echo -n -e 'abc' | dd of=3D/tmp/test - * for hash in sha512sum sha256sum md5sum; do $hash /tmp/test; done - * - */ -static const uint8_t test_vector[] =3D {0x61, 0x62, 0x63}; - -static const uint8_t test_result_sha512[] =3D { - 0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba, 0xcc, 0x41, 0x73, 0x49, - 0xae, 0x20, 0x41, 0x31, 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2, - 0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a, 0x21, 0x92, 0x99, 0x2a, - 0x27, 0x4f, 0xc1, 0xa8, 0x36, 0xba, 0x3c, 0x23, 0xa3, 0xfe, 0xeb, 0xbd, - 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, 0x2a, 0x9a, 0xc9, 0x4f, - 0xa5, 0x4c, 0xa4, 0x9f}; - -static const uint8_t test_result_sha256[] =3D { - 0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea, 0x41, 0x41, 0x40, 0xde, - 0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c, - 0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad}; - -static const uint8_t test_result_md5[] =3D { - 0x90, 0x01, 0x50, 0x98, 0x3c, 0xd2, 0x4f, 0xb0, 0xd6, 0x96, 0x3f, 0x7d, - 0x28, 0xe1, 0x7f, 0x72}; - -/* - * The Scatter-Gather Test vector is the ascii "abc" "def" "ghi", broken - * into blocks of 3 characters as shown - * - * Expected results were generated using command line utitiles: - * - * echo -n -e 'abcdefghijkl' | dd of=3D/tmp/test - * for hash in sha512sum sha256sum; do $hash /tmp/test; done - * - */ -static const uint8_t test_vector_sg1[] =3D {0x61, 0x62, 0x63, 0x64, 0x65, = 0x66}; -static const uint8_t test_vector_sg2[] =3D {0x67, 0x68, 0x69}; -static const uint8_t test_vector_sg3[] =3D {0x6a, 0x6b, 0x6c}; - -static const uint8_t test_result_sg_sha512[] =3D { - 0x17, 0x80, 0x7c, 0x72, 0x8e, 0xe3, 0xba, 0x35, 0xe7, 0xcf, 0x7a, 0xf8, - 0x23, 0x11, 0x6d, 0x26, 0xe4, 0x1e, 0x5d, 0x4d, 0x6c, 0x2f, 0xf1, 0xf3, - 0x72, 0x0d, 0x3d, 0x96, 0xaa, 0xcb, 0x6f, 0x69, 0xde, 0x64, 0x2e, 0x63, - 0xd5, 0xb7, 0x3f, 0xc3, 0x96, 0xc1, 0x2b, 0xe3, 0x8b, 0x2b, 0xd5, 0xd8, - 0x84, 0x25, 0x7c, 0x32, 0xc8, 0xf6, 0xd0, 0x85, 0x4a, 0xe6, 0xb5, 0x40, - 0xf8, 0x6d, 0xda, 0x2e}; - -static const uint8_t test_result_sg_sha256[] =3D { - 0xd6, 0x82, 0xed, 0x4c, 0xa4, 0xd9, 0x89, 0xc1, 0x34, 0xec, 0x94, 0xf1, - 0x55, 0x1e, 0x1e, 0xc5, 0x80, 0xdd, 0x6d, 0x5a, 0x6e, 0xcd, 0xe9, 0xf3, - 0xd3, 0x5e, 0x6e, 0x4a, 0x71, 0x7f, 0xbd, 0xe4}; - -/* - * The accumulative mode requires firmware to provide internal initial sta= te - * and message padding (including length L at the end of padding). - * - * This test vector is a ascii text "abc" with padding message. - * - * Expected results were generated using command line utitiles: - * - * echo -n -e 'abc' | dd of=3D/tmp/test - * for hash in sha512sum sha256sum; do $hash /tmp/test; done - */ -static const uint8_t test_vector_accum_512[] =3D { - 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18}; - -static const uint8_t test_vector_accum_256[] =3D { - 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18}; - -static const uint8_t test_result_accum_sha512[] =3D { - 0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba, 0xcc, 0x41, 0x73, 0x49, - 0xae, 0x20, 0x41, 0x31, 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2, - 0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a, 0x21, 0x92, 0x99, 0x2a, - 0x27, 0x4f, 0xc1, 0xa8, 0x36, 0xba, 0x3c, 0x23, 0xa3, 0xfe, 0xeb, 0xbd, - 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, 0x2a, 0x9a, 0xc9, 0x4f, - 0xa5, 0x4c, 0xa4, 0x9f}; - -static const uint8_t test_result_accum_sha256[] =3D { - 0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea, 0x41, 0x41, 0x40, 0xde, - 0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c, - 0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad}; - -static void write_regs(QTestState *s, uint32_t base, uint32_t src, - uint32_t length, uint32_t out, uint32_t method) -{ - qtest_writel(s, base + HACE_HASH_SRC, src); - qtest_writel(s, base + HACE_HASH_DIGEST, out); - qtest_writel(s, base + HACE_HASH_DATA_LEN, length); - qtest_writel(s, base + HACE_HASH_CMD, HACE_SHA_BE_EN | method); -} - -static void test_md5(const char *machine, const uint32_t base, - const uint32_t src_addr) - -{ - QTestState *s =3D qtest_init(machine); - - uint32_t digest_addr =3D src_addr + 0x01000000; - uint8_t digest[16] =3D {0}; - - /* Check engine is idle, no busy or irq bits set */ - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); - - /* Write test vector into memory */ - qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector)); - - write_regs(s, base, src_addr, sizeof(test_vector), digest_addr, HACE_A= LGO_MD5); - - /* Check hash IRQ status is asserted */ - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); - - /* Clear IRQ status and check status is deasserted */ - qtest_writel(s, base + HACE_STS, 0x00000200); - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); - - /* Read computed digest from memory */ - qtest_memread(s, digest_addr, digest, sizeof(digest)); - - /* Check result of computation */ - g_assert_cmpmem(digest, sizeof(digest), - test_result_md5, sizeof(digest)); - - qtest_quit(s); -} - -static void test_sha256(const char *machine, const uint32_t base, - const uint32_t src_addr) -{ - QTestState *s =3D qtest_init(machine); - - const uint32_t digest_addr =3D src_addr + 0x1000000; - uint8_t digest[32] =3D {0}; - - /* Check engine is idle, no busy or irq bits set */ - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); - - /* Write test vector into memory */ - qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector)); - - write_regs(s, base, src_addr, sizeof(test_vector), digest_addr, HACE_A= LGO_SHA256); - - /* Check hash IRQ status is asserted */ - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); - - /* Clear IRQ status and check status is deasserted */ - qtest_writel(s, base + HACE_STS, 0x00000200); - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); - - /* Read computed digest from memory */ - qtest_memread(s, digest_addr, digest, sizeof(digest)); - - /* Check result of computation */ - g_assert_cmpmem(digest, sizeof(digest), - test_result_sha256, sizeof(digest)); - - qtest_quit(s); -} - -static void test_sha512(const char *machine, const uint32_t base, - const uint32_t src_addr) -{ - QTestState *s =3D qtest_init(machine); - - const uint32_t digest_addr =3D src_addr + 0x1000000; - uint8_t digest[64] =3D {0}; - - /* Check engine is idle, no busy or irq bits set */ - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); - - /* Write test vector into memory */ - qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector)); - - write_regs(s, base, src_addr, sizeof(test_vector), digest_addr, HACE_A= LGO_SHA512); - - /* Check hash IRQ status is asserted */ - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); - - /* Clear IRQ status and check status is deasserted */ - qtest_writel(s, base + HACE_STS, 0x00000200); - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); - - /* Read computed digest from memory */ - qtest_memread(s, digest_addr, digest, sizeof(digest)); - - /* Check result of computation */ - g_assert_cmpmem(digest, sizeof(digest), - test_result_sha512, sizeof(digest)); - - qtest_quit(s); -} - -static void test_sha256_sg(const char *machine, const uint32_t base, - const uint32_t src_addr) -{ - QTestState *s =3D qtest_init(machine); - - const uint32_t src_addr_1 =3D src_addr + 0x1000000; - const uint32_t src_addr_2 =3D src_addr + 0x2000000; - const uint32_t src_addr_3 =3D src_addr + 0x3000000; - const uint32_t digest_addr =3D src_addr + 0x4000000; - uint8_t digest[32] =3D {0}; - struct AspeedSgList array[] =3D { - { cpu_to_le32(sizeof(test_vector_sg1)), - cpu_to_le32(src_addr_1) }, - { cpu_to_le32(sizeof(test_vector_sg2)), - cpu_to_le32(src_addr_2) }, - { cpu_to_le32(sizeof(test_vector_sg3) | SG_LIST_LEN_LAST), - cpu_to_le32(src_addr_3) }, - }; - - /* Check engine is idle, no busy or irq bits set */ - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); - - /* Write test vector into memory */ - qtest_memwrite(s, src_addr_1, test_vector_sg1, sizeof(test_vector_sg1)= ); - qtest_memwrite(s, src_addr_2, test_vector_sg2, sizeof(test_vector_sg2)= ); - qtest_memwrite(s, src_addr_3, test_vector_sg3, sizeof(test_vector_sg3)= ); - qtest_memwrite(s, src_addr, array, sizeof(array)); - - write_regs(s, base, src_addr, - (sizeof(test_vector_sg1) - + sizeof(test_vector_sg2) - + sizeof(test_vector_sg3)), - digest_addr, HACE_ALGO_SHA256 | HACE_SG_EN); - - /* Check hash IRQ status is asserted */ - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); - - /* Clear IRQ status and check status is deasserted */ - qtest_writel(s, base + HACE_STS, 0x00000200); - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); - - /* Read computed digest from memory */ - qtest_memread(s, digest_addr, digest, sizeof(digest)); - - /* Check result of computation */ - g_assert_cmpmem(digest, sizeof(digest), - test_result_sg_sha256, sizeof(digest)); - - qtest_quit(s); -} - -static void test_sha512_sg(const char *machine, const uint32_t base, - const uint32_t src_addr) -{ - QTestState *s =3D qtest_init(machine); - - const uint32_t src_addr_1 =3D src_addr + 0x1000000; - const uint32_t src_addr_2 =3D src_addr + 0x2000000; - const uint32_t src_addr_3 =3D src_addr + 0x3000000; - const uint32_t digest_addr =3D src_addr + 0x4000000; - uint8_t digest[64] =3D {0}; - struct AspeedSgList array[] =3D { - { cpu_to_le32(sizeof(test_vector_sg1)), - cpu_to_le32(src_addr_1) }, - { cpu_to_le32(sizeof(test_vector_sg2)), - cpu_to_le32(src_addr_2) }, - { cpu_to_le32(sizeof(test_vector_sg3) | SG_LIST_LEN_LAST), - cpu_to_le32(src_addr_3) }, - }; - - /* Check engine is idle, no busy or irq bits set */ - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); - - /* Write test vector into memory */ - qtest_memwrite(s, src_addr_1, test_vector_sg1, sizeof(test_vector_sg1)= ); - qtest_memwrite(s, src_addr_2, test_vector_sg2, sizeof(test_vector_sg2)= ); - qtest_memwrite(s, src_addr_3, test_vector_sg3, sizeof(test_vector_sg3)= ); - qtest_memwrite(s, src_addr, array, sizeof(array)); - - write_regs(s, base, src_addr, - (sizeof(test_vector_sg1) - + sizeof(test_vector_sg2) - + sizeof(test_vector_sg3)), - digest_addr, HACE_ALGO_SHA512 | HACE_SG_EN); - - /* Check hash IRQ status is asserted */ - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); - - /* Clear IRQ status and check status is deasserted */ - qtest_writel(s, base + HACE_STS, 0x00000200); - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); - - /* Read computed digest from memory */ - qtest_memread(s, digest_addr, digest, sizeof(digest)); - - /* Check result of computation */ - g_assert_cmpmem(digest, sizeof(digest), - test_result_sg_sha512, sizeof(digest)); - - qtest_quit(s); -} - -static void test_sha256_accum(const char *machine, const uint32_t base, - const uint32_t src_addr) -{ - QTestState *s =3D qtest_init(machine); - - const uint32_t buffer_addr =3D src_addr + 0x1000000; - const uint32_t digest_addr =3D src_addr + 0x4000000; - uint8_t digest[32] =3D {0}; - struct AspeedSgList array[] =3D { - { cpu_to_le32(sizeof(test_vector_accum_256) | SG_LIST_LEN_LAST), - cpu_to_le32(buffer_addr) }, - }; - - /* Check engine is idle, no busy or irq bits set */ - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); - - /* Write test vector into memory */ - qtest_memwrite(s, buffer_addr, test_vector_accum_256, - sizeof(test_vector_accum_256)); - qtest_memwrite(s, src_addr, array, sizeof(array)); - - write_regs(s, base, src_addr, sizeof(test_vector_accum_256), - digest_addr, HACE_ALGO_SHA256 | HACE_SG_EN | HACE_ACCUM_EN); - - /* Check hash IRQ status is asserted */ - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); - - /* Clear IRQ status and check status is deasserted */ - qtest_writel(s, base + HACE_STS, 0x00000200); - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); - - /* Read computed digest from memory */ - qtest_memread(s, digest_addr, digest, sizeof(digest)); - - /* Check result of computation */ - g_assert_cmpmem(digest, sizeof(digest), - test_result_accum_sha256, sizeof(digest)); - - qtest_quit(s); -} - -static void test_sha512_accum(const char *machine, const uint32_t base, - const uint32_t src_addr) -{ - QTestState *s =3D qtest_init(machine); - - const uint32_t buffer_addr =3D src_addr + 0x1000000; - const uint32_t digest_addr =3D src_addr + 0x4000000; - uint8_t digest[64] =3D {0}; - struct AspeedSgList array[] =3D { - { cpu_to_le32(sizeof(test_vector_accum_512) | SG_LIST_LEN_LAST), - cpu_to_le32(buffer_addr) }, - }; - - /* Check engine is idle, no busy or irq bits set */ - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); - - /* Write test vector into memory */ - qtest_memwrite(s, buffer_addr, test_vector_accum_512, - sizeof(test_vector_accum_512)); - qtest_memwrite(s, src_addr, array, sizeof(array)); - - write_regs(s, base, src_addr, sizeof(test_vector_accum_512), - digest_addr, HACE_ALGO_SHA512 | HACE_SG_EN | HACE_ACCUM_EN); - - /* Check hash IRQ status is asserted */ - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); - - /* Clear IRQ status and check status is deasserted */ - qtest_writel(s, base + HACE_STS, 0x00000200); - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); - - /* Read computed digest from memory */ - qtest_memread(s, digest_addr, digest, sizeof(digest)); - - /* Check result of computation */ - g_assert_cmpmem(digest, sizeof(digest), - test_result_accum_sha512, sizeof(digest)); - - qtest_quit(s); -} - -struct masks { - uint32_t src; - uint32_t dest; - uint32_t len; -}; - -static const struct masks ast2600_masks =3D { +static const struct AspeedMasks ast2600_masks =3D { .src =3D 0x7fffffff, .dest =3D 0x7ffffff8, .len =3D 0x0fffffff, }; =20 -static const struct masks ast2500_masks =3D { +static const struct AspeedMasks ast2500_masks =3D { .src =3D 0x3fffffff, .dest =3D 0x3ffffff8, .len =3D 0x0fffffff, }; =20 -static const struct masks ast2400_masks =3D { +static const struct AspeedMasks ast2400_masks =3D { .src =3D 0x0fffffff, .dest =3D 0x0ffffff8, .len =3D 0x0fffffff, }; =20 -static void test_addresses(const char *machine, const uint32_t base, - const struct masks *expected) -{ - QTestState *s =3D qtest_init(machine); - - /* - * Check command mode is zero, meaning engine is in direct access mode, - * as this affects the masking behavior of the HASH_SRC register. - */ - g_assert_cmphex(qtest_readl(s, base + HACE_CMD), =3D=3D, 0); - g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), =3D=3D, 0); - g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), =3D=3D, 0); - g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), =3D=3D, 0); - - - /* Check that the address masking is correct */ - qtest_writel(s, base + HACE_HASH_SRC, 0xffffffff); - g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), =3D=3D, expected= ->src); - - qtest_writel(s, base + HACE_HASH_DIGEST, 0xffffffff); - g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), =3D=3D, expec= ted->dest); - - qtest_writel(s, base + HACE_HASH_DATA_LEN, 0xffffffff); - g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), =3D=3D, exp= ected->len); - - /* Reset to zero */ - qtest_writel(s, base + HACE_HASH_SRC, 0); - qtest_writel(s, base + HACE_HASH_DIGEST, 0); - qtest_writel(s, base + HACE_HASH_DATA_LEN, 0); - - /* Check that all bits are now zero */ - g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), =3D=3D, 0); - g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), =3D=3D, 0); - g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), =3D=3D, 0); - - qtest_quit(s); -} - /* ast2600 */ static void test_md5_ast2600(void) { - test_md5("-machine ast2600-evb", 0x1e6d0000, 0x80000000); + aspeed_test_md5("-machine ast2600-evb", 0x1e6d0000, 0x80000000); } =20 static void test_sha256_ast2600(void) { - test_sha256("-machine ast2600-evb", 0x1e6d0000, 0x80000000); + aspeed_test_sha256("-machine ast2600-evb", 0x1e6d0000, 0x80000000); } =20 static void test_sha256_sg_ast2600(void) { - test_sha256_sg("-machine ast2600-evb", 0x1e6d0000, 0x80000000); + aspeed_test_sha256_sg("-machine ast2600-evb", 0x1e6d0000, 0x80000000); } =20 static void test_sha512_ast2600(void) { - test_sha512("-machine ast2600-evb", 0x1e6d0000, 0x80000000); + aspeed_test_sha512("-machine ast2600-evb", 0x1e6d0000, 0x80000000); } =20 static void test_sha512_sg_ast2600(void) { - test_sha512_sg("-machine ast2600-evb", 0x1e6d0000, 0x80000000); + aspeed_test_sha512_sg("-machine ast2600-evb", 0x1e6d0000, 0x80000000); } =20 static void test_sha256_accum_ast2600(void) { - test_sha256_accum("-machine ast2600-evb", 0x1e6d0000, 0x80000000); + aspeed_test_sha256_accum("-machine ast2600-evb", 0x1e6d0000, 0x8000000= 0); } =20 static void test_sha512_accum_ast2600(void) { - test_sha512_accum("-machine ast2600-evb", 0x1e6d0000, 0x80000000); + aspeed_test_sha512_accum("-machine ast2600-evb", 0x1e6d0000, 0x8000000= 0); } =20 static void test_addresses_ast2600(void) { - test_addresses("-machine ast2600-evb", 0x1e6d0000, &ast2600_masks); + aspeed_test_addresses("-machine ast2600-evb", 0x1e6d0000, &ast2600_mas= ks); } =20 /* ast2500 */ static void test_md5_ast2500(void) { - test_md5("-machine ast2500-evb", 0x1e6e3000, 0x80000000); + aspeed_test_md5("-machine ast2500-evb", 0x1e6e3000, 0x80000000); } =20 static void test_sha256_ast2500(void) { - test_sha256("-machine ast2500-evb", 0x1e6e3000, 0x80000000); + aspeed_test_sha256("-machine ast2500-evb", 0x1e6e3000, 0x80000000); } =20 static void test_sha512_ast2500(void) { - test_sha512("-machine ast2500-evb", 0x1e6e3000, 0x80000000); + aspeed_test_sha512("-machine ast2500-evb", 0x1e6e3000, 0x80000000); } =20 static void test_addresses_ast2500(void) { - test_addresses("-machine ast2500-evb", 0x1e6e3000, &ast2500_masks); + aspeed_test_addresses("-machine ast2500-evb", 0x1e6e3000, &ast2500_mas= ks); } =20 /* ast2400 */ static void test_md5_ast2400(void) { - test_md5("-machine palmetto-bmc", 0x1e6e3000, 0x40000000); + aspeed_test_md5("-machine palmetto-bmc", 0x1e6e3000, 0x40000000); } =20 static void test_sha256_ast2400(void) { - test_sha256("-machine palmetto-bmc", 0x1e6e3000, 0x40000000); + aspeed_test_sha256("-machine palmetto-bmc", 0x1e6e3000, 0x40000000); } =20 static void test_sha512_ast2400(void) { - test_sha512("-machine palmetto-bmc", 0x1e6e3000, 0x40000000); + aspeed_test_sha512("-machine palmetto-bmc", 0x1e6e3000, 0x40000000); } =20 static void test_addresses_ast2400(void) { - test_addresses("-machine palmetto-bmc", 0x1e6e3000, &ast2400_masks); + aspeed_test_addresses("-machine palmetto-bmc", 0x1e6e3000, &ast2400_ma= sks); } =20 int main(int argc, char **argv) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 6b5161a643..bb14a22ebe 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -360,6 +360,7 @@ if gnutls.found() endif =20 qtests =3D { + 'aspeed_hace-test': files('aspeed-hace-utils.c', 'aspeed_hace-test.c'), 'aspeed_smc-test': files('aspeed-smc-utils.c', 'aspeed_smc-test.c'), 'ast2700-smc-test': files('aspeed-smc-utils.c', 'ast2700-smc-test.c'), 'bios-tables-test': [io, 'boot-sector.c', 'acpi-utils.c', 'tpm-emu.c'], --=20 2.43.0 From nobody Sat Nov 15 20:52:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1747118165; cv=none; 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Tue, 13 May 2025 14:29:08 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v2 16/25] test/qtest/hace: Specify explicit array sizes for test vectors and hash results Date: Tue, 13 May 2025 14:28:46 +0800 Message-ID: <20250513062901.2256865-17-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> References: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1747118166866116600 Content-Type: text/plain; charset="utf-8" To enhance code readability and prevent potential buffer overflows or unint= ended size assumptions, this commit updates all fixed-size array declarations to = use explicit array sizes. Signed-off-by: Jamin Lin --- tests/qtest/aspeed-hace-utils.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/tests/qtest/aspeed-hace-utils.c b/tests/qtest/aspeed-hace-util= s.c index 8582847945..777fa5b986 100644 --- a/tests/qtest/aspeed-hace-utils.c +++ b/tests/qtest/aspeed-hace-utils.c @@ -19,9 +19,9 @@ * for hash in sha512sum sha256sum md5sum; do $hash /tmp/test; done * */ -static const uint8_t test_vector[] =3D {0x61, 0x62, 0x63}; +static const uint8_t test_vector[3] =3D {0x61, 0x62, 0x63}; =20 -static const uint8_t test_result_sha512[] =3D { +static const uint8_t test_result_sha512[64] =3D { 0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba, 0xcc, 0x41, 0x73, 0x49, 0xae, 0x20, 0x41, 0x31, 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2, 0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a, 0x21, 0x92, 0x99, 0x2a, @@ -29,12 +29,12 @@ static const uint8_t test_result_sha512[] =3D { 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, 0x2a, 0x9a, 0xc9, 0x4f, 0xa5, 0x4c, 0xa4, 0x9f}; =20 -static const uint8_t test_result_sha256[] =3D { +static const uint8_t test_result_sha256[32] =3D { 0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea, 0x41, 0x41, 0x40, 0xde, 0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c, 0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad}; =20 -static const uint8_t test_result_md5[] =3D { +static const uint8_t test_result_md5[16] =3D { 0x90, 0x01, 0x50, 0x98, 0x3c, 0xd2, 0x4f, 0xb0, 0xd6, 0x96, 0x3f, 0x7d, 0x28, 0xe1, 0x7f, 0x72}; =20 @@ -48,11 +48,11 @@ static const uint8_t test_result_md5[] =3D { * for hash in sha512sum sha256sum; do $hash /tmp/test; done * */ -static const uint8_t test_vector_sg1[] =3D {0x61, 0x62, 0x63, 0x64, 0x65, = 0x66}; -static const uint8_t test_vector_sg2[] =3D {0x67, 0x68, 0x69}; -static const uint8_t test_vector_sg3[] =3D {0x6a, 0x6b, 0x6c}; +static const uint8_t test_vector_sg1[6] =3D {0x61, 0x62, 0x63, 0x64, 0x65,= 0x66}; +static const uint8_t test_vector_sg2[3] =3D {0x67, 0x68, 0x69}; +static const uint8_t test_vector_sg3[3] =3D {0x6a, 0x6b, 0x6c}; =20 -static const uint8_t test_result_sg_sha512[] =3D { +static const uint8_t test_result_sg_sha512[64] =3D { 0x17, 0x80, 0x7c, 0x72, 0x8e, 0xe3, 0xba, 0x35, 0xe7, 0xcf, 0x7a, 0xf8, 0x23, 0x11, 0x6d, 0x26, 0xe4, 0x1e, 0x5d, 0x4d, 0x6c, 0x2f, 0xf1, 0xf3, 0x72, 0x0d, 0x3d, 0x96, 0xaa, 0xcb, 0x6f, 0x69, 0xde, 0x64, 0x2e, 0x63, @@ -60,7 +60,7 @@ static const uint8_t test_result_sg_sha512[] =3D { 0x84, 0x25, 0x7c, 0x32, 0xc8, 0xf6, 0xd0, 0x85, 0x4a, 0xe6, 0xb5, 0x40, 0xf8, 0x6d, 0xda, 0x2e}; =20 -static const uint8_t test_result_sg_sha256[] =3D { +static const uint8_t test_result_sg_sha256[32] =3D { 0xd6, 0x82, 0xed, 0x4c, 0xa4, 0xd9, 0x89, 0xc1, 0x34, 0xec, 0x94, 0xf1, 0x55, 0x1e, 0x1e, 0xc5, 0x80, 0xdd, 0x6d, 0x5a, 0x6e, 0xcd, 0xe9, 0xf3, 0xd3, 0x5e, 0x6e, 0x4a, 0x71, 0x7f, 0xbd, 0xe4}; @@ -76,7 +76,7 @@ static const uint8_t test_result_sg_sha256[] =3D { * echo -n -e 'abc' | dd of=3D/tmp/test * for hash in sha512sum sha256sum; do $hash /tmp/test; done */ -static const uint8_t test_vector_accum_512[] =3D { +static const uint8_t test_vector_accum_512[128] =3D { 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -94,7 +94,7 @@ static const uint8_t test_vector_accum_512[] =3D { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18}; =20 -static const uint8_t test_vector_accum_256[] =3D { +static const uint8_t test_vector_accum_256[64] =3D { 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -104,7 +104,7 @@ static const uint8_t test_vector_accum_256[] =3D { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18}; =20 -static const uint8_t test_result_accum_sha512[] =3D { +static const uint8_t test_result_accum_sha512[64] =3D { 0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba, 0xcc, 0x41, 0x73, 0x49, 0xae, 0x20, 0x41, 0x31, 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2, 0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a, 0x21, 0x92, 0x99, 0x2a, @@ -112,7 +112,7 @@ static const uint8_t test_result_accum_sha512[] =3D { 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, 0x2a, 0x9a, 0xc9, 0x4f, 0xa5, 0x4c, 0xa4, 0x9f}; =20 -static const uint8_t test_result_accum_sha256[] =3D { +static const uint8_t test_result_accum_sha256[32] =3D { 0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea, 0x41, 0x41, 0x40, 0xde, 0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c, 0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad}; --=20 2.43.0 From nobody Sat Nov 15 20:52:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1747118261; cv=none; d=zohomail.com; s=zohoarc; b=e2kff1QziuDGAgf4Wh5euC0uvJBluJ6jcKq6079dJLsgxYYqwdrBhuXYuV3mNvHP4X3gTIoUTowFM6Nhvrv9vcQ0Dr5ee2CZM8moOIP0j7H3cry7KrsuQke1PLwCrX0EQyo//wNBqn9YBGgVfKNPnTpfqGb6/HyhhYNr7iaZwKI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747118261; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=QHrvzQaJMy/BoR2zBPOSAEQXBKAGEDHzfe82lQK3yH4=; b=TT1WwG1OQnysiauRS6+g7uKN7DWaGB+xOb6dQXiv6ALkr/qSj8zzz7tvh1JcMPKE2PcINDySa72yqIuM1iB2zb2NuQ57lh9svCvdY0svYfvtc+2ORxF28vm5vm8vmcLcInBAW4Byn9MhKBQNQL0o6k0tJrMNugKB9n4JgCGLoqw= ARC-Authentication-Results: i=1; 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Tue, 13 May 2025 14:29:08 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 13 May 2025 14:29:08 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v2 17/25] test/qtest/hace: Adjust test address range for AST1030 due to SRAM limitations Date: Tue, 13 May 2025 14:28:47 +0800 Message-ID: <20250513062901.2256865-18-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> References: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1747118261894116600 Content-Type: text/plain; charset="utf-8" The digest_addr is set to "src_addr + 0x1000000", where src_addr is the DRAM base address. However, the value 0x1000000 (16MB) is too large because the AST1030 does not support DRAM, and its SRAM size is only 768KB. A range size of 0x10000 (64KB) is sufficient for HACE test cases, as the te= st vector size does not exceed 64KB. Updates: 1. Direct Access Mode Update digest_addr to "src_addr + 0x10000" in the following functions: aspeed_test_md5 aspeed_test_sha256 aspeed_test_sha512 2. Scatter-Gather (SG) Mode Update source address for different SG buffer addresses in the following functions: src_addr1 =3D src_addr + 0x10000 src_addr2 =3D src_addr + 0x20000 src_addr3 =3D src_addr + 0x30000 digest_addr =3D src_addr + 0x40000 aspeed_test_sha256_sg aspeed_test_sha512_sg 3. ACC Mode Update Update the SG List start address: src_addr + 0x10000 Update the SG List buffer size to 0x30000 (192KB). buffer_addr =3D src_addr + 0x10000 digest_addr =3D src_addr + 0x40000 Signed-off-by: Jamin Lin --- tests/qtest/aspeed-hace-utils.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/tests/qtest/aspeed-hace-utils.c b/tests/qtest/aspeed-hace-util= s.c index 777fa5b986..539d06e4f8 100644 --- a/tests/qtest/aspeed-hace-utils.c +++ b/tests/qtest/aspeed-hace-utils.c @@ -132,7 +132,7 @@ void aspeed_test_md5(const char *machine, const uint32_= t base, { QTestState *s =3D qtest_init(machine); =20 - uint32_t digest_addr =3D src_addr + 0x01000000; + uint32_t digest_addr =3D src_addr + 0x010000; uint8_t digest[16] =3D {0}; =20 /* Check engine is idle, no busy or irq bits set */ @@ -166,7 +166,7 @@ void aspeed_test_sha256(const char *machine, const uint= 32_t base, { QTestState *s =3D qtest_init(machine); =20 - const uint32_t digest_addr =3D src_addr + 0x1000000; + const uint32_t digest_addr =3D src_addr + 0x10000; uint8_t digest[32] =3D {0}; =20 /* Check engine is idle, no busy or irq bits set */ @@ -200,7 +200,7 @@ void aspeed_test_sha512(const char *machine, const uint= 32_t base, { QTestState *s =3D qtest_init(machine); =20 - const uint32_t digest_addr =3D src_addr + 0x1000000; + const uint32_t digest_addr =3D src_addr + 0x10000; uint8_t digest[64] =3D {0}; =20 /* Check engine is idle, no busy or irq bits set */ @@ -234,10 +234,10 @@ void aspeed_test_sha256_sg(const char *machine, const= uint32_t base, { QTestState *s =3D qtest_init(machine); =20 - const uint32_t src_addr_1 =3D src_addr + 0x1000000; - const uint32_t src_addr_2 =3D src_addr + 0x2000000; - const uint32_t src_addr_3 =3D src_addr + 0x3000000; - const uint32_t digest_addr =3D src_addr + 0x4000000; + const uint32_t src_addr_1 =3D src_addr + 0x10000; + const uint32_t src_addr_2 =3D src_addr + 0x20000; + const uint32_t src_addr_3 =3D src_addr + 0x30000; + const uint32_t digest_addr =3D src_addr + 0x40000; uint8_t digest[32] =3D {0}; struct AspeedSgList array[] =3D { { cpu_to_le32(sizeof(test_vector_sg1)), @@ -285,10 +285,10 @@ void aspeed_test_sha512_sg(const char *machine, const= uint32_t base, { QTestState *s =3D qtest_init(machine); =20 - const uint32_t src_addr_1 =3D src_addr + 0x1000000; - const uint32_t src_addr_2 =3D src_addr + 0x2000000; - const uint32_t src_addr_3 =3D src_addr + 0x3000000; - const uint32_t digest_addr =3D src_addr + 0x4000000; + const uint32_t src_addr_1 =3D src_addr + 0x10000; + const uint32_t src_addr_2 =3D src_addr + 0x20000; + const uint32_t src_addr_3 =3D src_addr + 0x30000; + const uint32_t digest_addr =3D src_addr + 0x40000; uint8_t digest[64] =3D {0}; struct AspeedSgList array[] =3D { { cpu_to_le32(sizeof(test_vector_sg1)), @@ -336,8 +336,8 @@ void aspeed_test_sha256_accum(const char *machine, cons= t uint32_t base, { QTestState *s =3D qtest_init(machine); =20 - const uint32_t buffer_addr =3D src_addr + 0x1000000; - const uint32_t digest_addr =3D src_addr + 0x4000000; + const uint32_t buffer_addr =3D src_addr + 0x10000; + const uint32_t digest_addr =3D src_addr + 0x40000; uint8_t digest[32] =3D {0}; struct AspeedSgList array[] =3D { { cpu_to_le32(sizeof(test_vector_accum_256) | SG_LIST_LEN_LAST), @@ -377,8 +377,8 @@ void aspeed_test_sha512_accum(const char *machine, cons= t uint32_t base, { QTestState *s =3D qtest_init(machine); =20 - const uint32_t buffer_addr =3D src_addr + 0x1000000; - const uint32_t digest_addr =3D src_addr + 0x4000000; + const uint32_t buffer_addr =3D src_addr + 0x10000; + const uint32_t digest_addr =3D src_addr + 0x40000; uint8_t digest[64] =3D {0}; struct AspeedSgList array[] =3D { { cpu_to_le32(sizeof(test_vector_accum_512) | SG_LIST_LEN_LAST), --=20 2.43.0 From nobody Sat Nov 15 20:52:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; 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Tue, 13 May 2025 14:29:08 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 13 May 2025 14:29:08 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v2 18/25] test/qtest/hace: Add SHA-384 test cases for ASPEED HACE model Date: Tue, 13 May 2025 14:28:48 +0800 Message-ID: <20250513062901.2256865-19-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> References: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1747118150868116600 Content-Type: text/plain; charset="utf-8" Introduced SHA-384 test functions to verify hashing operations. Extended support for scatter-gather ("_sg") and accumulation ("_accum") tes= ts. Updated test result vectors for SHA-384 validation. Signed-off-by: Jamin Lin --- tests/qtest/aspeed-hace-utils.h | 6 ++ tests/qtest/aspeed-hace-utils.c | 168 +++++++++++++++++++++++++++++++- 2 files changed, 171 insertions(+), 3 deletions(-) diff --git a/tests/qtest/aspeed-hace-utils.h b/tests/qtest/aspeed-hace-util= s.h index 598577c69b..f4440561de 100644 --- a/tests/qtest/aspeed-hace-utils.h +++ b/tests/qtest/aspeed-hace-utils.h @@ -54,14 +54,20 @@ void aspeed_test_md5(const char *machine, const uint32_= t base, const uint32_t src_addr); void aspeed_test_sha256(const char *machine, const uint32_t base, const uint32_t src_addr); +void aspeed_test_sha384(const char *machine, const uint32_t base, + const uint32_t src_addr); void aspeed_test_sha512(const char *machine, const uint32_t base, const uint32_t src_addr); void aspeed_test_sha256_sg(const char *machine, const uint32_t base, const uint32_t src_addr); +void aspeed_test_sha384_sg(const char *machine, const uint32_t base, + const uint32_t src_addr); void aspeed_test_sha512_sg(const char *machine, const uint32_t base, const uint32_t src_addr); void aspeed_test_sha256_accum(const char *machine, const uint32_t base, const uint32_t src_addr); +void aspeed_test_sha384_accum(const char *machine, const uint32_t base, + const uint32_t src_addr); void aspeed_test_sha512_accum(const char *machine, const uint32_t base, const uint32_t src_addr); void aspeed_test_addresses(const char *machine, const uint32_t base, diff --git a/tests/qtest/aspeed-hace-utils.c b/tests/qtest/aspeed-hace-util= s.c index 539d06e4f8..dad90ee81c 100644 --- a/tests/qtest/aspeed-hace-utils.c +++ b/tests/qtest/aspeed-hace-utils.c @@ -16,7 +16,7 @@ * Expected results were generated using command line utitiles: * * echo -n -e 'abc' | dd of=3D/tmp/test - * for hash in sha512sum sha256sum md5sum; do $hash /tmp/test; done + * for hash in sha512sum sha384sum sha256sum md5sum; do $hash /tmp/test; = done * */ static const uint8_t test_vector[3] =3D {0x61, 0x62, 0x63}; @@ -29,6 +29,12 @@ static const uint8_t test_result_sha512[64] =3D { 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, 0x2a, 0x9a, 0xc9, 0x4f, 0xa5, 0x4c, 0xa4, 0x9f}; =20 +static const uint8_t test_result_sha384[48] =3D { + 0xcb, 0x00, 0x75, 0x3f, 0x45, 0xa3, 0x5e, 0x8b, 0xb5, 0xa0, 0x3d, 0x69, + 0x9a, 0xc6, 0x50, 0x07, 0x27, 0x2c, 0x32, 0xab, 0x0e, 0xde, 0xd1, 0x63, + 0x1a, 0x8b, 0x60, 0x5a, 0x43, 0xff, 0x5b, 0xed, 0x80, 0x86, 0x07, 0x2b, + 0xa1, 0xe7, 0xcc, 0x23, 0x58, 0xba, 0xec, 0xa1, 0x34, 0xc8, 0x25, 0xa7= }; + static const uint8_t test_result_sha256[32] =3D { 0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea, 0x41, 0x41, 0x40, 0xde, 0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c, @@ -45,7 +51,7 @@ static const uint8_t test_result_md5[16] =3D { * Expected results were generated using command line utitiles: * * echo -n -e 'abcdefghijkl' | dd of=3D/tmp/test - * for hash in sha512sum sha256sum; do $hash /tmp/test; done + * for hash in sha512sum sha384sum sha256sum; do $hash /tmp/test; done * */ static const uint8_t test_vector_sg1[6] =3D {0x61, 0x62, 0x63, 0x64, 0x65,= 0x66}; @@ -60,6 +66,12 @@ static const uint8_t test_result_sg_sha512[64] =3D { 0x84, 0x25, 0x7c, 0x32, 0xc8, 0xf6, 0xd0, 0x85, 0x4a, 0xe6, 0xb5, 0x40, 0xf8, 0x6d, 0xda, 0x2e}; =20 +static const uint8_t test_result_sg_sha384[48] =3D { + 0x10, 0x3c, 0xa9, 0x6c, 0x06, 0xa1, 0xce, 0x79, 0x8f, 0x08, 0xf8, 0xef, + 0xf0, 0xdf, 0xb0, 0xcc, 0xdb, 0x56, 0x7d, 0x48, 0xb2, 0x85, 0xb2, 0x3d, + 0x0c, 0xd7, 0x73, 0x45, 0x46, 0x67, 0xa3, 0xc2, 0xfa, 0x5f, 0x1b, 0x58, + 0xd9, 0xcd, 0xf2, 0x32, 0x9b, 0xd9, 0x97, 0x97, 0x30, 0xbf, 0xaa, 0xff= }; + static const uint8_t test_result_sg_sha256[32] =3D { 0xd6, 0x82, 0xed, 0x4c, 0xa4, 0xd9, 0x89, 0xc1, 0x34, 0xec, 0x94, 0xf1, 0x55, 0x1e, 0x1e, 0xc5, 0x80, 0xdd, 0x6d, 0x5a, 0x6e, 0xcd, 0xe9, 0xf3, @@ -74,7 +86,7 @@ static const uint8_t test_result_sg_sha256[32] =3D { * Expected results were generated using command line utitiles: * * echo -n -e 'abc' | dd of=3D/tmp/test - * for hash in sha512sum sha256sum; do $hash /tmp/test; done + * for hash in sha512sum sha384sum sha256sum; do $hash /tmp/test; done */ static const uint8_t test_vector_accum_512[128] =3D { 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, @@ -94,6 +106,24 @@ static const uint8_t test_vector_accum_512[128] =3D { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18}; =20 +static const uint8_t test_vector_accum_384[128] =3D { + 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18}; + static const uint8_t test_vector_accum_256[64] =3D { 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -112,6 +142,12 @@ static const uint8_t test_result_accum_sha512[64] =3D { 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, 0x2a, 0x9a, 0xc9, 0x4f, 0xa5, 0x4c, 0xa4, 0x9f}; =20 +static const uint8_t test_result_accum_sha384[48] =3D { + 0xcb, 0x00, 0x75, 0x3f, 0x45, 0xa3, 0x5e, 0x8b, 0xb5, 0xa0, 0x3d, 0x69, + 0x9a, 0xc6, 0x50, 0x07, 0x27, 0x2c, 0x32, 0xab, 0x0e, 0xde, 0xd1, 0x63, + 0x1a, 0x8b, 0x60, 0x5a, 0x43, 0xff, 0x5b, 0xed, 0x80, 0x86, 0x07, 0x2b, + 0xa1, 0xe7, 0xcc, 0x23, 0x58, 0xba, 0xec, 0xa1, 0x34, 0xc8, 0x25, 0xa7= }; + static const uint8_t test_result_accum_sha256[32] =3D { 0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea, 0x41, 0x41, 0x40, 0xde, 0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c, @@ -195,6 +231,40 @@ void aspeed_test_sha256(const char *machine, const uin= t32_t base, qtest_quit(s); } =20 +void aspeed_test_sha384(const char *machine, const uint32_t base, + const uint32_t src_addr) +{ + QTestState *s =3D qtest_init(machine); + + const uint32_t digest_addr =3D src_addr + 0x10000; + uint8_t digest[48] =3D {0}; + + /* Check engine is idle, no busy or irq bits set */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Write test vector into memory */ + qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector)); + + write_regs(s, base, src_addr, sizeof(test_vector), digest_addr, + HACE_ALGO_SHA384); + + /* Check hash IRQ status is asserted */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); + + /* Clear IRQ status and check status is deasserted */ + qtest_writel(s, base + HACE_STS, 0x00000200); + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Read computed digest from memory */ + qtest_memread(s, digest_addr, digest, sizeof(digest)); + + /* Check result of computation */ + g_assert_cmpmem(digest, sizeof(digest), + test_result_sha384, sizeof(digest)); + + qtest_quit(s); +} + void aspeed_test_sha512(const char *machine, const uint32_t base, const uint32_t src_addr) { @@ -280,6 +350,57 @@ void aspeed_test_sha256_sg(const char *machine, const = uint32_t base, qtest_quit(s); } =20 +void aspeed_test_sha384_sg(const char *machine, const uint32_t base, + const uint32_t src_addr) +{ + QTestState *s =3D qtest_init(machine); + + const uint32_t src_addr_1 =3D src_addr + 0x10000; + const uint32_t src_addr_2 =3D src_addr + 0x20000; + const uint32_t src_addr_3 =3D src_addr + 0x30000; + const uint32_t digest_addr =3D src_addr + 0x40000; + uint8_t digest[48] =3D {0}; + struct AspeedSgList array[] =3D { + { cpu_to_le32(sizeof(test_vector_sg1)), + cpu_to_le32(src_addr_1) }, + { cpu_to_le32(sizeof(test_vector_sg2)), + cpu_to_le32(src_addr_2) }, + { cpu_to_le32(sizeof(test_vector_sg3) | SG_LIST_LEN_LAST), + cpu_to_le32(src_addr_3) }, + }; + + /* Check engine is idle, no busy or irq bits set */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Write test vector into memory */ + qtest_memwrite(s, src_addr_1, test_vector_sg1, sizeof(test_vector_sg1)= ); + qtest_memwrite(s, src_addr_2, test_vector_sg2, sizeof(test_vector_sg2)= ); + qtest_memwrite(s, src_addr_3, test_vector_sg3, sizeof(test_vector_sg3)= ); + qtest_memwrite(s, src_addr, array, sizeof(array)); + + write_regs(s, base, src_addr, + (sizeof(test_vector_sg1) + + sizeof(test_vector_sg2) + + sizeof(test_vector_sg3)), + digest_addr, HACE_ALGO_SHA384 | HACE_SG_EN); + + /* Check hash IRQ status is asserted */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); + + /* Clear IRQ status and check status is deasserted */ + qtest_writel(s, base + HACE_STS, 0x00000200); + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Read computed digest from memory */ + qtest_memread(s, digest_addr, digest, sizeof(digest)); + + /* Check result of computation */ + g_assert_cmpmem(digest, sizeof(digest), + test_result_sg_sha384, sizeof(digest)); + + qtest_quit(s); +} + void aspeed_test_sha512_sg(const char *machine, const uint32_t base, const uint32_t src_addr) { @@ -372,6 +493,47 @@ void aspeed_test_sha256_accum(const char *machine, con= st uint32_t base, qtest_quit(s); } =20 +void aspeed_test_sha384_accum(const char *machine, const uint32_t base, + const uint32_t src_addr) +{ + QTestState *s =3D qtest_init(machine); + + const uint32_t buffer_addr =3D src_addr + 0x10000; + const uint32_t digest_addr =3D src_addr + 0x40000; + uint8_t digest[48] =3D {0}; + struct AspeedSgList array[] =3D { + { cpu_to_le32(sizeof(test_vector_accum_384) | SG_LIST_LEN_LAST), + cpu_to_le32(buffer_addr) }, + }; + + /* Check engine is idle, no busy or irq bits set */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Write test vector into memory */ + qtest_memwrite(s, buffer_addr, test_vector_accum_384, + sizeof(test_vector_accum_384)); + qtest_memwrite(s, src_addr, array, sizeof(array)); + + write_regs(s, base, src_addr, sizeof(test_vector_accum_384), + digest_addr, HACE_ALGO_SHA384 | HACE_SG_EN | HACE_ACCUM_EN); + + /* Check hash IRQ status is asserted */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); + + /* Clear IRQ status and check status is deasserted */ + qtest_writel(s, base + HACE_STS, 0x00000200); + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Read computed digest from memory */ + qtest_memread(s, digest_addr, digest, sizeof(digest)); + + /* Check result of computation */ + g_assert_cmpmem(digest, sizeof(digest), + test_result_accum_sha384, sizeof(digest)); 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Tue, 13 May 2025 02:31:55 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 13 May 2025 14:29:09 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 13 May 2025 14:29:09 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v2 19/25] test/qtest/hace: Add SHA-384 tests for AST2600 Date: Tue, 13 May 2025 14:28:49 +0800 Message-ID: <20250513062901.2256865-20-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> References: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1747118118447116600 Introduced "test_sha384_ast2600" to validate SHA-384 hashing. Added "test_sha384_sg_ast2600" for scatter-gather SHA-384 verification. Implemented "test_sha384_accum_ast2600" to test SHA-384 accumulation. Registered new test cases in "main" to ensure execution. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- tests/qtest/aspeed_hace-test.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/tests/qtest/aspeed_hace-test.c b/tests/qtest/aspeed_hace-test.c index 42a306af2a..ab0c98330e 100644 --- a/tests/qtest/aspeed_hace-test.c +++ b/tests/qtest/aspeed_hace-test.c @@ -44,6 +44,16 @@ static void test_sha256_sg_ast2600(void) aspeed_test_sha256_sg("-machine ast2600-evb", 0x1e6d0000, 0x80000000); } =20 +static void test_sha384_ast2600(void) +{ + aspeed_test_sha384("-machine ast2600-evb", 0x1e6d0000, 0x80000000); +} + +static void test_sha384_sg_ast2600(void) +{ + aspeed_test_sha384_sg("-machine ast2600-evb", 0x1e6d0000, 0x80000000); +} + static void test_sha512_ast2600(void) { aspeed_test_sha512("-machine ast2600-evb", 0x1e6d0000, 0x80000000); @@ -59,6 +69,11 @@ static void test_sha256_accum_ast2600(void) aspeed_test_sha256_accum("-machine ast2600-evb", 0x1e6d0000, 0x8000000= 0); } =20 +static void test_sha384_accum_ast2600(void) +{ + aspeed_test_sha384_accum("-machine ast2600-evb", 0x1e6d0000, 0x8000000= 0); +} + static void test_sha512_accum_ast2600(void) { aspeed_test_sha512_accum("-machine ast2600-evb", 0x1e6d0000, 0x8000000= 0); @@ -117,13 +132,16 @@ int main(int argc, char **argv) =20 qtest_add_func("ast2600/hace/addresses", test_addresses_ast2600); qtest_add_func("ast2600/hace/sha512", test_sha512_ast2600); + qtest_add_func("ast2600/hace/sha384", test_sha384_ast2600); qtest_add_func("ast2600/hace/sha256", test_sha256_ast2600); qtest_add_func("ast2600/hace/md5", test_md5_ast2600); =20 qtest_add_func("ast2600/hace/sha512_sg", test_sha512_sg_ast2600); + qtest_add_func("ast2600/hace/sha384_sg", test_sha384_sg_ast2600); qtest_add_func("ast2600/hace/sha256_sg", test_sha256_sg_ast2600); =20 qtest_add_func("ast2600/hace/sha512_accum", test_sha512_accum_ast2600); + qtest_add_func("ast2600/hace/sha384_accum", test_sha384_accum_ast2600); qtest_add_func("ast2600/hace/sha256_accum", test_sha256_accum_ast2600); =20 qtest_add_func("ast2500/hace/addresses", test_addresses_ast2500); --=20 2.43.0 From nobody Sat Nov 15 20:52:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1747118170; cv=none; d=zohomail.com; s=zohoarc; b=jFn1lqxT+JNEIKu+uHDxCFtjiqgum+H/kZjIfv4fHQwW6CJRoHkr+R8IvmvLzx3w3c4pvEZChxFdHJ5wV9iy9+n6XCqnxdHC7yUUY/KGPV7hHqmJMx1fppVPC6BCJjbQi+YaCawOTEhe6v3ym4YZ6Fpu+VL1NVEevpV6FKfvTs8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747118170; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=TVc5oHSzKLTCtQ/LrmiHMHtyrdBfEcvDjhEI2AkTAW0=; b=KHFEqW118EQ4u8IeFgEGXd69/WuoqMcE32Vn8l+01DCA7Rzaemb4TOLJRP60J2UtYADoZ5l5qWt4u8Ah+f9Q6uBPFWYJs5J5hvexITheyrRn5ZpmWV7dMXKen+SniuZn3hSKsonaowBXi44ZGs5wRHPBDRcheVeFCw5c2yjq+rw= ARC-Authentication-Results: i=1; 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Tue, 13 May 2025 14:29:09 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 13 May 2025 14:29:09 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v2 20/25] test/qtest/hace: Add tests for AST1030 Date: Tue, 13 May 2025 14:28:50 +0800 Message-ID: <20250513062901.2256865-21-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> References: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1747118170984116600 The HACE model in AST2600 and AST1030 is identical. Referencing the AST2600 test cases, new tests have been created for AST1030. Implemented test functions for SHA-256, SHA-384, SHA-512, and MD5. Added scatter-gather and accumulation test variants. For AST1030, the HACE controller base address starts at "0x7e6d0000", and t= he SDRAM start address is "0x0". Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- tests/qtest/aspeed_hace-test.c | 76 ++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/tests/qtest/aspeed_hace-test.c b/tests/qtest/aspeed_hace-test.c index ab0c98330e..31890d574e 100644 --- a/tests/qtest/aspeed_hace-test.c +++ b/tests/qtest/aspeed_hace-test.c @@ -10,6 +10,12 @@ #include "qemu/bitops.h" #include "aspeed-hace-utils.h" =20 +static const struct AspeedMasks ast1030_masks =3D { + .src =3D 0x7fffffff, + .dest =3D 0x7ffffff8, + .len =3D 0x0fffffff, +}; + static const struct AspeedMasks ast2600_masks =3D { .src =3D 0x7fffffff, .dest =3D 0x7ffffff8, @@ -28,6 +34,62 @@ static const struct AspeedMasks ast2400_masks =3D { .len =3D 0x0fffffff, }; =20 +/* ast1030 */ +static void test_md5_ast1030(void) +{ + aspeed_test_md5("-machine ast1030-evb", 0x7e6d0000, 0x00000000); +} + +static void test_sha256_ast1030(void) +{ + aspeed_test_sha256("-machine ast1030-evb", 0x7e6d0000, 0x00000000); +} + +static void test_sha256_sg_ast1030(void) +{ + aspeed_test_sha256_sg("-machine ast1030-evb", 0x7e6d0000, 0x00000000); +} + +static void test_sha384_ast1030(void) +{ + aspeed_test_sha384("-machine ast1030-evb", 0x7e6d0000, 0x00000000); +} + +static void test_sha384_sg_ast1030(void) +{ + aspeed_test_sha384_sg("-machine ast1030-evb", 0x7e6d0000, 0x00000000); +} + +static void test_sha512_ast1030(void) +{ + aspeed_test_sha512("-machine ast1030-evb", 0x7e6d0000, 0x00000000); +} + +static void test_sha512_sg_ast1030(void) +{ + aspeed_test_sha512_sg("-machine ast1030-evb", 0x7e6d0000, 0x00000000); +} + +static void test_sha256_accum_ast1030(void) +{ + aspeed_test_sha256_accum("-machine ast1030-evb", 0x7e6d0000, 0x0000000= 0); +} + +static void test_sha384_accum_ast1030(void) +{ + aspeed_test_sha384_accum("-machine ast1030-evb", 0x7e6d0000, 0x0000000= 0); +} + +static void test_sha512_accum_ast1030(void) +{ + aspeed_test_sha512_accum("-machine ast1030-evb", 0x7e6d0000, 0x0000000= 0); +} + +static void test_addresses_ast1030(void) +{ + aspeed_test_addresses("-machine ast1030-evb", 0x7e6d0000, &ast1030_mas= ks); +} + /* ast2600 */ static void test_md5_ast2600(void) { @@ -130,6 +192,20 @@ int main(int argc, char **argv) { g_test_init(&argc, &argv, NULL); =20 + qtest_add_func("ast1030/hace/addresses", test_addresses_ast1030); + qtest_add_func("ast1030/hace/sha512", test_sha512_ast1030); + qtest_add_func("ast1030/hace/sha384", test_sha384_ast1030); + qtest_add_func("ast1030/hace/sha256", test_sha256_ast1030); + qtest_add_func("ast1030/hace/md5", test_md5_ast1030); + + qtest_add_func("ast1030/hace/sha512_sg", test_sha512_sg_ast1030); + qtest_add_func("ast1030/hace/sha384_sg", test_sha384_sg_ast1030); + qtest_add_func("ast1030/hace/sha256_sg", test_sha256_sg_ast1030); + + qtest_add_func("ast1030/hace/sha512_accum", test_sha512_accum_ast1030); + qtest_add_func("ast1030/hace/sha384_accum", test_sha384_accum_ast1030); + qtest_add_func("ast1030/hace/sha256_accum", test_sha256_accum_ast1030); + qtest_add_func("ast2600/hace/addresses", test_addresses_ast2600); qtest_add_func("ast2600/hace/sha512", test_sha512_ast2600); qtest_add_func("ast2600/hace/sha384", test_sha384_ast2600); --=20 2.43.0 From nobody Sat Nov 15 20:52:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1747118135; cv=none; d=zohomail.com; s=zohoarc; b=EJh668QfG/B9nL6oAlN6mBmBJRYObxJSKEBsMYSmDWVeLuBt+8+qqgce3zwklmjnU/DjQP57PqlNUETLgO+93m/TV/l1EBUBeh+qiH+81AuIunqFJvoSZ3W5GOHGUo02/B3LkK1vaDQ/xL6Ns5jK0xv84m4SZrKMBAmL6FfcLSM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747118135; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=0LIupLKkwr6LGbDe/jSTvQVyvgv/LKgNCYRBFPmWkoI=; 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Tue, 13 May 2025 02:32:05 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 13 May 2025 14:29:09 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 13 May 2025 14:29:09 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v2 21/25] test/qtest/hace: Update source data and digest data type to 64-bit Date: Tue, 13 May 2025 14:28:51 +0800 Message-ID: <20250513062901.2256865-22-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> References: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1747118136988019000 Content-Type: text/plain; charset="utf-8" Currently, the hash data source and digest result buffer addresses are set = to 32-bit. However, the AST2700 CPU is a 64-bit Cortex-A35 architecture, and i= ts DRAM base address is also 64-bit. To support AST2700, update the hash data source address and digest result b= uffer address to use 64-bit addressing. Signed-off-by: Jamin Lin --- tests/qtest/aspeed-hace-utils.h | 20 ++++----- tests/qtest/aspeed-hace-utils.c | 72 ++++++++++++++++----------------- 2 files changed, 46 insertions(+), 46 deletions(-) diff --git a/tests/qtest/aspeed-hace-utils.h b/tests/qtest/aspeed-hace-util= s.h index f4440561de..0382570fa2 100644 --- a/tests/qtest/aspeed-hace-utils.h +++ b/tests/qtest/aspeed-hace-utils.h @@ -51,25 +51,25 @@ struct AspeedMasks { }; =20 void aspeed_test_md5(const char *machine, const uint32_t base, - const uint32_t src_addr); + const uint64_t src_addr); void aspeed_test_sha256(const char *machine, const uint32_t base, - const uint32_t src_addr); + const uint64_t src_addr); void aspeed_test_sha384(const char *machine, const uint32_t base, - const uint32_t src_addr); + const uint64_t src_addr); void aspeed_test_sha512(const char *machine, const uint32_t base, - const uint32_t src_addr); + const uint64_t src_addr); void aspeed_test_sha256_sg(const char *machine, const uint32_t base, - const uint32_t src_addr); + const uint64_t src_addr); void aspeed_test_sha384_sg(const char *machine, const uint32_t base, - const uint32_t src_addr); + const uint64_t src_addr); void aspeed_test_sha512_sg(const char *machine, const uint32_t base, - const uint32_t src_addr); + const uint64_t src_addr); void aspeed_test_sha256_accum(const char *machine, const uint32_t base, - const uint32_t src_addr); + const uint64_t src_addr); void aspeed_test_sha384_accum(const char *machine, const uint32_t base, - const uint32_t src_addr); + const uint64_t src_addr); void aspeed_test_sha512_accum(const char *machine, const uint32_t base, - const uint32_t src_addr); + const uint64_t src_addr); void aspeed_test_addresses(const char *machine, const uint32_t base, const struct AspeedMasks *expected); =20 diff --git a/tests/qtest/aspeed-hace-utils.c b/tests/qtest/aspeed-hace-util= s.c index dad90ee81c..1b54870dd4 100644 --- a/tests/qtest/aspeed-hace-utils.c +++ b/tests/qtest/aspeed-hace-utils.c @@ -153,22 +153,22 @@ static const uint8_t test_result_accum_sha256[32] =3D= { 0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c, 0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad}; =20 -static void write_regs(QTestState *s, uint32_t base, uint32_t src, - uint32_t length, uint32_t out, uint32_t method) +static void write_regs(QTestState *s, uint32_t base, uint64_t src, + uint32_t length, uint64_t out, uint32_t method) { - qtest_writel(s, base + HACE_HASH_SRC, src); - qtest_writel(s, base + HACE_HASH_DIGEST, out); + qtest_writel(s, base + HACE_HASH_SRC, extract64(src, 0, 32)); + qtest_writel(s, base + HACE_HASH_DIGEST, extract64(out, 0, 32)); qtest_writel(s, base + HACE_HASH_DATA_LEN, length); qtest_writel(s, base + HACE_HASH_CMD, HACE_SHA_BE_EN | method); } =20 void aspeed_test_md5(const char *machine, const uint32_t base, - const uint32_t src_addr) + const uint64_t src_addr) =20 { QTestState *s =3D qtest_init(machine); =20 - uint32_t digest_addr =3D src_addr + 0x010000; + uint64_t digest_addr =3D src_addr + 0x010000; uint8_t digest[16] =3D {0}; =20 /* Check engine is idle, no busy or irq bits set */ @@ -198,11 +198,11 @@ void aspeed_test_md5(const char *machine, const uint3= 2_t base, } =20 void aspeed_test_sha256(const char *machine, const uint32_t base, - const uint32_t src_addr) + const uint64_t src_addr) { QTestState *s =3D qtest_init(machine); =20 - const uint32_t digest_addr =3D src_addr + 0x10000; + const uint64_t digest_addr =3D src_addr + 0x10000; uint8_t digest[32] =3D {0}; =20 /* Check engine is idle, no busy or irq bits set */ @@ -232,11 +232,11 @@ void aspeed_test_sha256(const char *machine, const ui= nt32_t base, } =20 void aspeed_test_sha384(const char *machine, const uint32_t base, - const uint32_t src_addr) + const uint64_t src_addr) { QTestState *s =3D qtest_init(machine); =20 - const uint32_t digest_addr =3D src_addr + 0x10000; + const uint64_t digest_addr =3D src_addr + 0x10000; uint8_t digest[48] =3D {0}; =20 /* Check engine is idle, no busy or irq bits set */ @@ -266,11 +266,11 @@ void aspeed_test_sha384(const char *machine, const ui= nt32_t base, } =20 void aspeed_test_sha512(const char *machine, const uint32_t base, - const uint32_t src_addr) + const uint64_t src_addr) { QTestState *s =3D qtest_init(machine); =20 - const uint32_t digest_addr =3D src_addr + 0x10000; + const uint64_t digest_addr =3D src_addr + 0x10000; uint8_t digest[64] =3D {0}; =20 /* Check engine is idle, no busy or irq bits set */ @@ -300,14 +300,14 @@ void aspeed_test_sha512(const char *machine, const ui= nt32_t base, } =20 void aspeed_test_sha256_sg(const char *machine, const uint32_t base, - const uint32_t src_addr) + const uint64_t src_addr) { QTestState *s =3D qtest_init(machine); =20 - const uint32_t src_addr_1 =3D src_addr + 0x10000; - const uint32_t src_addr_2 =3D src_addr + 0x20000; - const uint32_t src_addr_3 =3D src_addr + 0x30000; - const uint32_t digest_addr =3D src_addr + 0x40000; + const uint64_t src_addr_1 =3D src_addr + 0x10000; + const uint64_t src_addr_2 =3D src_addr + 0x20000; + const uint64_t src_addr_3 =3D src_addr + 0x30000; + const uint64_t digest_addr =3D src_addr + 0x40000; uint8_t digest[32] =3D {0}; struct AspeedSgList array[] =3D { { cpu_to_le32(sizeof(test_vector_sg1)), @@ -351,14 +351,14 @@ void aspeed_test_sha256_sg(const char *machine, const= uint32_t base, } =20 void aspeed_test_sha384_sg(const char *machine, const uint32_t base, - const uint32_t src_addr) + const uint64_t src_addr) { QTestState *s =3D qtest_init(machine); =20 - const uint32_t src_addr_1 =3D src_addr + 0x10000; - const uint32_t src_addr_2 =3D src_addr + 0x20000; - const uint32_t src_addr_3 =3D src_addr + 0x30000; - const uint32_t digest_addr =3D src_addr + 0x40000; + const uint64_t src_addr_1 =3D src_addr + 0x10000; + const uint64_t src_addr_2 =3D src_addr + 0x20000; + const uint64_t src_addr_3 =3D src_addr + 0x30000; + const uint64_t digest_addr =3D src_addr + 0x40000; uint8_t digest[48] =3D {0}; struct AspeedSgList array[] =3D { { cpu_to_le32(sizeof(test_vector_sg1)), @@ -402,14 +402,14 @@ void aspeed_test_sha384_sg(const char *machine, const= uint32_t base, } =20 void aspeed_test_sha512_sg(const char *machine, const uint32_t base, - const uint32_t src_addr) + const uint64_t src_addr) { QTestState *s =3D qtest_init(machine); =20 - const uint32_t src_addr_1 =3D src_addr + 0x10000; - const uint32_t src_addr_2 =3D src_addr + 0x20000; - const uint32_t src_addr_3 =3D src_addr + 0x30000; - const uint32_t digest_addr =3D src_addr + 0x40000; + const uint64_t src_addr_1 =3D src_addr + 0x10000; + const uint64_t src_addr_2 =3D src_addr + 0x20000; + const uint64_t src_addr_3 =3D src_addr + 0x30000; + const uint64_t digest_addr =3D src_addr + 0x40000; uint8_t digest[64] =3D {0}; struct AspeedSgList array[] =3D { { cpu_to_le32(sizeof(test_vector_sg1)), @@ -453,12 +453,12 @@ void aspeed_test_sha512_sg(const char *machine, const= uint32_t base, } =20 void aspeed_test_sha256_accum(const char *machine, const uint32_t base, - const uint32_t src_addr) + const uint64_t src_addr) { QTestState *s =3D qtest_init(machine); =20 - const uint32_t buffer_addr =3D src_addr + 0x10000; - const uint32_t digest_addr =3D src_addr + 0x40000; + const uint64_t buffer_addr =3D src_addr + 0x10000; + const uint64_t digest_addr =3D src_addr + 0x40000; uint8_t digest[32] =3D {0}; struct AspeedSgList array[] =3D { { cpu_to_le32(sizeof(test_vector_accum_256) | SG_LIST_LEN_LAST), @@ -494,12 +494,12 @@ void aspeed_test_sha256_accum(const char *machine, co= nst uint32_t base, } =20 void aspeed_test_sha384_accum(const char *machine, const uint32_t base, - const uint32_t src_addr) + const uint64_t src_addr) { QTestState *s =3D qtest_init(machine); =20 - const uint32_t buffer_addr =3D src_addr + 0x10000; - const uint32_t digest_addr =3D src_addr + 0x40000; + const uint64_t buffer_addr =3D src_addr + 0x10000; + const uint64_t digest_addr =3D src_addr + 0x40000; uint8_t digest[48] =3D {0}; struct AspeedSgList array[] =3D { { cpu_to_le32(sizeof(test_vector_accum_384) | SG_LIST_LEN_LAST), @@ -535,12 +535,12 @@ void aspeed_test_sha384_accum(const char *machine, co= nst uint32_t base, } =20 void aspeed_test_sha512_accum(const char *machine, const uint32_t base, - const uint32_t src_addr) + const uint64_t src_addr) { QTestState *s =3D qtest_init(machine); =20 - const uint32_t buffer_addr =3D src_addr + 0x10000; - const uint32_t digest_addr =3D src_addr + 0x40000; + const uint64_t buffer_addr =3D src_addr + 0x10000; + const uint64_t digest_addr =3D src_addr + 0x40000; uint8_t digest[64] =3D {0}; struct AspeedSgList array[] =3D { { cpu_to_le32(sizeof(test_vector_accum_512) | SG_LIST_LEN_LAST), --=20 2.43.0 From nobody Sat Nov 15 20:52:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 13 May 2025 14:29:10 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 13 May 2025 14:29:10 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v2 22/25] test/qtest/hace: Support 64-bit source and digest addresses for AST2700 Date: Tue, 13 May 2025 14:28:52 +0800 Message-ID: <20250513062901.2256865-23-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> References: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1747118172879116600 Added "HACE_HASH_SRC_HI" and "HACE_HASH_DIGEST_HI", "HACE_HASH_KEY_BUFF_HI" registers to store upper 32 bits. Updated "write_regs" to handle 64-bit source and digest addresses. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- tests/qtest/aspeed-hace-utils.h | 3 +++ tests/qtest/aspeed-hace-utils.c | 2 ++ 2 files changed, 5 insertions(+) diff --git a/tests/qtest/aspeed-hace-utils.h b/tests/qtest/aspeed-hace-util= s.h index 0382570fa2..d8684d3f83 100644 --- a/tests/qtest/aspeed-hace-utils.h +++ b/tests/qtest/aspeed-hace-utils.h @@ -36,6 +36,9 @@ #define HACE_HASH_KEY_BUFF 0x28 #define HACE_HASH_DATA_LEN 0x2c #define HACE_HASH_CMD 0x30 +#define HACE_HASH_SRC_HI 0x90 +#define HACE_HASH_DIGEST_HI 0x94 +#define HACE_HASH_KEY_BUFF_HI 0x98 =20 /* Scatter-Gather Hash */ #define SG_LIST_LEN_LAST BIT(31) diff --git a/tests/qtest/aspeed-hace-utils.c b/tests/qtest/aspeed-hace-util= s.c index 1b54870dd4..842bf5630d 100644 --- a/tests/qtest/aspeed-hace-utils.c +++ b/tests/qtest/aspeed-hace-utils.c @@ -157,7 +157,9 @@ static void write_regs(QTestState *s, uint32_t base, ui= nt64_t src, uint32_t length, uint64_t out, uint32_t method) { qtest_writel(s, base + HACE_HASH_SRC, extract64(src, 0, 32)); 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Tue, 13 May 2025 02:35:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEjBT-0005nf-SU; Tue, 13 May 2025 02:32:14 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEjBS-00029w-2C; Tue, 13 May 2025 02:32:11 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 13 May 2025 14:29:10 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 13 May 2025 14:29:10 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v2 23/25] test/qtest/hace: Support to test upper 32 bits of digest and source addresses Date: Tue, 13 May 2025 14:28:53 +0800 Message-ID: <20250513062901.2256865-24-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> References: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1747118140806019000 Added "src_hi" and "dest_hi" fields to "AspeedMasks" for 64-bit addresses t= est. Updated "aspeed_test_addresses" to validate "HACE_HASH_SRC_HI" and "HACE_HASH_DIGEST_HI". Ensured correct masking of 64-bit addresses by checking both lower and upper 32-bit registers. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- tests/qtest/aspeed-hace-utils.h | 2 ++ tests/qtest/aspeed-hace-utils.c | 15 ++++++++++++++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/tests/qtest/aspeed-hace-utils.h b/tests/qtest/aspeed-hace-util= s.h index d8684d3f83..de8055a1db 100644 --- a/tests/qtest/aspeed-hace-utils.h +++ b/tests/qtest/aspeed-hace-utils.h @@ -51,6 +51,8 @@ struct AspeedMasks { uint32_t src; uint32_t dest; uint32_t len; + uint32_t src_hi; + uint32_t dest_hi; }; =20 void aspeed_test_md5(const char *machine, const uint32_t base, diff --git a/tests/qtest/aspeed-hace-utils.c b/tests/qtest/aspeed-hace-util= s.c index 842bf5630d..cb78f18117 100644 --- a/tests/qtest/aspeed-hace-utils.c +++ b/tests/qtest/aspeed-hace-utils.c @@ -588,30 +588,43 @@ void aspeed_test_addresses(const char *machine, const= uint32_t base, */ g_assert_cmphex(qtest_readl(s, base + HACE_CMD), =3D=3D, 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), =3D=3D, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC_HI), =3D=3D, 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), =3D=3D, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), =3D=3D, 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), =3D=3D, 0); =20 - /* Check that the address masking is correct */ qtest_writel(s, base + HACE_HASH_SRC, 0xffffffff); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), =3D=3D, expected= ->src); =20 + qtest_writel(s, base + HACE_HASH_SRC_HI, 0xffffffff); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC_HI), + =3D=3D, expected->src_hi); + qtest_writel(s, base + HACE_HASH_DIGEST, 0xffffffff); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), =3D=3D, expected->dest); =20 + qtest_writel(s, base + HACE_HASH_DIGEST_HI, 0xffffffff); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), =3D=3D, + expected->dest_hi); + qtest_writel(s, base + HACE_HASH_DATA_LEN, 0xffffffff); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), =3D=3D, expected->len); =20 /* Reset to zero */ qtest_writel(s, base + HACE_HASH_SRC, 0); + qtest_writel(s, base + HACE_HASH_SRC_HI, 0); qtest_writel(s, base + HACE_HASH_DIGEST, 0); + qtest_writel(s, base + HACE_HASH_DIGEST_HI, 0); qtest_writel(s, base + HACE_HASH_DATA_LEN, 0); =20 /* Check that all bits are now zero */ g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), =3D=3D, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC_HI), =3D=3D, 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), =3D=3D, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), =3D=3D, 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), =3D=3D, 0); =20 qtest_quit(s); --=20 2.43.0 From nobody Sat Nov 15 20:52:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1747118172552886.3589585386228; Mon, 12 May 2025 23:36:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uEjEI-0002U5-06; Tue, 13 May 2025 02:35:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEjBy-0006J6-FN; Tue, 13 May 2025 02:32:48 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEjBu-00029w-55; Tue, 13 May 2025 02:32:42 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 13 May 2025 14:29:11 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 13 May 2025 14:29:11 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v2 24/25] test/qtest/hace: Support to validate 64-bit hmac key buffer addresses Date: Tue, 13 May 2025 14:28:54 +0800 Message-ID: <20250513062901.2256865-25-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> References: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1747118175040019000 Added "key" and "key_hi" fields to "AspeedMasks" for 64-bit addresses test. Updated "aspeed_test_addresses" to validate "HACE_HASH_KEY_BUFF" and "HACE_HASH_KEY_BUFF_HI". Ensured correct masking of 64-bit addresses by checking both lower and upper 32-bit registers. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- tests/qtest/aspeed-hace-utils.h | 2 ++ tests/qtest/aspeed-hace-utils.c | 14 ++++++++++++++ tests/qtest/aspeed_hace-test.c | 4 ++++ 3 files changed, 20 insertions(+) diff --git a/tests/qtest/aspeed-hace-utils.h b/tests/qtest/aspeed-hace-util= s.h index de8055a1db..c8b2ec45af 100644 --- a/tests/qtest/aspeed-hace-utils.h +++ b/tests/qtest/aspeed-hace-utils.h @@ -50,9 +50,11 @@ struct AspeedSgList { struct AspeedMasks { uint32_t src; uint32_t dest; + uint32_t key; uint32_t len; uint32_t src_hi; uint32_t dest_hi; + uint32_t key_hi; }; =20 void aspeed_test_md5(const char *machine, const uint32_t base, diff --git a/tests/qtest/aspeed-hace-utils.c b/tests/qtest/aspeed-hace-util= s.c index cb78f18117..0f7f911e5e 100644 --- a/tests/qtest/aspeed-hace-utils.c +++ b/tests/qtest/aspeed-hace-utils.c @@ -591,6 +591,8 @@ void aspeed_test_addresses(const char *machine, const u= int32_t base, g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC_HI), =3D=3D, 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), =3D=3D, 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), =3D=3D, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF), =3D=3D, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF_HI), =3D=3D, = 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), =3D=3D, 0); =20 /* Check that the address masking is correct */ @@ -609,6 +611,14 @@ void aspeed_test_addresses(const char *machine, const = uint32_t base, g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), =3D=3D, expected->dest_hi); =20 + qtest_writel(s, base + HACE_HASH_KEY_BUFF, 0xffffffff); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF), =3D=3D, + expected->key); + + qtest_writel(s, base + HACE_HASH_KEY_BUFF_HI, 0xffffffff); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF_HI), =3D=3D, + expected->key_hi); + qtest_writel(s, base + HACE_HASH_DATA_LEN, 0xffffffff); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), =3D=3D, expected->len); @@ -618,6 +628,8 @@ void aspeed_test_addresses(const char *machine, const u= int32_t base, qtest_writel(s, base + HACE_HASH_SRC_HI, 0); qtest_writel(s, base + HACE_HASH_DIGEST, 0); qtest_writel(s, base + HACE_HASH_DIGEST_HI, 0); + qtest_writel(s, base + HACE_HASH_KEY_BUFF, 0); + qtest_writel(s, base + HACE_HASH_KEY_BUFF_HI, 0); qtest_writel(s, base + HACE_HASH_DATA_LEN, 0); =20 /* Check that all bits are now zero */ @@ -625,6 +637,8 @@ void aspeed_test_addresses(const char *machine, const u= int32_t base, g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC_HI), =3D=3D, 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), =3D=3D, 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), =3D=3D, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF), =3D=3D, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF_HI), =3D=3D, = 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), =3D=3D, 0); =20 qtest_quit(s); diff --git a/tests/qtest/aspeed_hace-test.c b/tests/qtest/aspeed_hace-test.c index 31890d574e..38777020ca 100644 --- a/tests/qtest/aspeed_hace-test.c +++ b/tests/qtest/aspeed_hace-test.c @@ -13,24 +13,28 @@ static const struct AspeedMasks ast1030_masks =3D { .src =3D 0x7fffffff, .dest =3D 0x7ffffff8, + .key =3D 0x7ffffff8, .len =3D 0x0fffffff, }; =20 static const struct AspeedMasks ast2600_masks =3D { .src =3D 0x7fffffff, .dest =3D 0x7ffffff8, + .key =3D 0x7ffffff8, .len =3D 0x0fffffff, }; =20 static const struct AspeedMasks ast2500_masks =3D { .src =3D 0x3fffffff, .dest =3D 0x3ffffff8, + .key =3D 0x3fffffc0, .len =3D 0x0fffffff, }; =20 static const struct AspeedMasks ast2400_masks =3D { .src =3D 0x0fffffff, .dest =3D 0x0ffffff8, + .key =3D 0x0fffffc0, .len =3D 0x0fffffff, }; =20 --=20 2.43.0 From nobody Sat Nov 15 20:52:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1747118231; cv=none; d=zohomail.com; s=zohoarc; b=hpMQrPL1IPdJRF6fO8uT+MMbfIm8P0+iJVUZ8M3sdXxAymCCZ+zYGWqNTBsMp44vhP+0jVquuzzWvy9Ep58Wo9OTtF+zFh3+qRUEWBBaPraG1XJrKXn9wux9R/mGRy/PrFry21gIe3IzV6cJRaQ3za0Tw+7b2r84xEZLR5wmdGs= ARC-Message-Signature: i=1; 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Tue, 13 May 2025 02:35:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEjC2-0006Kr-PQ; Tue, 13 May 2025 02:32:51 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uEjC1-0002Ee-07; Tue, 13 May 2025 02:32:46 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 13 May 2025 14:29:11 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 13 May 2025 14:29:11 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v2 25/25] test/qtest/hace: Add tests for AST2700 Date: Tue, 13 May 2025 14:28:55 +0800 Message-ID: <20250513062901.2256865-26-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> References: <20250513062901.2256865-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1747118232972019000 The HACE models in AST2600 and AST2700 are nearly identical. Based on the AST2600 test cases, new tests have been added for AST2700. Implemented test functions for SHA-256, SHA-384, SHA-512, and MD5. Added scatter-gather and accumulation test variants. For AST2700, the HACE controller base address starts at "0x12070000", and the DRAM start address is "0x4_00000000". Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- tests/qtest/ast2700-hace-test.c | 98 +++++++++++++++++++++++++++++++++ tests/qtest/meson.build | 2 + 2 files changed, 100 insertions(+) create mode 100644 tests/qtest/ast2700-hace-test.c diff --git a/tests/qtest/ast2700-hace-test.c b/tests/qtest/ast2700-hace-tes= t.c new file mode 100644 index 0000000000..a400e2962b --- /dev/null +++ b/tests/qtest/ast2700-hace-test.c @@ -0,0 +1,98 @@ +/* + * QTest testcase for the ASPEED Hash and Crypto Engine + * + * SPDX-License-Identifier: GPL-2.0-or-later + * Copyright (C) 2025 ASPEED Technology Inc. + */ + +#include "qemu/osdep.h" +#include "libqtest.h" +#include "qemu/bitops.h" +#include "aspeed-hace-utils.h" + +static const struct AspeedMasks as2700_masks =3D { + .src =3D 0x7fffffff, + .dest =3D 0x7ffffff8, + .key =3D 0x7ffffff8, + .len =3D 0x0fffffff, + .src_hi =3D 0x00000003, + .dest_hi =3D 0x00000003, + .key_hi =3D 0x00000003, +}; + +/* ast2700 */ +static void test_md5_ast2700(void) +{ + aspeed_test_md5("-machine ast2700a1-evb", 0x12070000, 0x400000000); +} + +static void test_sha256_ast2700(void) +{ + aspeed_test_sha256("-machine ast2700a1-evb", 0x12070000, 0x400000000); +} + +static void test_sha256_sg_ast2700(void) +{ + aspeed_test_sha256_sg("-machine ast2700a1-evb", 0x12070000, 0x40000000= 0); +} + +static void test_sha384_ast2700(void) +{ + aspeed_test_sha384("-machine ast2700a1-evb", 0x12070000, 0x400000000); +} + +static void test_sha384_sg_ast2700(void) +{ + aspeed_test_sha384_sg("-machine ast2700a1-evb", 0x12070000, 0x40000000= 0); +} + +static void test_sha512_ast2700(void) +{ + aspeed_test_sha512("-machine ast2700a1-evb", 0x12070000, 0x400000000); +} + +static void test_sha512_sg_ast2700(void) +{ + aspeed_test_sha512_sg("-machine ast2700a1-evb", 0x12070000, 0x40000000= 0); +} + +static void test_sha256_accum_ast2700(void) +{ + aspeed_test_sha256_accum("-machine ast2700a1-evb", 0x12070000, 0x40000= 0000); +} + +static void test_sha384_accum_ast2700(void) +{ + aspeed_test_sha384_accum("-machine ast2700a1-evb", 0x12070000, 0x40000= 0000); +} + +static void test_sha512_accum_ast2700(void) +{ + aspeed_test_sha512_accum("-machine ast2700a1-evb", 0x12070000, 0x40000= 0000); +} + +static void test_addresses_ast2700(void) +{ + aspeed_test_addresses("-machine ast2700a1-evb", 0x12070000, &as2700_ma= sks); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + qtest_add_func("ast2700/hace/addresses", test_addresses_ast2700); + qtest_add_func("ast2700/hace/sha512", test_sha512_ast2700); + qtest_add_func("ast2700/hace/sha384", test_sha384_ast2700); + qtest_add_func("ast2700/hace/sha256", test_sha256_ast2700); + qtest_add_func("ast2700/hace/md5", test_md5_ast2700); + + qtest_add_func("ast2700/hace/sha512_sg", test_sha512_sg_ast2700); + qtest_add_func("ast2700/hace/sha384_sg", test_sha384_sg_ast2700); + qtest_add_func("ast2700/hace/sha256_sg", test_sha256_sg_ast2700); + + qtest_add_func("ast2700/hace/sha512_accum", test_sha512_accum_ast2700); + qtest_add_func("ast2700/hace/sha384_accum", test_sha384_accum_ast2700); + qtest_add_func("ast2700/hace/sha256_accum", test_sha256_accum_ast2700); + + return g_test_run(); +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index bb14a22ebe..c587688f67 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -216,6 +216,7 @@ qtests_aspeed =3D \ 'aspeed_smc-test'] qtests_aspeed64 =3D \ ['ast2700-gpio-test', + 'ast2700-hace-test', 'ast2700-smc-test'] =20 qtests_stm32l4x5 =3D \ @@ -362,6 +363,7 @@ endif qtests =3D { 'aspeed_hace-test': files('aspeed-hace-utils.c', 'aspeed_hace-test.c'), 'aspeed_smc-test': files('aspeed-smc-utils.c', 'aspeed_smc-test.c'), + 'ast2700-hace-test': files('aspeed-hace-utils.c', 'ast2700-hace-test.c'), 'ast2700-smc-test': files('aspeed-smc-utils.c', 'ast2700-smc-test.c'), 'bios-tables-test': [io, 'boot-sector.c', 'acpi-utils.c', 'tpm-emu.c'], 'cdrom-test': files('boot-sector.c'), --=20 2.43.0