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([38.41.223.211]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22fc82a2e4fsm65792005ad.232.2025.05.12.11.05.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 May 2025 11:05:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1747073131; x=1747677931; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ynPpe+7xoYBYdred6SBN6w9Y0IgzDdC2ZAA3L0jAu5s=; b=eFJ0GRLVx+DxDeZWgGHmv4SEG4+1MNLAEGE5f1E04HeD5Wx0vziffJb+EOuRIVMdUw GMH9gqJ6vX61PagfRCUG8v9TQeIMiTar4o3b1XkqBsHtnV4qm964eFvnc7vT/o7BZsN7 TwySzFwWzTa64/6koi6Y0OtYqajcYpe+pHSi2X4dB8mK2mGyBrHbfEqOMEFK8vuxJT9B eL6jXz0+vBmyVUYeO9XV7EcmSKNoAPCuMEbTP3TPtDuegRN4tAgUbskFmB2ZSdrgA5D/ xiSD3Q8CMIBCI9LUXP7UgDM0kT4kF8xDJJtnLZYGBs/NMxL+UYMZHp5HMVMAJ0RsyPVP 3LRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747073131; x=1747677931; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ynPpe+7xoYBYdred6SBN6w9Y0IgzDdC2ZAA3L0jAu5s=; b=BhQY7GcyUZqqZNsdra8JV9Y63hENwge6uvlWgj/682V6Gxyo4T1utfdbUorES+3HET UCEDX8UnfUwhoI0AvT+8VIpDsRqM7l8KCLJ9nn4JZCmyYZl34DIz3RwDv5oXsv6zudwj 2Y0orJeK2zOQyvTW3EMw8whCCIzl+LBPuucRJnndzZeFJNns60qZNMitt3DPOg0V/zUN hYgQehq012nQilaeVQoPkGpb2RUH55IV5FCha2JWS4ztzJ70NKhzypyXQcmFeLB3+I4S MD3wZc/g8wX47KqUQ7ihTJyceDYg9h/OVkpy3arQcsZkPQMnvoQ/8DyEutF+X1KpSxlC MTOQ== X-Gm-Message-State: AOJu0YwchgXZ0ej0gudno06bGqoRDQaycia1dy9AZ2XwmRyrM2tOqFoE HzBssrzJHacuPX7i7UhQfH45jzBmJ4rjv4ITlolc/6eY+tFRxJrGNrt0KSVzB4hx2QI592w6y3Z M X-Gm-Gg: ASbGncvJPlQCbOccEZfsoT4GQSwtUpZSdyVWEX/DqOGioehF2vqTuPbKEpX3TjgtDks Oouqxm6htrgB0QMt/61k+nVueQGRb2jBzZalax/8y5lFkPw4fl6x+OZ6Z7LxhEy3MVx9vUEsIlh YgBAvxHLpq2SLScu3f5uutZrGR+cRubcTMHtm51ESFjTRoUmhu8gjmD02a0qw3qfUwN+/D4wqdq bjIco29FN56nMwIYZ6r6l4I0oyzD00LZ5ehH9IBpSxy1hMH/Pt/lULlN1rT0wcZHtmWxv9sl8uE QhutNVgAOolSGblGdJOqTiVEL29i3S5i+618oWvd3USYVkmde/EKUPUPy7jjHw== X-Google-Smtp-Source: AGHT+IHOIsMsSo9l7r0BSna7qr5cjMQFR4caBJLTeNrnfl8hHoLW5O8u+UyBnmKRl9wmyrnYPFvZiw== X-Received: by 2002:a17:903:41c7:b0:220:be86:a421 with SMTP id d9443c01a7336-22fc9185f46mr214714525ad.38.1747073130756; Mon, 12 May 2025 11:05:30 -0700 (PDT) From: Pierrick Bouvier To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , kvm@vger.kernel.org, alex.bennee@linaro.org, anjo@rev.ng, qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Richard Henderson , Pierrick Bouvier Subject: [PATCH v8 21/48] target/arm/helper: expose aarch64 cpu registration Date: Mon, 12 May 2025 11:04:35 -0700 Message-ID: <20250512180502.2395029-22-pierrick.bouvier@linaro.org> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250512180502.2395029-1-pierrick.bouvier@linaro.org> References: <20250512180502.2395029-1-pierrick.bouvier@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1747073503249019000 associated define_arm_cp_regs are guarded by "cpu_isar_feature(aa64_*)", so it's safe to expose that code for arm target (32 bit). Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Pierrick Bouvier --- target/arm/helper.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index d2607107eb9..92a975bbf78 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6590,7 +6590,6 @@ static const ARMCPRegInfo zcr_reginfo[] =3D { .writefn =3D zcr_write, .raw_writefn =3D raw_write }, }; =20 -#ifdef TARGET_AARCH64 static CPAccessResult access_tpidr2(CPUARMState *env, const ARMCPRegInfo *= ri, bool isread) { @@ -6824,7 +6823,6 @@ static const ARMCPRegInfo nmi_reginfo[] =3D { .writefn =3D aa64_allint_write, .readfn =3D aa64_allint_read, .resetfn =3D arm_cp_reset_ignore }, }; -#endif /* TARGET_AARCH64 */ =20 static void define_pmu_regs(ARMCPU *cpu) { @@ -7016,7 +7014,6 @@ static const ARMCPRegInfo lor_reginfo[] =3D { .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, }; =20 -#ifdef TARGET_AARCH64 static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *r= i, bool isread) { @@ -7509,8 +7506,6 @@ static const ARMCPRegInfo nv2_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.vncr_el2) }, }; =20 -#endif /* TARGET_AARCH64 */ - static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo = *ri, bool isread) { @@ -8951,7 +8946,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &hcrx_el2_reginfo); } =20 -#ifdef TARGET_AARCH64 if (cpu_isar_feature(aa64_sme, cpu)) { define_arm_cp_regs(cpu, sme_reginfo); } @@ -9012,7 +9006,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_nmi, cpu)) { define_arm_cp_regs(cpu, nmi_reginfo); } -#endif =20 if (cpu_isar_feature(any_predinv, cpu)) { define_arm_cp_regs(cpu, predinv_reginfo); --=20 2.47.2