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Iglesias" , Stafford Horne , Yoshinori Sato , Bastian Koppelmann , Max Filippov Subject: [PATCH 03/12] target: Use cpu_pointer_wrap_uint32 for 32-bit targets Date: Sun, 4 May 2025 13:57:04 -0700 Message-ID: <20250504205714.3432096-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250504205714.3432096-1-richard.henderson@linaro.org> References: <20250504205714.3432096-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746392364954116600 Content-Type: text/plain; charset="utf-8" M68K, MicroBlaze, OpenRISC, RX, TriCore and Xtensa are all 32-bit targets. AVR is more complicated, but using a 32-bit wrap preserves current behaviour. Cc: Michael Rolnik Cc: Laurent Vivier Cc: Edgar E. Iglesias Cc: Stafford Horne Cc: Yoshinori Sato Cc: Bastian Koppelmann Cc: Max Filippov Signed-off-by: Richard Henderson Reviewed-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/accel/tcg/cpu-ops.h | 1 + accel/tcg/cputlb.c | 6 ++++++ target/avr/cpu.c | 6 ++++++ target/m68k/cpu.c | 1 + target/microblaze/cpu.c | 1 + target/openrisc/cpu.c | 1 + target/rx/cpu.c | 1 + target/tricore/cpu.c | 1 + target/xtensa/cpu.c | 1 + 9 files changed, 19 insertions(+) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index 4f3b4fd3bc..dd8ea30016 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -326,6 +326,7 @@ int cpu_watchpoint_address_matches(CPUState *cpu, vaddr= addr, vaddr len); * Common pointer_wrap implementations. */ vaddr cpu_pointer_wrap_notreached(CPUState *, int, vaddr, vaddr); +vaddr cpu_pointer_wrap_uint32(CPUState *, int, vaddr, vaddr); =20 #endif =20 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 75cd875948..022d555f48 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2945,3 +2945,9 @@ vaddr cpu_pointer_wrap_notreached(CPUState *cs, int i= dx, vaddr res, vaddr base) { g_assert_not_reached(); } + +/* To be used for strict 32-bit targets. */ +vaddr cpu_pointer_wrap_uint32(CPUState *cs, int idx, vaddr res, vaddr base) +{ + return (uint32_t)res; +} diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 250241541b..6995de6a12 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -250,6 +250,12 @@ static const TCGCPUOps avr_tcg_ops =3D { .cpu_exec_reset =3D cpu_reset, .tlb_fill =3D avr_cpu_tlb_fill, .do_interrupt =3D avr_cpu_do_interrupt, + /* + * TODO: code and data wrapping are different, but for the most part + * AVR only references bytes or aligned code fetches. But we use + * non-aligned MO_16 accesses for stack push/pop. + */ + .pointer_wrap =3D cpu_pointer_wrap_uint32, }; =20 static void avr_cpu_class_init(ObjectClass *oc, const void *data) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index c5196a612e..6a09db3a6f 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -619,6 +619,7 @@ static const TCGCPUOps m68k_tcg_ops =3D { =20 #ifndef CONFIG_USER_ONLY .tlb_fill =3D m68k_cpu_tlb_fill, + .pointer_wrap =3D cpu_pointer_wrap_uint32, .cpu_exec_interrupt =3D m68k_cpu_exec_interrupt, .cpu_exec_halt =3D m68k_cpu_has_work, .cpu_exec_reset =3D cpu_reset, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index d069e40e70..5eff1610c2 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -449,6 +449,7 @@ static const TCGCPUOps mb_tcg_ops =3D { =20 #ifndef CONFIG_USER_ONLY .tlb_fill =3D mb_cpu_tlb_fill, + .pointer_wrap =3D cpu_pointer_wrap_uint32, .cpu_exec_interrupt =3D mb_cpu_exec_interrupt, .cpu_exec_halt =3D mb_cpu_has_work, .cpu_exec_reset =3D cpu_reset, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 054ad33360..dfbb2df643 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -265,6 +265,7 @@ static const TCGCPUOps openrisc_tcg_ops =3D { =20 #ifndef CONFIG_USER_ONLY .tlb_fill =3D openrisc_cpu_tlb_fill, + .pointer_wrap =3D cpu_pointer_wrap_uint32, .cpu_exec_interrupt =3D openrisc_cpu_exec_interrupt, .cpu_exec_halt =3D openrisc_cpu_has_work, .cpu_exec_reset =3D cpu_reset, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 36eba75545..c6dd5d6f83 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -225,6 +225,7 @@ static const TCGCPUOps rx_tcg_ops =3D { .restore_state_to_opc =3D rx_restore_state_to_opc, .mmu_index =3D rx_cpu_mmu_index, .tlb_fill =3D rx_cpu_tlb_fill, + .pointer_wrap =3D cpu_pointer_wrap_uint32, =20 .cpu_exec_interrupt =3D rx_cpu_exec_interrupt, .cpu_exec_halt =3D rx_cpu_has_work, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index e56f90fde9..4f035b6f76 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -190,6 +190,7 @@ static const TCGCPUOps tricore_tcg_ops =3D { .restore_state_to_opc =3D tricore_restore_state_to_opc, .mmu_index =3D tricore_cpu_mmu_index, .tlb_fill =3D tricore_cpu_tlb_fill, + .pointer_wrap =3D cpu_pointer_wrap_uint32, .cpu_exec_interrupt =3D tricore_cpu_exec_interrupt, .cpu_exec_halt =3D tricore_cpu_has_work, .cpu_exec_reset =3D cpu_reset, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 91b71b6caa..ea9b6df3aa 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -318,6 +318,7 @@ static const TCGCPUOps xtensa_tcg_ops =3D { =20 #ifndef CONFIG_USER_ONLY .tlb_fill =3D xtensa_cpu_tlb_fill, + .pointer_wrap =3D cpu_pointer_wrap_uint32, .cpu_exec_interrupt =3D xtensa_cpu_exec_interrupt, .cpu_exec_halt =3D xtensa_cpu_has_work, .cpu_exec_reset =3D cpu_reset, --=20 2.43.0