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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Suravee Suthikulpanit To: CC: , , , , , , , , , , , , Suravee Suthikulpanit Subject: [PATCH v5 1/2] hw/i386/amd_iommu: Isolate AMDVI-PCI from amd-iommu device to allow full control over the PCI device creation Date: Sun, 4 May 2025 17:04:04 +0000 Message-ID: <20250504170405.12623-2-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250504170405.12623-1-suravee.suthikulpanit@amd.com> References: <20250504170405.12623-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 Content-Type: text/plain; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 May 2025 17:04:28.3888 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d6e2e482-d17b-4c93-41ee-08dd8b2dbb0e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000014A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6920 Received-SPF: permerror client-ip=2a01:111:f403:200a::618; envelope-from=Suravee.Suthikulpanit@amd.com; helo=NAM12-MW2-obe.outbound.protection.outlook.com X-Spam_score_int: -34 X-Spam_score: -3.5 X-Spam_bar: --- X-Spam_report: (-3.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.411, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1746378323737019000 Current amd-iommu model internally creates an AMDVI-PCI device. Here is a snippet from info qtree: bus: main-system-bus type System dev: amd-iommu, id "" xtsup =3D false pci-id =3D "" intremap =3D "on" device-iotlb =3D false pt =3D true ... dev: q35-pcihost, id "" MCFG =3D -1 (0xffffffffffffffff) pci-hole64-size =3D 34359738368 (32 GiB) below-4g-mem-size =3D 134217728 (128 MiB) above-4g-mem-size =3D 0 (0 B) smm-ranges =3D true x-pci-hole64-fix =3D true x-config-reg-migration-enabled =3D true bypass-iommu =3D false bus: pcie.0 type PCIE dev: AMDVI-PCI, id "" addr =3D 01.0 romfile =3D "" romsize =3D 4294967295 (0xffffffff) rombar =3D -1 (0xffffffffffffffff) multifunction =3D false x-pcie-lnksta-dllla =3D true x-pcie-extcap-init =3D true failover_pair_id =3D "" acpi-index =3D 0 (0x0) x-pcie-err-unc-mask =3D true x-pcie-ari-nextfn-1 =3D false x-max-bounce-buffer-size =3D 4096 (4 KiB) x-pcie-ext-tag =3D true busnr =3D 0 (0x0) class Class 0806, addr 00:01.0, pci id 1022:0000 (sub 1af4:1100) ... This prohibits users from specifying the PCI topology for the amd-iommu dev= ice, which becomes a problem when trying to support VM migration since it does n= ot guarantee the same enumeration of AMD IOMMU device. Therefore, allow the 'AMDVI-PCI' device to optionally be pre-created and associated with a 'amd-iommu' device via a new 'pci-id' parameter on the latter. For example: -device AMDVI-PCI,id=3Diommupci0,bus=3Dpcie.0,addr=3D0x05 \ -device amd-iommu,intremap=3Don,pt=3Don,xtsup=3Don,pci-id=3Diommupci0 \ For backward-compatibility, internally create the AMDVI-PCI device if not specified on the CLI. Co-developed-by: Daniel P. Berrang=C3=A9 Reviewed-by: Daniel P. Berrang=C3=A9 Signed-off-by: Suravee Suthikulpanit --- hw/i386/acpi-build.c | 8 +++---- hw/i386/amd_iommu.c | 53 ++++++++++++++++++++++++++------------------ hw/i386/amd_iommu.h | 3 ++- 3 files changed, 38 insertions(+), 26 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 3fffa4a332..f4b65701a4 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -2333,10 +2333,10 @@ build_amd_iommu(GArray *table_data, BIOSLinker *lin= ker, const char *oem_id, build_append_int_noprefix(table_data, ivhd_blob->len + 24, 2); /* DeviceID */ build_append_int_noprefix(table_data, - object_property_get_int(OBJECT(&s->pci), "ad= dr", + object_property_get_int(OBJECT(s->pci), "add= r", &error_abort), 2); /* Capability offset */ - build_append_int_noprefix(table_data, s->pci.capab_offset, 2); + build_append_int_noprefix(table_data, s->pci->capab_offset, 2); /* IOMMU base address */ build_append_int_noprefix(table_data, s->mr_mmio.addr, 8); /* PCI Segment Group */ @@ -2368,10 +2368,10 @@ build_amd_iommu(GArray *table_data, BIOSLinker *lin= ker, const char *oem_id, build_append_int_noprefix(table_data, ivhd_blob->len + 40, 2); /* DeviceID */ build_append_int_noprefix(table_data, - object_property_get_int(OBJECT(&s->pci), "ad= dr", + object_property_get_int(OBJECT(s->pci), "add= r", &error_abort), 2); /* Capability offset */ - build_append_int_noprefix(table_data, s->pci.capab_offset, 2); + build_append_int_noprefix(table_data, s->pci->capab_offset, 2); /* IOMMU base address */ build_append_int_noprefix(table_data, s->mr_mmio.addr, 8); /* PCI Segment Group */ diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 2cf7e24a21..f5466fdc98 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -167,11 +167,11 @@ static void amdvi_generate_msi_interrupt(AMDVIState *= s) { MSIMessage msg =3D {}; MemTxAttrs attrs =3D { - .requester_id =3D pci_requester_id(&s->pci.dev) + .requester_id =3D pci_requester_id(&s->pci->dev) }; =20 - if (msi_enabled(&s->pci.dev)) { - msg =3D msi_get_message(&s->pci.dev, 0); + if (msi_enabled(&s->pci->dev)) { + msg =3D msi_get_message(&s->pci->dev, 0); address_space_stl_le(&address_space_memory, msg.address, msg.data, attrs, NULL); } @@ -239,7 +239,7 @@ static void amdvi_page_fault(AMDVIState *s, uint16_t de= vid, info |=3D AMDVI_EVENT_IOPF_I | AMDVI_EVENT_IOPF; amdvi_encode_event(evt, devid, addr, info); amdvi_log_event(s, evt); - pci_word_test_and_set_mask(s->pci.dev.config + PCI_STATUS, + pci_word_test_and_set_mask(s->pci->dev.config + PCI_STATUS, PCI_STATUS_SIG_TARGET_ABORT); } /* @@ -256,7 +256,7 @@ static void amdvi_log_devtab_error(AMDVIState *s, uint1= 6_t devid, =20 amdvi_encode_event(evt, devid, devtab, info); amdvi_log_event(s, evt); - pci_word_test_and_set_mask(s->pci.dev.config + PCI_STATUS, + pci_word_test_and_set_mask(s->pci->dev.config + PCI_STATUS, PCI_STATUS_SIG_TARGET_ABORT); } /* log an event trying to access command buffer @@ -269,7 +269,7 @@ static void amdvi_log_command_error(AMDVIState *s, hwad= dr addr) =20 amdvi_encode_event(evt, 0, addr, info); amdvi_log_event(s, evt); - pci_word_test_and_set_mask(s->pci.dev.config + PCI_STATUS, + pci_word_test_and_set_mask(s->pci->dev.config + PCI_STATUS, PCI_STATUS_SIG_TARGET_ABORT); } /* log an illegal command event @@ -310,7 +310,7 @@ static void amdvi_log_pagetab_error(AMDVIState *s, uint= 16_t devid, info |=3D AMDVI_EVENT_PAGE_TAB_HW_ERROR; amdvi_encode_event(evt, devid, addr, info); amdvi_log_event(s, evt); - pci_word_test_and_set_mask(s->pci.dev.config + PCI_STATUS, + pci_word_test_and_set_mask(s->pci->dev.config + PCI_STATUS, PCI_STATUS_SIG_TARGET_ABORT); } =20 @@ -1607,7 +1607,7 @@ static void amdvi_sysbus_reset(DeviceState *dev) { AMDVIState *s =3D AMD_IOMMU_DEVICE(dev); =20 - msi_reset(&s->pci.dev); + msi_reset(&s->pci->dev); amdvi_init(s); } =20 @@ -1619,14 +1619,32 @@ static void amdvi_sysbus_realize(DeviceState *dev, = Error **errp) X86MachineState *x86ms =3D X86_MACHINE(ms); PCIBus *bus =3D pcms->pcibus; =20 - s->iotlb =3D g_hash_table_new_full(amdvi_uint64_hash, - amdvi_uint64_equal, g_free, g_free); + if (s->pci_id) { + PCIDevice *pdev =3D NULL; + int ret =3D pci_qdev_find_device(s->pci_id, &pdev); =20 - /* This device should take care of IOMMU PCI properties */ - if (!qdev_realize(DEVICE(&s->pci), &bus->qbus, errp)) { - return; + if (ret) { + error_report("Cannot find PCI device '%s'", s->pci_id); + return; + } + + if (!object_dynamic_cast(OBJECT(pdev), TYPE_AMD_IOMMU_PCI)) { + error_report("Device '%s' must be an AMDVI-PCI device type", s= ->pci_id); + return; + } + + s->pci =3D AMD_IOMMU_PCI(pdev); + } else { + s->pci =3D AMD_IOMMU_PCI(object_new(TYPE_AMD_IOMMU_PCI)); + /* This device should take care of IOMMU PCI properties */ + if (!qdev_realize(DEVICE(s->pci), &bus->qbus, errp)) { + return; + } } =20 + s->iotlb =3D g_hash_table_new_full(amdvi_uint64_hash, + amdvi_uint64_equal, g_free, g_free); + /* Pseudo address space under root PCI bus. */ x86ms->ioapic_as =3D amdvi_host_dma_iommu(bus, s, AMDVI_IOAPIC_SB_DEVI= D); =20 @@ -1663,6 +1681,7 @@ static void amdvi_sysbus_realize(DeviceState *dev, Er= ror **errp) =20 static const Property amdvi_properties[] =3D { DEFINE_PROP_BOOL("xtsup", AMDVIState, xtsup, false), + DEFINE_PROP_STRING("pci-id", AMDVIState, pci_id), }; =20 static const VMStateDescription vmstate_amdvi_sysbus =3D { @@ -1670,13 +1689,6 @@ static const VMStateDescription vmstate_amdvi_sysbus= =3D { .unmigratable =3D 1 }; =20 -static void amdvi_sysbus_instance_init(Object *klass) -{ - AMDVIState *s =3D AMD_IOMMU_DEVICE(klass); - - object_initialize(&s->pci, sizeof(s->pci), TYPE_AMD_IOMMU_PCI); -} - static void amdvi_sysbus_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -1696,7 +1708,6 @@ static const TypeInfo amdvi_sysbus =3D { .name =3D TYPE_AMD_IOMMU_DEVICE, .parent =3D TYPE_X86_IOMMU_DEVICE, .instance_size =3D sizeof(AMDVIState), - .instance_init =3D amdvi_sysbus_instance_init, .class_init =3D amdvi_sysbus_class_init }; =20 diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index 28125130c6..7a28181d9c 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -315,7 +315,8 @@ struct AMDVIPCIState { =20 struct AMDVIState { X86IOMMUState iommu; /* IOMMU bus device */ - AMDVIPCIState pci; /* IOMMU PCI device */ + AMDVIPCIState *pci; /* IOMMU PCI device */ + char *pci_id; /* ID of AMDVI-PCI device, if user created= */ =20 uint32_t version; =20 --=20 2.34.1 From nobody Fri Dec 19 16:06:32 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Add migration support for AMD IOMMU model by saving necessary AMDVIState parameters for MMIO registers, device table, command buffer, and event buffers. Also change devtab_len type from size_t to uint64_t to avoid 32-bit build issue. Signed-off-by: Suravee Suthikulpanit --- hw/i386/amd_iommu.c | 48 +++++++++++++++++++++++++++++++++++++++++++++ hw/i386/amd_iommu.h | 2 +- 2 files changed, 49 insertions(+), 1 deletion(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index f5466fdc98..0775c8f3bb 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -1611,8 +1611,55 @@ static void amdvi_sysbus_reset(DeviceState *dev) amdvi_init(s); } =20 +static const VMStateDescription vmstate_amdvi_sysbus_migratable =3D { + .name =3D "amd-iommu", + .version_id =3D 1, + .minimum_version_id =3D 1, + .priority =3D MIG_PRI_IOMMU, + .fields =3D (VMStateField[]) { + /* Updated in amdvi_handle_control_write() */ + VMSTATE_BOOL(enabled, AMDVIState), + VMSTATE_BOOL(ga_enabled, AMDVIState), + VMSTATE_BOOL(ats_enabled, AMDVIState), + VMSTATE_BOOL(cmdbuf_enabled, AMDVIState), + VMSTATE_BOOL(completion_wait_intr, AMDVIState), + VMSTATE_BOOL(evtlog_enabled, AMDVIState), + VMSTATE_BOOL(evtlog_intr, AMDVIState), + /* Updated in amdvi_handle_devtab_write() */ + VMSTATE_UINT64(devtab, AMDVIState), + VMSTATE_UINT64(devtab_len, AMDVIState), + /* Updated in amdvi_handle_cmdbase_write() */ + VMSTATE_UINT64(cmdbuf, AMDVIState), + VMSTATE_UINT64(cmdbuf_len, AMDVIState), + /* Updated in amdvi_handle_cmdhead_write() */ + VMSTATE_UINT32(cmdbuf_head, AMDVIState), + /* Updated in amdvi_handle_cmdtail_write() */ + VMSTATE_UINT32(cmdbuf_tail, AMDVIState), + /* Updated in amdvi_handle_evtbase_write() */ + VMSTATE_UINT64(evtlog, AMDVIState), + VMSTATE_UINT32(evtlog_len, AMDVIState), + /* Updated in amdvi_handle_evthead_write() */ + VMSTATE_UINT32(evtlog_head, AMDVIState), + /* Updated in amdvi_handle_evttail_write() */ + VMSTATE_UINT32(evtlog_tail, AMDVIState), + /* Updated in amdvi_handle_pprbase_write() */ + VMSTATE_UINT64(ppr_log, AMDVIState), + VMSTATE_UINT32(pprlog_len, AMDVIState), + /* Updated in amdvi_handle_pprhead_write() */ + VMSTATE_UINT32(pprlog_head, AMDVIState), + /* Updated in amdvi_handle_tailhead_write() */ + VMSTATE_UINT32(pprlog_tail, AMDVIState), + /* MMIO registers */ + VMSTATE_UINT8_ARRAY(mmior, AMDVIState, AMDVI_MMIO_SIZE), + VMSTATE_UINT8_ARRAY(romask, AMDVIState, AMDVI_MMIO_SIZE), + VMSTATE_UINT8_ARRAY(w1cmask, AMDVIState, AMDVI_MMIO_SIZE), + VMSTATE_END_OF_LIST() + } +}; + static void amdvi_sysbus_realize(DeviceState *dev, Error **errp) { + DeviceClass *dc =3D (DeviceClass *) object_get_class(OBJECT(dev)); AMDVIState *s =3D AMD_IOMMU_DEVICE(dev); MachineState *ms =3D MACHINE(qdev_get_machine()); PCMachineState *pcms =3D PC_MACHINE(ms); @@ -1634,6 +1681,7 @@ static void amdvi_sysbus_realize(DeviceState *dev, Er= ror **errp) } =20 s->pci =3D AMD_IOMMU_PCI(pdev); + dc->vmsd =3D &vmstate_amdvi_sysbus_migratable; } else { s->pci =3D AMD_IOMMU_PCI(object_new(TYPE_AMD_IOMMU_PCI)); /* This device should take care of IOMMU PCI properties */ diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index 7a28181d9c..5672bdef89 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -329,7 +329,7 @@ struct AMDVIState { bool excl_enabled; =20 hwaddr devtab; /* base address device table */ - size_t devtab_len; /* device table length */ + uint64_t devtab_len; /* device table length */ =20 hwaddr cmdbuf; /* command buffer base address */ uint64_t cmdbuf_len; /* command buffer length */ --=20 2.34.1