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Fri, 02 May 2025 14:48:49 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFKAyfooXxXAG+rZMSH15GRgAyIB4EB+ecKaPlpSp0jbfwhiUKTVWPLCtAtI7P7jOhag94f/Q== X-Received: by 2002:a5d:62c7:0:b0:3a0:99e9:bc98 with SMTP id ffacd0b85a97d-3a099e9c21bmr2537457f8f.8.1746222529218; Fri, 02 May 2025 14:48:49 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: wei.liu@kernel.org Subject: [PATCH 3/4] target/i386/emulate: mostly rewrite flags handling Date: Fri, 2 May 2025 23:48:40 +0200 Message-ID: <20250502214841.242584-4-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250502214841.242584-1-pbonzini@redhat.com> References: <20250502214841.242584-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.644, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1746222576619116600 Content-Type: text/plain; charset="utf-8" While Bochs's algorithms are pretty solid, there are small opportunities to improve them or to make their logic more similar to TCG's handling of condition codes. - use a single bit for the difference between bits 0..7 of result and PF. This is useful because "set only ZF" is not a common case. - place SD in the same place as SF - move CF and PO at bits 62 and 63 when target_ulong is 64-bits wide, so that 64-bit ALU operations need fewer shifts - use rotates to move CF and AF from auxbits to their eflags position Signed-off-by: Paolo Bonzini --- target/i386/emulate/x86_flags.h | 12 +- target/i386/emulate/x86_emu.c | 4 +- target/i386/emulate/x86_flags.c | 197 ++++++++++++++------------------ 3 files changed, 86 insertions(+), 127 deletions(-) diff --git a/target/i386/emulate/x86_flags.h b/target/i386/emulate/x86_flag= s.h index 6c175007b57..28b008e5771 100644 --- a/target/i386/emulate/x86_flags.h +++ b/target/i386/emulate/x86_flags.h @@ -28,20 +28,10 @@ void lflags_to_rflags(CPUX86State *env); void rflags_to_lflags(CPUX86State *env); =20 -bool get_PF(CPUX86State *env); -void set_PF(CPUX86State *env, bool val); bool get_CF(CPUX86State *env); void set_CF(CPUX86State *env, bool val); -bool get_AF(CPUX86State *env); -void set_AF(CPUX86State *env, bool val); -bool get_ZF(CPUX86State *env); -void set_ZF(CPUX86State *env, bool val); -bool get_SF(CPUX86State *env); -void set_SF(CPUX86State *env, bool val); -bool get_OF(CPUX86State *env); -void set_OF(CPUX86State *env, bool val); =20 -void SET_FLAGS_OxxxxC(CPUX86State *env, uint32_t new_of, uint32_t new_cf); +void SET_FLAGS_OxxxxC(CPUX86State *env, bool new_of, bool new_cf); =20 void SET_FLAGS_OSZAPC_SUB32(CPUX86State *env, uint32_t v1, uint32_t v2, uint32_t diff); diff --git a/target/i386/emulate/x86_emu.c b/target/i386/emulate/x86_emu.c index 4c07f08942e..61bd5af5bb1 100644 --- a/target/i386/emulate/x86_emu.c +++ b/target/i386/emulate/x86_emu.c @@ -474,10 +474,10 @@ static inline void string_rep(CPUX86State *env, struc= t x86_decode *decode, while (rcx--) { func(env, decode); write_reg(env, R_ECX, rcx, decode->addressing_size); - if ((PREFIX_REP =3D=3D rep) && !get_ZF(env)) { + if ((PREFIX_REP =3D=3D rep) && !env->lflags.result) { break; } - if ((PREFIX_REPN =3D=3D rep) && get_ZF(env)) { + if ((PREFIX_REPN =3D=3D rep) && env->lflags.result) { break; } } diff --git a/target/i386/emulate/x86_flags.c b/target/i386/emulate/x86_flag= s.c index 84e27364a03..c347a951889 100644 --- a/target/i386/emulate/x86_flags.c +++ b/target/i386/emulate/x86_flags.c @@ -29,41 +29,50 @@ #include "x86.h" =20 =20 -/* this is basically bocsh code */ +/* + * The algorithms here are similar to those in Bochs. After an ALU + * operation, RESULT can be used to compute ZF, SF and PF, whereas + * AUXBITS is used to compute AF, CF and OF. In reality, SF and PF are the + * XOR of the value computed from RESULT and the value found in bits 7 and= 2 + * of AUXBITS; this way the same logic can be used to compute the flags + * both before and after an ALU operation. + * + * Compared to the TCG CC_OP codes, this avoids conditionals when converti= ng + * to and from the RFLAGS representation. + */ =20 -#define LF_SIGN_BIT 31 +#define LF_SIGN_BIT (TARGET_LONG_BITS - 1) =20 -#define LF_BIT_SD (0) /* lazy Sign Flag Delta */ -#define LF_BIT_AF (3) /* lazy Adjust flag */ -#define LF_BIT_PDB (8) /* lazy Parity Delta Byte (8 bits) */ -#define LF_BIT_CF (31) /* lazy Carry Flag */ -#define LF_BIT_PO (30) /* lazy Partial Overflow =3D CF ^ OF */ +#define LF_BIT_PD (2) /* lazy Parity Delta, same bit as PF */ +#define LF_BIT_AF (3) /* lazy Adjust flag */ +#define LF_BIT_SD (7) /* lazy Sign Flag Delta, same bit as S= F */ +#define LF_BIT_CF (TARGET_LONG_BITS - 1) /* lazy Carry Flag */ +#define LF_BIT_PO (TARGET_LONG_BITS - 2) /* lazy Partial Overflow =3D= CF ^ OF */ =20 -#define LF_MASK_SD (0x01 << LF_BIT_SD) -#define LF_MASK_AF (0x01 << LF_BIT_AF) -#define LF_MASK_PDB (0xFF << LF_BIT_PDB) -#define LF_MASK_CF (0x01 << LF_BIT_CF) -#define LF_MASK_PO (0x01 << LF_BIT_PO) +#define LF_MASK_PD ((target_ulong)0x01 << LF_BIT_PD) +#define LF_MASK_AF ((target_ulong)0x01 << LF_BIT_AF) +#define LF_MASK_SD ((target_ulong)0x01 << LF_BIT_SD) +#define LF_MASK_CF ((target_ulong)0x01 << LF_BIT_CF) +#define LF_MASK_PO ((target_ulong)0x01 << LF_BIT_PO) =20 /* ******************* */ /* OSZAPC */ /* ******************* */ =20 -/* size, carries, result */ +/* use carries to fill in AF, PO and CF, while ensuring PD and SD are clea= r. + * for full-word operations just clear PD and SD; for smaller operand + * sizes only keep AF in the low byte and shift the carries left to + * place PO and CF in the top two bits. + */ #define SET_FLAGS_OSZAPC_SIZE(size, lf_carries, lf_result) { \ - target_ulong temp =3D ((lf_carries) & (LF_MASK_AF)) | \ - (((lf_carries) >> (size - 2)) << LF_BIT_PO); \ env->lflags.result =3D (target_ulong)(int##size##_t)(lf_result); \ - if ((size) =3D=3D 32) { \ - temp =3D ((lf_carries) & ~(LF_MASK_PDB | LF_MASK_SD)); \ - } else if ((size) =3D=3D 16) { \ - temp =3D ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 16); \ - } else if ((size) =3D=3D 8) { \ - temp =3D ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 24); \ + target_ulong temp =3D (lf_carries); \ + if ((size) =3D=3D TARGET_LONG_BITS) { \ + temp =3D temp & ~(LF_MASK_PD | LF_MASK_SD); \ } else { \ - VM_PANIC("unimplemented"); \ + temp =3D (temp & LF_MASK_AF) | (temp << (TARGET_LONG_BITS - (size)= )); \ } \ - env->lflags.auxbits =3D (target_ulong)(uint32_t)temp; \ + env->lflags.auxbits =3D temp; \ } =20 /* carries, result */ @@ -77,23 +86,18 @@ /* ******************* */ /* OSZAP */ /* ******************* */ -/* size, carries, result */ +/* same as setting OSZAPC, but preserve CF and flip PO if the old value of= CF + * did not match the high bit of lf_carries. */ #define SET_FLAGS_OSZAP_SIZE(size, lf_carries, lf_result) { \ - target_ulong temp =3D ((lf_carries) & (LF_MASK_AF)) | \ - (((lf_carries) >> (size - 2)) << LF_BIT_PO); \ - if ((size) =3D=3D 32) { \ - temp =3D ((lf_carries) & ~(LF_MASK_PDB | LF_MASK_SD)); \ - } else if ((size) =3D=3D 16) { \ - temp =3D ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 16); \ - } else if ((size) =3D=3D 8) { \ - temp =3D ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 24); \ - } else { \ - VM_PANIC("unimplemented"); \ - } \ env->lflags.result =3D (target_ulong)(int##size##_t)(lf_result); \ - target_ulong delta_c =3D (env->lflags.auxbits ^ temp) & LF_MASK_CF; \ - delta_c ^=3D (delta_c >> 1); \ - env->lflags.auxbits =3D (target_ulong)(uint32_t)(temp ^ delta_c); \ + target_ulong temp =3D (lf_carries); \ + if ((size) =3D=3D TARGET_LONG_BITS) { \ + temp =3D (temp & ~(LF_MASK_PD | LF_MASK_SD)); \ + } else { \ + temp =3D (temp & LF_MASK_AF) | (temp << (TARGET_LONG_BITS - (size)= )); \ + } \ + target_ulong cf_changed =3D ((target_long)(env->lflags.auxbits ^ temp)= ) < 0; \ + env->lflags.auxbits =3D temp ^ (cf_changed * (LF_MASK_PO | LF_MASK_CF)= ); \ } =20 /* carries, result */ @@ -104,11 +108,11 @@ #define SET_FLAGS_OSZAP_32(carries, result) \ SET_FLAGS_OSZAP_SIZE(32, carries, result) =20 -void SET_FLAGS_OxxxxC(CPUX86State *env, uint32_t new_of, uint32_t new_cf) +void SET_FLAGS_OxxxxC(CPUX86State *env, bool new_of, bool new_cf) { - uint32_t temp_po =3D new_of ^ new_cf; env->lflags.auxbits &=3D ~(LF_MASK_PO | LF_MASK_CF); - env->lflags.auxbits |=3D (temp_po << LF_BIT_PO) | (new_cf << LF_BIT_CF= ); + env->lflags.auxbits |=3D (-(target_ulong)new_cf << LF_BIT_PO); + env->lflags.auxbits ^=3D ((target_ulong)new_of << LF_BIT_PO); } =20 void SET_FLAGS_OSZAPC_SUB32(CPUX86State *env, uint32_t v1, uint32_t v2, @@ -202,104 +206,69 @@ void SET_FLAGS_OSZAPC_LOGIC8(CPUX86State *env, uint8= _t v1, uint8_t v2, SET_FLAGS_OSZAPC_8(0, diff); } =20 -bool get_PF(CPUX86State *env) +static inline uint32_t get_PF(CPUX86State *env) { - uint32_t temp =3D (255 & env->lflags.result); - temp =3D temp ^ (255 & (env->lflags.auxbits >> LF_BIT_PDB)); - temp =3D (temp ^ (temp >> 4)) & 0x0F; - return (0x9669U >> temp) & 1; + uint8_t temp =3D env->lflags.result; + return ((parity8(temp) - 1) ^ env->lflags.auxbits) & CC_P; } =20 -void set_PF(CPUX86State *env, bool val) +static inline uint32_t get_OF(CPUX86State *env) { - uint32_t temp =3D (255 & env->lflags.result) ^ (!val); - env->lflags.auxbits &=3D ~(LF_MASK_PDB); - env->lflags.auxbits |=3D (temp << LF_BIT_PDB); -} - -bool get_OF(CPUX86State *env) -{ - return ((env->lflags.auxbits + (1U << LF_BIT_PO)) >> LF_BIT_CF) & 1; + return ((env->lflags.auxbits >> (LF_BIT_CF - 11)) + CC_O / 2) & CC_O; } =20 bool get_CF(CPUX86State *env) { - return (env->lflags.auxbits >> LF_BIT_CF) & 1; -} - -void set_OF(CPUX86State *env, bool val) -{ - bool old_cf =3D get_CF(env); - SET_FLAGS_OxxxxC(env, val, old_cf); + return ((target_long)env->lflags.auxbits) < 0; } =20 void set_CF(CPUX86State *env, bool val) { - bool old_of =3D get_OF(env); - SET_FLAGS_OxxxxC(env, old_of, val); + /* If CF changes, flip PO and CF */ + target_ulong temp =3D -(target_ulong)val; + target_ulong cf_changed =3D ((target_long)(env->lflags.auxbits ^ temp)= ) < 0; + env->lflags.auxbits ^=3D cf_changed * (LF_MASK_PO | LF_MASK_CF); } =20 -bool get_AF(CPUX86State *env) +static inline uint32_t get_ZF(CPUX86State *env) { - return (env->lflags.auxbits >> LF_BIT_AF) & 1; + return env->lflags.result ? 0 : CC_Z; } =20 -void set_AF(CPUX86State *env, bool val) +static inline uint32_t get_SF(CPUX86State *env) { - env->lflags.auxbits &=3D ~(LF_MASK_AF); - env->lflags.auxbits |=3D val << LF_BIT_AF; -} - -bool get_ZF(CPUX86State *env) -{ - return !env->lflags.result; -} - -void set_ZF(CPUX86State *env, bool val) -{ - if (val) { - env->lflags.auxbits ^=3D - (((env->lflags.result >> LF_SIGN_BIT) & 1) << LF_BIT_SD); - /* merge the parity bits into the Parity Delta Byte */ - uint32_t temp_pdb =3D (255 & env->lflags.result); - env->lflags.auxbits ^=3D (temp_pdb << LF_BIT_PDB); - /* now zero the .result value */ - env->lflags.result =3D 0; - } else { - env->lflags.result |=3D (1 << 8); - } -} - -bool get_SF(CPUX86State *env) -{ - return ((env->lflags.result >> LF_SIGN_BIT) ^ - (env->lflags.auxbits >> LF_BIT_SD)) & 1; -} - -void set_SF(CPUX86State *env, bool val) -{ - bool temp_sf =3D get_SF(env); - env->lflags.auxbits ^=3D (temp_sf ^ val) << LF_BIT_SD; + return ((env->lflags.result >> (LF_SIGN_BIT - LF_BIT_SD)) ^ + env->lflags.auxbits) & CC_S; } =20 void lflags_to_rflags(CPUX86State *env) { env->eflags &=3D ~(CC_C|CC_P|CC_A|CC_Z|CC_S|CC_O); - env->eflags |=3D get_CF(env) ? CC_C : 0; - env->eflags |=3D get_PF(env) ? CC_P : 0; - env->eflags |=3D get_AF(env) ? CC_A : 0; - env->eflags |=3D get_ZF(env) ? CC_Z : 0; - env->eflags |=3D get_SF(env) ? CC_S : 0; - env->eflags |=3D get_OF(env) ? CC_O : 0; + /* rotate left by one to move carry-out bits into CF and AF */ + env->eflags |=3D ( + (env->lflags.auxbits << 1) | + (env->lflags.auxbits >> (TARGET_LONG_BITS - 1))) & (CC_C | CC_A); + env->eflags |=3D get_SF(env); + env->eflags |=3D get_PF(env); + env->eflags |=3D get_ZF(env); + env->eflags |=3D get_OF(env); } =20 void rflags_to_lflags(CPUX86State *env) { - env->lflags.auxbits =3D env->lflags.result =3D 0; - set_OF(env, env->eflags & CC_O); - set_SF(env, env->eflags & CC_S); - set_ZF(env, env->eflags & CC_Z); - set_AF(env, env->eflags & CC_A); - set_PF(env, env->eflags & CC_P); - set_CF(env, env->eflags & CC_C); + target_ulong cf_xor_of; + + env->lflags.auxbits =3D CC_P; + env->lflags.auxbits ^=3D env->eflags & (CC_S | CC_P); + + /* rotate right by one to move CF and AF into the carry-out positions = */ + env->lflags.auxbits |=3D ( + (env->eflags >> 1) | + (env->eflags << (TARGET_LONG_BITS - 1))) & (CC_C | CC_A); + + cf_xor_of =3D (env->eflags & (CC_C | CC_O)) + (CC_O - CC_C); + env->lflags.auxbits |=3D -cf_xor_of & LF_MASK_PO; + + /* Leave the low byte zero so that parity is not affected. */ + env->lflags.result =3D !(env->eflags & CC_Z) << 8; } --=20 2.49.0