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Fri, 02 May 2025 14:48:46 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGHbzYC8n8muNxZMT4HixA9pL6hMLK/HZjFp6P2v1cjwH6caPNCazsMdiXiBVr31HUA3puizg== X-Received: by 2002:a05:600c:528f:b0:43b:c95f:fd9 with SMTP id 5b1f17b1804b1-441bbea0e11mr41187905e9.5.1746222525660; Fri, 02 May 2025 14:48:45 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: wei.liu@kernel.org Subject: [PATCH 1/4] target/i386/emulate: fix target_ulong format strings Date: Fri, 2 May 2025 23:48:38 +0200 Message-ID: <20250502214841.242584-2-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250502214841.242584-1-pbonzini@redhat.com> References: <20250502214841.242584-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.644, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1746222584585116600 Content-Type: text/plain; charset="utf-8" Do not assume that TARGET_FMT_lx is %llx. Signed-off-by: Paolo Bonzini --- target/i386/emulate/x86_decode.c | 2 +- target/i386/emulate/x86_emu.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/i386/emulate/x86_decode.c b/target/i386/emulate/x86_dec= ode.c index 7efa2f570ea..88be9479a82 100644 --- a/target/i386/emulate/x86_decode.c +++ b/target/i386/emulate/x86_decode.c @@ -26,7 +26,7 @@ =20 static void decode_invalid(CPUX86State *env, struct x86_decode *decode) { - printf("%llx: failed to decode instruction ", env->eip); + printf(TARGET_FMT_lx ": failed to decode instruction ", env->eip); for (int i =3D 0; i < decode->opcode_len; i++) { printf("%x ", decode->opcode[i]); } diff --git a/target/i386/emulate/x86_emu.c b/target/i386/emulate/x86_emu.c index 26a4876aac0..7773b51b95e 100644 --- a/target/i386/emulate/x86_emu.c +++ b/target/i386/emulate/x86_emu.c @@ -1241,7 +1241,7 @@ static void init_cmd_handler(void) bool exec_instruction(CPUX86State *env, struct x86_decode *ins) { if (!_cmd_handler[ins->cmd].handler) { - printf("Unimplemented handler (%llx) for %d (%x %x) \n", env->eip, + printf("Unimplemented handler (" TARGET_FMT_lx ") for %d (%x %x) \= n", env->eip, ins->cmd, ins->opcode[0], ins->opcode_len > 1 ? ins->opcode[1] : 0); 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Fri, 02 May 2025 14:48:48 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFd/SJVH6sNOMJd4gDeW+Jn6AZ/uAL6SZ+sztycAn8JJd2Y8AGjGwcSZJg6orunPqqmjVO9TQ== X-Received: by 2002:a05:6000:4312:b0:3a0:90be:fe79 with SMTP id ffacd0b85a97d-3a099ad1a1emr3753646f8f.9.1746222528032; Fri, 02 May 2025 14:48:48 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: wei.liu@kernel.org Subject: [PATCH 2/4] target/i386/emulate: stop overloading decode->op[N].ptr Date: Fri, 2 May 2025 23:48:39 +0200 Message-ID: <20250502214841.242584-3-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250502214841.242584-1-pbonzini@redhat.com> References: <20250502214841.242584-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.644, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1746222566463116600 Content-Type: text/plain; charset="utf-8" decode->op[N].ptr can contain either a host pointer (!) in CPUState or a guest virtual address. Pass the whole struct to read_val_ext and write_val_ext, so that it can decide the contents based on the operand type. Signed-off-by: Paolo Bonzini --- target/i386/emulate/x86_decode.h | 9 ++- target/i386/emulate/x86_emu.h | 8 +-- target/i386/emulate/x86_decode.c | 74 +++++++++---------- target/i386/emulate/x86_emu.c | 119 ++++++++++++++++--------------- 4 files changed, 109 insertions(+), 101 deletions(-) diff --git a/target/i386/emulate/x86_decode.h b/target/i386/emulate/x86_dec= ode.h index 87cc728598d..497cbdef9c7 100644 --- a/target/i386/emulate/x86_decode.h +++ b/target/i386/emulate/x86_decode.h @@ -266,7 +266,10 @@ typedef struct x86_decode_op { int reg; target_ulong val; =20 - target_ulong ptr; + union { + target_ulong addr; + void *regptr; + }; } x86_decode_op; =20 typedef struct x86_decode { @@ -301,8 +304,8 @@ uint64_t sign(uint64_t val, int size); =20 uint32_t decode_instruction(CPUX86State *env, struct x86_decode *decode); =20 -target_ulong get_reg_ref(CPUX86State *env, int reg, int rex_present, - int is_extended, int size); +void * get_reg_ref(CPUX86State *env, int reg, int rex_present, + int is_extended, int size); target_ulong get_reg_val(CPUX86State *env, int reg, int rex_present, int is_extended, int size); void calc_modrm_operand(CPUX86State *env, struct x86_decode *decode, diff --git a/target/i386/emulate/x86_emu.h b/target/i386/emulate/x86_emu.h index 555b567e2c7..a1a961284b2 100644 --- a/target/i386/emulate/x86_emu.h +++ b/target/i386/emulate/x86_emu.h @@ -42,11 +42,11 @@ void x86_emul_raise_exception(CPUX86State *env, int exc= eption_index, int error_c =20 target_ulong read_reg(CPUX86State *env, int reg, int size); void write_reg(CPUX86State *env, int reg, target_ulong val, int size); -target_ulong read_val_from_reg(target_ulong reg_ptr, int size); -void write_val_to_reg(target_ulong reg_ptr, target_ulong val, int size); -void write_val_ext(CPUX86State *env, target_ulong ptr, target_ulong val, i= nt size); +target_ulong read_val_from_reg(void *reg_ptr, int size); +void write_val_to_reg(void *reg_ptr, target_ulong val, int size); +void write_val_ext(CPUX86State *env, struct x86_decode_op *decode, target_= ulong val, int size); uint8_t *read_mmio(CPUX86State *env, target_ulong ptr, int bytes); -target_ulong read_val_ext(CPUX86State *env, target_ulong ptr, int size); +target_ulong read_val_ext(CPUX86State *env, struct x86_decode_op *decode, = int size); =20 void exec_movzx(CPUX86State *env, struct x86_decode *decode); void exec_shl(CPUX86State *env, struct x86_decode *decode); diff --git a/target/i386/emulate/x86_decode.c b/target/i386/emulate/x86_dec= ode.c index 88be9479a82..2eca39802e3 100644 --- a/target/i386/emulate/x86_decode.c +++ b/target/i386/emulate/x86_decode.c @@ -109,8 +109,8 @@ static void decode_modrm_reg(CPUX86State *env, struct x= 86_decode *decode, { op->type =3D X86_VAR_REG; op->reg =3D decode->modrm.reg; - op->ptr =3D get_reg_ref(env, op->reg, decode->rex.rex, decode->rex.r, - decode->operand_size); + op->regptr =3D get_reg_ref(env, op->reg, decode->rex.rex, decode->rex.= r, + decode->operand_size); } =20 static void decode_rax(CPUX86State *env, struct x86_decode *decode, @@ -119,8 +119,8 @@ static void decode_rax(CPUX86State *env, struct x86_dec= ode *decode, op->type =3D X86_VAR_REG; op->reg =3D R_EAX; /* Since reg is always AX, REX prefix has no impact. */ - op->ptr =3D get_reg_ref(env, op->reg, false, 0, - decode->operand_size); + op->regptr =3D get_reg_ref(env, op->reg, false, 0, + decode->operand_size); } =20 static inline void decode_immediate(CPUX86State *env, struct x86_decode *d= ecode, @@ -262,16 +262,16 @@ static void decode_incgroup(CPUX86State *env, struct = x86_decode *decode) { decode->op[0].type =3D X86_VAR_REG; decode->op[0].reg =3D decode->opcode[0] - 0x40; - decode->op[0].ptr =3D get_reg_ref(env, decode->op[0].reg, decode->rex.= rex, - decode->rex.b, decode->operand_size); + decode->op[0].regptr =3D get_reg_ref(env, decode->op[0].reg, decode->r= ex.rex, + decode->rex.b, decode->operand_size= ); } =20 static void decode_decgroup(CPUX86State *env, struct x86_decode *decode) { decode->op[0].type =3D X86_VAR_REG; decode->op[0].reg =3D decode->opcode[0] - 0x48; - decode->op[0].ptr =3D get_reg_ref(env, decode->op[0].reg, decode->rex.= rex, - decode->rex.b, decode->operand_size); + decode->op[0].regptr =3D get_reg_ref(env, decode->op[0].reg, decode->r= ex.rex, + decode->rex.b, decode->operand_size= ); } =20 static void decode_incgroup2(CPUX86State *env, struct x86_decode *decode) @@ -287,16 +287,16 @@ static void decode_pushgroup(CPUX86State *env, struct= x86_decode *decode) { decode->op[0].type =3D X86_VAR_REG; decode->op[0].reg =3D decode->opcode[0] - 0x50; - decode->op[0].ptr =3D get_reg_ref(env, decode->op[0].reg, decode->rex.= rex, - decode->rex.b, decode->operand_size); + decode->op[0].regptr =3D get_reg_ref(env, decode->op[0].reg, decode->r= ex.rex, + decode->rex.b, decode->operand_size= ); } =20 static void decode_popgroup(CPUX86State *env, struct x86_decode *decode) { decode->op[0].type =3D X86_VAR_REG; decode->op[0].reg =3D decode->opcode[0] - 0x58; - decode->op[0].ptr =3D get_reg_ref(env, decode->op[0].reg, decode->rex.= rex, - decode->rex.b, decode->operand_size); + decode->op[0].regptr =3D get_reg_ref(env, decode->op[0].reg, decode->r= ex.rex, + decode->rex.b, decode->operand_size= ); } =20 static void decode_jxx(CPUX86State *env, struct x86_decode *decode) @@ -377,16 +377,16 @@ static void decode_xchgroup(CPUX86State *env, struct = x86_decode *decode) { decode->op[0].type =3D X86_VAR_REG; decode->op[0].reg =3D decode->opcode[0] - 0x90; - decode->op[0].ptr =3D get_reg_ref(env, decode->op[0].reg, decode->rex.= rex, - decode->rex.b, decode->operand_size); + decode->op[0].regptr =3D get_reg_ref(env, decode->op[0].reg, decode->r= ex.rex, + decode->rex.b, decode->operand_size= ); } =20 static void decode_movgroup(CPUX86State *env, struct x86_decode *decode) { decode->op[0].type =3D X86_VAR_REG; decode->op[0].reg =3D decode->opcode[0] - 0xb8; - decode->op[0].ptr =3D get_reg_ref(env, decode->op[0].reg, decode->rex.= rex, - decode->rex.b, decode->operand_size); + decode->op[0].regptr =3D get_reg_ref(env, decode->op[0].reg, decode->r= ex.rex, + decode->rex.b, decode->operand_size= ); decode_immediate(env, decode, &decode->op[1], decode->operand_size); } =20 @@ -394,15 +394,15 @@ static void fetch_moffs(CPUX86State *env, struct x86_= decode *decode, struct x86_decode_op *op) { op->type =3D X86_VAR_OFFSET; - op->ptr =3D decode_bytes(env, decode, decode->addressing_size); + op->addr =3D decode_bytes(env, decode, decode->addressing_size); } =20 static void decode_movgroup8(CPUX86State *env, struct x86_decode *decode) { decode->op[0].type =3D X86_VAR_REG; decode->op[0].reg =3D decode->opcode[0] - 0xb0; - decode->op[0].ptr =3D get_reg_ref(env, decode->op[0].reg, decode->rex.= rex, - decode->rex.b, decode->operand_size); + decode->op[0].regptr =3D get_reg_ref(env, decode->op[0].reg, decode->r= ex.rex, + decode->rex.b, decode->operand_size= ); decode_immediate(env, decode, &decode->op[1], decode->operand_size); } =20 @@ -411,8 +411,8 @@ static void decode_rcx(CPUX86State *env, struct x86_dec= ode *decode, { op->type =3D X86_VAR_REG; op->reg =3D R_ECX; - op->ptr =3D get_reg_ref(env, op->reg, decode->rex.rex, decode->rex.b, - decode->operand_size); + op->regptr =3D get_reg_ref(env, op->reg, decode->rex.rex, decode->rex.= b, + decode->operand_size); } =20 struct decode_tbl { @@ -631,8 +631,8 @@ static void decode_bswap(CPUX86State *env, struct x86_d= ecode *decode) { decode->op[0].type =3D X86_VAR_REG; decode->op[0].reg =3D decode->opcode[1] - 0xc8; - decode->op[0].ptr =3D get_reg_ref(env, decode->op[0].reg, decode->rex.= rex, - decode->rex.b, decode->operand_size); + decode->op[0].regptr =3D get_reg_ref(env, decode->op[0].reg, decode->r= ex.rex, + decode->rex.b, decode->operand_size= ); } =20 static void decode_d9_4(CPUX86State *env, struct x86_decode *decode) @@ -1656,16 +1656,16 @@ void calc_modrm_operand16(CPUX86State *env, struct = x86_decode *decode, } calc_addr: if (X86_DECODE_CMD_LEA =3D=3D decode->cmd) { - op->ptr =3D (uint16_t)ptr; + op->addr =3D (uint16_t)ptr; } else { - op->ptr =3D decode_linear_addr(env, decode, (uint16_t)ptr, seg); + op->addr =3D decode_linear_addr(env, decode, (uint16_t)ptr, seg); } } =20 -target_ulong get_reg_ref(CPUX86State *env, int reg, int rex_present, +void *get_reg_ref(CPUX86State *env, int reg, int rex_present, int is_extended, int size) { - target_ulong ptr =3D 0; + void *ptr =3D NULL; =20 if (is_extended) { reg |=3D R_R8; @@ -1674,13 +1674,13 @@ target_ulong get_reg_ref(CPUX86State *env, int reg,= int rex_present, switch (size) { case 1: if (is_extended || reg < 4 || rex_present) { - ptr =3D (target_ulong)&RL(env, reg); + ptr =3D &RL(env, reg); } else { - ptr =3D (target_ulong)&RH(env, reg - 4); + ptr =3D &RH(env, reg - 4); } break; default: - ptr =3D (target_ulong)&RRX(env, reg); + ptr =3D &RRX(env, reg); break; } return ptr; @@ -1691,7 +1691,7 @@ target_ulong get_reg_val(CPUX86State *env, int reg, i= nt rex_present, { target_ulong val =3D 0; memcpy(&val, - (void *)get_reg_ref(env, reg, rex_present, is_extended, size), + get_reg_ref(env, reg, rex_present, is_extended, size), size); return val; } @@ -1758,9 +1758,9 @@ void calc_modrm_operand32(CPUX86State *env, struct x8= 6_decode *decode, } =20 if (X86_DECODE_CMD_LEA =3D=3D decode->cmd) { - op->ptr =3D (uint32_t)ptr; + op->addr =3D (uint32_t)ptr; } else { - op->ptr =3D decode_linear_addr(env, decode, (uint32_t)ptr, seg); + op->addr =3D decode_linear_addr(env, decode, (uint32_t)ptr, seg); } } =20 @@ -1788,9 +1788,9 @@ void calc_modrm_operand64(CPUX86State *env, struct x8= 6_decode *decode, } =20 if (X86_DECODE_CMD_LEA =3D=3D decode->cmd) { - op->ptr =3D ptr; + op->addr =3D ptr; } else { - op->ptr =3D decode_linear_addr(env, decode, ptr, seg); + op->addr =3D decode_linear_addr(env, decode, ptr, seg); } } =20 @@ -1801,8 +1801,8 @@ void calc_modrm_operand(CPUX86State *env, struct x86_= decode *decode, if (3 =3D=3D decode->modrm.mod) { op->reg =3D decode->modrm.reg; op->type =3D X86_VAR_REG; - op->ptr =3D get_reg_ref(env, decode->modrm.rm, decode->rex.rex, - decode->rex.b, decode->operand_size); + op->regptr =3D get_reg_ref(env, decode->modrm.rm, decode->rex.rex, + decode->rex.b, decode->operand_size); return; } =20 diff --git a/target/i386/emulate/x86_emu.c b/target/i386/emulate/x86_emu.c index 7773b51b95e..4c07f08942e 100644 --- a/target/i386/emulate/x86_emu.c +++ b/target/i386/emulate/x86_emu.c @@ -52,7 +52,7 @@ uint8_t v2 =3D (uint8_t)decode->op[1].val; \ uint8_t diff =3D v1 cmd v2; \ if (save_res) { \ - write_val_ext(env, decode->op[0].ptr, diff, 1); \ + write_val_ext(env, &decode->op[0], diff, 1); \ } \ FLAGS_FUNC##8(env, v1, v2, diff); \ break; \ @@ -63,7 +63,7 @@ uint16_t v2 =3D (uint16_t)decode->op[1].val; \ uint16_t diff =3D v1 cmd v2; \ if (save_res) { \ - write_val_ext(env, decode->op[0].ptr, diff, 2); \ + write_val_ext(env, &decode->op[0], diff, 2); \ } \ FLAGS_FUNC##16(env, v1, v2, diff); \ break; \ @@ -74,7 +74,7 @@ uint32_t v2 =3D (uint32_t)decode->op[1].val; \ uint32_t diff =3D v1 cmd v2; \ if (save_res) { \ - write_val_ext(env, decode->op[0].ptr, diff, 4); \ + write_val_ext(env, &decode->op[0], diff, 4); \ } \ FLAGS_FUNC##32(env, v1, v2, diff); \ break; \ @@ -121,7 +121,7 @@ void write_reg(CPUX86State *env, int reg, target_ulong = val, int size) } } =20 -target_ulong read_val_from_reg(target_ulong reg_ptr, int size) +target_ulong read_val_from_reg(void *reg_ptr, int size) { target_ulong val; =20 @@ -144,7 +144,7 @@ target_ulong read_val_from_reg(target_ulong reg_ptr, in= t size) return val; } =20 -void write_val_to_reg(target_ulong reg_ptr, target_ulong val, int size) +void write_val_to_reg(void *reg_ptr, target_ulong val, int size) { switch (size) { case 1: @@ -164,18 +164,18 @@ void write_val_to_reg(target_ulong reg_ptr, target_ul= ong val, int size) } } =20 -static bool is_host_reg(CPUX86State *env, target_ulong ptr) +static void write_val_to_mem(CPUX86State *env, target_ulong ptr, target_ul= ong val, int size) { - return (ptr - (target_ulong)&env->regs[0]) < sizeof(env->regs); + emul_ops->write_mem(env_cpu(env), &val, ptr, size); } =20 -void write_val_ext(CPUX86State *env, target_ulong ptr, target_ulong val, i= nt size) +void write_val_ext(CPUX86State *env, struct x86_decode_op *decode, target_= ulong val, int size) { - if (is_host_reg(env, ptr)) { - write_val_to_reg(ptr, val, size); - return; + if (decode->type =3D=3D X86_VAR_REG) { + write_val_to_reg(decode->regptr, val, size); + } else { + write_val_to_mem(env, decode->addr, val, size); } - emul_ops->write_mem(env_cpu(env), &val, ptr, size); } =20 uint8_t *read_mmio(CPUX86State *env, target_ulong ptr, int bytes) @@ -185,15 +185,11 @@ uint8_t *read_mmio(CPUX86State *env, target_ulong ptr= , int bytes) } =20 =20 -target_ulong read_val_ext(CPUX86State *env, target_ulong ptr, int size) +static target_ulong read_val_from_mem(CPUX86State *env, target_long ptr, i= nt size) { target_ulong val; uint8_t *mmio_ptr; =20 - if (is_host_reg(env, ptr)) { - return read_val_from_reg(ptr, size); - } - mmio_ptr =3D read_mmio(env, ptr, size); switch (size) { case 1: @@ -215,6 +211,15 @@ target_ulong read_val_ext(CPUX86State *env, target_ulo= ng ptr, int size) return val; } =20 +target_ulong read_val_ext(CPUX86State *env, struct x86_decode_op *decode, = int size) +{ + if (decode->type =3D=3D X86_VAR_REG) { + return read_val_from_reg(decode->regptr, size); + } else { + return read_val_from_mem(env, decode->addr, size); + } +} + static void fetch_operands(CPUX86State *env, struct x86_decode *decode, int n, bool val_op0, bool val_op1, bool val_op2) { @@ -226,25 +231,25 @@ static void fetch_operands(CPUX86State *env, struct x= 86_decode *decode, case X86_VAR_IMMEDIATE: break; case X86_VAR_REG: - VM_PANIC_ON(!decode->op[i].ptr); + VM_PANIC_ON(!decode->op[i].regptr); if (calc_val[i]) { - decode->op[i].val =3D read_val_from_reg(decode->op[i].ptr, + decode->op[i].val =3D read_val_from_reg(decode->op[i].regp= tr, decode->operand_size= ); } break; case X86_VAR_RM: calc_modrm_operand(env, decode, &decode->op[i]); if (calc_val[i]) { - decode->op[i].val =3D read_val_ext(env, decode->op[i].ptr, + decode->op[i].val =3D read_val_ext(env, &decode->op[i], decode->operand_size); } break; case X86_VAR_OFFSET: - decode->op[i].ptr =3D decode_linear_addr(env, decode, - decode->op[i].ptr, - R_DS); + decode->op[i].addr =3D decode_linear_addr(env, decode, + decode->op[i].addr, + R_DS); if (calc_val[i]) { - decode->op[i].val =3D read_val_ext(env, decode->op[i].ptr, + decode->op[i].val =3D read_val_ext(env, &decode->op[i], decode->operand_size); } break; @@ -257,7 +262,7 @@ static void fetch_operands(CPUX86State *env, struct x86= _decode *decode, static void exec_mov(CPUX86State *env, struct x86_decode *decode) { fetch_operands(env, decode, 2, false, true, false); - write_val_ext(env, decode->op[0].ptr, decode->op[1].val, + write_val_ext(env, &decode->op[0], decode->op[1].val, decode->operand_size); =20 env->eip +=3D decode->len; @@ -312,7 +317,7 @@ static void exec_neg(CPUX86State *env, struct x86_decod= e *decode) fetch_operands(env, decode, 2, true, true, false); =20 val =3D 0 - sign(decode->op[1].val, decode->operand_size); - write_val_ext(env, decode->op[1].ptr, val, decode->operand_size); + write_val_ext(env, &decode->op[1], val, decode->operand_size); =20 if (4 =3D=3D decode->operand_size) { SET_FLAGS_OSZAPC_SUB32(env, 0, 0 - val, val); @@ -363,7 +368,7 @@ static void exec_not(CPUX86State *env, struct x86_decod= e *decode) { fetch_operands(env, decode, 1, true, false, false); =20 - write_val_ext(env, decode->op[0].ptr, ~decode->op[0].val, + write_val_ext(env, &decode->op[0], ~decode->op[0].val, decode->operand_size); env->eip +=3D decode->len; } @@ -382,8 +387,8 @@ void exec_movzx(CPUX86State *env, struct x86_decode *de= code) } decode->operand_size =3D src_op_size; calc_modrm_operand(env, decode, &decode->op[1]); - decode->op[1].val =3D read_val_ext(env, decode->op[1].ptr, src_op_size= ); - write_val_ext(env, decode->op[0].ptr, decode->op[1].val, op_size); + decode->op[1].val =3D read_val_ext(env, &decode->op[1], src_op_size); + write_val_ext(env, &decode->op[0], decode->op[1].val, op_size); =20 env->eip +=3D decode->len; } @@ -535,8 +540,8 @@ static void exec_movs_single(CPUX86State *env, struct x= 86_decode *decode) dst_addr =3D linear_addr_size(env_cpu(env), RDI(env), decode->addressing_size, R_ES); =20 - val =3D read_val_ext(env, src_addr, decode->operand_size); - write_val_ext(env, dst_addr, val, decode->operand_size); + val =3D read_val_from_mem(env, src_addr, decode->operand_size); + write_val_to_mem(env, dst_addr, val, decode->operand_size); =20 string_increment_reg(env, R_ESI, decode); string_increment_reg(env, R_EDI, decode); @@ -563,9 +568,9 @@ static void exec_cmps_single(CPUX86State *env, struct x= 86_decode *decode) decode->addressing_size, R_ES); =20 decode->op[0].type =3D X86_VAR_IMMEDIATE; - decode->op[0].val =3D read_val_ext(env, src_addr, decode->operand_size= ); + decode->op[0].val =3D read_val_from_mem(env, src_addr, decode->operand= _size); decode->op[1].type =3D X86_VAR_IMMEDIATE; - decode->op[1].val =3D read_val_ext(env, dst_addr, decode->operand_size= ); + decode->op[1].val =3D read_val_from_mem(env, dst_addr, decode->operand= _size); =20 EXEC_2OP_FLAGS_CMD(env, decode, -, SET_FLAGS_OSZAPC_SUB, false); =20 @@ -697,15 +702,15 @@ static void do_bt(CPUX86State *env, struct x86_decode= *decode, int flag) if (decode->op[0].type !=3D X86_VAR_REG) { if (4 =3D=3D decode->operand_size) { displacement =3D ((int32_t) (decode->op[1].val & 0xffffffe0)) = / 32; - decode->op[0].ptr +=3D 4 * displacement; + decode->op[0].addr +=3D 4 * displacement; } else if (2 =3D=3D decode->operand_size) { displacement =3D ((int16_t) (decode->op[1].val & 0xfff0)) / 16; - decode->op[0].ptr +=3D 2 * displacement; + decode->op[0].addr +=3D 2 * displacement; } else { VM_PANIC("bt 64bit\n"); } } - decode->op[0].val =3D read_val_ext(env, decode->op[0].ptr, + decode->op[0].val =3D read_val_ext(env, &decode->op[0], decode->operand_size); cf =3D (decode->op[0].val >> index) & 0x01; =20 @@ -723,7 +728,7 @@ static void do_bt(CPUX86State *env, struct x86_decode *= decode, int flag) decode->op[0].val &=3D ~(1u << index); break; } - write_val_ext(env, decode->op[0].ptr, decode->op[0].val, + write_val_ext(env, &decode->op[0], decode->op[0].val, decode->operand_size); set_CF(env, cf); } @@ -775,7 +780,7 @@ void exec_shl(CPUX86State *env, struct x86_decode *deco= de) of =3D cf ^ (res >> 7); } =20 - write_val_ext(env, decode->op[0].ptr, res, 1); + write_val_ext(env, &decode->op[0], res, 1); SET_FLAGS_OSZAPC_LOGIC8(env, 0, 0, res); SET_FLAGS_OxxxxC(env, of, cf); break; @@ -791,7 +796,7 @@ void exec_shl(CPUX86State *env, struct x86_decode *deco= de) of =3D cf ^ (res >> 15); /* of =3D cf ^ result15 */ } =20 - write_val_ext(env, decode->op[0].ptr, res, 2); + write_val_ext(env, &decode->op[0], res, 2); SET_FLAGS_OSZAPC_LOGIC16(env, 0, 0, res); SET_FLAGS_OxxxxC(env, of, cf); break; @@ -800,7 +805,7 @@ void exec_shl(CPUX86State *env, struct x86_decode *deco= de) { uint32_t res =3D decode->op[0].val << count; =20 - write_val_ext(env, decode->op[0].ptr, res, 4); + write_val_ext(env, &decode->op[0], res, 4); SET_FLAGS_OSZAPC_LOGIC32(env, 0, 0, res); cf =3D (decode->op[0].val >> (32 - count)) & 0x1; of =3D cf ^ (res >> 31); /* of =3D cf ^ result31 */ @@ -831,10 +836,10 @@ void exec_movsx(CPUX86State *env, struct x86_decode *= decode) =20 decode->operand_size =3D src_op_size; calc_modrm_operand(env, decode, &decode->op[1]); - decode->op[1].val =3D sign(read_val_ext(env, decode->op[1].ptr, src_op= _size), + decode->op[1].val =3D sign(read_val_ext(env, &decode->op[1], src_op_si= ze), src_op_size); =20 - write_val_ext(env, decode->op[0].ptr, decode->op[1].val, op_size); + write_val_ext(env, &decode->op[0], decode->op[1].val, op_size); =20 env->eip +=3D decode->len; } @@ -862,7 +867,7 @@ void exec_ror(CPUX86State *env, struct x86_decode *deco= de) count &=3D 0x7; /* use only bottom 3 bits */ res =3D ((uint8_t)decode->op[0].val >> count) | ((uint8_t)decode->op[0].val << (8 - count)); - write_val_ext(env, decode->op[0].ptr, res, 1); + write_val_ext(env, &decode->op[0], res, 1); bit6 =3D (res >> 6) & 1; bit7 =3D (res >> 7) & 1; /* set eflags: ROR count affects the following flags: C, O */ @@ -886,7 +891,7 @@ void exec_ror(CPUX86State *env, struct x86_decode *deco= de) count &=3D 0x0f; /* use only 4 LSB's */ res =3D ((uint16_t)decode->op[0].val >> count) | ((uint16_t)decode->op[0].val << (16 - count)); - write_val_ext(env, decode->op[0].ptr, res, 2); + write_val_ext(env, &decode->op[0], res, 2); =20 bit14 =3D (res >> 14) & 1; bit15 =3D (res >> 15) & 1; @@ -904,7 +909,7 @@ void exec_ror(CPUX86State *env, struct x86_decode *deco= de) if (count) { res =3D ((uint32_t)decode->op[0].val >> count) | ((uint32_t)decode->op[0].val << (32 - count)); - write_val_ext(env, decode->op[0].ptr, res, 4); + write_val_ext(env, &decode->op[0], res, 4); =20 bit31 =3D (res >> 31) & 1; bit30 =3D (res >> 30) & 1; @@ -941,7 +946,7 @@ void exec_rol(CPUX86State *env, struct x86_decode *deco= de) res =3D ((uint8_t)decode->op[0].val << count) | ((uint8_t)decode->op[0].val >> (8 - count)); =20 - write_val_ext(env, decode->op[0].ptr, res, 1); + write_val_ext(env, &decode->op[0], res, 1); /* set eflags: * ROL count affects the following flags: C, O */ @@ -968,7 +973,7 @@ void exec_rol(CPUX86State *env, struct x86_decode *deco= de) res =3D ((uint16_t)decode->op[0].val << count) | ((uint16_t)decode->op[0].val >> (16 - count)); =20 - write_val_ext(env, decode->op[0].ptr, res, 2); + write_val_ext(env, &decode->op[0], res, 2); bit0 =3D (res & 0x1); bit15 =3D (res >> 15); /* of =3D cf ^ result15 */ @@ -986,7 +991,7 @@ void exec_rol(CPUX86State *env, struct x86_decode *deco= de) res =3D ((uint32_t)decode->op[0].val << count) | ((uint32_t)decode->op[0].val >> (32 - count)); =20 - write_val_ext(env, decode->op[0].ptr, res, 4); + write_val_ext(env, &decode->op[0], res, 4); bit0 =3D (res & 0x1); bit31 =3D (res >> 31); /* of =3D cf ^ result31 */ @@ -1024,7 +1029,7 @@ void exec_rcl(CPUX86State *env, struct x86_decode *de= code) (op1_8 >> (9 - count)); } =20 - write_val_ext(env, decode->op[0].ptr, res, 1); + write_val_ext(env, &decode->op[0], res, 1); =20 cf =3D (op1_8 >> (8 - count)) & 0x01; of =3D cf ^ (res >> 7); /* of =3D cf ^ result7 */ @@ -1050,7 +1055,7 @@ void exec_rcl(CPUX86State *env, struct x86_decode *de= code) (op1_16 >> (17 - count)); } =20 - write_val_ext(env, decode->op[0].ptr, res, 2); + write_val_ext(env, &decode->op[0], res, 2); =20 cf =3D (op1_16 >> (16 - count)) & 0x1; of =3D cf ^ (res >> 15); /* of =3D cf ^ result15 */ @@ -1073,7 +1078,7 @@ void exec_rcl(CPUX86State *env, struct x86_decode *de= code) (op1_32 >> (33 - count)); } =20 - write_val_ext(env, decode->op[0].ptr, res, 4); + write_val_ext(env, &decode->op[0], res, 4); =20 cf =3D (op1_32 >> (32 - count)) & 0x1; of =3D cf ^ (res >> 31); /* of =3D cf ^ result31 */ @@ -1105,7 +1110,7 @@ void exec_rcr(CPUX86State *env, struct x86_decode *de= code) res =3D (op1_8 >> count) | (get_CF(env) << (8 - count)) | (op1_8 << (9 - count)); =20 - write_val_ext(env, decode->op[0].ptr, res, 1); + write_val_ext(env, &decode->op[0], res, 1); =20 cf =3D (op1_8 >> (count - 1)) & 0x1; of =3D (((res << 1) ^ res) >> 7) & 0x1; /* of =3D result6 ^ result= 7 */ @@ -1124,7 +1129,7 @@ void exec_rcr(CPUX86State *env, struct x86_decode *de= code) res =3D (op1_16 >> count) | (get_CF(env) << (16 - count)) | (op1_16 << (17 - count)); =20 - write_val_ext(env, decode->op[0].ptr, res, 2); + write_val_ext(env, &decode->op[0], res, 2); =20 cf =3D (op1_16 >> (count - 1)) & 0x1; of =3D ((uint16_t)((res << 1) ^ res) >> 15) & 0x1; /* of =3D resul= t15 ^ @@ -1148,7 +1153,7 @@ void exec_rcr(CPUX86State *env, struct x86_decode *de= code) (op1_32 << (33 - count)); } =20 - write_val_ext(env, decode->op[0].ptr, res, 4); + write_val_ext(env, &decode->op[0], res, 4); =20 cf =3D (op1_32 >> (count - 1)) & 0x1; of =3D ((res << 1) ^ res) >> 31; /* of =3D result30 ^ result31 */ @@ -1163,9 +1168,9 @@ static void exec_xchg(CPUX86State *env, struct x86_de= code *decode) { fetch_operands(env, decode, 2, true, true, false); =20 - write_val_ext(env, decode->op[0].ptr, decode->op[1].val, + write_val_ext(env, &decode->op[0], decode->op[1].val, decode->operand_size); - write_val_ext(env, decode->op[1].ptr, decode->op[0].val, + write_val_ext(env, &decode->op[1], decode->op[0].val, decode->operand_size); =20 env->eip +=3D decode->len; @@ -1174,7 +1179,7 @@ static void exec_xchg(CPUX86State *env, struct x86_de= code *decode) static void exec_xadd(CPUX86State *env, struct x86_decode *decode) { EXEC_2OP_FLAGS_CMD(env, decode, +, SET_FLAGS_OSZAPC_ADD, true); - write_val_ext(env, decode->op[1].ptr, decode->op[0].val, + write_val_ext(env, &decode->op[1], decode->op[0].val, decode->operand_size); =20 env->eip +=3D decode->len; --=20 2.49.0 From nobody Sat Nov 15 22:24:44 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 02 May 2025 14:48:49 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFKAyfooXxXAG+rZMSH15GRgAyIB4EB+ecKaPlpSp0jbfwhiUKTVWPLCtAtI7P7jOhag94f/Q== X-Received: by 2002:a5d:62c7:0:b0:3a0:99e9:bc98 with SMTP id ffacd0b85a97d-3a099e9c21bmr2537457f8f.8.1746222529218; Fri, 02 May 2025 14:48:49 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: wei.liu@kernel.org Subject: [PATCH 3/4] target/i386/emulate: mostly rewrite flags handling Date: Fri, 2 May 2025 23:48:40 +0200 Message-ID: <20250502214841.242584-4-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250502214841.242584-1-pbonzini@redhat.com> References: <20250502214841.242584-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.644, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1746222576619116600 Content-Type: text/plain; charset="utf-8" While Bochs's algorithms are pretty solid, there are small opportunities to improve them or to make their logic more similar to TCG's handling of condition codes. - use a single bit for the difference between bits 0..7 of result and PF. This is useful because "set only ZF" is not a common case. - place SD in the same place as SF - move CF and PO at bits 62 and 63 when target_ulong is 64-bits wide, so that 64-bit ALU operations need fewer shifts - use rotates to move CF and AF from auxbits to their eflags position Signed-off-by: Paolo Bonzini --- target/i386/emulate/x86_flags.h | 12 +- target/i386/emulate/x86_emu.c | 4 +- target/i386/emulate/x86_flags.c | 197 ++++++++++++++------------------ 3 files changed, 86 insertions(+), 127 deletions(-) diff --git a/target/i386/emulate/x86_flags.h b/target/i386/emulate/x86_flag= s.h index 6c175007b57..28b008e5771 100644 --- a/target/i386/emulate/x86_flags.h +++ b/target/i386/emulate/x86_flags.h @@ -28,20 +28,10 @@ void lflags_to_rflags(CPUX86State *env); void rflags_to_lflags(CPUX86State *env); =20 -bool get_PF(CPUX86State *env); -void set_PF(CPUX86State *env, bool val); bool get_CF(CPUX86State *env); void set_CF(CPUX86State *env, bool val); -bool get_AF(CPUX86State *env); -void set_AF(CPUX86State *env, bool val); -bool get_ZF(CPUX86State *env); -void set_ZF(CPUX86State *env, bool val); -bool get_SF(CPUX86State *env); -void set_SF(CPUX86State *env, bool val); -bool get_OF(CPUX86State *env); -void set_OF(CPUX86State *env, bool val); =20 -void SET_FLAGS_OxxxxC(CPUX86State *env, uint32_t new_of, uint32_t new_cf); +void SET_FLAGS_OxxxxC(CPUX86State *env, bool new_of, bool new_cf); =20 void SET_FLAGS_OSZAPC_SUB32(CPUX86State *env, uint32_t v1, uint32_t v2, uint32_t diff); diff --git a/target/i386/emulate/x86_emu.c b/target/i386/emulate/x86_emu.c index 4c07f08942e..61bd5af5bb1 100644 --- a/target/i386/emulate/x86_emu.c +++ b/target/i386/emulate/x86_emu.c @@ -474,10 +474,10 @@ static inline void string_rep(CPUX86State *env, struc= t x86_decode *decode, while (rcx--) { func(env, decode); write_reg(env, R_ECX, rcx, decode->addressing_size); - if ((PREFIX_REP =3D=3D rep) && !get_ZF(env)) { + if ((PREFIX_REP =3D=3D rep) && !env->lflags.result) { break; } - if ((PREFIX_REPN =3D=3D rep) && get_ZF(env)) { + if ((PREFIX_REPN =3D=3D rep) && env->lflags.result) { break; } } diff --git a/target/i386/emulate/x86_flags.c b/target/i386/emulate/x86_flag= s.c index 84e27364a03..c347a951889 100644 --- a/target/i386/emulate/x86_flags.c +++ b/target/i386/emulate/x86_flags.c @@ -29,41 +29,50 @@ #include "x86.h" =20 =20 -/* this is basically bocsh code */ +/* + * The algorithms here are similar to those in Bochs. After an ALU + * operation, RESULT can be used to compute ZF, SF and PF, whereas + * AUXBITS is used to compute AF, CF and OF. In reality, SF and PF are the + * XOR of the value computed from RESULT and the value found in bits 7 and= 2 + * of AUXBITS; this way the same logic can be used to compute the flags + * both before and after an ALU operation. + * + * Compared to the TCG CC_OP codes, this avoids conditionals when converti= ng + * to and from the RFLAGS representation. + */ =20 -#define LF_SIGN_BIT 31 +#define LF_SIGN_BIT (TARGET_LONG_BITS - 1) =20 -#define LF_BIT_SD (0) /* lazy Sign Flag Delta */ -#define LF_BIT_AF (3) /* lazy Adjust flag */ -#define LF_BIT_PDB (8) /* lazy Parity Delta Byte (8 bits) */ -#define LF_BIT_CF (31) /* lazy Carry Flag */ -#define LF_BIT_PO (30) /* lazy Partial Overflow =3D CF ^ OF */ +#define LF_BIT_PD (2) /* lazy Parity Delta, same bit as PF */ +#define LF_BIT_AF (3) /* lazy Adjust flag */ +#define LF_BIT_SD (7) /* lazy Sign Flag Delta, same bit as S= F */ +#define LF_BIT_CF (TARGET_LONG_BITS - 1) /* lazy Carry Flag */ +#define LF_BIT_PO (TARGET_LONG_BITS - 2) /* lazy Partial Overflow =3D= CF ^ OF */ =20 -#define LF_MASK_SD (0x01 << LF_BIT_SD) -#define LF_MASK_AF (0x01 << LF_BIT_AF) -#define LF_MASK_PDB (0xFF << LF_BIT_PDB) -#define LF_MASK_CF (0x01 << LF_BIT_CF) -#define LF_MASK_PO (0x01 << LF_BIT_PO) +#define LF_MASK_PD ((target_ulong)0x01 << LF_BIT_PD) +#define LF_MASK_AF ((target_ulong)0x01 << LF_BIT_AF) +#define LF_MASK_SD ((target_ulong)0x01 << LF_BIT_SD) +#define LF_MASK_CF ((target_ulong)0x01 << LF_BIT_CF) +#define LF_MASK_PO ((target_ulong)0x01 << LF_BIT_PO) =20 /* ******************* */ /* OSZAPC */ /* ******************* */ =20 -/* size, carries, result */ +/* use carries to fill in AF, PO and CF, while ensuring PD and SD are clea= r. + * for full-word operations just clear PD and SD; for smaller operand + * sizes only keep AF in the low byte and shift the carries left to + * place PO and CF in the top two bits. + */ #define SET_FLAGS_OSZAPC_SIZE(size, lf_carries, lf_result) { \ - target_ulong temp =3D ((lf_carries) & (LF_MASK_AF)) | \ - (((lf_carries) >> (size - 2)) << LF_BIT_PO); \ env->lflags.result =3D (target_ulong)(int##size##_t)(lf_result); \ - if ((size) =3D=3D 32) { \ - temp =3D ((lf_carries) & ~(LF_MASK_PDB | LF_MASK_SD)); \ - } else if ((size) =3D=3D 16) { \ - temp =3D ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 16); \ - } else if ((size) =3D=3D 8) { \ - temp =3D ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 24); \ + target_ulong temp =3D (lf_carries); \ + if ((size) =3D=3D TARGET_LONG_BITS) { \ + temp =3D temp & ~(LF_MASK_PD | LF_MASK_SD); \ } else { \ - VM_PANIC("unimplemented"); \ + temp =3D (temp & LF_MASK_AF) | (temp << (TARGET_LONG_BITS - (size)= )); \ } \ - env->lflags.auxbits =3D (target_ulong)(uint32_t)temp; \ + env->lflags.auxbits =3D temp; \ } =20 /* carries, result */ @@ -77,23 +86,18 @@ /* ******************* */ /* OSZAP */ /* ******************* */ -/* size, carries, result */ +/* same as setting OSZAPC, but preserve CF and flip PO if the old value of= CF + * did not match the high bit of lf_carries. */ #define SET_FLAGS_OSZAP_SIZE(size, lf_carries, lf_result) { \ - target_ulong temp =3D ((lf_carries) & (LF_MASK_AF)) | \ - (((lf_carries) >> (size - 2)) << LF_BIT_PO); \ - if ((size) =3D=3D 32) { \ - temp =3D ((lf_carries) & ~(LF_MASK_PDB | LF_MASK_SD)); \ - } else if ((size) =3D=3D 16) { \ - temp =3D ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 16); \ - } else if ((size) =3D=3D 8) { \ - temp =3D ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 24); \ - } else { \ - VM_PANIC("unimplemented"); \ - } \ env->lflags.result =3D (target_ulong)(int##size##_t)(lf_result); \ - target_ulong delta_c =3D (env->lflags.auxbits ^ temp) & LF_MASK_CF; \ - delta_c ^=3D (delta_c >> 1); \ - env->lflags.auxbits =3D (target_ulong)(uint32_t)(temp ^ delta_c); \ + target_ulong temp =3D (lf_carries); \ + if ((size) =3D=3D TARGET_LONG_BITS) { \ + temp =3D (temp & ~(LF_MASK_PD | LF_MASK_SD)); \ + } else { \ + temp =3D (temp & LF_MASK_AF) | (temp << (TARGET_LONG_BITS - (size)= )); \ + } \ + target_ulong cf_changed =3D ((target_long)(env->lflags.auxbits ^ temp)= ) < 0; \ + env->lflags.auxbits =3D temp ^ (cf_changed * (LF_MASK_PO | LF_MASK_CF)= ); \ } =20 /* carries, result */ @@ -104,11 +108,11 @@ #define SET_FLAGS_OSZAP_32(carries, result) \ SET_FLAGS_OSZAP_SIZE(32, carries, result) =20 -void SET_FLAGS_OxxxxC(CPUX86State *env, uint32_t new_of, uint32_t new_cf) +void SET_FLAGS_OxxxxC(CPUX86State *env, bool new_of, bool new_cf) { - uint32_t temp_po =3D new_of ^ new_cf; env->lflags.auxbits &=3D ~(LF_MASK_PO | LF_MASK_CF); - env->lflags.auxbits |=3D (temp_po << LF_BIT_PO) | (new_cf << LF_BIT_CF= ); + env->lflags.auxbits |=3D (-(target_ulong)new_cf << LF_BIT_PO); + env->lflags.auxbits ^=3D ((target_ulong)new_of << LF_BIT_PO); } =20 void SET_FLAGS_OSZAPC_SUB32(CPUX86State *env, uint32_t v1, uint32_t v2, @@ -202,104 +206,69 @@ void SET_FLAGS_OSZAPC_LOGIC8(CPUX86State *env, uint8= _t v1, uint8_t v2, SET_FLAGS_OSZAPC_8(0, diff); } =20 -bool get_PF(CPUX86State *env) +static inline uint32_t get_PF(CPUX86State *env) { - uint32_t temp =3D (255 & env->lflags.result); - temp =3D temp ^ (255 & (env->lflags.auxbits >> LF_BIT_PDB)); - temp =3D (temp ^ (temp >> 4)) & 0x0F; - return (0x9669U >> temp) & 1; + uint8_t temp =3D env->lflags.result; + return ((parity8(temp) - 1) ^ env->lflags.auxbits) & CC_P; } =20 -void set_PF(CPUX86State *env, bool val) +static inline uint32_t get_OF(CPUX86State *env) { - uint32_t temp =3D (255 & env->lflags.result) ^ (!val); - env->lflags.auxbits &=3D ~(LF_MASK_PDB); - env->lflags.auxbits |=3D (temp << LF_BIT_PDB); -} - -bool get_OF(CPUX86State *env) -{ - return ((env->lflags.auxbits + (1U << LF_BIT_PO)) >> LF_BIT_CF) & 1; + return ((env->lflags.auxbits >> (LF_BIT_CF - 11)) + CC_O / 2) & CC_O; } =20 bool get_CF(CPUX86State *env) { - return (env->lflags.auxbits >> LF_BIT_CF) & 1; -} - -void set_OF(CPUX86State *env, bool val) -{ - bool old_cf =3D get_CF(env); - SET_FLAGS_OxxxxC(env, val, old_cf); + return ((target_long)env->lflags.auxbits) < 0; } =20 void set_CF(CPUX86State *env, bool val) { - bool old_of =3D get_OF(env); - SET_FLAGS_OxxxxC(env, old_of, val); + /* If CF changes, flip PO and CF */ + target_ulong temp =3D -(target_ulong)val; + target_ulong cf_changed =3D ((target_long)(env->lflags.auxbits ^ temp)= ) < 0; + env->lflags.auxbits ^=3D cf_changed * (LF_MASK_PO | LF_MASK_CF); } =20 -bool get_AF(CPUX86State *env) +static inline uint32_t get_ZF(CPUX86State *env) { - return (env->lflags.auxbits >> LF_BIT_AF) & 1; + return env->lflags.result ? 0 : CC_Z; } =20 -void set_AF(CPUX86State *env, bool val) +static inline uint32_t get_SF(CPUX86State *env) { - env->lflags.auxbits &=3D ~(LF_MASK_AF); - env->lflags.auxbits |=3D val << LF_BIT_AF; -} - -bool get_ZF(CPUX86State *env) -{ - return !env->lflags.result; -} - -void set_ZF(CPUX86State *env, bool val) -{ - if (val) { - env->lflags.auxbits ^=3D - (((env->lflags.result >> LF_SIGN_BIT) & 1) << LF_BIT_SD); - /* merge the parity bits into the Parity Delta Byte */ - uint32_t temp_pdb =3D (255 & env->lflags.result); - env->lflags.auxbits ^=3D (temp_pdb << LF_BIT_PDB); - /* now zero the .result value */ - env->lflags.result =3D 0; - } else { - env->lflags.result |=3D (1 << 8); - } -} - -bool get_SF(CPUX86State *env) -{ - return ((env->lflags.result >> LF_SIGN_BIT) ^ - (env->lflags.auxbits >> LF_BIT_SD)) & 1; -} - -void set_SF(CPUX86State *env, bool val) -{ - bool temp_sf =3D get_SF(env); - env->lflags.auxbits ^=3D (temp_sf ^ val) << LF_BIT_SD; + return ((env->lflags.result >> (LF_SIGN_BIT - LF_BIT_SD)) ^ + env->lflags.auxbits) & CC_S; } =20 void lflags_to_rflags(CPUX86State *env) { env->eflags &=3D ~(CC_C|CC_P|CC_A|CC_Z|CC_S|CC_O); - env->eflags |=3D get_CF(env) ? CC_C : 0; - env->eflags |=3D get_PF(env) ? CC_P : 0; - env->eflags |=3D get_AF(env) ? CC_A : 0; - env->eflags |=3D get_ZF(env) ? CC_Z : 0; - env->eflags |=3D get_SF(env) ? CC_S : 0; - env->eflags |=3D get_OF(env) ? CC_O : 0; + /* rotate left by one to move carry-out bits into CF and AF */ + env->eflags |=3D ( + (env->lflags.auxbits << 1) | + (env->lflags.auxbits >> (TARGET_LONG_BITS - 1))) & (CC_C | CC_A); + env->eflags |=3D get_SF(env); + env->eflags |=3D get_PF(env); + env->eflags |=3D get_ZF(env); + env->eflags |=3D get_OF(env); } =20 void rflags_to_lflags(CPUX86State *env) { - env->lflags.auxbits =3D env->lflags.result =3D 0; - set_OF(env, env->eflags & CC_O); - set_SF(env, env->eflags & CC_S); - set_ZF(env, env->eflags & CC_Z); - set_AF(env, env->eflags & CC_A); - set_PF(env, env->eflags & CC_P); - set_CF(env, env->eflags & CC_C); + target_ulong cf_xor_of; + + env->lflags.auxbits =3D CC_P; + env->lflags.auxbits ^=3D env->eflags & (CC_S | CC_P); + + /* rotate right by one to move CF and AF into the carry-out positions = */ + env->lflags.auxbits |=3D ( + (env->eflags >> 1) | + (env->eflags << (TARGET_LONG_BITS - 1))) & (CC_C | CC_A); + + cf_xor_of =3D (env->eflags & (CC_C | CC_O)) + (CC_O - CC_C); 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Signed-off-by: Paolo Bonzini --- target/i386/cpu.h | 6 ---- target/i386/emulate/x86_emu.c | 4 +-- target/i386/emulate/x86_flags.c | 55 ++++++++++++++++----------------- 3 files changed, 29 insertions(+), 36 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 54bf9639f19..8e3323f96f8 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1809,11 +1809,6 @@ typedef struct CPUCaches { CPUCacheInfo *l3_cache; } CPUCaches; =20 -typedef struct X86LazyFlags { - target_ulong result; - target_ulong auxbits; -} X86LazyFlags; - typedef struct CPUArchState { /* standard registers */ target_ulong regs[CPU_NB_REGS]; @@ -2106,7 +2101,6 @@ typedef struct CPUArchState { QemuMutex xen_timers_lock; #endif #if defined(CONFIG_HVF) - X86LazyFlags lflags; void *emu_mmio_buf; #endif =20 diff --git a/target/i386/emulate/x86_emu.c b/target/i386/emulate/x86_emu.c index 61bd5af5bb1..4890e0a4e5e 100644 --- a/target/i386/emulate/x86_emu.c +++ b/target/i386/emulate/x86_emu.c @@ -474,10 +474,10 @@ static inline void string_rep(CPUX86State *env, struc= t x86_decode *decode, while (rcx--) { func(env, decode); write_reg(env, R_ECX, rcx, decode->addressing_size); - if ((PREFIX_REP =3D=3D rep) && !env->lflags.result) { + if ((PREFIX_REP =3D=3D rep) && !env->cc_dst) { break; } - if ((PREFIX_REPN =3D=3D rep) && env->lflags.result) { + if ((PREFIX_REPN =3D=3D rep) && env->cc_dst) { break; } } diff --git a/target/i386/emulate/x86_flags.c b/target/i386/emulate/x86_flag= s.c index c347a951889..a4f7af8aacd 100644 --- a/target/i386/emulate/x86_flags.c +++ b/target/i386/emulate/x86_flags.c @@ -31,10 +31,10 @@ =20 /* * The algorithms here are similar to those in Bochs. After an ALU - * operation, RESULT can be used to compute ZF, SF and PF, whereas - * AUXBITS is used to compute AF, CF and OF. In reality, SF and PF are the - * XOR of the value computed from RESULT and the value found in bits 7 and= 2 - * of AUXBITS; this way the same logic can be used to compute the flags + * operation, CC_DST can be used to compute ZF, SF and PF, whereas + * CC_SRC is used to compute AF, CF and OF. In reality, SF and PF are the + * XOR of the value computed from CC_DST and the value found in bits 7 and= 2 + * of CC_SRC; this way the same logic can be used to compute the flags * both before and after an ALU operation. * * Compared to the TCG CC_OP codes, this avoids conditionals when converti= ng @@ -65,14 +65,14 @@ * place PO and CF in the top two bits. */ #define SET_FLAGS_OSZAPC_SIZE(size, lf_carries, lf_result) { \ - env->lflags.result =3D (target_ulong)(int##size##_t)(lf_result); \ + env->cc_dst =3D (target_ulong)(int##size##_t)(lf_result); \ target_ulong temp =3D (lf_carries); \ if ((size) =3D=3D TARGET_LONG_BITS) { \ temp =3D temp & ~(LF_MASK_PD | LF_MASK_SD); \ } else { \ temp =3D (temp & LF_MASK_AF) | (temp << (TARGET_LONG_BITS - (size)= )); \ } \ - env->lflags.auxbits =3D temp; \ + env->cc_src =3D temp; \ } =20 /* carries, result */ @@ -89,15 +89,15 @@ /* same as setting OSZAPC, but preserve CF and flip PO if the old value of= CF * did not match the high bit of lf_carries. */ #define SET_FLAGS_OSZAP_SIZE(size, lf_carries, lf_result) { \ - env->lflags.result =3D (target_ulong)(int##size##_t)(lf_result); \ + env->cc_dst =3D (target_ulong)(int##size##_t)(lf_result); \ target_ulong temp =3D (lf_carries); \ if ((size) =3D=3D TARGET_LONG_BITS) { \ temp =3D (temp & ~(LF_MASK_PD | LF_MASK_SD)); \ } else { \ temp =3D (temp & LF_MASK_AF) | (temp << (TARGET_LONG_BITS - (size)= )); \ } \ - target_ulong cf_changed =3D ((target_long)(env->lflags.auxbits ^ temp)= ) < 0; \ - env->lflags.auxbits =3D temp ^ (cf_changed * (LF_MASK_PO | LF_MASK_CF)= ); \ + target_ulong cf_changed =3D ((target_long)(env->cc_src ^ temp)) < 0; \ + env->cc_src =3D temp ^ (cf_changed * (LF_MASK_PO | LF_MASK_CF)); \ } =20 /* carries, result */ @@ -110,9 +110,9 @@ =20 void SET_FLAGS_OxxxxC(CPUX86State *env, bool new_of, bool new_cf) { - env->lflags.auxbits &=3D ~(LF_MASK_PO | LF_MASK_CF); - env->lflags.auxbits |=3D (-(target_ulong)new_cf << LF_BIT_PO); - env->lflags.auxbits ^=3D ((target_ulong)new_of << LF_BIT_PO); + env->cc_src &=3D ~(LF_MASK_PO | LF_MASK_CF); + env->cc_src |=3D (-(target_ulong)new_cf << LF_BIT_PO); + env->cc_src ^=3D ((target_ulong)new_of << LF_BIT_PO); } =20 void SET_FLAGS_OSZAPC_SUB32(CPUX86State *env, uint32_t v1, uint32_t v2, @@ -208,37 +208,36 @@ void SET_FLAGS_OSZAPC_LOGIC8(CPUX86State *env, uint8_= t v1, uint8_t v2, =20 static inline uint32_t get_PF(CPUX86State *env) { - uint8_t temp =3D env->lflags.result; - return ((parity8(temp) - 1) ^ env->lflags.auxbits) & CC_P; + return ((parity8(env->cc_dst) - 1) ^ env->cc_src) & CC_P; } =20 static inline uint32_t get_OF(CPUX86State *env) { - return ((env->lflags.auxbits >> (LF_BIT_CF - 11)) + CC_O / 2) & CC_O; + return ((env->cc_src >> (LF_BIT_CF - 11)) + CC_O / 2) & CC_O; } =20 bool get_CF(CPUX86State *env) { - return ((target_long)env->lflags.auxbits) < 0; + return ((target_long)env->cc_src) < 0; } =20 void set_CF(CPUX86State *env, bool val) { /* If CF changes, flip PO and CF */ target_ulong temp =3D -(target_ulong)val; - target_ulong cf_changed =3D ((target_long)(env->lflags.auxbits ^ temp)= ) < 0; - env->lflags.auxbits ^=3D cf_changed * (LF_MASK_PO | LF_MASK_CF); + target_ulong cf_changed =3D ((target_long)(env->cc_src ^ temp)) < 0; + env->cc_src ^=3D cf_changed * (LF_MASK_PO | LF_MASK_CF); } =20 static inline uint32_t get_ZF(CPUX86State *env) { - return env->lflags.result ? 0 : CC_Z; + return env->cc_dst ? 0 : CC_Z; } =20 static inline uint32_t get_SF(CPUX86State *env) { - return ((env->lflags.result >> (LF_SIGN_BIT - LF_BIT_SD)) ^ - env->lflags.auxbits) & CC_S; + return ((env->cc_dst >> (LF_SIGN_BIT - LF_BIT_SD)) ^ + env->cc_src) & CC_S; } =20 void lflags_to_rflags(CPUX86State *env) @@ -246,8 +245,8 @@ void lflags_to_rflags(CPUX86State *env) env->eflags &=3D ~(CC_C|CC_P|CC_A|CC_Z|CC_S|CC_O); /* rotate left by one to move carry-out bits into CF and AF */ env->eflags |=3D ( - (env->lflags.auxbits << 1) | - (env->lflags.auxbits >> (TARGET_LONG_BITS - 1))) & (CC_C | CC_A); + (env->cc_src << 1) | + (env->cc_src >> (TARGET_LONG_BITS - 1))) & (CC_C | CC_A); env->eflags |=3D get_SF(env); env->eflags |=3D get_PF(env); env->eflags |=3D get_ZF(env); @@ -258,17 +257,17 @@ void rflags_to_lflags(CPUX86State *env) { target_ulong cf_xor_of; =20 - env->lflags.auxbits =3D CC_P; - env->lflags.auxbits ^=3D env->eflags & (CC_S | CC_P); + env->cc_src =3D CC_P; + env->cc_src ^=3D env->eflags & (CC_S | CC_P); =20 /* rotate right by one to move CF and AF into the carry-out positions = */ - env->lflags.auxbits |=3D ( + env->cc_src |=3D ( (env->eflags >> 1) | (env->eflags << (TARGET_LONG_BITS - 1))) & (CC_C | CC_A); =20 cf_xor_of =3D (env->eflags & (CC_C | CC_O)) + (CC_O - CC_C); - env->lflags.auxbits |=3D -cf_xor_of & LF_MASK_PO; + env->cc_src |=3D -cf_xor_of & LF_MASK_PO; =20 /* Leave the low byte zero so that parity is not affected. */ - env->lflags.result =3D !(env->eflags & CC_Z) << 8; + env->cc_dst =3D !(env->eflags & CC_Z) << 8; } --=20 2.49.0