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Tsirkin" , Marcel Apfelbaum , Fabiano Rosas , Laurent Vivier , Phil Dennis-Jordan , Bernhard Beschow , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v4 21/22] tests/qtest/xhci: Test USB Mass Storage relaxed CSW order Date: Fri, 2 May 2025 13:30:45 +1000 Message-ID: <20250502033047.102465-22-npiggin@gmail.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250502033047.102465-1-npiggin@gmail.com> References: <20250502033047.102465-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1746156925971019100 Content-Type: text/plain; charset="utf-8" This adds a qtest for the improvement to the MSD protocol that allows an IN packet before the CBW packet. Send a CSW packet before a zero-length CBW command packet is sent. This test would fail with the MSD change reverted. Signed-off-by: Nicholas Piggin Reviewed-by: Fabiano Rosas --- tests/qtest/usb-hcd-xhci-test.c | 180 ++++++++++++++++++++++++++++---- 1 file changed, 158 insertions(+), 22 deletions(-) diff --git a/tests/qtest/usb-hcd-xhci-test.c b/tests/qtest/usb-hcd-xhci-tes= t.c index 428200d9e41..740e9cd3815 100644 --- a/tests/qtest/usb-hcd-xhci-test.c +++ b/tests/qtest/usb-hcd-xhci-test.c @@ -287,11 +287,48 @@ static bool xhci_test_isr(XHCIQState *s) s->guest_msix_addr, s->msix_data); } =20 -static void wait_event_trb(XHCIQState *s, XHCITRB *trb) +static bool check_event_trb(XHCIQState *s, XHCITRB *trb) { + XHCIQTRState *tr =3D &s->event_ring; + uint64_t er_addr =3D tr->addr + tr->trb_idx * TRB_SIZE; XHCITRB t; + + qtest_memread(s->parent->qts, er_addr, &t, TRB_SIZE); + trb->parameter =3D le64_to_cpu(t.parameter); + trb->status =3D le32_to_cpu(t.status); + trb->control =3D le32_to_cpu(t.control); + + return ((trb->control & TRB_C) =3D=3D tr->trb_c); +} + +static void consume_event(XHCIQState *s) +{ XHCIQTRState *tr =3D &s->event_ring; uint64_t er_addr =3D tr->addr + tr->trb_idx * TRB_SIZE; + + tr->trb_idx++; + if (tr->trb_idx =3D=3D tr->trb_entries) { + tr->trb_idx =3D 0; + tr->trb_c ^=3D 1; + } + /* Update ERDP to processed TRB addr and EHB bit, which clears EHB */ + er_addr =3D tr->addr + tr->trb_idx * TRB_SIZE; + xhci_intr_writel(s, 0, XHCI_INTR_REG_ERDP_LO, + (er_addr & 0xffffffff) | XHCI_ERDP_EHB); +} + +static bool try_get_event_trb(XHCIQState *s, XHCITRB *trb) +{ + if (check_event_trb(s, trb)) { + consume_event(s); + return true; + } + return false; +} + +static void wait_event_trb(XHCIQState *s, XHCITRB *trb) +{ + XHCIQTRState *tr =3D &s->event_ring; uint32_t value; guint64 end_time =3D g_get_monotonic_time() + 5 * G_TIME_SPAN_SECOND; =20 @@ -306,30 +343,24 @@ static void wait_event_trb(XHCIQState *s, XHCITRB *tr= b) value =3D xhci_op_readl(s, XHCI_OPER_REG_USBSTS); g_assert(value & XHCI_USBSTS_EINT); =20 - /* With MSI-X enabled, IMAN IP is cleared after raising the interrupt = */ - value =3D xhci_intr_readl(s, 0, XHCI_INTR_REG_IMAN); - g_assert(!(value & XHCI_IMAN_IP)); - - xhci_op_writel(s, XHCI_OPER_REG_USBSTS, XHCI_USBSTS_EINT); /* clear EI= NT */ - - qtest_memread(s->parent->qts, er_addr, &t, TRB_SIZE); - - trb->parameter =3D le64_to_cpu(t.parameter); - trb->status =3D le32_to_cpu(t.status); - trb->control =3D le32_to_cpu(t.control); + if (0) { + /* + * With MSI-X enabled, IMAN IP is cleared after raising the interr= upt, + * but if concurrent events may be occurring, it could be set agai= n. + */ + value =3D xhci_intr_readl(s, 0, XHCI_INTR_REG_IMAN); + g_assert(!(value & XHCI_IMAN_IP)); + } =20 - g_assert((trb->status >> 24) =3D=3D CC_SUCCESS); + if (!check_event_trb(s, trb)) { + g_assert_not_reached(); + } + g_assert_cmpint((trb->status >> 24), =3D=3D, CC_SUCCESS); g_assert((trb->control & TRB_C) =3D=3D tr->trb_c); /* C bit has been s= et */ =20 - tr->trb_idx++; - if (tr->trb_idx =3D=3D tr->trb_entries) { - tr->trb_idx =3D 0; - tr->trb_c ^=3D 1; - } - /* Update ERDP to processed TRB addr and EHB bit, which clears EHB */ - er_addr =3D tr->addr + tr->trb_idx * TRB_SIZE; - xhci_intr_writel(s, 0, XHCI_INTR_REG_ERDP_LO, - (er_addr & 0xffffffff) | XHCI_ERDP_EHB); + xhci_op_writel(s, XHCI_OPER_REG_USBSTS, XHCI_USBSTS_EINT); /* clear EI= NT */ + + consume_event(s); } =20 static void set_link_trb(XHCIQState *s, uint64_t ring, uint32_t c, @@ -763,6 +794,106 @@ static ssize_t xhci_submit_scsi_cmd(XHCIQState *s, return data_len - le32_to_cpu(csw.residue); /* bytes copied */ } =20 +/* + * Submit command with CSW sent ahead of CBW. + * Can only be no-data or data-out commands (because a data-in command + * would interpret the CSW as a data-in). + */ +static ssize_t xhci_submit_out_of_order_scsi_cmd(XHCIQState *s, + const uint8_t *cmd, uint8_t cmd_len, + void *data, uint32_t data_len) +{ + struct usb_msd_cbw cbw; + struct usb_msd_csw csw; + uint64_t trb_data, csw_data; + XHCITRB trb, csw_trb; + uint64_t tag, csw_tag; + bool got_csw =3D false; + + /* TRB data payload */ + trb_data =3D xhci_guest_zalloc(s, data_len > sizeof(cbw) ? data_len : = sizeof(cbw)); + csw_data =3D xhci_guest_zalloc(s, sizeof(csw)); + + /* Issue a transfer ring ep 2 data (in) */ + memset(&csw_trb, 0, TRB_SIZE); + csw_trb.parameter =3D csw_data; + csw_trb.status =3D sizeof(csw); + csw_trb.control |=3D TR_NORMAL << TRB_TYPE_SHIFT; + csw_trb.control |=3D TRB_TR_IOC; + csw_tag =3D submit_tr_trb(s, s->slotid, 2, &csw_trb); + + memset(&cbw, 0, sizeof(cbw)); + cbw.sig =3D cpu_to_le32(0x43425355); + cbw.tag =3D cpu_to_le32(0); + cbw.data_len =3D cpu_to_le32(data_len); + cbw.flags =3D 0x00; + cbw.lun =3D 0; + cbw.cmd_len =3D cmd_len; /* cmd len */ + memcpy(cbw.cmd, cmd, cmd_len); + qtest_memwrite(s->parent->qts, trb_data, &cbw, sizeof(cbw)); + + /* Issue a transfer ring ep 3 data (out) */ + memset(&trb, 0, TRB_SIZE); + trb.parameter =3D trb_data; + trb.status =3D sizeof(cbw); + trb.control |=3D TR_NORMAL << TRB_TYPE_SHIFT; + trb.control |=3D TRB_TR_IOC; + tag =3D submit_tr_trb(s, s->slotid, 3, &trb); + + wait_event_trb(s, &trb); + if (trb.parameter =3D=3D csw_tag) { + g_assert_cmpint(TRB_TYPE(trb), =3D=3D, ER_TRANSFER); + got_csw =3D true; + if (!try_get_event_trb(s, &trb)) { + wait_event_trb(s, &trb); + } + } + g_assert_cmphex(trb.parameter, =3D=3D, tag); + g_assert_cmpint(TRB_TYPE(trb), =3D=3D, ER_TRANSFER); + + if (data_len) { + qtest_memwrite(s->parent->qts, trb_data, data, data_len); + + /* Issue a transfer ring ep 3 data (out) */ + memset(&trb, 0, TRB_SIZE); + trb.parameter =3D trb_data; + trb.status =3D data_len; /* data_len bytes, no more packets */ + trb.control |=3D TR_NORMAL << TRB_TYPE_SHIFT; + trb.control |=3D TRB_TR_IOC; + tag =3D submit_tr_trb(s, s->slotid, 3, &trb); + wait_event_trb(s, &trb); + if (trb.parameter =3D=3D csw_tag) { + g_assert_cmpint(TRB_TYPE(trb), =3D=3D, ER_TRANSFER); + got_csw =3D true; + if (!try_get_event_trb(s, &trb)) { + wait_event_trb(s, &trb); + } + } + g_assert_cmphex(trb.parameter, =3D=3D, tag); + g_assert_cmpint(TRB_TYPE(trb), =3D=3D, ER_TRANSFER); + } else { + /* No data */ + } + + if (!got_csw) { + wait_event_trb(s, &csw_trb); + g_assert_cmphex(csw_trb.parameter, =3D=3D, csw_tag); + g_assert_cmpint(TRB_TYPE(csw_trb), =3D=3D, ER_TRANSFER); + } + + qtest_memread(s->parent->qts, csw_data, &csw, sizeof(csw)); + + guest_free(&s->parent->alloc, trb_data); + guest_free(&s->parent->alloc, csw_data); + + g_assert(csw.sig =3D=3D cpu_to_le32(0x53425355)); + g_assert(csw.tag =3D=3D cpu_to_le32(0)); + if (csw.status) { + return -1; + } + return data_len - le32_to_cpu(csw.residue); /* bytes copied */ +} + #include "scsi/constants.h" =20 static void xhci_test_msd(XHCIQState *s) @@ -797,6 +928,11 @@ static void xhci_test_msd(XHCIQState *s) g_assert_not_reached(); } =20 + /* Try an "out of order" command */ + if (xhci_submit_out_of_order_scsi_cmd(s, scsi_cmd, 6, mem, 0) < 0) { + g_assert_not_reached(); + } + /* Report LUNs */ memset(scsi_cmd, 0, sizeof(scsi_cmd)); scsi_cmd[0] =3D REPORT_LUNS; --=20 2.47.1