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Thu, 01 May 2025 20:17:56 -0700 (PDT) From: Nicholas Piggin To: Akihiko Odaki Cc: Nicholas Piggin , qemu-devel@nongnu.org, Dmitry Fleytman , Jason Wang , Sriram Yagnaraman , Fabiano Rosas , Laurent Vivier , Paolo Bonzini Subject: [PATCH v3 08/12] hw/net/e1000e: Postponed msix interrupt processing should auto-clear cause Date: Fri, 2 May 2025 13:17:00 +1000 Message-ID: <20250502031705.100768-9-npiggin@gmail.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250502031705.100768-1-npiggin@gmail.com> References: <20250502031705.100768-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1746155949177019100 Content-Type: text/plain; charset="utf-8" Cause auto-clearing and masking should be performed during msix interrupt processing. Signed-off-by: Nicholas Piggin --- hw/net/e1000e_core.c | 86 +++++++++++++++++++++++++++++++++++--------- 1 file changed, 69 insertions(+), 17 deletions(-) diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c index f8e6522f810..5969f49e8fd 100644 --- a/hw/net/e1000e_core.c +++ b/hw/net/e1000e_core.c @@ -178,16 +178,62 @@ e1000e_intrmgr_on_throttling_timer(void *opaque) } } =20 +/* returns the bitmap of causes that are mapped to a given vector */ +static uint32_t find_msix_causes(E1000ECore *core, int vec) +{ + uint32_t causes =3D 0; + uint32_t int_cfg; + + int_cfg =3D E1000_IVAR_RXQ0(core->mac[IVAR]); + if (E1000_IVAR_ENTRY_VALID(int_cfg) && + E1000_IVAR_ENTRY_VEC(int_cfg) =3D=3D vec) { + causes |=3D E1000_ICR_RXQ0; + } + + int_cfg =3D E1000_IVAR_RXQ1(core->mac[IVAR]); + if (E1000_IVAR_ENTRY_VALID(int_cfg) && + E1000_IVAR_ENTRY_VEC(int_cfg) =3D=3D vec) { + causes |=3D E1000_ICR_RXQ1; + } + + int_cfg =3D E1000_IVAR_TXQ0(core->mac[IVAR]); + if (E1000_IVAR_ENTRY_VALID(int_cfg) && + E1000_IVAR_ENTRY_VEC(int_cfg) =3D=3D vec) { + causes |=3D E1000_ICR_TXQ0; + } + + int_cfg =3D E1000_IVAR_TXQ1(core->mac[IVAR]); + if (E1000_IVAR_ENTRY_VALID(int_cfg) && + E1000_IVAR_ENTRY_VEC(int_cfg) =3D=3D vec) { + causes |=3D E1000_ICR_TXQ1; + } + + int_cfg =3D E1000_IVAR_OTHER(core->mac[IVAR]); + if (E1000_IVAR_ENTRY_VALID(int_cfg) && + E1000_IVAR_ENTRY_VEC(int_cfg) =3D=3D vec) { + causes |=3D E1000_ICR_OTHER; + } + + return causes; +} + +static void +e1000e_msix_auto_clear_mask(E1000ECore *core, uint32_t cause); + static void e1000e_intrmgr_on_msix_throttling_timer(void *opaque) { E1000IntrDelayTimer *timer =3D opaque; - int idx =3D timer - &timer->core->eitr[0]; + E1000ECore *core =3D timer->core; + int idx =3D timer - &core->eitr[0]; + uint32_t causes; =20 timer->running =3D false; =20 + causes =3D find_msix_causes(core, idx); trace_e1000e_irq_msix_notify_postponed_vec(idx); - msix_notify(timer->core->owner, idx); + msix_notify(core->owner, idx); + e1000e_msix_auto_clear_mask(core, causes); } =20 static void @@ -1985,24 +2031,10 @@ e1000e_eitr_should_postpone(E1000ECore *core, int i= dx) } =20 static void -e1000e_msix_notify_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg) +e1000e_msix_auto_clear_mask(E1000ECore *core, uint32_t cause) { uint32_t effective_eiac; =20 - if (E1000_IVAR_ENTRY_VALID(int_cfg)) { - uint32_t vec =3D E1000_IVAR_ENTRY_VEC(int_cfg); - if (vec < E1000E_MSIX_VEC_NUM) { - if (!e1000e_eitr_should_postpone(core, vec)) { - trace_e1000e_irq_msix_notify_vec(vec); - msix_notify(core->owner, vec); - } - } else { - trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg); - } - } else { - trace_e1000e_wrn_msix_invalid(cause, int_cfg); - } - if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_EIAME) { trace_e1000e_irq_iam_clear_eiame(core->mac[IAM], cause); core->mac[IAM] &=3D ~cause; @@ -2019,6 +2051,26 @@ e1000e_msix_notify_one(E1000ECore *core, uint32_t ca= use, uint32_t int_cfg) } } =20 +static void +e1000e_msix_notify_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg) +{ + if (E1000_IVAR_ENTRY_VALID(int_cfg)) { + uint32_t vec =3D E1000_IVAR_ENTRY_VEC(int_cfg); + if (vec < E1000E_MSIX_VEC_NUM) { + if (!e1000e_eitr_should_postpone(core, vec)) { + trace_e1000e_irq_msix_notify_vec(vec); + msix_notify(core->owner, vec); + } + } else { + trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg); + } + } else { + trace_e1000e_wrn_msix_invalid(cause, int_cfg); + } + + e1000e_msix_auto_clear_mask(core, cause); +} + static void e1000e_msix_notify(E1000ECore *core, uint32_t causes) { --=20 2.47.1