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Thu, 01 May 2025 20:17:21 -0700 (PDT) From: Nicholas Piggin To: Akihiko Odaki Cc: Nicholas Piggin , qemu-devel@nongnu.org, Dmitry Fleytman , Jason Wang , Sriram Yagnaraman , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "Michael S. Tsirkin" , Marcel Apfelbaum Subject: [PATCH v3 01/12] qtest/e1000e|igb: Clear interrupt-cause and msix pending bits after irq Date: Fri, 2 May 2025 13:16:53 +1000 Message-ID: <20250502031705.100768-2-npiggin@gmail.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250502031705.100768-1-npiggin@gmail.com> References: <20250502031705.100768-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1746155874974124100 Content-Type: text/plain; charset="utf-8" The e1000e and igb tests do not clear the ICR/EICR cause bits (or set auto-clear) on seeing queue interrupts, which inhibits the triggering of a new interrupt. The msix pending bit which is used to test for the interrupt is also not cleared (the vector is masked). Fix this by clearing the ICR/EICR cause bits, and the msix pending bit using the PBACLR device register. Cc: Michael S. Tsirkin Cc: Marcel Apfelbaum Cc: Dmitry Fleytman Cc: Akihiko Odaki Cc: Sriram Yagnaraman Signed-off-by: Nicholas Piggin Reviewed-by: Fabiano Rosas --- tests/qtest/e1000e-test.c | 9 ++++++++- tests/qtest/igb-test.c | 8 ++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/tests/qtest/e1000e-test.c b/tests/qtest/e1000e-test.c index de9738fdb74..746d26cfb67 100644 --- a/tests/qtest/e1000e-test.c +++ b/tests/qtest/e1000e-test.c @@ -66,6 +66,10 @@ static void e1000e_send_verify(QE1000E *d, int *test_soc= kets, QGuestAllocator *a =20 /* Wait for TX WB interrupt */ e1000e_wait_isr(d, E1000E_TX0_MSG_ID); + /* Read ICR to make it ready for next interrupt, assert TXQ0 cause */ + g_assert(e1000e_macreg_read(d, E1000_ICR) & E1000_ICR_TXQ0); + /* Write PBACLR to clear the MSIX pending bit */ + e1000e_macreg_write(d, E1000_PBACLR, (1 << E1000E_TX0_MSG_ID)); =20 /* Check DD bit */ g_assert_cmphex(le32_to_cpu(descr.upper.data) & E1000_TXD_STAT_DD, =3D= =3D, @@ -117,7 +121,10 @@ static void e1000e_receive_verify(QE1000E *d, int *tes= t_sockets, QGuestAllocator =20 /* Wait for TX WB interrupt */ e1000e_wait_isr(d, E1000E_RX0_MSG_ID); - + /* Read ICR to make it ready for next interrupt, assert RXQ0 cause */ + g_assert(e1000e_macreg_read(d, E1000_ICR) & E1000_ICR_RXQ0); + /* Write PBACLR to clear the MSIX pending bit */ + e1000e_macreg_write(d, E1000_PBACLR, (1 << E1000E_RX0_MSG_ID)); /* Check DD bit */ g_assert_cmphex(le32_to_cpu(descr.wb.upper.status_error) & E1000_RXD_STAT_DD, =3D=3D, E1000_RXD_STAT_DD); diff --git a/tests/qtest/igb-test.c b/tests/qtest/igb-test.c index 3d397ea6973..cf8b4131cf2 100644 --- a/tests/qtest/igb-test.c +++ b/tests/qtest/igb-test.c @@ -69,6 +69,10 @@ static void igb_send_verify(QE1000E *d, int *test_socket= s, QGuestAllocator *allo =20 /* Wait for TX WB interrupt */ e1000e_wait_isr(d, E1000E_TX0_MSG_ID); + /* Read EICR which clears it ready for next interrupt, assert TXQ0 cau= se */ + g_assert(e1000e_macreg_read(d, E1000_EICR) & (1 << E1000E_TX0_MSG_ID)); + /* Write PBACLR to clear the MSIX pending bit */ + e1000e_macreg_write(d, E1000_PBACLR, (1 << E1000E_TX0_MSG_ID)); =20 /* Check DD bit */ g_assert_cmphex(le32_to_cpu(descr.wb.status) & E1000_TXD_STAT_DD, =3D= =3D, @@ -120,6 +124,10 @@ static void igb_receive_verify(QE1000E *d, int *test_s= ockets, QGuestAllocator *a =20 /* Wait for TX WB interrupt */ e1000e_wait_isr(d, E1000E_RX0_MSG_ID); + /* Read EICR which clears it ready for next interrupt, assert RXQ0 cau= se */ + g_assert(e1000e_macreg_read(d, E1000_EICR) & (1 << E1000E_RX0_MSG_ID)); + /* Write PBACLR to clear the MSIX pending bit */ + e1000e_macreg_write(d, E1000_PBACLR, (1 << E1000E_RX0_MSG_ID)); =20 /* Check DD bit */ g_assert_cmphex(le32_to_cpu(descr.wb.upper.status_error) & --=20 2.47.1