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Thu, 01 May 2025 20:05:13 -0700 (PDT) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Akihiko Odaki , Fabiano Rosas , Harsh Prateek Bora , John Snow , Laurent Vivier , Paolo Bonzini , "Michael S . Tsirkin" , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-block@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v5 03/11] tests/qtest: Add libqos function for testing msix interrupt status Date: Fri, 2 May 2025 13:04:37 +1000 Message-ID: <20250502030446.88310-4-npiggin@gmail.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250502030446.88310-1-npiggin@gmail.com> References: <20250502030446.88310-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1746155226980019100 This function is duplicated 3 times, with more potential future users. Factor it into libqos, using qtest_memset instead of qtest_writel to clear the message just because that looks nicer with the qtest_memread used to read it. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Nicholas Piggin --- tests/qtest/libqos/pci.h | 2 ++ tests/qtest/libqos/pci.c | 48 ++++++++++++++++++++++++++ tests/qtest/libqos/virtio-pci-modern.c | 31 +++-------------- tests/qtest/libqos/virtio-pci.c | 40 ++++----------------- 4 files changed, 62 insertions(+), 59 deletions(-) diff --git a/tests/qtest/libqos/pci.h b/tests/qtest/libqos/pci.h index 83896145235..9f8f154c301 100644 --- a/tests/qtest/libqos/pci.h +++ b/tests/qtest/libqos/pci.h @@ -92,6 +92,8 @@ void qpci_msix_enable(QPCIDevice *dev); void qpci_msix_disable(QPCIDevice *dev); bool qpci_msix_pending(QPCIDevice *dev, uint16_t entry); bool qpci_msix_masked(QPCIDevice *dev, uint16_t entry); +bool qpci_msix_test_interrupt(QPCIDevice *dev, uint32_t msix_entry, + uint64_t msix_addr, uint32_t msix_data); uint16_t qpci_msix_table_size(QPCIDevice *dev); =20 uint8_t qpci_config_readb(QPCIDevice *dev, uint8_t offset); diff --git a/tests/qtest/libqos/pci.c b/tests/qtest/libqos/pci.c index a59197b9922..773fd1fb6cf 100644 --- a/tests/qtest/libqos/pci.c +++ b/tests/qtest/libqos/pci.c @@ -351,6 +351,54 @@ bool qpci_msix_masked(QPCIDevice *dev, uint16_t entry) } } =20 +/** + * qpci_msix_test_interrupt - test whether msix interrupt has been raised + * @dev: PCI device + * @msix_entry: msix entry to test + * @msix_addr: address of msix message + * @msix_data: expected msix message payload + * + * This tests whether the msix source has raised an interrupt. If the msix + * entry is masked, it tests the pending bit array for a pending message + * and @msix_addr and @msix_data need not be supplied. If the entry is not + * masked, it tests the address for corresponding data to see if the inter= rupt + * fired. + * + * Note that this does not lower the interrupt, however it does clear the + * msix message address to 0 if it is found set. This must be called with + * the msix address memory containing either 0 or the value of data, other= wise + * it will assert on incorrect message. + */ +bool qpci_msix_test_interrupt(QPCIDevice *dev, uint32_t msix_entry, + uint64_t msix_addr, uint32_t msix_data) +{ + uint32_t data; + + g_assert(dev->msix_enabled); + g_assert_cmpint(msix_entry, !=3D, -1); + + if (qpci_msix_masked(dev, msix_entry)) { + /* No ISR checking should be done if masked, but read anyway */ + return qpci_msix_pending(dev, msix_entry); + } + + g_assert_cmpint(msix_addr, !=3D, 0); + g_assert_cmpint(msix_data, !=3D, 0); + + /* msix payload is written in little-endian format */ + qtest_memread(dev->bus->qts, msix_addr, &data, 4); + data =3D le32_to_cpu(data); + if (data =3D=3D 0) { + return false; + } + + /* got a message, ensure it matches expected value then clear it. */ + g_assert_cmphex(data, =3D=3D, msix_data); + qtest_memset(dev->bus->qts, msix_addr, 0, 4); + + return true; +} + uint16_t qpci_msix_table_size(QPCIDevice *dev) { uint8_t addr; diff --git a/tests/qtest/libqos/virtio-pci-modern.c b/tests/qtest/libqos/vi= rtio-pci-modern.c index 5dae41e6d74..0d7d89bbcb1 100644 --- a/tests/qtest/libqos/virtio-pci-modern.c +++ b/tests/qtest/libqos/virtio-pci-modern.c @@ -126,28 +126,6 @@ static void set_status(QVirtioDevice *d, uint8_t statu= s) status); } =20 -static bool get_msix_status(QVirtioPCIDevice *dev, uint32_t msix_entry, - uint32_t msix_addr, uint32_t msix_data) -{ - uint32_t data; - - g_assert_cmpint(msix_entry, !=3D, -1); - if (qpci_msix_masked(dev->pdev, msix_entry)) { - /* No ISR checking should be done if masked, but read anyway */ - return qpci_msix_pending(dev->pdev, msix_entry); - } - - qtest_memread(dev->pdev->bus->qts, msix_addr, &data, 4); - data =3D le32_to_cpu(data); - if (data =3D=3D 0) { - return false; - } - /* got a message, ensure it matches expected value then clear it. */ - g_assert_cmphex(data, =3D=3D, msix_data); - qtest_writel(dev->pdev->bus->qts, msix_addr, 0); - return true; -} - static bool get_queue_isr_status(QVirtioDevice *d, QVirtQueue *vq) { QVirtioPCIDevice *dev =3D container_of(d, QVirtioPCIDevice, vdev); @@ -155,8 +133,8 @@ static bool get_queue_isr_status(QVirtioDevice *d, QVir= tQueue *vq) if (dev->pdev->msix_enabled) { QVirtQueuePCI *vqpci =3D container_of(vq, QVirtQueuePCI, vq); =20 - return get_msix_status(dev, vqpci->msix_entry, vqpci->msix_addr, - vqpci->msix_data); + return qpci_msix_test_interrupt(dev->pdev, vqpci->msix_entry, + vqpci->msix_addr, vqpci->msix_data= ); } =20 return qpci_io_readb(dev->pdev, dev->bar, dev->isr_cfg_offset) & 1; @@ -167,8 +145,9 @@ static bool get_config_isr_status(QVirtioDevice *d) QVirtioPCIDevice *dev =3D container_of(d, QVirtioPCIDevice, vdev); =20 if (dev->pdev->msix_enabled) { - return get_msix_status(dev, dev->config_msix_entry, - dev->config_msix_addr, dev->config_msix_dat= a); + return qpci_msix_test_interrupt(dev->pdev, dev->config_msix_entry, + dev->config_msix_addr, + dev->config_msix_data); } =20 return qpci_io_readb(dev->pdev, dev->bar, dev->isr_cfg_offset) & 2; diff --git a/tests/qtest/libqos/virtio-pci.c b/tests/qtest/libqos/virtio-pc= i.c index 76ea1f45ba9..ea8114e2438 100644 --- a/tests/qtest/libqos/virtio-pci.c +++ b/tests/qtest/libqos/virtio-pci.c @@ -122,25 +122,12 @@ static void qvirtio_pci_set_status(QVirtioDevice *d, = uint8_t status) static bool qvirtio_pci_get_queue_isr_status(QVirtioDevice *d, QVirtQueue = *vq) { QVirtioPCIDevice *dev =3D container_of(d, QVirtioPCIDevice, vdev); - QVirtQueuePCI *vqpci =3D (QVirtQueuePCI *)vq; - uint32_t data; =20 if (dev->pdev->msix_enabled) { - g_assert_cmpint(vqpci->msix_entry, !=3D, -1); - if (qpci_msix_masked(dev->pdev, vqpci->msix_entry)) { - /* No ISR checking should be done if masked, but read anyway */ - return qpci_msix_pending(dev->pdev, vqpci->msix_entry); - } else { - qtest_memread(dev->pdev->bus->qts, vqpci->msix_addr, &data, 4); - data =3D le32_to_cpu(data); - if (data =3D=3D 0) { - return false; - } - /* got a message, ensure it matches expected value then clear = it. */ - g_assert_cmphex(data, =3D=3D, vqpci->msix_data); - qtest_writel(dev->pdev->bus->qts, vqpci->msix_addr, 0); - return true; - } + QVirtQueuePCI *vqpci =3D (QVirtQueuePCI *)vq; + + return qpci_msix_test_interrupt(dev->pdev, vqpci->msix_entry, + vqpci->msix_addr, vqpci->msix_data= ); } else { return qpci_io_readb(dev->pdev, dev->bar, VIRTIO_PCI_ISR) & 1; } @@ -149,24 +136,11 @@ static bool qvirtio_pci_get_queue_isr_status(QVirtioD= evice *d, QVirtQueue *vq) static bool qvirtio_pci_get_config_isr_status(QVirtioDevice *d) { QVirtioPCIDevice *dev =3D container_of(d, QVirtioPCIDevice, vdev); - uint32_t data; =20 if (dev->pdev->msix_enabled) { - g_assert_cmpint(dev->config_msix_entry, !=3D, -1); - if (qpci_msix_masked(dev->pdev, dev->config_msix_entry)) { - /* No ISR checking should be done if masked, but read anyway */ - return qpci_msix_pending(dev->pdev, dev->config_msix_entry); - } else { - qtest_memread(dev->pdev->bus->qts, dev->config_msix_addr, &dat= a, 4); - data =3D le32_to_cpu(data); - if (data =3D=3D 0) { - return false; - } - /* got a message, ensure it matches expected value then clear = it. */ - g_assert_cmphex(data, =3D=3D, dev->config_msix_data); - qtest_writel(dev->pdev->bus->qts, dev->config_msix_addr, 0); - return true; - } + return qpci_msix_test_interrupt(dev->pdev, dev->config_msix_entry, + dev->config_msix_addr, + dev->config_msix_data); } else { return qpci_io_readb(dev->pdev, dev->bar, VIRTIO_PCI_ISR) & 2; } --=20 2.47.1