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Thu, 01 May 2025 20:06:00 -0700 (PDT) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Akihiko Odaki , Fabiano Rosas , Harsh Prateek Bora , John Snow , Laurent Vivier , Paolo Bonzini , "Michael S . Tsirkin" , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-block@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v5 11/11] qtest/libqos/pci: Factor msix entry helpers into pci common code Date: Fri, 2 May 2025 13:04:45 +1000 Message-ID: <20250502030446.88310-12-npiggin@gmail.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250502030446.88310-1-npiggin@gmail.com> References: <20250502030446.88310-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1746155265354124100 Content-Type: text/plain; charset="utf-8" Setting msix entry address and data and masking is moved into common code helpers from virtio tests. For now that remains the only user, but there are changes under development to enable msix vectors for msix, e1000e, and xhci tests, which can make use of them. Reviewed-by: Akihiko Odaki Signed-off-by: Nicholas Piggin --- tests/qtest/libqos/pci.h | 3 ++ tests/qtest/libqos/pci.c | 53 +++++++++++++++++++++++++++++++++ tests/qtest/libqos/virtio-pci.c | 48 ++++------------------------- 3 files changed, 61 insertions(+), 43 deletions(-) diff --git a/tests/qtest/libqos/pci.h b/tests/qtest/libqos/pci.h index 852d4a85f6f..1c4f5406c58 100644 --- a/tests/qtest/libqos/pci.h +++ b/tests/qtest/libqos/pci.h @@ -96,8 +96,11 @@ void qpci_device_enable(QPCIDevice *dev); uint8_t qpci_find_capability(QPCIDevice *dev, uint8_t id, uint8_t start_ad= dr); void qpci_msix_enable(QPCIDevice *dev); void qpci_msix_disable(QPCIDevice *dev); +void qpci_msix_set_entry(QPCIDevice *dev, uint16_t entry, + uint64_t guest_addr, uint32_t data); bool qpci_msix_pending(QPCIDevice *dev, uint16_t entry); bool qpci_msix_masked(QPCIDevice *dev, uint16_t entry); +void qpci_msix_set_masked(QPCIDevice *dev, uint16_t entry, bool masked); bool qpci_msix_test_interrupt(QPCIDevice *dev, uint32_t msix_entry, uint64_t msix_addr, uint32_t msix_data); uint16_t qpci_msix_table_size(QPCIDevice *dev); diff --git a/tests/qtest/libqos/pci.c b/tests/qtest/libqos/pci.c index cc83dcc163a..e26cb4dee13 100644 --- a/tests/qtest/libqos/pci.c +++ b/tests/qtest/libqos/pci.c @@ -339,6 +339,25 @@ void qpci_msix_disable(QPCIDevice *dev) dev->msix_pba_off =3D 0; } =20 +void qpci_msix_set_entry(QPCIDevice *dev, uint16_t entry, + uint64_t guest_addr, uint32_t data) +{ + uint64_t vector_off =3D dev->msix_table_off + entry * PCI_MSIX_ENTRY_S= IZE; + + g_assert(dev->msix_enabled); + g_assert_cmpint(entry, >=3D, 0); + g_assert_cmpint(entry, <, qpci_msix_table_size(dev)); + + qpci_io_writel(dev, dev->msix_table_bar, + vector_off + PCI_MSIX_ENTRY_LOWER_ADDR, guest_addr & ~0= UL); + qpci_io_writel(dev, dev->msix_table_bar, + vector_off + PCI_MSIX_ENTRY_UPPER_ADDR, + (guest_addr >> 32) & ~0UL); + + qpci_io_writel(dev, dev->msix_table_bar, + vector_off + PCI_MSIX_ENTRY_DATA, data); +} + bool qpci_msix_pending(QPCIDevice *dev, uint16_t entry) { uint32_t pba_entry; @@ -346,6 +365,9 @@ bool qpci_msix_pending(QPCIDevice *dev, uint16_t entry) uint64_t off =3D (entry / 32) * PCI_MSIX_ENTRY_SIZE / 4; =20 g_assert(dev->msix_enabled); + g_assert_cmpint(entry, >=3D, 0); + g_assert_cmpint(entry, <, qpci_msix_table_size(dev)); + pba_entry =3D qpci_io_readl(dev, dev->msix_pba_bar, dev->msix_pba_off = + off); return (pba_entry & (1 << bit_n)) !=3D 0; } @@ -357,6 +379,9 @@ bool qpci_msix_masked(QPCIDevice *dev, uint16_t entry) uint64_t vector_off =3D dev->msix_table_off + entry * PCI_MSIX_ENTRY_S= IZE; =20 g_assert(dev->msix_enabled); + g_assert_cmpint(entry, >=3D, 0); + g_assert_cmpint(entry, <, qpci_msix_table_size(dev)); + addr =3D qpci_find_capability(dev, PCI_CAP_ID_MSIX, 0); g_assert_cmphex(addr, !=3D, 0); val =3D qpci_config_readw(dev, addr + PCI_MSIX_FLAGS); @@ -370,6 +395,34 @@ bool qpci_msix_masked(QPCIDevice *dev, uint16_t entry) } } =20 +void qpci_msix_set_masked(QPCIDevice *dev, uint16_t entry, bool masked) +{ + uint8_t addr; + uint16_t val; + uint64_t vector_off =3D dev->msix_table_off + entry * PCI_MSIX_ENTRY_S= IZE; + + g_assert(dev->msix_enabled); + g_assert_cmpint(entry, >=3D, 0); + g_assert_cmpint(entry, <, qpci_msix_table_size(dev)); + + addr =3D qpci_find_capability(dev, PCI_CAP_ID_MSIX, 0); + g_assert_cmphex(addr, !=3D, 0); + val =3D qpci_config_readw(dev, addr + PCI_MSIX_FLAGS); + g_assert(!(val & PCI_MSIX_FLAGS_MASKALL)); + + val =3D qpci_io_readl(dev, dev->msix_table_bar, + vector_off + PCI_MSIX_ENTRY_VECTOR_CTRL); + if (masked && !(val & PCI_MSIX_ENTRY_CTRL_MASKBIT)) { + qpci_io_writel(dev, dev->msix_table_bar, + vector_off + PCI_MSIX_ENTRY_VECTOR_CTRL, + val | PCI_MSIX_ENTRY_CTRL_MASKBIT); + } else if (!masked && (val & PCI_MSIX_ENTRY_CTRL_MASKBIT)) { + qpci_io_writel(dev, dev->msix_table_bar, + vector_off + PCI_MSIX_ENTRY_VECTOR_CTRL, + val & ~PCI_MSIX_ENTRY_CTRL_MASKBIT); + } +} + /** * qpci_msix_test_interrupt - test whether msix interrupt has been raised * @dev: PCI device diff --git a/tests/qtest/libqos/virtio-pci.c b/tests/qtest/libqos/virtio-pc= i.c index d6333a4d576..4e27b7a7931 100644 --- a/tests/qtest/libqos/virtio-pci.c +++ b/tests/qtest/libqos/virtio-pci.c @@ -299,66 +299,28 @@ void qvirtio_pci_device_disable(QVirtioPCIDevice *d) void qvirtqueue_pci_msix_setup(QVirtioPCIDevice *d, QVirtQueuePCI *vqpci, QGuestAllocator *alloc, uint16_t e= ntry) { - uint32_t control; - uint64_t off; - g_assert(d->pdev->msix_enabled); - off =3D d->pdev->msix_table_off + (entry * 16); - - g_assert_cmpint(entry, >=3D, 0); - g_assert_cmpint(entry, <, qpci_msix_table_size(d->pdev)); vqpci->msix_entry =3D entry; - vqpci->msix_addr =3D guest_alloc(alloc, 4); qtest_memset(d->pdev->bus->qts, vqpci->msix_addr, 0, 4); - qpci_io_writel(d->pdev, d->pdev->msix_table_bar, - off + PCI_MSIX_ENTRY_LOWER_ADDR, vqpci->msix_addr & ~0U= L); - qpci_io_writel(d->pdev, d->pdev->msix_table_bar, - off + PCI_MSIX_ENTRY_UPPER_ADDR, - (vqpci->msix_addr >> 32) & ~0UL); - qpci_io_writel(d->pdev, d->pdev->msix_table_bar, - off + PCI_MSIX_ENTRY_DATA, vqpci->msix_data); - - control =3D qpci_io_readl(d->pdev, d->pdev->msix_table_bar, - off + PCI_MSIX_ENTRY_VECTOR_CTRL); - qpci_io_writel(d->pdev, d->pdev->msix_table_bar, - off + PCI_MSIX_ENTRY_VECTOR_CTRL, - control & ~PCI_MSIX_ENTRY_CTRL_MASKBIT); =20 + qpci_msix_set_entry(d->pdev, entry, vqpci->msix_addr, vqpci->msix_data= ); + qpci_msix_set_masked(d->pdev, entry, false); d->msix_ops->set_queue_vector(d, vqpci->vq.index, entry); } =20 void qvirtio_pci_set_msix_configuration_vector(QVirtioPCIDevice *d, QGuestAllocator *alloc, uint16_t e= ntry) { - uint32_t control; - uint64_t off; - g_assert(d->pdev->msix_enabled); - off =3D d->pdev->msix_table_off + (entry * 16); - - g_assert_cmpint(entry, >=3D, 0); - g_assert_cmpint(entry, <, qpci_msix_table_size(d->pdev)); d->config_msix_entry =3D entry; - d->config_msix_data =3D 0x12345678; d->config_msix_addr =3D guest_alloc(alloc, 4); qtest_memset(d->pdev->bus->qts, d->config_msix_addr, 0, 4); =20 - qpci_io_writel(d->pdev, d->pdev->msix_table_bar, - off + PCI_MSIX_ENTRY_LOWER_ADDR, d->config_msix_addr & = ~0UL); - qpci_io_writel(d->pdev, d->pdev->msix_table_bar, - off + PCI_MSIX_ENTRY_UPPER_ADDR, - (d->config_msix_addr >> 32) & ~0UL); - qpci_io_writel(d->pdev, d->pdev->msix_table_bar, - off + PCI_MSIX_ENTRY_DATA, d->config_msix_data); - - control =3D qpci_io_readl(d->pdev, d->pdev->msix_table_bar, - off + PCI_MSIX_ENTRY_VECTOR_CTRL); - qpci_io_writel(d->pdev, d->pdev->msix_table_bar, - off + PCI_MSIX_ENTRY_VECTOR_CTRL, - control & ~PCI_MSIX_ENTRY_CTRL_MASKBIT); - + qpci_msix_set_entry(d->pdev, entry, d->config_msix_addr, + d->config_msix_data); + qpci_msix_set_masked(d->pdev, entry, false); d->msix_ops->set_config_vector(d, entry); } =20 --=20 2.47.1