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Fri, 2 May 2025 02:16:07 GMT Received: from alaljimee5bm-ol9-20250405.osdevelopmeniad.oraclevcn.com (alaljimee5bm-ol9-20250405.allregionaliads.osdevelopmeniad.oraclevcn.com [100.100.254.235]) by iadpaimrmta03.imrmtpd1.prodappiadaev1.oraclevcn.com (PPS) with ESMTP id 468nxkgyvr-2; Fri, 02 May 2025 02:16:07 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=corp-2025-04-25; bh=hKrBO z8OIwOttjAENHLGK1nsTuVaVp/DcWOGP++OoSY=; b=a4zmTwlUpNPhQ+a9fMz6l e6x5emBF62Aea3zFGNuniQJY3+EFpqw0EIifGEbiFe2lH5Lm9/A18+n8kdN4wBYI /LUvnBUpjwQ1oLg82PAUXaXxn1txsrmT/SJQO7cZ/0IrxffiD8FMyvKYsSX/SxrN XjhbfKhvJeM2lTFb9bk92eAU1F7DYFIxa4JcisycKbTPjrlLnQsLsNkZeSKLQ4tx +P38sjPJMDq2uptEqx4yLRWQyHS1nu1J1j6jwoml8aDlimQj8mF11TbVJ6+hPdcZ y1BA1zagEQXh7Zd6Sjav0V7OA0L4YB1vyuulwJo9ZDcbbg6lMiHRf4e2XCtg3tnl g== From: Alejandro Jimenez To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, richard.henderson@linaro.org, eduardo@habkost.net, peterx@redhat.com, david@redhat.com, philmd@linaro.org, mst@redhat.com, marcel.apfelbaum@gmail.com, alex.williamson@redhat.com, vasant.hegde@amd.com, suravee.suthikulpanit@amd.com, santosh.shukla@amd.com, sarunkod@amd.com, Wei.Huang2@amd.com, clement.mathieu--drif@eviden.com, ethan.milon@eviden.com, joao.m.martins@oracle.com, boris.ostrovsky@oracle.com, alejandro.j.jimenez@oracle.com Subject: [PATCH v2 01/20] memory: Adjust event ranges to fit within notifier boundaries Date: Fri, 2 May 2025 02:15:46 +0000 Message-ID: <20250502021605.1795985-2-alejandro.j.jimenez@oracle.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20250502021605.1795985-1-alejandro.j.jimenez@oracle.com> References: <20250502021605.1795985-1-alejandro.j.jimenez@oracle.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-01_06,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxlogscore=999 phishscore=0 suspectscore=0 spamscore=0 adultscore=0 mlxscore=0 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2504070000 definitions=main-2505020015 X-Proofpoint-GUID: G_5WN9qPnXwEZv7UuO8SS6CE95BnrHbd X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDAxNCBTYWx0ZWRfX+2mUSjIEkhj2 YkjZPV5Xn1Lf8jVPfEBKOt8AgzqKfGUMEI/sJRP8NH/nbl7eVI+frvs9MtV6PeCRyMm40dLpqrq J3Doby5XZRUm0b6S9eg+PA5mF+KWHKTNgRxPfT+L1JCHgj+D4CUGxF6iHwrMCf49la+Ob8x5hXZ o2RFQKBe4Ejv2M31RRS8kD+Z/p7FD/Tv8NXoJndetZlYLH2ZbrniGTHx1q0VSDIZK+9ZQ33g3IK Fgf8daBqRVJSPHbHBCvt9OD6+cpkoJlqpKuYwl1MAKzG0rcnbUmTbLIIA1YQG1ng4fhBCPI6iJk mYs+gE+dUKDCekOZendPHIUmFVv5+YTZEvahGmXGEtJGA337cEepLfqVzqq5eiEKLPW6chqveE6 do5cL5CBrKr7VNbMlcnW+l8lrg29iISNfF1kJiP7AS086vqiQyZ6gmgGpmIRGy4iWCf012PG X-Authority-Analysis: v=2.4 cv=ZuHtK87G c=1 sm=1 tr=0 ts=68142ae9 b=1 cx=c_pps a=qoll8+KPOyaMroiJ2sR5sw==:117 a=qoll8+KPOyaMroiJ2sR5sw==:17 a=dt9VzEwgFbYA:10 a=yPCof4ZbAAAA:8 a=JiNCCaSHPG-izbK7Su4A:9 cc=ntf awl=host:13130 X-Proofpoint-ORIG-GUID: G_5WN9qPnXwEZv7UuO8SS6CE95BnrHbd Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Invalidating the entire address space (i.e. range of [0, ~0ULL]) is a valid and required operation by vIOMMU implementations. However, such invalidations currently trigger an assertion unless they originate from device IOTLB invalidations. Although in recent Linux guests this case is not exercised by the VTD implementation due to various optimizations, the assertion will be hit by upcoming AMD vIOMMU changes to support DMA address translation. More specifically, when running a Linux guest with VFIO passthrough device, and a kernel that does not contain commmit 3f2571fed2fa ("iommu/amd: Remove redundant domain flush from attach_device()"). Remove the assertion altogether and adjust the range to ensure it does not cross notifier boundaries. Signed-off-by: Alejandro Jimenez Tested-by: Sairaj Kodilkar --- system/memory.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/system/memory.c b/system/memory.c index 71434e7ad02c..7ad2fc098341 100644 --- a/system/memory.c +++ b/system/memory.c @@ -2021,13 +2021,9 @@ void memory_region_notify_iommu_one(IOMMUNotifier *n= otifier, return; } =20 - if (notifier->notifier_flags & IOMMU_NOTIFIER_DEVIOTLB_UNMAP) { - /* Crop (iova, addr_mask) to range */ - tmp.iova =3D MAX(tmp.iova, notifier->start); - tmp.addr_mask =3D MIN(entry_end, notifier->end) - tmp.iova; - } else { - assert(entry->iova >=3D notifier->start && entry_end <=3D notifier= ->end); - } + /* Crop (iova, addr_mask) to range */ + tmp.iova =3D MAX(tmp.iova, notifier->start); + tmp.addr_mask =3D MIN(entry_end, notifier->end) - tmp.iova; =20 if (event->type & notifier->notifier_flags) { notifier->notify(notifier, &tmp); --=20 2.43.5 From nobody Mon Feb 9 09:04:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Document the common parameters used when emulating AMD vIOMMU. Besides the two amd-iommu specific options: 'xtsup' and 'dma-remap', the the generic x86 IOMMU option 'intremap' is also included, since it is typically specified in QEMU command line examples and mailing list threads. Signed-off-by: Alejandro Jimenez Tested-by: Sairaj Kodilkar --- qemu-options.hx | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/qemu-options.hx b/qemu-options.hx index dc694a99a30a..198acab48e8e 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -1226,6 +1226,29 @@ SRST ``aw-bits=3Dval`` (val between 32 and 64, default depends on machine) This decides the address width of the IOVA address space. =20 +``-device amd-iommu[,option=3D...]`` + Enables emulation of an AMD-Vi I/O Memory Management Unit (IOMMU). + Only available with ``-machine q35``, it supports the following option= s: + + ``dma-remap=3Don|off`` (default: off) + Support for DMA address translation and access permission checking= for + guests attaching passthrough devices to paging domains, using the = AMD v1 + I/O Page Table format. This enables ``-device vfio-pci,...`` to wo= rk + correctly with a guest using the DMA remapping feature of the vIOM= MU. + + ``intremap=3Don|off`` (default: auto) + Generic x86 IOMMU functionality implemented by ``amd-iommu`` devic= e. + Enables interrupt remapping feature in guests, which is also requi= red to + enable x2apic support. + Currently only available with ``kernel-irqchip=3Doff|split``, it is + automatically enabled when either of those modes is in use, and di= sabled + with ``kernel-irqchip=3Don``. + + ``xtsup=3Don|off`` (default: off) + Interrupt remapping table supports x2apic mode, enabling the use of + 128-bit IRTE format with 32-bit destination field by the guest. Re= quired + to support routing interrupts to vCPUs with APIC IDs larger than 0= xff. + ERST =20 DEF("name", HAS_ARG, QEMU_OPTION_name, --=20 2.43.5 From nobody Mon Feb 9 09:04:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1746152390; cv=none; d=zohomail.com; s=zohoarc; b=lO8g+3cgmwrAszRKRQyjBMrB8qy3Qk7vFYd7016rtn4E8COW3CKp7bb+m7uAZbiuUg/u8yd6lfr+6iZx2mUC6OzjRP3Sp5Ol0SBLLW8OGWD3xhE5irfXnBS6jceUHxnZfjutQ0pRtAfBErisqXAA48DsGXvuqZqj2PAdqt22VVQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746152390; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" Move code related to Device Table and Page Table to an earlier location in the file, where it does not require forward declarations to be used by the various invalidation functions that will need to query the DTE and walk the page table in upcoming changes. This change consist of code movement only, no functional change intended. Signed-off-by: Alejandro Jimenez Tested-by: Sairaj Kodilkar --- hw/i386/amd_iommu.c | 170 ++++++++++++++++++++++---------------------- 1 file changed, 85 insertions(+), 85 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 2cf7e24a21d8..9e500121f6e8 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -407,6 +407,91 @@ static void amdvi_completion_wait(AMDVIState *s, uint6= 4_t *cmd) trace_amdvi_completion_wait(addr, data); } =20 +static inline uint64_t amdvi_get_perms(uint64_t entry) +{ + return (entry & (AMDVI_DEV_PERM_READ | AMDVI_DEV_PERM_WRITE)) >> + AMDVI_DEV_PERM_SHIFT; +} + +/* validate that reserved bits are honoured */ +static bool amdvi_validate_dte(AMDVIState *s, uint16_t devid, + uint64_t *dte) +{ + if ((dte[0] & AMDVI_DTE_LOWER_QUAD_RESERVED) + || (dte[1] & AMDVI_DTE_MIDDLE_QUAD_RESERVED) + || (dte[2] & AMDVI_DTE_UPPER_QUAD_RESERVED) || dte[3]) { + amdvi_log_illegaldevtab_error(s, devid, + s->devtab + + devid * AMDVI_DEVTAB_ENTRY_SIZE, 0); + return false; + } + + return true; +} + +/* get a device table entry given the devid */ +static bool amdvi_get_dte(AMDVIState *s, int devid, uint64_t *entry) +{ + uint32_t offset =3D devid * AMDVI_DEVTAB_ENTRY_SIZE; + + if (dma_memory_read(&address_space_memory, s->devtab + offset, entry, + AMDVI_DEVTAB_ENTRY_SIZE, MEMTXATTRS_UNSPECIFIED)) { + trace_amdvi_dte_get_fail(s->devtab, offset); + /* log error accessing dte */ + amdvi_log_devtab_error(s, devid, s->devtab + offset, 0); + return false; + } + + *entry =3D le64_to_cpu(*entry); + if (!amdvi_validate_dte(s, devid, entry)) { + trace_amdvi_invalid_dte(entry[0]); + return false; + } + + return true; +} + +/* get pte translation mode */ +static inline uint8_t get_pte_translation_mode(uint64_t pte) +{ + return (pte >> AMDVI_DEV_MODE_RSHIFT) & AMDVI_DEV_MODE_MASK; +} + +static inline uint64_t pte_override_page_mask(uint64_t pte) +{ + uint8_t page_mask =3D 13; + uint64_t addr =3D (pte & AMDVI_DEV_PT_ROOT_MASK) >> 12; + /* find the first zero bit */ + while (addr & 1) { + page_mask++; + addr =3D addr >> 1; + } + + return ~((1ULL << page_mask) - 1); +} + +static inline uint64_t pte_get_page_mask(uint64_t oldlevel) +{ + return ~((1UL << ((oldlevel * 9) + 3)) - 1); +} + +static inline uint64_t amdvi_get_pte_entry(AMDVIState *s, uint64_t pte_add= r, + uint16_t devid) +{ + uint64_t pte; + + if (dma_memory_read(&address_space_memory, pte_addr, + &pte, sizeof(pte), MEMTXATTRS_UNSPECIFIED)) { + trace_amdvi_get_pte_hwerror(pte_addr); + amdvi_log_pagetab_error(s, devid, pte_addr, 0); + pte =3D 0; + return pte; + } + + pte =3D le64_to_cpu(pte); + return pte; +} + /* log error without aborting since linux seems to be using reserved bits = */ static void amdvi_inval_devtab_entry(AMDVIState *s, uint64_t *cmd) { @@ -838,91 +923,6 @@ static void amdvi_mmio_write(void *opaque, hwaddr addr= , uint64_t val, } } =20 -static inline uint64_t amdvi_get_perms(uint64_t entry) -{ - return (entry & (AMDVI_DEV_PERM_READ | AMDVI_DEV_PERM_WRITE)) >> - AMDVI_DEV_PERM_SHIFT; -} - -/* validate that reserved bits are honoured */ -static bool amdvi_validate_dte(AMDVIState *s, uint16_t devid, - uint64_t *dte) -{ - if ((dte[0] & AMDVI_DTE_LOWER_QUAD_RESERVED) - || (dte[1] & AMDVI_DTE_MIDDLE_QUAD_RESERVED) - || (dte[2] & AMDVI_DTE_UPPER_QUAD_RESERVED) || dte[3]) { - amdvi_log_illegaldevtab_error(s, devid, - s->devtab + - devid * AMDVI_DEVTAB_ENTRY_SIZE, 0); - return false; - } - - return true; -} - -/* get a device table entry given the devid */ -static bool amdvi_get_dte(AMDVIState *s, int devid, uint64_t *entry) -{ - uint32_t offset =3D devid * AMDVI_DEVTAB_ENTRY_SIZE; - - if (dma_memory_read(&address_space_memory, s->devtab + offset, entry, - AMDVI_DEVTAB_ENTRY_SIZE, MEMTXATTRS_UNSPECIFIED)) { - trace_amdvi_dte_get_fail(s->devtab, offset); - /* log error accessing dte */ - amdvi_log_devtab_error(s, devid, s->devtab + offset, 0); - return false; - } - - *entry =3D le64_to_cpu(*entry); - if (!amdvi_validate_dte(s, devid, entry)) { - trace_amdvi_invalid_dte(entry[0]); - return false; - } - - return true; -} - -/* get pte translation mode */ -static inline uint8_t get_pte_translation_mode(uint64_t pte) -{ - return (pte >> AMDVI_DEV_MODE_RSHIFT) & AMDVI_DEV_MODE_MASK; -} - -static inline uint64_t pte_override_page_mask(uint64_t pte) -{ - uint8_t page_mask =3D 13; - uint64_t addr =3D (pte & AMDVI_DEV_PT_ROOT_MASK) >> 12; - /* find the first zero bit */ - while (addr & 1) { - page_mask++; - addr =3D addr >> 1; - } - - return ~((1ULL << page_mask) - 1); -} - -static inline uint64_t pte_get_page_mask(uint64_t oldlevel) -{ - return ~((1UL << ((oldlevel * 9) + 3)) - 1); -} - -static inline uint64_t amdvi_get_pte_entry(AMDVIState *s, uint64_t pte_add= r, - uint16_t devid) -{ - uint64_t pte; - - if (dma_memory_read(&address_space_memory, pte_addr, - &pte, sizeof(pte), MEMTXATTRS_UNSPECIFIED)) { - trace_amdvi_get_pte_hwerror(pte_addr); - amdvi_log_pagetab_error(s, devid, pte_addr, 0); - pte =3D 0; - return pte; - } - - pte =3D le64_to_cpu(pte); - return pte; -} - static void amdvi_page_walk(AMDVIAddressSpace *as, uint64_t *dte, IOMMUTLBEntry *ret, unsigned perms, hwaddr addr) --=20 2.43.5 From nobody Mon Feb 9 09:04:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; 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Fri, 02 May 2025 02:16:09 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=corp-2025-04-25; bh=zoGe6 YyEra8gRkKlb1MUbh2SB2o7LNCG7SXe9RaFZc4=; b=Qc67yLWOXsuB+wpy5UP19 EiP1PVUs2xyf2kJnlF3d5kX3HTdMyNoprjdlzOF43+AOwOiRP9iHWLdt2bpTHq3p 9KUBEVu0aMdYzcD2VOX2ThUE9apPADRY6MWupjQgYgJoPUAiw/UVtNov5XjHIvP7 QYRw7CHh9UEe6eGeV9k3ILho+YtMM16FPW+W9N/RxoPgmXVFSRqQE7l5tNuYXxos WXd1ZR+Aw2SIaFWpiQl/11CtBbuwMV4uMoKtukrAscUXI3hhTJyC9+p6zzTYDLO3 C2DbFA+nqKRr3MQ4ZbgRbH2oZ7AcHgY24RfVms1BEexVMBG2k/e3VkpewE1TYSi8 Q== From: Alejandro Jimenez To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, richard.henderson@linaro.org, eduardo@habkost.net, peterx@redhat.com, david@redhat.com, philmd@linaro.org, mst@redhat.com, marcel.apfelbaum@gmail.com, alex.williamson@redhat.com, vasant.hegde@amd.com, suravee.suthikulpanit@amd.com, santosh.shukla@amd.com, sarunkod@amd.com, Wei.Huang2@amd.com, clement.mathieu--drif@eviden.com, ethan.milon@eviden.com, joao.m.martins@oracle.com, boris.ostrovsky@oracle.com, alejandro.j.jimenez@oracle.com Subject: [PATCH v2 04/20] amd_iommu: Helper to decode size of page invalidation command Date: Fri, 2 May 2025 02:15:49 +0000 Message-ID: <20250502021605.1795985-5-alejandro.j.jimenez@oracle.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20250502021605.1795985-1-alejandro.j.jimenez@oracle.com> References: <20250502021605.1795985-1-alejandro.j.jimenez@oracle.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-01_06,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxlogscore=999 phishscore=0 suspectscore=0 spamscore=0 adultscore=0 mlxscore=0 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2504070000 definitions=main-2505020015 X-Proofpoint-ORIG-GUID: GYRyDCh9PFgfJeJQKMSsDFC-5aDdjm07 X-Authority-Analysis: v=2.4 cv=Vq8jA/2n c=1 sm=1 tr=0 ts=68142aeb b=1 cx=c_pps a=qoll8+KPOyaMroiJ2sR5sw==:117 a=qoll8+KPOyaMroiJ2sR5sw==:17 a=dt9VzEwgFbYA:10 a=yPCof4ZbAAAA:8 a=ZVecacK4M2hnvEF20eUA:9 cc=ntf awl=host:13130 X-Proofpoint-GUID: GYRyDCh9PFgfJeJQKMSsDFC-5aDdjm07 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDAxNSBTYWx0ZWRfX8++b010sODFu QSvIGAuSYb8KKlWl2+s0EcUKUrkHt/0DkVhAEuBSRZQC1u/LGdTp0s7Pjv3ODYiFmyMyosqLaHX ZIqXIyvdg/w8zSCM6kukSD4hSXS+nOWVaikYyohCyxBCSMElV/2cl35Q3IlfrdDjCUbZOIoNAvU xNo6oQ2bWkVzEHrJIfvn9wKkbbxUhkfq9UFVXIfdCOd3NaaH0ZKvLnAIq7wvwzrAwBbqsEfZ+OE 7PKp6JNJ/QtDfaH8mFol17gFMQv4jz2hWad4059TK3uiLKihH8wbJYgSTocsLyFi+3rCxkh5FvE FZDAJnYyxNYoHx3mf69yYiWdv9fRAPdQ6cjmUJBZSlmrX44XWZ+eAWNckr5BO1gIsgh3nOPnTUd 1UUQ0flL0bzkZ1tYmNYYApB8rHoD+1EQJ9lU264Cx9o+fE/cezhfsFtH3xyX/kmmhPcm+Ro5 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" The size of the region to invalidate depends on the S bit and address encoded in the command. Add a helper to extract this information, which will be used to sync shadow page tables in upcoming changes. Signed-off-by: Alejandro Jimenez Tested-by: Sairaj Kodilkar --- hw/i386/amd_iommu.c | 34 ++++++++++++++++++++++++++++++++++ hw/i386/amd_iommu.h | 4 ++++ 2 files changed, 38 insertions(+) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 9e500121f6e8..dff6f04c8651 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -545,6 +545,40 @@ static gboolean amdvi_iotlb_remove_by_domid(gpointer k= ey, gpointer value, return entry->domid =3D=3D domid; } =20 +/* + * Helper to decode the size of the range to invalidate encoded in the + * INVALIDATE_IOMMU_PAGES Command format. + * The size of the region to invalidate depends on the S bit and address. + * S bit value: + * 0 : Invalidation size is 4 Kbytes. + * 1 : Invalidation size is determined by first zero bit in the address + * starting from Address[12]. + * + * In the AMD IOMMU Linux driver, an invalidation command with address + * ((1 << 63) - 1) is sent when intending to clear the entire cache. + * However, Table 14: Example Page Size Encodings shows that an address of + * ((1ULL << 51) - 1) encodes the entire cache, so effectively any address= with + * first zero at bit 51 or larger is a request to invalidate the entire ad= dress + * space. + */ +static uint64_t __attribute__((unused)) +amdvi_decode_invalidation_size(hwaddr addr, uint16_t flags) +{ + uint64_t size =3D AMDVI_PAGE_SIZE; + uint8_t fzbit =3D 0; + + if (flags & AMDVI_CMD_INVAL_IOMMU_PAGES_S) { + fzbit =3D cto64(addr | 0xFFF); + + if (fzbit >=3D 51) { + size =3D AMDVI_INV_ALL_PAGES; + } else { + size =3D 1ULL << (fzbit + 1); + } + } + return size; +} + /* we don't have devid - we can't remove pages by address */ static void amdvi_inval_pages(AMDVIState *s, uint64_t *cmd) { diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index 28125130c6fc..6f35b0595054 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -123,6 +123,10 @@ #define AMDVI_CMD_COMPLETE_PPR_REQUEST 0x07 #define AMDVI_CMD_INVAL_AMDVI_ALL 0x08 =20 + +#define AMDVI_CMD_INVAL_IOMMU_PAGES_S (1ULL << 0) +#define AMDVI_INV_ALL_PAGES (1ULL << 52) + #define AMDVI_DEVTAB_ENTRY_SIZE 32 =20 /* Device table entry bits 0:63 */ --=20 2.43.5 From nobody Mon Feb 9 09:04:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=corp-2025-04-25; bh=hpsuf gT5jNLYenP3VebynLEFuRx2pYt00pc+2Sm8wgY=; b=lexn2cH67Dt1GzPElN34V zArbXYbHmD2QTl9JJzvim6uJNB/Rac7priHR3YSIaIe7rAa1mVzNFmBPWyW/H1B3 LsatjXophDgBPtl7Pn83zIWuoQEOpbNovdSOtK5lRKoVC95R1zf+wShux66UYm+g WZP7bflFGDF0K46hHi8UiGnnX3bz7vERZKdhi+ktsMQV2Gi2a0J6lufIjepeyYqJ vtFkj53lp2O5HSBu1GGze1c5tzrkf3YR1VCO9cBfI4LG57QrJ6o6kX7yoF5t0JlF Bzq8lWRBS6QvZtEM/CxCzETFead5aynz1/ovO2IopfpNgxvMPQ1Z1SCjzv084NEQ g== From: Alejandro Jimenez To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, richard.henderson@linaro.org, eduardo@habkost.net, peterx@redhat.com, david@redhat.com, philmd@linaro.org, mst@redhat.com, marcel.apfelbaum@gmail.com, alex.williamson@redhat.com, vasant.hegde@amd.com, suravee.suthikulpanit@amd.com, santosh.shukla@amd.com, sarunkod@amd.com, Wei.Huang2@amd.com, clement.mathieu--drif@eviden.com, ethan.milon@eviden.com, joao.m.martins@oracle.com, boris.ostrovsky@oracle.com, alejandro.j.jimenez@oracle.com Subject: [PATCH v2 05/20] amd_iommu: Add helper function to extract the DTE Date: Fri, 2 May 2025 02:15:50 +0000 Message-ID: <20250502021605.1795985-6-alejandro.j.jimenez@oracle.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20250502021605.1795985-1-alejandro.j.jimenez@oracle.com> References: <20250502021605.1795985-1-alejandro.j.jimenez@oracle.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-01_06,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxlogscore=999 phishscore=0 suspectscore=0 spamscore=0 adultscore=0 mlxscore=0 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2504070000 definitions=main-2505020015 X-Proofpoint-ORIG-GUID: Z_neTDe7WxXAc2nqz9aMEh47JqN5stg5 X-Proofpoint-GUID: Z_neTDe7WxXAc2nqz9aMEh47JqN5stg5 X-Authority-Analysis: v=2.4 cv=Hd0UTjE8 c=1 sm=1 tr=0 ts=68142aec b=1 cx=c_pps a=qoll8+KPOyaMroiJ2sR5sw==:117 a=qoll8+KPOyaMroiJ2sR5sw==:17 a=dt9VzEwgFbYA:10 a=yPCof4ZbAAAA:8 a=e7RXMJMBNNZR3-p0WbYA:9 cc=ntf awl=host:13130 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDAxNSBTYWx0ZWRfX6XC/Aco6TGIh B4HUMKUbFp3LzMBT6Pukjw8S+ImecTLSdJNqsWZfXWOvkRRZyyIn6x9g6fdRQk9NcUq5dBW7FcL edBYIEUBfbiiTlrJHQwDooPLkmG0W9ZA3sFVg8iGzt1HUo9/QPW2evCybs3vim9SowPOJ7RRmiy /XJIVX4tFsmy4yM16RePg7irlTQoiBPTRTHN55UDm0uoa/M9aNfFWJR+cYZJwHNileD2IPllHoG Xt744tXwZR73p1L09Zv+aZfKrClQTb0HRB71KD5GkgToRK2l9whTnMZWkipRORx2+jg+C84Gi4V jcXwSj8RjbUETXQ7tQ/mEDyhMGyqTb4pe0Z3xA2DXCChOZK1TLVBQMPNhCTKypPimQOVuJrjeTA SQTHj9IHbfgANhQ8eZbzDhEwSjaki0JN2B+9wBU0cohMtwdkbuN0Ryrr+8wnmjFB8Hp1SHKZ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Extracting the DTE from a given AMDVIAddressSpace pointer structure is a common operation required for syncing the shadow page tables. Implement a helper to do it and check for common error conditions. Signed-off-by: Alejandro Jimenez Tested-by: Sairaj Kodilkar --- hw/i386/amd_iommu.c | 45 ++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 40 insertions(+), 5 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index dff6f04c8651..5322a614f5d6 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -77,6 +77,18 @@ typedef struct AMDVIIOTLBEntry { uint64_t page_mask; /* physical page size */ } AMDVIIOTLBEntry; =20 +/* + * These 'fault' reasons have an overloaded meaning since they are not only + * intended for describing reasons that generate an IO_PAGE_FAULT as per t= he AMD + * IOMMU specification, but are also used to signal internal errors in the + * emulation code. + */ +typedef enum AMDVIFaultReason { + AMDVI_FR_DTE_RTR_ERR =3D 1, /* Failure to retrieve DTE */ + AMDVI_FR_DTE_V, /* DTE[V] =3D 0 */ + AMDVI_FR_DTE_TV, /* DTE[TV] =3D 0 */ +} AMDVIFaultReason; + uint64_t amdvi_extended_feature_register(AMDVIState *s) { uint64_t feature =3D AMDVI_DEFAULT_EXT_FEATURES; @@ -492,6 +504,28 @@ static inline uint64_t amdvi_get_pte_entry(AMDVIState = *s, uint64_t pte_addr, return pte; } =20 +static int amdvi_as_to_dte(AMDVIAddressSpace *as, uint64_t *dte) +{ + uint16_t devid =3D PCI_BUILD_BDF(as->bus_num, as->devfn); + AMDVIState *s =3D as->iommu_state; + + if (!amdvi_get_dte(s, devid, dte)) { + /* Unable to retrieve DTE for devid */ + return -AMDVI_FR_DTE_RTR_ERR; + } + + if (!(dte[0] & AMDVI_DEV_VALID)) { + /* DTE[V] not set, address is passed untranslated for devid */ + return -AMDVI_FR_DTE_V; + } + + if (!(dte[0] & AMDVI_DEV_TRANSLATION_VALID)) { + /* DTE[TV] not set, host page table not valid for devid */ + return -AMDVI_FR_DTE_TV; + } + return 0; +} + /* log error without aborting since linux seems to be using reserved bits = */ static void amdvi_inval_devtab_entry(AMDVIState *s, uint64_t *cmd) { @@ -1024,6 +1058,7 @@ static void amdvi_do_translate(AMDVIAddressSpace *as,= hwaddr addr, uint16_t devid =3D PCI_BUILD_BDF(as->bus_num, as->devfn); AMDVIIOTLBEntry *iotlb_entry =3D amdvi_iotlb_lookup(s, addr, devid); uint64_t entry[4]; + int dte_ret; =20 if (iotlb_entry) { trace_amdvi_iotlb_hit(PCI_BUS_NUM(devid), PCI_SLOT(devid), @@ -1035,13 +1070,13 @@ static void amdvi_do_translate(AMDVIAddressSpace *a= s, hwaddr addr, return; } =20 - if (!amdvi_get_dte(s, devid, entry)) { - return; - } + dte_ret =3D amdvi_as_to_dte(as, entry); =20 - /* devices with V =3D 0 are not translated */ - if (!(entry[0] & AMDVI_DEV_VALID)) { + if (dte_ret =3D=3D -AMDVI_FR_DTE_V) { + /* DTE[V]=3D0, address is passed untranslated */ goto out; + } else if (dte_ret =3D=3D -AMDVI_FR_DTE_TV) { + return; } =20 amdvi_page_walk(as, entry, ret, --=20 2.43.5 From nobody Mon Feb 9 09:04:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1746152397; cv=none; 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charset="utf-8" Make amdvi_get_pte_entry() return an error value (-1) in cases where the memory read fails, versus the current return of 0 to indicate failure. The reason is that 0 is also a valid PTE value, and it is useful to know when a PTE points to memory that is zero i.e. the guest unmapped the page. Signed-off-by: Alejandro Jimenez Tested-by: Sairaj Kodilkar --- hw/i386/amd_iommu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 5322a614f5d6..698967cc1a88 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -496,7 +496,7 @@ static inline uint64_t amdvi_get_pte_entry(AMDVIState *= s, uint64_t pte_addr, &pte, sizeof(pte), MEMTXATTRS_UNSPECIFIED)) { trace_amdvi_get_pte_hwerror(pte_addr); amdvi_log_pagetab_error(s, devid, pte_addr, 0); - pte =3D 0; + pte =3D (uint64_t)-1; return pte; } =20 @@ -1024,7 +1024,7 @@ static void amdvi_page_walk(AMDVIAddressSpace *as, ui= nt64_t *dte, /* add offset and load pte */ pte_addr +=3D ((addr >> (3 + 9 * level)) & 0x1FF) << 3; pte =3D amdvi_get_pte_entry(as->iommu_state, pte_addr, as->dev= fn); - if (!pte) { + if (!pte || (pte =3D=3D (uint64_t)-1)) { return; } oldlevel =3D level; --=20 2.43.5 From nobody Mon Feb 9 09:04:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 2 May 2025 02:16:11 GMT Received: from alaljimee5bm-ol9-20250405.osdevelopmeniad.oraclevcn.com (alaljimee5bm-ol9-20250405.allregionaliads.osdevelopmeniad.oraclevcn.com [100.100.254.235]) by iadpaimrmta03.imrmtpd1.prodappiadaev1.oraclevcn.com (PPS) with ESMTP id 468nxkgyvr-8; Fri, 02 May 2025 02:16:11 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=corp-2025-04-25; bh=SN4nf EL87DQOWsJXiUY5OwrVT2mpuVBirz/b+gLKWMs=; b=Y51j535ONCx5XQmm8RmLp VEsrfh6CMRuCHXCs5TeiOY7XoSRhwau58sFFPvTzUP9XWLhEVyb93a0Cv9E7orhp W8789EEC77GaSAkH4jkXIpqJRkCPcW7gg6wr0wpeeaZCCd8GPbQk6OZlsEPXpmee qNwC132E9KRAj1t6YcptCC6F2ZZM5mv4e2QoMtVz3TVF5Yf6mFi5q5HHzC1YvV9H 1A4F2F7N05mzsXWyWlPreeajLwc9JRMD8/9CicxibRgMpm1ZKp9w/Kp1HVQJr2KU oVACoKaU5hMgHCcoZdGbMFEa+l4sn2/rdTuN9tyAl3PdolLTBhk79nPIHICzxlrj A== From: Alejandro Jimenez To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, richard.henderson@linaro.org, eduardo@habkost.net, peterx@redhat.com, david@redhat.com, philmd@linaro.org, mst@redhat.com, marcel.apfelbaum@gmail.com, alex.williamson@redhat.com, vasant.hegde@amd.com, suravee.suthikulpanit@amd.com, santosh.shukla@amd.com, sarunkod@amd.com, Wei.Huang2@amd.com, clement.mathieu--drif@eviden.com, ethan.milon@eviden.com, joao.m.martins@oracle.com, boris.ostrovsky@oracle.com, alejandro.j.jimenez@oracle.com Subject: [PATCH v2 07/20] amd_iommu: Add helpers to walk AMD v1 Page Table format Date: Fri, 2 May 2025 02:15:52 +0000 Message-ID: <20250502021605.1795985-8-alejandro.j.jimenez@oracle.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20250502021605.1795985-1-alejandro.j.jimenez@oracle.com> References: <20250502021605.1795985-1-alejandro.j.jimenez@oracle.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-01_06,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxlogscore=999 phishscore=0 suspectscore=0 spamscore=0 adultscore=0 mlxscore=0 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2504070000 definitions=main-2505020015 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDAxNiBTYWx0ZWRfX4HoWoecBcEYK 7b8stKwBVkRR4+6s9XWFFw6iwxA4oLb+o0Saib2FdtvtOSSIYrjJBZkSc8ZFbL/H3hRGEDNWj0m /kDeOicdvDRjCpg8/nGExxH5GVSNwA8X4iKJXphZN4GlrbqXy29Wexmtz/FOK4nfG4GG0ifoX5t 4LCWANZAqalgXSCSnYV1gZYQ3QmOe9LD2n8He06m+Kkl796ZphQIf5P63zr6ZlMw1reXloDVZLS 9wcmtAbshgJOguhKZOJyAoJZOM40R/wo0Z3MDdpFvXXy+oiP/Ht9uyF/AgWDyoG8QJ1KI6aTDjX iusftUo4NOY95hCtz9OoHfAPOzOC7F+009ouep05uBqWiLBhIuRFB3aMSXBvPjkPajiZ7ENYISn N7Qt1oDer2nz5BlV5Qij86TK3HY1Ylw5Xm4ErwLmrN62QdRKAqhdcjzoKxjdN4QDm/PR8d7y X-Proofpoint-GUID: ylsWirsjMzQ-nwsTEX-ociJHENCglWlf X-Authority-Analysis: v=2.4 cv=A5VsP7WG c=1 sm=1 tr=0 ts=68142af9 b=1 cx=c_pps a=qoll8+KPOyaMroiJ2sR5sw==:117 a=qoll8+KPOyaMroiJ2sR5sw==:17 a=dt9VzEwgFbYA:10 a=yPCof4ZbAAAA:8 a=hF7hyPbbb6ONIRq6hAgA:9 cc=ntf awl=host:13130 X-Proofpoint-ORIG-GUID: ylsWirsjMzQ-nwsTEX-ociJHENCglWlf Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" The current amdvi_page_walk() is designed to be called by the replay() method. Rather than drastically altering it, introduce helpers to fetch guest PTEs that will be used by a page walker implementation. Signed-off-by: Alejandro Jimenez Tested-by: Sairaj Kodilkar --- hw/i386/amd_iommu.c | 123 ++++++++++++++++++++++++++++++++++++++++++++ hw/i386/amd_iommu.h | 42 +++++++++++++++ 2 files changed, 165 insertions(+) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 698967cc1a88..44bf8ebe303e 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -87,6 +87,8 @@ typedef enum AMDVIFaultReason { AMDVI_FR_DTE_RTR_ERR =3D 1, /* Failure to retrieve DTE */ AMDVI_FR_DTE_V, /* DTE[V] =3D 0 */ AMDVI_FR_DTE_TV, /* DTE[TV] =3D 0 */ + AMDVI_FR_PT_ROOT_INV, /* Page Table Root ptr invalid */ + AMDVI_FR_PT_ENTRY_INV, /* Failure to read PTE from guest memory */ } AMDVIFaultReason; =20 uint64_t amdvi_extended_feature_register(AMDVIState *s) @@ -526,6 +528,127 @@ static int amdvi_as_to_dte(AMDVIAddressSpace *as, uin= t64_t *dte) return 0; } =20 +/* + * For a PTE encoding a large page, return the page size it encodes as des= cribed + * by the AMD IOMMU Specification Table 14: Example Page Size Encodings. + * No need to adjust the value of the PTE to point to the first PTE in the= large + * page since the encoding guarantees all "base" PTEs in the large page ar= e the + * same. + */ +static uint64_t large_pte_page_size(uint64_t pte) +{ + assert(PTE_NEXT_LEVEL(pte) =3D=3D 7); + + /* Determine size of the large/contiguous page encoded in the PTE */ + return PTE_LARGE_PAGE_SIZE(pte); +} + +/* + * Helper function to fetch a PTE using AMD v1 pgtable format. + * On successful page walk, returns 0 and pte parameter points to a valid = PTE. + * On failure, returns: + * -AMDVI_FR_PT_ROOT_INV: A page walk is not possible due to conditions li= ke DTE + * with invalid permissions, Page Table Root can not be read from DTE= , or a + * larger IOVA than supported by page table level encoded in DTE[Mode= ]. + * -AMDVI_FR_PT_ENTRY_INV: A PTE could not be read from guest memory durin= g a + * page table walk. This means that the DTE has valid data, but one o= f the + * lower level entries in the Page Table could not be read. + */ +static int __attribute__((unused)) +fetch_pte(AMDVIAddressSpace *as, hwaddr address, uint64_t dte, uint64_t *p= te, + hwaddr *page_size) +{ + IOMMUAccessFlags perms =3D amdvi_get_perms(dte); + + uint8_t level, mode; + uint64_t pte_addr; + + *pte =3D dte; + *page_size =3D 0; + + if (perms =3D=3D IOMMU_NONE) { + return -AMDVI_FR_PT_ROOT_INV; + } + + /* + * The Linux kernel driver initializes the default mode to 3, correspo= nding + * to a 39-bit GPA space, where each entry in the pagetable translates= to a + * 1GB (2^30) page size. + */ + level =3D mode =3D get_pte_translation_mode(dte); + assert(mode > 0 && mode < 7); + + /* + * If IOVA is larger than the max supported by the current pgtable lev= el, + * there is nothing to do. + */ + if (address > PT_LEVEL_MAX_ADDR(mode - 1)) { + /* IOVA too large for the current DTE */ + return -AMDVI_FR_PT_ROOT_INV; + } + + do { + level -=3D 1; + + /* Update the page_size */ + *page_size =3D PTE_LEVEL_PAGE_SIZE(level); + + /* Permission bits are ANDed at every level, including the DTE */ + perms &=3D amdvi_get_perms(*pte); + if (perms =3D=3D IOMMU_NONE) { + return 0; + } + + /* Not Present */ + if (!IOMMU_PTE_PRESENT(*pte)) { + return 0; + } + + /* Large or Leaf PTE found */ + if (PTE_NEXT_LEVEL(*pte) =3D=3D 7 || PTE_NEXT_LEVEL(*pte) =3D=3D 0= ) { + /* Leaf PTE found */ + break; + } + + /* + * Index the pgtable using the IOVA bits corresponding to current = level + * and walk down to the lower level. + */ + pte_addr =3D NEXT_PTE_ADDR(*pte, level, address); + *pte =3D amdvi_get_pte_entry(as->iommu_state, pte_addr, as->devfn); + + if (*pte =3D=3D (uint64_t)-1) { + /* + * A returned PTE of -1 indicates a failure to read the page t= able + * entry from guest memory. + */ + if (level =3D=3D mode - 1) { + /* Failure to retrieve the Page Table from Root Pointer */ + *page_size =3D 0; + return -AMDVI_FR_PT_ROOT_INV; + } else { + /* Failure to read PTE. Page walk skips a page_size chunk = */ + return -AMDVI_FR_PT_ENTRY_INV; + } + } + } while (level > 0); + + assert(PTE_NEXT_LEVEL(*pte) =3D=3D 0 || PTE_NEXT_LEVEL(*pte) =3D=3D 7 = || + level =3D=3D 0); + /* + * Page walk ends when Next Level field on PTE shows that either a lea= f PTE + * or a series of large PTEs have been reached. In the latter case, ev= en if + * the range starts in the middle of a contiguous page, the returned P= TE + * must be the first PTE of the series. + */ + if (PTE_NEXT_LEVEL(*pte) =3D=3D 7) { + /* Update page_size with the large PTE page size */ + *page_size =3D large_pte_page_size(*pte); + } + + return 0; +} + /* log error without aborting since linux seems to be using reserved bits = */ static void amdvi_inval_devtab_entry(AMDVIState *s, uint64_t *cmd) { diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index 6f35b0595054..5e35d4b15167 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -25,6 +25,8 @@ #include "hw/i386/x86-iommu.h" #include "qom/object.h" =20 +#define GENMASK64(h, l) (((~0ULL) >> (63 - (h) + (l))) << (l)) + /* Capability registers */ #define AMDVI_CAPAB_BAR_LOW 0x04 #define AMDVI_CAPAB_BAR_HIGH 0x08 @@ -174,6 +176,46 @@ #define AMDVI_GATS_MODE (2ULL << 12) #define AMDVI_HATS_MODE (2ULL << 10) =20 +/* Page Table format */ + +#define AMDVI_PTE_PR (1ULL << 0) +#define AMDVI_PTE_NEXT_LEVEL_MASK GENMASK64(11, 9) + +#define IOMMU_PTE_PRESENT(pte) ((pte) & AMDVI_PTE_PR) + +/* Using level=3D0 for leaf PTE at 4K page size */ +#define PT_LEVEL_SHIFT(level) (12 + ((level) * 9)) + +/* Return IOVA bit group used to index the Page Table at specific level */ +#define PT_LEVEL_INDEX(level, iova) (((iova) >> PT_LEVEL_SHIFT(level))= & \ + GENMASK64(8, 0)) + +/* Return the max address for a specified level i.e. max_oaddr */ +#define PT_LEVEL_MAX_ADDR(x) (((x) < 5) ? \ + ((1ULL << PT_LEVEL_SHIFT((x + 1))) - 1) : \ + (~(0ULL))) + +/* Extract the NextLevel field from PTE/PDE */ +#define PTE_NEXT_LEVEL(pte) (((pte) & AMDVI_PTE_NEXT_LEVEL_MASK) >> 9) + +/* Take page table level and return default pagetable size for level */ +#define PTE_LEVEL_PAGE_SIZE(level) (1ULL << (PT_LEVEL_SHIFT(level))) + +/* + * Return address of lower level page table encoded in PTE and specified by + * current level and corresponding IOVA bit group at such level. + */ +#define NEXT_PTE_ADDR(pte, level, iova) (((pte) & AMDVI_DEV_PT_ROOT_MASK) = + \ + (PT_LEVEL_INDEX(level, iova) * 8)) + +/* + * Take a PTE value with mode=3D0x07 and return the page size it encodes. + */ +#define PTE_LARGE_PAGE_SIZE(pte) (1ULL << (1 + cto64(((pte) | 0xfffULL)= ))) + +/* Return number of PTEs to use for a given page size (expected power of 2= ) */ +#define PAGE_SIZE_PTE_COUNT(pgsz) (1ULL << ((ctz64(pgsz) - 12) % 9)) + /* IOTLB */ #define AMDVI_IOTLB_MAX_SIZE 1024 #define AMDVI_DEVID_SHIFT 36 --=20 2.43.5 From nobody Mon Feb 9 09:04:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" For the specified address range, walk the page table identifying regions as mapped or unmapped and invoke registered notifiers with the corresponding event type. Signed-off-by: Alejandro Jimenez Tested-by: Sairaj Kodilkar --- hw/i386/amd_iommu.c | 75 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 44bf8ebe303e..6a2ba878dfa7 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -649,6 +649,81 @@ fetch_pte(AMDVIAddressSpace *as, hwaddr address, uint6= 4_t dte, uint64_t *pte, return 0; } =20 +/* + * Walk the guest page table for an IOVA and range and signal the register= ed + * notifiers to sync the shadow page tables in the host. + * Must be called with a valid DTE for DMA remapping i.e. V=3D1,TV=3D1 + */ +static void __attribute__((unused)) +amdvi_sync_shadow_page_table_range(AMDVIAddressSpace *as, uint64_t *dte, + hwaddr addr, uint64_t size, bool send_u= nmap) +{ + IOMMUTLBEvent event; + + hwaddr iova_next, page_mask, pagesize; + hwaddr iova =3D addr; + hwaddr end =3D iova + size - 1; + + uint64_t pte; + int ret; + + while (iova < end) { + + ret =3D fetch_pte(as, iova, dte[0], &pte, &pagesize); + + if (ret =3D=3D -AMDVI_FR_PT_ROOT_INV) { + /* + * Invalid conditions such as the IOVA being larger than suppo= rted + * by current page table mode as configured in the DTE, or a f= ailure + * to fetch the Page Table from the Page Table Root Pointer in= DTE. + */ + assert(pagesize =3D=3D 0); + return; + } + /* PTE has been validated for major errors and pagesize is set */ + assert(pagesize); + page_mask =3D ~(pagesize - 1); + iova_next =3D (iova & page_mask) + pagesize; + + if (ret =3D=3D -AMDVI_FR_PT_ENTRY_INV) { + /* + * Failure to read PTE from memory, the pagesize matches the c= urrent + * level. Unable to determine the region type, so a safe strat= egy is + * to skip the range and continue the page walk. + */ + goto next; + } + + event.entry.target_as =3D &address_space_memory; + event.entry.iova =3D iova & page_mask; + /* translated_addr is irrelevant for the unmap case */ + event.entry.translated_addr =3D (pte & AMDVI_DEV_PT_ROOT_MASK) & + page_mask; + event.entry.addr_mask =3D ~page_mask; + event.entry.perm =3D amdvi_get_perms(pte); + + /* + * In cases where the leaf PTE is not found, or it has invalid + * permissions, an UNMAP type notification is sent, but only if the + * caller requested it. + */ + if (!IOMMU_PTE_PRESENT(pte) || (event.entry.perm =3D=3D IOMMU_NONE= )) { + if (!send_unmap) { + goto next; + } + event.type =3D IOMMU_NOTIFIER_UNMAP; + } else { + event.type =3D IOMMU_NOTIFIER_MAP; + } + + /* Invoke the notifiers registered for this address space */ + memory_region_notify_iommu(&as->iommu, 0, event); + +next: + iova =3D iova_next; + } +} + /* log error without aborting since linux seems to be using reserved bits = */ static void amdvi_inval_devtab_entry(AMDVIState *s, uint64_t *cmd) { --=20 2.43.5 From nobody Mon Feb 9 09:04:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Add the minimal data structures required to maintain a list of address spaces (i.e. devices) with registered notifiers, and to update the type of events that require notifications. Note that the ability to register for MAP notifications is not available. It will be unblocked by following changes that enable the synchronization of guest I/O page tables with host IOMMU state, at which point an amd-iommu device property will be introduced to control this capability. Signed-off-by: Alejandro Jimenez Tested-by: Sairaj Kodilkar --- hw/i386/amd_iommu.c | 26 +++++++++++++++++++++++--- hw/i386/amd_iommu.h | 3 +++ 2 files changed, 26 insertions(+), 3 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 6a2ba878dfa7..2f69459ab68d 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -66,6 +66,11 @@ struct AMDVIAddressSpace { MemoryRegion iommu_nodma; /* Alias of shared nodma memory region */ MemoryRegion iommu_ir; /* Device's interrupt remapping region */ AddressSpace as; /* device's corresponding address space */ + + /* DMA address translation support */ + IOMMUNotifierFlag notifier_flags; + /* entry in list of Address spaces with registered notifiers */ + QLIST_ENTRY(AMDVIAddressSpace) next; }; =20 /* AMDVI cache entry */ @@ -1711,6 +1716,7 @@ static AddressSpace *amdvi_host_dma_iommu(PCIBus *bus= , void *opaque, int devfn) iommu_as[devfn]->bus_num =3D (uint8_t)bus_num; iommu_as[devfn]->devfn =3D (uint8_t)devfn; iommu_as[devfn]->iommu_state =3D s; + iommu_as[devfn]->notifier_flags =3D IOMMU_NONE; =20 amdvi_dev_as =3D iommu_as[devfn]; =20 @@ -1791,14 +1797,28 @@ static int amdvi_iommu_notify_flag_changed(IOMMUMem= oryRegion *iommu, Error **errp) { AMDVIAddressSpace *as =3D container_of(iommu, AMDVIAddressSpace, iommu= ); + AMDVIState *s =3D as->iommu_state; =20 if (new & IOMMU_NOTIFIER_MAP) { error_setg(errp, - "device %02x.%02x.%x requires iommu notifier which is n= ot " - "currently supported", as->bus_num, PCI_SLOT(as->devfn), - PCI_FUNC(as->devfn)); + "device %02x.%02x.%x requires iommu notifier which is not " + "currently supported", as->bus_num, PCI_SLOT(as->devfn), + PCI_FUNC(as->devfn)); return -EINVAL; } + + /* + * Update notifier flags for address space and the list of address spa= ces + * with registered notifiers. + */ + as->notifier_flags =3D new; + + if (old =3D=3D IOMMU_NOTIFIER_NONE) { + QLIST_INSERT_HEAD(&s->amdvi_as_with_notifiers, as, next); + } else if (new =3D=3D IOMMU_NOTIFIER_NONE) { + QLIST_REMOVE(as, next); + } + return 0; } =20 diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index 5e35d4b15167..a7462b2adb79 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -411,6 +411,9 @@ struct AMDVIState { /* for each served device */ AMDVIAddressSpace **address_spaces[PCI_BUS_MAX]; =20 + /* list of address spaces with registered notifiers */ + QLIST_HEAD(, AMDVIAddressSpace) amdvi_as_with_notifiers; + /* IOTLB */ GHashTable *iotlb; =20 --=20 2.43.5 From nobody Mon Feb 9 09:04:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1746152310; cv=none; d=zohomail.com; s=zohoarc; b=Uim6ub1YVxkI0UR654fcNdERYcP4ybiaqZh55OGxyOYgQiXQ/I6/dF0NPobaKkHqhvAu2Dwv8dPNWrCYAFiQZM8a+JumgECoWM4f/2dPsI9fbrqL1Mgd+c0bP8LZKjkJQ87vMnH7LeLTCz8LBVluIqhhMLkkumRNXeDewqjkP0A= ARC-Message-Signature: i=1; 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charset="utf-8" When the guest issues an INVALIDATE_IOMMU_PAGES command, decode the address and size of the invalidation and sync the guest page table state with the host. This requires walking the guest page table and calling notifiers registered for address spaces matching the domain ID encoded in the command. Signed-off-by: Alejandro Jimenez Tested-by: Sairaj Kodilkar --- hw/i386/amd_iommu.c | 82 ++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 74 insertions(+), 8 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 2f69459ab68d..bddfe2f93136 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -559,9 +559,8 @@ static uint64_t large_pte_page_size(uint64_t pte) * page table walk. This means that the DTE has valid data, but one o= f the * lower level entries in the Page Table could not be read. */ -static int __attribute__((unused)) -fetch_pte(AMDVIAddressSpace *as, hwaddr address, uint64_t dte, uint64_t *p= te, - hwaddr *page_size) +static uint64_t fetch_pte(AMDVIAddressSpace *as, hwaddr address, uint64_t = dte, + uint64_t *pte, hwaddr *page_size) { IOMMUAccessFlags perms =3D amdvi_get_perms(dte); =20 @@ -659,9 +658,9 @@ fetch_pte(AMDVIAddressSpace *as, hwaddr address, uint64= _t dte, uint64_t *pte, * notifiers to sync the shadow page tables in the host. * Must be called with a valid DTE for DMA remapping i.e. V=3D1,TV=3D1 */ -static void __attribute__((unused)) -amdvi_sync_shadow_page_table_range(AMDVIAddressSpace *as, uint64_t *dte, - hwaddr addr, uint64_t size, bool send_u= nmap) +static void amdvi_sync_shadow_page_table_range(AMDVIAddressSpace *as, + uint64_t *dte, hwaddr addr, + uint64_t size, bool send_un= map) { IOMMUTLBEvent event; =20 @@ -798,8 +797,7 @@ static gboolean amdvi_iotlb_remove_by_domid(gpointer ke= y, gpointer value, * first zero at bit 51 or larger is a request to invalidate the entire ad= dress * space. */ -static uint64_t __attribute__((unused)) -amdvi_decode_invalidation_size(hwaddr addr, uint16_t flags) +static uint64_t amdvi_decode_invalidation_size(hwaddr addr, uint16_t flags) { uint64_t size =3D AMDVI_PAGE_SIZE; uint8_t fzbit =3D 0; @@ -816,10 +814,76 @@ amdvi_decode_invalidation_size(hwaddr addr, uint16_t = flags) return size; } =20 +/* + * Synchronize the guest page tables with the shadow page tables kept in t= he + * host for the specified range. + * The invalidation command issued by the guest and intercepted by the VMM + * does not specify a device, but a domain, since all devices in the same = domain + * share the same page tables. However, vIOMMU emulation creates separate + * address spaces per device, so it is necessary to traverse the list of a= ll of + * address spaces (i.e. devices) that have notifiers registered in order to + * propagate the changes to the host page tables. + * We cannot return early from this function once a matching domain has be= en + * identified and its page tables synced (based on the fact that all devic= es in + * the same domain share the page tables). The reason is that different de= vices + * (i.e. address spaces) could have different notifiers registered, and by + * skipping address spaces that appear later on the amdvi_as_with_notifier= s list + * their notifiers (which could differ from the ones registered for the fi= rst + * device/address space) would not be invoked. + */ +static void amdvi_sync_domain(AMDVIState *s, uint16_t domid, uint64_t addr, + uint16_t flags) +{ + AMDVIAddressSpace *as; + + uint64_t size =3D amdvi_decode_invalidation_size(addr, flags); + + if (size =3D=3D AMDVI_INV_ALL_PAGES) { + addr =3D 0; /* Set start address to 0 and invalidate entire = AS */ + } else { + addr &=3D ~(size - 1); + } + + /* + * Call notifiers that have registered for each address space matching= the + * domain ID, in order to sync the guest pagetable state with the host. + */ + QLIST_FOREACH(as, &s->amdvi_as_with_notifiers, next) { + + uint64_t dte[4] =3D { 0 }; + + /* + * Retrieve the Device Table entry for the devid corresponding to = the + * current address space, and verify the DomainID matches i.e. the= page + * tables to be synced belong to devices in the domain. + */ + if (amdvi_as_to_dte(as, dte)) { + continue; + } + + /* Only need to sync the Page Tables for a matching domain */ + if (domid !=3D (dte[1] & AMDVI_DEV_DOMID_ID_MASK)) { + continue; + } + + /* + * We have determined that there is a valid Device Table Entry for= a + * device matching the DomainID in the INV_IOMMU_PAGES command iss= ued by + * the guest. Walk the guest page table to sync shadow page table. + */ + if (as->notifier_flags & IOMMU_NOTIFIER_MAP) { + /* Sync guest IOMMU mappings with host */ + amdvi_sync_shadow_page_table_range(as, &dte[0], addr, size, tr= ue); + } + } +} + /* we don't have devid - we can't remove pages by address */ static void amdvi_inval_pages(AMDVIState *s, uint64_t *cmd) { uint16_t domid =3D cpu_to_le16((uint16_t)extract64(cmd[0], 32, 16)); + uint64_t addr =3D cpu_to_le64(extract64(cmd[1], 12, 52)) << 12; + uint16_t flags =3D cpu_to_le16((uint16_t)extract64(cmd[1], 0, 3)); =20 if (extract64(cmd[0], 20, 12) || extract64(cmd[0], 48, 12) || extract64(cmd[1], 3, 9)) { @@ -829,6 +893,8 @@ static void amdvi_inval_pages(AMDVIState *s, uint64_t *= cmd) =20 g_hash_table_foreach_remove(s->iotlb, amdvi_iotlb_remove_by_domid, &domid); + + amdvi_sync_domain(s, domid, addr, flags); trace_amdvi_pages_inval(domid); } =20 --=20 2.43.5 From nobody Mon Feb 9 09:04:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 2 May 2025 02:16:14 GMT Received: from alaljimee5bm-ol9-20250405.osdevelopmeniad.oraclevcn.com (alaljimee5bm-ol9-20250405.allregionaliads.osdevelopmeniad.oraclevcn.com [100.100.254.235]) by iadpaimrmta03.imrmtpd1.prodappiadaev1.oraclevcn.com (PPS) with ESMTP id 468nxkgyvr-12; Fri, 02 May 2025 02:16:14 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=corp-2025-04-25; bh=Ge694 OK/WX30qgMogNvU+mFU3lE6Ta5XVxReHHIKxB4=; b=YKBDXffVF/WI/FeIAVBVq faKmEtdJ1Q1DJoe0jz9t1k1QBoE8KxQ15Pnwvm4X+GUmLb8otoanaTncjXjHPLnh ZnwPjMWlezb3o1+UfPTpzc8SFlGmNQv+ZEOG1V0CYkLIFjzyNo4thXnl51q2Brbr 3KUKs4zCE/iFLgLun0cwWLRZAJSEcNXK7OanqCiPzVp72fjIuEarANJkF4yqb9eE Q0rN9Pf0g5EwKiWYfCaqSOCvyO9jreqEYiLcJD9PAywm/UevL04Y/SBfrIJaNBxL VaiKGvv05jlmWjOMeACNrAIK7gZEeqFM50q/2HD3Kz+aSqM48oyaiPJ9gekOl+QL g== From: Alejandro Jimenez To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, richard.henderson@linaro.org, eduardo@habkost.net, peterx@redhat.com, david@redhat.com, philmd@linaro.org, mst@redhat.com, marcel.apfelbaum@gmail.com, alex.williamson@redhat.com, vasant.hegde@amd.com, suravee.suthikulpanit@amd.com, santosh.shukla@amd.com, sarunkod@amd.com, Wei.Huang2@amd.com, clement.mathieu--drif@eviden.com, ethan.milon@eviden.com, joao.m.martins@oracle.com, boris.ostrovsky@oracle.com, alejandro.j.jimenez@oracle.com Subject: [PATCH v2 11/20] amd_iommu: Use iova_tree records to determine large page size on UNMAP Date: Fri, 2 May 2025 02:15:56 +0000 Message-ID: <20250502021605.1795985-12-alejandro.j.jimenez@oracle.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20250502021605.1795985-1-alejandro.j.jimenez@oracle.com> References: <20250502021605.1795985-1-alejandro.j.jimenez@oracle.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-01_06,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxlogscore=999 phishscore=0 suspectscore=0 spamscore=0 adultscore=0 mlxscore=0 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2504070000 definitions=main-2505020015 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDAxNiBTYWx0ZWRfX/BNi1WtP1tFf SLd1c0cTYzymqrcMb8gNkCP+zDHCo3a5yFzpS0XQNamtuLcgEmEAECg9Jo7Mh8VLR8YH9xRDzqc 3ecHj04JXr04D9XJKhmVe311enWCACHVPDkHQFST/BsehOz8frHvuoxv1u+Gj2MlEDWNnkUqo33 J8mU2cHfaogQ1a4m9OCvE6/cx8m7PNLNNfhbTL3d9/e+NuazgnDXuPhoiurt5nmDK+yZaq7yys0 zjpdIyDH/a7jId8xMb0Y3Upbv6RiJ8KyasN67rzIafNIGLnIW4P8Qjmmcr4fgb+4PFVTMPJxDDD 8XUU3p0kLOZMWZFfrU4SA4WhxgSmRJlz43oO8VP0l5ExQeV3bBADdN+cuIr7dhfa+u7BiyRzo8R H3Ssm8rwjaoFQWULCGNPef1ekoVzoSEN23mtigsUIfin6ZnY3u+8XWJCQBTkLUq03QptHTxS X-Proofpoint-GUID: tP0HFvlzDDc_f8oL6MXJtwqmSyZpKO3A X-Authority-Analysis: v=2.4 cv=A5VsP7WG c=1 sm=1 tr=0 ts=68142af9 b=1 cx=c_pps a=qoll8+KPOyaMroiJ2sR5sw==:117 a=qoll8+KPOyaMroiJ2sR5sw==:17 a=dt9VzEwgFbYA:10 a=yPCof4ZbAAAA:8 a=7d1lPJd8Oj0-l-ugTcUA:9 cc=ntf awl=host:13130 X-Proofpoint-ORIG-GUID: tP0HFvlzDDc_f8oL6MXJtwqmSyZpKO3A Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Keep a record of mapped IOVA ranges per address space, using the iova_tree implementation. Besides enabling optimizations like avoiding unnecessary notifications, a record of existing mappings makes it possible to determine if a specific IOVA is mapped by the guest using a large page, and adjust the size when notifying UNMAP events. When unmapping a large page, the information in the guest PTE encoding the page size is lost, since the guest clears the PTE before issuing the invalidation command to the IOMMU. In such case, the size of the original mapping can be retrieved from the iova_tree and used to issue the UNMAP notification. Using the correct size is essential since the VFIO IOMMU Type1v2 driver in the host kernel will reject unmap requests that do not fully cover previous mappings. Signed-off-by: Alejandro Jimenez Tested-by: Sairaj Kodilkar --- hw/i386/amd_iommu.c | 91 ++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 86 insertions(+), 5 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index bddfe2f93136..4f44ef159ff9 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -33,6 +33,7 @@ #include "hw/i386/apic-msidef.h" #include "hw/qdev-properties.h" #include "kvm/kvm_i386.h" +#include "qemu/iova-tree.h" =20 /* used AMD-Vi MMIO registers */ const char *amdvi_mmio_low[] =3D { @@ -71,6 +72,8 @@ struct AMDVIAddressSpace { IOMMUNotifierFlag notifier_flags; /* entry in list of Address spaces with registered notifiers */ QLIST_ENTRY(AMDVIAddressSpace) next; + /* Record DMA translation ranges */ + IOVATree *iova_tree; }; =20 /* AMDVI cache entry */ @@ -653,6 +656,75 @@ static uint64_t fetch_pte(AMDVIAddressSpace *as, hwadd= r address, uint64_t dte, return 0; } =20 +/* + * Invoke notifiers registered for the address space. Update record of map= ped + * ranges in IOVA Tree. + */ +static void amdvi_notify_iommu(AMDVIAddressSpace *as, IOMMUTLBEvent *event) +{ + IOMMUTLBEntry *entry =3D &event->entry; + + DMAMap target =3D { + .iova =3D entry->iova, + .size =3D entry->addr_mask, + .translated_addr =3D entry->translated_addr, + .perm =3D entry->perm, + }; + + /* + * Search the IOVA Tree for an existing translation for the target, an= d skip + * the notification if the mapping is already recorded. + * When the guest uses large pages, comparing against the record makes= it + * possible to determine the size of the original MAP and adjust the U= NMAP + * request to match it. This avoids failed checks against the mappings= kept + * by the VFIO kernel driver. + */ + const DMAMap *mapped =3D iova_tree_find(as->iova_tree, &target); + + if (event->type =3D=3D IOMMU_NOTIFIER_UNMAP) { + if (!mapped) { + /* No record exists of this mapping, nothing to do */ + return; + } + /* + * Adjust the size based on the original record. This is essential= to + * determine when large/contiguous pages are used, since the guest= has + * already cleared the PTE (erasing the pagesize encoded on it) be= fore + * issuing the invalidation command. + */ + if (mapped->size !=3D target.size) { + assert(mapped->size > target.size); + target.size =3D mapped->size; + /* Adjust event to invoke notifier with correct range */ + entry->addr_mask =3D mapped->size; + } + iova_tree_remove(as->iova_tree, target); + } else { /* IOMMU_NOTIFIER_MAP */ + if (mapped) { + /* + * If a mapping is present and matches the request, skip the + * notification. + */ + if (!memcmp(mapped, &target, sizeof(DMAMap))) { + return; + } else { + /* + * This should never happen unless a buggy guest OS omits = or + * sends incorrect invalidation(s). Report an error in the= event + * it does happen. + */ + error_report("Found conflicting translation. This could be= due " + "to an incorrect or missing invalidation comm= and"); + } + } + /* Record the new mapping */ + iova_tree_insert(as->iova_tree, &target); + } + + /* Invoke the notifiers registered for this address space */ + memory_region_notify_iommu(&as->iommu, 0, *event); +} + /* * Walk the guest page table for an IOVA and range and signal the register= ed * notifiers to sync the shadow page tables in the host. @@ -664,7 +736,7 @@ static void amdvi_sync_shadow_page_table_range(AMDVIAdd= ressSpace *as, { IOMMUTLBEvent event; =20 - hwaddr iova_next, page_mask, pagesize; + hwaddr page_mask, pagesize; hwaddr iova =3D addr; hwaddr end =3D iova + size - 1; =20 @@ -687,7 +759,6 @@ static void amdvi_sync_shadow_page_table_range(AMDVIAdd= ressSpace *as, /* PTE has been validated for major errors and pagesize is set */ assert(pagesize); page_mask =3D ~(pagesize - 1); - iova_next =3D (iova & page_mask) + pagesize; =20 if (ret =3D=3D -AMDVI_FR_PT_ENTRY_INV) { /* @@ -720,11 +791,20 @@ static void amdvi_sync_shadow_page_table_range(AMDVIA= ddressSpace *as, event.type =3D IOMMU_NOTIFIER_MAP; } =20 - /* Invoke the notifiers registered for this address space */ - memory_region_notify_iommu(&as->iommu, 0, event); + /* + * The following call might need to adjust event.entry.size in cas= es + * where the guest unmapped a series of large pages. + */ + amdvi_notify_iommu(as, &event); + /* + * In the special scenario where the guest is unmapping a large pa= ge, + * addr_mask has been adjusted before sending the notification. Up= date + * pagesize accordingly in order to correctly compute the next IOV= A. + */ + pagesize =3D event.entry.addr_mask + 1; =20 next: - iova =3D iova_next; + iova =3D (iova & ~(pagesize - 1)) + pagesize; } } =20 @@ -1783,6 +1863,7 @@ static AddressSpace *amdvi_host_dma_iommu(PCIBus *bus= , void *opaque, int devfn) iommu_as[devfn]->devfn =3D (uint8_t)devfn; iommu_as[devfn]->iommu_state =3D s; iommu_as[devfn]->notifier_flags =3D IOMMU_NONE; + iommu_as[devfn]->iova_tree =3D iova_tree_new(); =20 amdvi_dev_as =3D iommu_as[devfn]; =20 --=20 2.43.5 From nobody Mon Feb 9 09:04:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1746152232; cv=none; d=zohomail.com; s=zohoarc; b=RBLDFfmREc1H0FZUYF3uGkY2QRR8+pWMy2/41uQrA+HHW6dhEe31O9V2Y+G3COG7SlkBpOjvYJJquCxYbOYMwPx3ievxrOSyLG97Yv5531TU1SK5/weM6tWNnR9k7QkFUDgJxHnZ75UcOeZZOtkp9Wc1wuuRc1asWXN8kvQfGQM= ARC-Message-Signature: i=1; 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b=rOnknRziHFZXfLuMGILOE wU8qIB9Y/KCyyF66mbn/uTGpXJ7NuNiG2wjYFwNZaZwenI/2PiELGLfeQ8DNkR7N ARFJbJ7h0pv8444OyLaaKx1TlL0Af8N9C89iKXAGV/S2pUcsaY9nYUGtwzZ1wZ76 OuUxJ0OU7jfmoSZnqtlRQ2Assj+fc+NQ1MpF8LG5T1VW3zt93FJpSkgeLs6350fr ZKpdG6rdRjmhRqbtgrF+H/9e0cKd313a/UoNum6OcTrxqn4IkzdXOyBq5Iv68UB7 P+r0KmUpuuyERFln3gQV1JVfAQlfS8k1UgwNaMb6x0iYAKpOV75sFtH0qqLZzu2e g== From: Alejandro Jimenez To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, richard.henderson@linaro.org, eduardo@habkost.net, peterx@redhat.com, david@redhat.com, philmd@linaro.org, mst@redhat.com, marcel.apfelbaum@gmail.com, alex.williamson@redhat.com, vasant.hegde@amd.com, suravee.suthikulpanit@amd.com, santosh.shukla@amd.com, sarunkod@amd.com, Wei.Huang2@amd.com, clement.mathieu--drif@eviden.com, ethan.milon@eviden.com, joao.m.martins@oracle.com, boris.ostrovsky@oracle.com, alejandro.j.jimenez@oracle.com Subject: [PATCH v2 12/20] amd_iommu: Unmap all address spaces under the AMD IOMMU on reset Date: Fri, 2 May 2025 02:15:57 +0000 Message-ID: <20250502021605.1795985-13-alejandro.j.jimenez@oracle.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20250502021605.1795985-1-alejandro.j.jimenez@oracle.com> References: <20250502021605.1795985-1-alejandro.j.jimenez@oracle.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-01_06,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxlogscore=999 phishscore=0 suspectscore=0 spamscore=0 adultscore=0 mlxscore=0 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2504070000 definitions=main-2505020015 X-Proofpoint-ORIG-GUID: 1ZNi22iJxpsT2G_GwvHp_ohu9Trh0XVe X-Authority-Analysis: v=2.4 cv=Vq8jA/2n c=1 sm=1 tr=0 ts=68142af1 b=1 cx=c_pps a=qoll8+KPOyaMroiJ2sR5sw==:117 a=qoll8+KPOyaMroiJ2sR5sw==:17 a=dt9VzEwgFbYA:10 a=yPCof4ZbAAAA:8 a=SEEq26f7jwHSYcXadsMA:9 cc=ntf awl=host:13130 X-Proofpoint-GUID: 1ZNi22iJxpsT2G_GwvHp_ohu9Trh0XVe X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDAxNSBTYWx0ZWRfXwI0JmyiHKGYp xcLJGVAZHY1bOxR03lQ6IvIxRU5Zm3zlW/S0Rn5HiuZ+eRA1Too2F+2vTaucdTVp1tPg2w/CJch 4t6BO/6zYfbqAGQ97g9V4ooNc0cb+6DSwRTHWx3+sCwH/b1Lr+/yaxNkI27uYqLeulrhS5YTMtR pcdbP/3WBj8eKAIWKV7k62SatIXGiCHXwGI4qDqSt6cuh8ie2ydBt2t6T7L8eG06NUdLP5OW9ze nCt3Dt6QqqN6MDLmeRv7AtsDAaY9xEle+Zpa0nOX6cY4PSQyJ8rEusbUoFKiykcTnsfSakslHQH baxOmSzhxdma16Ajyt2bzXeYbntCoHLXBVhZpqhXgGpP8byjTfiqYWP4t7mRDiB47G95NZxxmmS CmmUPCmTNETMWBuNTXN7ej1Y4o4te4hfEquAK2XDqTcJgSImRqX4MIdtC+EGrhLKFV5hr//3 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Support dropping all existing mappings on reset. When the guest kernel reboots it will create new ones, but other components that run before the kernel (e.g. OVMF) should not be able to use existing mappings from the previous boot. Signed-off-by: Alejandro Jimenez Tested-by: Sairaj Kodilkar --- hw/i386/amd_iommu.c | 74 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 4f44ef159ff9..7bcba47a01ba 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -808,6 +808,77 @@ next: } } =20 +/* + * Unmap entire range that the notifier registered for i.e. the full AS. + * + * This is seemingly technically equivalent to directly calling + * memory_region_unmap_iommu_notifier_range(), but it allows to check for + * notifier boundaries and issue notifications with ranges within those bo= unds. + */ +static void amdvi_address_space_unmap(AMDVIAddressSpace *as, IOMMUNotifier= *n) +{ + + hwaddr start =3D n->start; + hwaddr end =3D n->end; + hwaddr remain; + DMAMap map; + + assert(start <=3D end); + remain =3D end - start + 1; + + /* + * Divide the notifier range into chunks that are aligned and do not e= xceed + * the notifier boundaries. + */ + while (remain >=3D AMDVI_PAGE_SIZE) { + + IOMMUTLBEvent event; + + uint64_t mask =3D dma_aligned_pow2_mask(start, end, 64); + + event.type =3D IOMMU_NOTIFIER_UNMAP; + + IOMMUTLBEntry entry =3D { + .target_as =3D &address_space_memory, + .iova =3D start, + .translated_addr =3D 0, /* irrelevant for unmap case */ + .addr_mask =3D mask, + .perm =3D IOMMU_NONE, + }; + event.entry =3D entry; + + /* Call notifier registered for updates on this address space */ + memory_region_notify_iommu_one(n, &event); + + start +=3D mask + 1; + remain -=3D mask + 1; + } + + assert(!remain); + + map.iova =3D n->start; + map.size =3D n->end - n->start; + + iova_tree_remove(as->iova_tree, map); +} + +/* + * For all the address spaces with notifiers registered, unmap the entire = range + * the notifier registered for i.e. clear all the address spaces managed b= y the + * IOMMU. + */ +static void amdvi_address_space_unmap_all(AMDVIState *s) +{ + AMDVIAddressSpace *as; + IOMMUNotifier *n; + + QLIST_FOREACH(as, &s->amdvi_as_with_notifiers, next) { + IOMMU_NOTIFIER_FOREACH(n, &as->iommu) { + amdvi_address_space_unmap(as, n); + } + } +} + /* log error without aborting since linux seems to be using reserved bits = */ static void amdvi_inval_devtab_entry(AMDVIState *s, uint64_t *cmd) { @@ -2043,6 +2114,9 @@ static void amdvi_sysbus_reset(DeviceState *dev) =20 msi_reset(&s->pci.dev); amdvi_init(s); + + /* Discard all mappings on device reset */ + amdvi_address_space_unmap_all(s); } =20 static void amdvi_sysbus_realize(DeviceState *dev, Error **errp) --=20 2.43.5 From nobody Mon Feb 9 09:04:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1746152480; cv=none; d=zohomail.com; s=zohoarc; b=Xs24J01Xnz0xxMg4AA0wow8eHQ9OjC+pR35nPHIF1nfJnCUiz72YAe1lxWdV/QQ+N0I8mxAm4SlygrL2XncY4HlF5xgfXdzbTDT+UqoRSjr7b6D9+nyTyOIXlsY7gTmoFjAGpqWR5XXlUp0+e43QkyYS4ZcNOvI6xLdDCSpc7AU= ARC-Message-Signature: i=1; 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b=Pk9jMzLlhaAygYPSQgcSV rkWCnXCy7+gV/o/U5rd+B1kuPVvqzaEUVt2WTICwM3K61A/iRSWsJm6fdH89foac jziW9OLaRflLzpXrktteKUI+GTK3foQ+TySFwRWkElhDHs/9h7wqeyEEVWwl9g+l RntojcjxzRaij3V6dN0kgQIe7Hk7A26R1CBtAsknlVfQJZQ3TtT2cBjrID2M1KGP XkmKG1y81s/GYimOrKwJmaOMSaCeEnvd6ZhrmMrbcyzpuiiaUUxKgGv80mR7Oo03 HZV9jFBm0rd/j5ctX3z+kUcbYT7xcfBlfp8wNq90alP1Rt1aFDwIZOsVSCI9V0Pd Q== From: Alejandro Jimenez To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, richard.henderson@linaro.org, eduardo@habkost.net, peterx@redhat.com, david@redhat.com, philmd@linaro.org, mst@redhat.com, marcel.apfelbaum@gmail.com, alex.williamson@redhat.com, vasant.hegde@amd.com, suravee.suthikulpanit@amd.com, santosh.shukla@amd.com, sarunkod@amd.com, Wei.Huang2@amd.com, clement.mathieu--drif@eviden.com, ethan.milon@eviden.com, joao.m.martins@oracle.com, boris.ostrovsky@oracle.com, alejandro.j.jimenez@oracle.com Subject: [PATCH v2 13/20] amd_iommu: Add replay callback Date: Fri, 2 May 2025 02:15:58 +0000 Message-ID: <20250502021605.1795985-14-alejandro.j.jimenez@oracle.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20250502021605.1795985-1-alejandro.j.jimenez@oracle.com> References: <20250502021605.1795985-1-alejandro.j.jimenez@oracle.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-01_06,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxlogscore=999 phishscore=0 suspectscore=0 spamscore=0 adultscore=0 mlxscore=0 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2504070000 definitions=main-2505020015 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDAxNiBTYWx0ZWRfX7NOY773uX7zB 6L6YS5n311i42inJ8cMtsNTDry4K4l2DL2iwgMzCfqL7z96QIfAk2U66MyIiGP+RG1OVaH2q02t 1FLfJwjiNI2RFN/scC1S+0SQIkEGjrbmAtW8RDpo0nDuJqKxKHimvma257vs6S3a403JfhZhONt /SPJNoNxPOYV3YmpEpwrvm1Rk3vF2IL4QygVznZRTcFgxQiFa0lkh3Y8ZMSaihiX6bMssgcaNlz 5CjBUVxAO/89lx1+NAPyMY+Al0icX/OrRwxuQS3TfMCAppBE7mT1ZKmxAV/OdP+qCclE6iWmqsd mHbhNBWHbgWw0yPiItdGyysP5IQ1tRK9M4e5Wrgq6iPp/s27XfvwKgqA3MmYlZIVaY26DnUcUpP 82jExQZcc3hJQNi7aCYCWZMNP6LI8JnkXJ8RPvlLssoTAEcbKsxMXEUHmk28mFjJ7YgC1oU8 X-Proofpoint-GUID: Ae1xsQGW63AkSm6jUKnw42cNOOzTACBB X-Authority-Analysis: v=2.4 cv=A5VsP7WG c=1 sm=1 tr=0 ts=68142af9 b=1 cx=c_pps a=qoll8+KPOyaMroiJ2sR5sw==:117 a=qoll8+KPOyaMroiJ2sR5sw==:17 a=dt9VzEwgFbYA:10 a=yPCof4ZbAAAA:8 a=TyYeUvuNVc17vi0sGpoA:9 cc=ntf awl=host:13130 X-Proofpoint-ORIG-GUID: Ae1xsQGW63AkSm6jUKnw42cNOOzTACBB Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" A replay() method is necessary to efficiently synchronize the host page tables after VFIO registers a notifier for IOMMU events. It is called to ensure that existing mappings from an IOMMU memory region are "replayed" to a specified notifier, initializing or updating the shadow page tables on the host. Signed-off-by: Alejandro Jimenez Tested-by: Sairaj Kodilkar --- hw/i386/amd_iommu.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 7bcba47a01ba..5ce74f2c052d 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -879,6 +879,29 @@ static void amdvi_address_space_unmap_all(AMDVIState *= s) } } =20 +/* + * For every translation present in the IOMMU, construct IOMMUTLBEntry data + * and pass it as parameter to notifier callback. + */ +static void amdvi_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier = *n) +{ + AMDVIAddressSpace *as =3D container_of(iommu_mr, AMDVIAddressSpace, io= mmu); + uint64_t dte[4] =3D { 0 }; + + if (!(n->notifier_flags & IOMMU_NOTIFIER_MAP)) { + return; + } + + if (amdvi_as_to_dte(as, dte)) { + return; + } + + /* Dropping all mappings for the address space. Also clears the IOVA t= ree */ + amdvi_address_space_unmap(as, n); + + amdvi_sync_shadow_page_table_range(as, &dte[0], 0, UINT64_MAX, false); +} + /* log error without aborting since linux seems to be using reserved bits = */ static void amdvi_inval_devtab_entry(AMDVIState *s, uint64_t *cmd) { @@ -2240,6 +2263,7 @@ static void amdvi_iommu_memory_region_class_init(Obje= ctClass *klass, =20 imrc->translate =3D amdvi_translate; imrc->notify_flag_changed =3D amdvi_iommu_notify_flag_changed; + imrc->replay =3D amdvi_iommu_replay; } =20 static const TypeInfo amdvi_iommu_memory_region_info =3D { --=20 2.43.5 From nobody Mon Feb 9 09:04:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1746152339; cv=none; d=zohomail.com; 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charset="utf-8" When the kernel IOMMU driver issues an INVALIDATE_IOMMU_ALL, the address translation and interrupt remapping information must be cleared for all Device IDs and all domains. Introduce a helper to sync the shadow page table for all the address spaces with registered notifiers, which replays both MAP and UNMAP events. Signed-off-by: Alejandro Jimenez Tested-by: Sairaj Kodilkar --- hw/i386/amd_iommu.c | 48 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 5ce74f2c052d..fa5dbc3cc700 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -902,6 +902,47 @@ static void amdvi_iommu_replay(IOMMUMemoryRegion *iomm= u_mr, IOMMUNotifier *n) amdvi_sync_shadow_page_table_range(as, &dte[0], 0, UINT64_MAX, false); } =20 +static void amdvi_address_space_sync(AMDVIAddressSpace *as) +{ + IOMMUNotifier *n; + uint64_t dte[4] =3D { 0 }; + + /* If only UNMAP notifiers are registered, drop all existing mappings = */ + if (!(as->notifier_flags & IOMMU_NOTIFIER_MAP)) { + IOMMU_NOTIFIER_FOREACH(n, &as->iommu) { + /* + * Directly calling memory_region_unmap_iommu_notifier_range()= does + * not guarantee that the addr_mask eventually passed as param= eter + * to the notifier is valid. Use amdvi_address_space_unmap() w= hich + * ensures the notifier range is divided into properly aligned + * regions, and issues notifications for each one. + */ + amdvi_address_space_unmap(as, n); + } + return; + } + + if (amdvi_as_to_dte(as, dte)) { + return; + } + + amdvi_sync_shadow_page_table_range(as, &dte[0], 0, UINT64_MAX, true); +} + +/* + * This differs from the replay() method in that it issues both MAP and UN= MAP + * notifications since it is called after global invalidation events in or= der to + * re-sync all address spaces. + */ +static void amdvi_iommu_address_space_sync_all(AMDVIState *s) +{ + AMDVIAddressSpace *as; + + QLIST_FOREACH(as, &s->amdvi_as_with_notifiers, next) { + amdvi_address_space_sync(as); + } +} + /* log error without aborting since linux seems to be using reserved bits = */ static void amdvi_inval_devtab_entry(AMDVIState *s, uint64_t *cmd) { @@ -944,6 +985,13 @@ static void amdvi_inval_all(AMDVIState *s, uint64_t *c= md) amdvi_intremap_inval_notify_all(s, true, 0, 0); =20 amdvi_iotlb_reset(s); + + /* + * Fully replay the address space i.e. send both UNMAP and MAP events = in + * order to synchronize guest and host IO page tables tables. + */ + amdvi_iommu_address_space_sync_all(s); + trace_amdvi_all_inval(); } =20 --=20 2.43.5 From nobody Mon Feb 9 09:04:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1746152232; cv=none; d=zohomail.com; s=zohoarc; b=GuZAn4FX8fyUgOC8xLZ9TH70/Sl0/GdBrfjpbcf6gemxMZoD3hSgtVjQY2JI54mOmWl0ihysJ3dIrnS9EZvVinCC9EoYTm0ixMhFwy0cizopADXIf7MC9iSaB3/qx9hLOvcE1hcwx43d555CQkCYuYB7BkF53ursQGIouNJzz+Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746152232; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" Enable the appropriate memory region for an address space depending on the address translation mode selected for it. This is currently based on a generic x86 IOMMMU property, and only done during the address space initialization. Extract the code into a helper and toggle the regions based on whether the specific address space is using address translation (via the newly introduced addr_translation field). Later, region activation will also be controlled by availability of DMA remapping capability (via dma-remap property to be introduced in follow up changes). Signed-off-by: Alejandro Jimenez Tested-by: Sairaj Kodilkar --- hw/i386/amd_iommu.c | 31 +++++++++++++++++++++---------- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index fa5dbc3cc700..71018d70dd10 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -74,6 +74,8 @@ struct AMDVIAddressSpace { QLIST_ENTRY(AMDVIAddressSpace) next; /* Record DMA translation ranges */ IOVATree *iova_tree; + /* DMA address translation active */ + bool addr_translation; }; =20 /* AMDVI cache entry */ @@ -943,6 +945,23 @@ static void amdvi_iommu_address_space_sync_all(AMDVISt= ate *s) } } =20 +/* + * Toggle between address translation and passthrough modes by enabling the + * corresponding memory regions. + */ +static void amdvi_switch_address_space(AMDVIAddressSpace *amdvi_as) +{ + if (amdvi_as->addr_translation) { + /* Enabling DMA region */ + memory_region_set_enabled(&amdvi_as->iommu_nodma, false); + memory_region_set_enabled(MEMORY_REGION(&amdvi_as->iommu), true); + } else { + /* Disabling DMA region, using passthrough */ + memory_region_set_enabled(MEMORY_REGION(&amdvi_as->iommu), false); + memory_region_set_enabled(&amdvi_as->iommu_nodma, true); + } +} + /* log error without aborting since linux seems to be using reserved bits = */ static void amdvi_inval_devtab_entry(AMDVIState *s, uint64_t *cmd) { @@ -1986,7 +2005,6 @@ static AddressSpace *amdvi_host_dma_iommu(PCIBus *bus= , void *opaque, int devfn) AMDVIState *s =3D opaque; AMDVIAddressSpace **iommu_as, *amdvi_dev_as; int bus_num =3D pci_bus_num(bus); - X86IOMMUState *x86_iommu =3D X86_IOMMU_DEVICE(s); =20 iommu_as =3D s->address_spaces[bus_num]; =20 @@ -2006,6 +2024,7 @@ static AddressSpace *amdvi_host_dma_iommu(PCIBus *bus= , void *opaque, int devfn) iommu_as[devfn]->iommu_state =3D s; iommu_as[devfn]->notifier_flags =3D IOMMU_NONE; iommu_as[devfn]->iova_tree =3D iova_tree_new(); + iommu_as[devfn]->addr_translation =3D false; =20 amdvi_dev_as =3D iommu_as[devfn]; =20 @@ -2048,15 +2067,7 @@ static AddressSpace *amdvi_host_dma_iommu(PCIBus *bu= s, void *opaque, int devfn) AMDVI_INT_ADDR_FIRST, &amdvi_dev_as->iommu_ir, 1); =20 - if (!x86_iommu->pt_supported) { - memory_region_set_enabled(&amdvi_dev_as->iommu_nodma, false); - memory_region_set_enabled(MEMORY_REGION(&amdvi_dev_as->iommu), - true); - } else { - memory_region_set_enabled(MEMORY_REGION(&amdvi_dev_as->iommu), - false); - memory_region_set_enabled(&amdvi_dev_as->iommu_nodma, true); - } + amdvi_switch_address_space(amdvi_dev_as); } return &iommu_as[devfn]->as; } --=20 2.43.5 From nobody Mon Feb 9 09:04:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1746152316; cv=none; d=zohomail.com; s=zohoarc; b=dc7onKcCXXJTkwVxSSlAPijj9uErSoxE7YlzK5UiD7ae8qt7T0N6bM9LWMo/C2DOp7F8R/oV0F/MnWTBj9zZ3Q66TPmrqmPdJjVRkBvQnQbjyX/lljFz0byzTX7RDpp7MFpRQ0KsGjcntyPPiMR//TLy4aLNhVyw2NfvNk+hGDk= ARC-Message-Signature: i=1; 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charset="utf-8" On reset, restore the default address translation mode for all the address spaces managed by the vIOMMU. Signed-off-by: Alejandro Jimenez Tested-by: Sairaj Kodilkar --- hw/i386/amd_iommu.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 71018d70dd10..90491367594b 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -962,6 +962,33 @@ static void amdvi_switch_address_space(AMDVIAddressSpa= ce *amdvi_as) } } =20 +/* + * For all existing address spaces managed by the IOMMU, enable/disable the + * corresponding memory regions depending on the address translation mode + * as determined by the global and individual address space settings. + */ +static void amdvi_switch_address_space_all(AMDVIState *s) +{ + AMDVIAddressSpace **iommu_as; + + for (int bus_num =3D 0; bus_num < PCI_BUS_MAX; bus_num++) { + + /* Nothing to do if there are no devices on the current bus */ + if (!s->address_spaces[bus_num]) { + continue; + } + iommu_as =3D s->address_spaces[bus_num]; + + for (int devfn =3D 0; devfn < PCI_DEVFN_MAX; devfn++) { + + if (!iommu_as[devfn]) { + continue; + } + amdvi_switch_address_space(iommu_as[devfn]); + } + } +} + /* log error without aborting since linux seems to be using reserved bits = */ static void amdvi_inval_devtab_entry(AMDVIState *s, uint64_t *cmd) { @@ -2199,6 +2226,7 @@ static void amdvi_sysbus_reset(DeviceState *dev) =20 /* Discard all mappings on device reset */ amdvi_address_space_unmap_all(s); + amdvi_switch_address_space_all(s); } =20 static void amdvi_sysbus_realize(DeviceState *dev, Error **errp) --=20 2.43.5 From nobody Mon Feb 9 09:04:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1746152391; cv=none; d=zohomail.com; s=zohoarc; b=FZtc7mOnlT/fXAE003yIg/AD8yPV6iWtslIOzMD2mjMtjlXwCB5L/aJcj7RyAWHOCFQ/aZKkgYifZEWOMvAKBEHYf8VHI6Bo0wmWe0IrzxoWl8JVHe7favTNXUq3IjBEmoMjakfdA9k/+vQPCXMvqYfI2pFtrUJeEULKO1+pNgM= ARC-Message-Signature: i=1; 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charset="utf-8" In order to enable device assignment with IOMMU protection and guest DMA address translation, IOMMU MAP notifier support is necessary to allow users like VFIO to synchronize the shadow page tables i.e. to receive notifications when the guest updates its I/O page tables and replay the mappings onto host I/O page tables. Provide a new dma-remap property to govern the ability to register for MAP notifications, effectively providing global control over the DMA address translation functionality that was implemented in previous changes. Note that DMA remapping support also requires the vIOMMU is configured with the NpCache capability, so a guest driver issues IOMMU invalidations for both map() and unmap() operations. This capability is already set by default and written to the configuration in amdvi_pci_realize() as part of AMDVI_CAPAB_FEATURES. Signed-off-by: Alejandro Jimenez Tested-by: Sairaj Kodilkar --- hw/i386/amd_iommu.c | 24 +++++++++++++++++------- hw/i386/amd_iommu.h | 3 +++ 2 files changed, 20 insertions(+), 7 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 90491367594b..a2df73062bf7 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -951,7 +951,9 @@ static void amdvi_iommu_address_space_sync_all(AMDVISta= te *s) */ static void amdvi_switch_address_space(AMDVIAddressSpace *amdvi_as) { - if (amdvi_as->addr_translation) { + AMDVIState *s =3D amdvi_as->iommu_state; + + if (s->dma_remap && amdvi_as->addr_translation) { /* Enabling DMA region */ memory_region_set_enabled(&amdvi_as->iommu_nodma, false); memory_region_set_enabled(MEMORY_REGION(&amdvi_as->iommu), true); @@ -2126,12 +2128,19 @@ static int amdvi_iommu_notify_flag_changed(IOMMUMem= oryRegion *iommu, AMDVIAddressSpace *as =3D container_of(iommu, AMDVIAddressSpace, iommu= ); AMDVIState *s =3D as->iommu_state; =20 - if (new & IOMMU_NOTIFIER_MAP) { - error_setg(errp, - "device %02x.%02x.%x requires iommu notifier which is not " - "currently supported", as->bus_num, PCI_SLOT(as->devfn), - PCI_FUNC(as->devfn)); - return -EINVAL; + /* + * Accurate synchronization of the vIOMMU page tables required to supp= ort + * MAP notifiers is provided by the dma-remap feature. In addition, th= is + * also requires that the vIOMMU presents the NpCache capability, so a= guest + * driver issues invalidations for both map() and unmap() operations. = The + * capability is already set by default as part of AMDVI_CAPAB_FEATURE= S and + * written to the configuration in amdvi_pci_realize(). + */ + if (!s->dma_remap && (new & IOMMU_NOTIFIER_MAP)) { + error_setg_errno(errp, ENOTSUP, + "device %02x.%02x.%x requires dma-remap=3D1", + as->bus_num, PCI_SLOT(as->devfn), PCI_FUNC(as->devfn)); + return -ENOTSUP; } =20 /* @@ -2281,6 +2290,7 @@ static void amdvi_sysbus_realize(DeviceState *dev, Er= ror **errp) =20 static const Property amdvi_properties[] =3D { DEFINE_PROP_BOOL("xtsup", AMDVIState, xtsup, false), + DEFINE_PROP_BOOL("dma-remap", AMDVIState, dma_remap, false), }; =20 static const VMStateDescription vmstate_amdvi_sysbus =3D { diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index a7462b2adb79..fc4d2f7a4575 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -420,6 +420,9 @@ struct AMDVIState { /* Interrupt remapping */ bool ga_enabled; bool xtsup; + + /* DMA address translation */ + bool dma_remap; }; =20 uint64_t amdvi_extended_feature_register(AMDVIState *s); --=20 2.43.5 From nobody Mon Feb 9 09:04:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1746152445; cv=none; d=zohomail.com; s=zohoarc; b=gk/oKa2dY4hiG5vOjNMQFoWg0MDL3G8gTetDvQNnuH85zs2L+tkFKDyuDlrkKuyNN0wLoqHn+glTmOHi30MHX0ckWE+pxVkI8nExkwjlH6nPBf/MibA6J0ZkR4s0FMCdTEsIxY3wZMxtdule3m5T49NgyXpk+KHFAx1suWglV6g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746152445; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" A guest must issue an INVALIDATE_DEVTAB_ENTRY command after changing a Device Table entry (DTE) e.g. after attaching a device and setting up its DTE. When intercepting this event, determine if the DTE has been configured for paging or not, and toggle the appropriate memory regions to allow DMA address translation for the address space if needed. Requires dma-remap=3Do= n. Signed-off-by: Alejandro Jimenez Tested-by: Sairaj Kodilkar --- hw/i386/amd_iommu.c | 78 +++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 76 insertions(+), 2 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index a2df73062bf7..75a92067f35f 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -991,18 +991,92 @@ static void amdvi_switch_address_space_all(AMDVIState= *s) } } =20 +/* + * A guest driver must issue the INVALIDATE_DEVTAB_ENTRY command to the IO= MMU + * after changing a Device Table entry. We can use this fact to detect whe= n a + * Device Table entry is created for a device attached to a paging domain = and + * enable the corresponding IOMMU memory region to allow for DMA translati= on if + * appropriate. + */ +static void amdvi_update_addr_translation_mode(AMDVIState *s, uint16_t dev= id) +{ + uint8_t bus_num, devfn, dte_mode; + AMDVIAddressSpace *as; + uint64_t dte[4] =3D { 0 }; + IOMMUNotifier *n; + int ret; + + /* + * Convert the devid encoded in the command to a bus and devfn in + * order to retrieve the corresponding address space. + */ + bus_num =3D PCI_BUS_NUM(devid); + devfn =3D devid & 0xff; + + /* + * The main buffer of size (AMDVIAddressSpace *) * (PCI_BUS_MAX) has a= lready + * been allocated within AMDVIState, but must be careful to not access + * unallocated devfn. + */ + if (!s->address_spaces[bus_num] || !s->address_spaces[bus_num][devfn])= { + return; + } + as =3D s->address_spaces[bus_num][devfn]; + + ret =3D amdvi_as_to_dte(as, dte); + + if (!ret) { + dte_mode =3D (dte[0] >> AMDVI_DEV_MODE_RSHIFT) & AMDVI_DEV_MODE_MA= SK; + } + + if ((ret < 0) || (!ret && !dte_mode)) { + /* + * The DTE could not be retrieved, it is not valid, or it is not s= etup + * for paging. In either case, ensure that if paging was previousl= y in + * use then invalidate all existing mappings and then switch to us= e the + * no_dma memory region. + */ + if (as->addr_translation) { + as->addr_translation =3D false; + + IOMMU_NOTIFIER_FOREACH(n, &as->iommu) { + amdvi_address_space_unmap(as, n); + } + amdvi_switch_address_space(as); + } + } else if (!as->addr_translation) { + /* + * Installing a DTE that enables translation where it wasn't previ= ously + * active. Activate the DMA memory region. + */ + as->addr_translation =3D true; + amdvi_switch_address_space(as); + amdvi_address_space_sync(as); + } +} + /* log error without aborting since linux seems to be using reserved bits = */ static void amdvi_inval_devtab_entry(AMDVIState *s, uint64_t *cmd) { uint16_t devid =3D cpu_to_le16((uint16_t)extract64(cmd[0], 0, 16)); =20 + trace_amdvi_devtab_inval(PCI_BUS_NUM(devid), PCI_SLOT(devid), + PCI_FUNC(devid)); + /* This command should invalidate internal caches of which there isn't= */ if (extract64(cmd[0], 16, 44) || cmd[1]) { amdvi_log_illegalcom_error(s, extract64(cmd[0], 60, 4), s->cmdbuf + s->cmdbuf_head); + return; + } + + /* + * When DMA remapping capability is enabled, check if updated DTE is s= etup + * for paging or not, and configure the corresponding memory regions. + */ + if (s->dma_remap) { + amdvi_update_addr_translation_mode(s, devid); } - trace_amdvi_devtab_inval(PCI_BUS_NUM(devid), PCI_SLOT(devid), - PCI_FUNC(devid)); } =20 static void amdvi_complete_ppr(AMDVIState *s, uint64_t *cmd) --=20 2.43.5 From nobody Mon Feb 9 09:04:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 2 May 2025 02:16:19 GMT Received: from alaljimee5bm-ol9-20250405.osdevelopmeniad.oraclevcn.com (alaljimee5bm-ol9-20250405.allregionaliads.osdevelopmeniad.oraclevcn.com [100.100.254.235]) by iadpaimrmta03.imrmtpd1.prodappiadaev1.oraclevcn.com (PPS) with ESMTP id 468nxkgyvr-20; Fri, 02 May 2025 02:16:19 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=corp-2025-04-25; bh=MXUbN L9dFuyRW6dtsmiXKHbRdnOOnvGvXPT1TmWhgAU=; b=iRwcejQ1xjR8nDYO9u1oR ANBqCAOuhPFDiQz01w5ROvyyWSjM+I87N+euS47R7JIdrYWEZAZNM9pIYyhvPekA d3hrmydjzrU2mY5EQ02cVwQ8cY3iBHuKg3isGolgNlwG8K3u7uceqlq7Mx9musbD QDupGAEF/KrqWhzWSHWlxf5oUTr0lO9UgDda4B4ydrN53jmNmFGKLwPeV+6foad1 xXG5tShViFRmzSLKKcSGGYebM3+RLKEnYOH6rA6KFIjkYAKlu5ycvXWkW+/7L/5D 6cN0r1c/zWm4gWT5kQC4jMFj0dbeETVaPpXoT6ffB7UoXiiWX9QBxfYTbJqrtIw8 g== From: Alejandro Jimenez To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, richard.henderson@linaro.org, eduardo@habkost.net, peterx@redhat.com, david@redhat.com, philmd@linaro.org, mst@redhat.com, marcel.apfelbaum@gmail.com, alex.williamson@redhat.com, vasant.hegde@amd.com, suravee.suthikulpanit@amd.com, santosh.shukla@amd.com, sarunkod@amd.com, Wei.Huang2@amd.com, clement.mathieu--drif@eviden.com, ethan.milon@eviden.com, joao.m.martins@oracle.com, boris.ostrovsky@oracle.com, alejandro.j.jimenez@oracle.com Subject: [PATCH v2 19/20] amd_iommu: Do not assume passthrough translation when DTE[TV]=0 Date: Fri, 2 May 2025 02:16:04 +0000 Message-ID: <20250502021605.1795985-20-alejandro.j.jimenez@oracle.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20250502021605.1795985-1-alejandro.j.jimenez@oracle.com> References: <20250502021605.1795985-1-alejandro.j.jimenez@oracle.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-01_06,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxlogscore=999 phishscore=0 suspectscore=0 spamscore=0 adultscore=0 mlxscore=0 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2504070000 definitions=main-2505020015 X-Authority-Analysis: v=2.4 cv=dfSA3WXe c=1 sm=1 tr=0 ts=68142afe b=1 cx=c_pps a=qoll8+KPOyaMroiJ2sR5sw==:117 a=qoll8+KPOyaMroiJ2sR5sw==:17 a=dt9VzEwgFbYA:10 a=yPCof4ZbAAAA:8 a=QsCEJq6UzS2LWQETwqwA:9 cc=ntf awl=host:13130 X-Proofpoint-GUID: tb_-ahigq50pMTY_5TmUU1XM6YnoWtSU X-Proofpoint-ORIG-GUID: tb_-ahigq50pMTY_5TmUU1XM6YnoWtSU X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDAxNiBTYWx0ZWRfX8wpMOcrpJ1KY SzxVmKApwCasVkHr8mfeAI8KrLdBze1J1ROIUw6NrZJH3yYQktrp4fYD4chZLLfPNhAyrqnL3oz 8RuVM83rQATnNcNNN0SOIJrYCSBdsanyGFed4Gt1yFCab36tRDVXn+KqaBGF9x/sfZmaLDOzvRk KRHz95/OfTgQE84EtF9C6nCCL+1FO6s9la9d9O7dzC2mOffzn3dp/BMapPy7Zcevz1PU7dG73NE W13QGm/ljox4TqsAwzAMN4qmmEAZ9+nb8FTLxb/iExFu2nErIAe/5wk2zB2AM9nBv9GGLApTsZ0 gcsmAoVPfTdr44YZMNO4E+ArRx0M62pNAteWAIKF3TiEPZNa/+zO2QdZGgyHXjRXH+TJikdOZUw TV+5OO91Zafamrih2XUQBft3kkQWrHnxhNFip76VFWItv01rvX4JElbRsgfpLLeKPmFoYBEl Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.177.32; envelope-from=alejandro.j.jimenez@oracle.com; helo=mx0b-00069f02.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @oracle.com) X-ZM-MESSAGEID: 1746152402851124100 Content-Type: text/plain; charset="utf-8" The AMD I/O Virtualization Technology (IOMMU) Specification (see Table 8: V, TV, and GV Fields in Device Table Entry), specifies that a DTE with V=3D1, TV=3D0 does not contain a valid address translation information. If a request requires a table walk, the walk is terminated when this condition is encountered. Do not assume that addresses for a device with DTE[TV]=3D0 are passed through (i.e. not remapped) and instead terminate the page table walk early. Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU") Signed-off-by: Alejandro Jimenez Tested-by: Sairaj Kodilkar --- hw/i386/amd_iommu.c | 87 +++++++++++++++++++++++++-------------------- 1 file changed, 48 insertions(+), 39 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 75a92067f35f..6d1e7cc65f83 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -1612,51 +1612,60 @@ static void amdvi_page_walk(AMDVIAddressSpace *as, = uint64_t *dte, uint64_t pte =3D dte[0], pte_addr, page_mask; =20 /* make sure the DTE has TV =3D 1 */ - if (pte & AMDVI_DEV_TRANSLATION_VALID) { - level =3D get_pte_translation_mode(pte); - if (level >=3D 7) { - trace_amdvi_mode_invalid(level, addr); + if (!(pte & AMDVI_DEV_TRANSLATION_VALID)) { + /* + * A DTE with V=3D1, TV=3D0 does not have a valid Page Table Root = Pointer. + * An IOMMU processing a request that requires a table walk termin= ates + * the walk when it encounters this condition. Do the same and ret= urn + * instead of assuming that the address is forwarded without trans= lation + * i.e. the passthrough case, as it is done for the case where DTE= [V]=3D0. + */ + return; + } + + level =3D get_pte_translation_mode(pte); + if (level >=3D 7) { + trace_amdvi_mode_invalid(level, addr); + return; + } + if (level =3D=3D 0) { + goto no_remap; + } + + /* we are at the leaf page table or page table encodes a huge page */ + do { + pte_perms =3D amdvi_get_perms(pte); + present =3D pte & 1; + if (!present || perms !=3D (perms & pte_perms)) { + amdvi_page_fault(as->iommu_state, as->devfn, addr, perms); + trace_amdvi_page_fault(addr); return; } - if (level =3D=3D 0) { - goto no_remap; + /* go to the next lower level */ + pte_addr =3D pte & AMDVI_DEV_PT_ROOT_MASK; + /* add offset and load pte */ + pte_addr +=3D ((addr >> (3 + 9 * level)) & 0x1FF) << 3; + pte =3D amdvi_get_pte_entry(as->iommu_state, pte_addr, as->devfn); + if (!pte) { + return; } + oldlevel =3D level; + level =3D get_pte_translation_mode(pte); + } while (level > 0 && level < 7); =20 - /* we are at the leaf page table or page table encodes a huge page= */ - do { - pte_perms =3D amdvi_get_perms(pte); - present =3D pte & 1; - if (!present || perms !=3D (perms & pte_perms)) { - amdvi_page_fault(as->iommu_state, as->devfn, addr, perms); - trace_amdvi_page_fault(addr); - return; - } - - /* go to the next lower level */ - pte_addr =3D pte & AMDVI_DEV_PT_ROOT_MASK; - /* add offset and load pte */ - pte_addr +=3D ((addr >> (3 + 9 * level)) & 0x1FF) << 3; - pte =3D amdvi_get_pte_entry(as->iommu_state, pte_addr, as->dev= fn); - if (!pte || (pte =3D=3D (uint64_t)-1)) { - return; - } - oldlevel =3D level; - level =3D get_pte_translation_mode(pte); - } while (level > 0 && level < 7); + if (level =3D=3D 0x7) { + page_mask =3D pte_override_page_mask(pte); + } else { + page_mask =3D pte_get_page_mask(oldlevel); + } =20 - if (level =3D=3D 0x7) { - page_mask =3D pte_override_page_mask(pte); - } else { - page_mask =3D pte_get_page_mask(oldlevel); - } + /* get access permissions from pte */ + ret->iova =3D addr & page_mask; + ret->translated_addr =3D (pte & AMDVI_DEV_PT_ROOT_MASK) & page_mask; + ret->addr_mask =3D ~page_mask; + ret->perm =3D amdvi_get_perms(pte); + return; =20 - /* get access permissions from pte */ - ret->iova =3D addr & page_mask; - ret->translated_addr =3D (pte & AMDVI_DEV_PT_ROOT_MASK) & page_mas= k; - ret->addr_mask =3D ~page_mask; - ret->perm =3D amdvi_get_perms(pte); - return; - } no_remap: ret->iova =3D addr & AMDVI_PAGE_MASK_4K; ret->translated_addr =3D addr & AMDVI_PAGE_MASK_4K; --=20 2.43.5 From nobody Mon Feb 9 09:04:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1746152231; cv=none; d=zohomail.com; s=zohoarc; b=Tz22dMqA/Xb07QNFOYUmMFmvCO6Gg4IkePsPyW7fDBYRfpm9NYJKHFKmT0XSNytbBhhzye64n+hbGfzLUu6B6dkz/2BNVhvgGC/VIKwrDzwJJyr4GMVBNVuqco7Jiv2cySh7BwSx23Bhn02AESW7QS2x0wnrNqorp4LPAaC6sqg= ARC-Message-Signature: i=1; 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b=GHNRyoAL3thJwSXzrQ56+ r3KS7AmJIYPuXiM+yNtjHLAboSGN6dNCvF5Ys6103RnKEZMbk7guRFuM1FcD/P0L fDIeWM9jOnK/TDkWvBVJ+J1WDejHWR7BqM68+o3WiZYEB9fXac4s3p4VrESKBlyk VGrgcRo5gA5glKCXHLCIZtaOb/QEvUDjJ4cde2H52Z4RmbV1f99JOgMIXu3tsdbf wJvTcX5zYjleleBskOLddnV03MmurzIyACUrmPxAnPN1P0U+1yYsUSrXp7jtnroc lLRDkoz8yjZKRmFxcfR6R4ojC7Dy+RPSTnzcGg+ly5EzptoaIOOlRKG2sBSxU+aP A== From: Alejandro Jimenez To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, richard.henderson@linaro.org, eduardo@habkost.net, peterx@redhat.com, david@redhat.com, philmd@linaro.org, mst@redhat.com, marcel.apfelbaum@gmail.com, alex.williamson@redhat.com, vasant.hegde@amd.com, suravee.suthikulpanit@amd.com, santosh.shukla@amd.com, sarunkod@amd.com, Wei.Huang2@amd.com, clement.mathieu--drif@eviden.com, ethan.milon@eviden.com, joao.m.martins@oracle.com, boris.ostrovsky@oracle.com, alejandro.j.jimenez@oracle.com Subject: [PATCH v2 20/20] amd_iommu: Refactor amdvi_page_walk() to use common code for page walk Date: Fri, 2 May 2025 02:16:05 +0000 Message-ID: <20250502021605.1795985-21-alejandro.j.jimenez@oracle.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20250502021605.1795985-1-alejandro.j.jimenez@oracle.com> References: <20250502021605.1795985-1-alejandro.j.jimenez@oracle.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-01_06,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxlogscore=999 phishscore=0 suspectscore=0 spamscore=0 adultscore=0 mlxscore=0 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2504070000 definitions=main-2505020015 X-Proofpoint-GUID: vOeqr5Iz5DIhOtRbohipgXLinlwAcluU X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDAxNiBTYWx0ZWRfX+bPl6Kpovm3j HNysKGQlOdAr5f/WRqVCE7xJurxcieXATA0qE2YtWXljAnjWWLehAHIZkjaB1KHmPsGgJWQs2SG nh2hUGVqrbSV2XShKcUiD/RNIN2F1hHM8A9bX64YfV4TzOjEX02QF/Rt5vIbWo9vNi9JTJfKT0g mnZEhDzCA7TI/UfieYuTwcz2nkXtGP9lcYyd70auv+5cTouVXB2wlkCq9YTLFay/WUqcO0q+Z7M bpN4zUYWo18Eb/Y38mxS/XQ7mfMeTFHDPrTWgPLpzCJM+J5jGV7Y1wedJ1fBgl589AYgJXS8E9O kjBH8GzlANkrRI6AKRg0iJlRRE4EsXN/Sw2xI4NqVbUJ7XoG6RP9OAJkS0ShANkS3a9XrEWPI6I oiA5vRQVAcsbPtRNBz9wBsoKq/Noe0OD1XRHjCdnkf10ylUVrWCUB2GYJS1140YKhl7f1bB2 X-Authority-Analysis: v=2.4 cv=ZuHtK87G c=1 sm=1 tr=0 ts=68142b04 b=1 cx=c_pps a=qoll8+KPOyaMroiJ2sR5sw==:117 a=qoll8+KPOyaMroiJ2sR5sw==:17 a=dt9VzEwgFbYA:10 a=yPCof4ZbAAAA:8 a=vEuQwzgZqMseO_9XBp0A:9 cc=ntf awl=host:13130 X-Proofpoint-ORIG-GUID: vOeqr5Iz5DIhOtRbohipgXLinlwAcluU Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Simplify amdvi_page_walk() by making it call the fetch_pte() helper that is already in use by the shadow page synchronization code. Ensures all code uses the same page table walking algorithm. Signed-off-by: Alejandro Jimenez Tested-by: Sairaj Kodilkar --- hw/i386/amd_iommu.c | 59 +++++++++++++++++++++------------------------ 1 file changed, 27 insertions(+), 32 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 6d1e7cc65f83..ab236a8e016d 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -1608,11 +1608,13 @@ static void amdvi_page_walk(AMDVIAddressSpace *as, = uint64_t *dte, IOMMUTLBEntry *ret, unsigned perms, hwaddr addr) { - unsigned level, present, pte_perms, oldlevel; - uint64_t pte =3D dte[0], pte_addr, page_mask; + hwaddr page_mask, pagesize =3D 0; + uint8_t mode; + uint64_t pte; + int fetch_ret; =20 /* make sure the DTE has TV =3D 1 */ - if (!(pte & AMDVI_DEV_TRANSLATION_VALID)) { + if (!(dte[0] & AMDVI_DEV_TRANSLATION_VALID)) { /* * A DTE with V=3D1, TV=3D0 does not have a valid Page Table Root = Pointer. * An IOMMU processing a request that requires a table walk termin= ates @@ -1623,42 +1625,35 @@ static void amdvi_page_walk(AMDVIAddressSpace *as, = uint64_t *dte, return; } =20 - level =3D get_pte_translation_mode(pte); - if (level >=3D 7) { - trace_amdvi_mode_invalid(level, addr); + mode =3D get_pte_translation_mode(dte[0]); + if (mode >=3D 7) { + trace_amdvi_mode_invalid(mode, addr); return; } - if (level =3D=3D 0) { + if (mode =3D=3D 0) { goto no_remap; } =20 - /* we are at the leaf page table or page table encodes a huge page */ - do { - pte_perms =3D amdvi_get_perms(pte); - present =3D pte & 1; - if (!present || perms !=3D (perms & pte_perms)) { - amdvi_page_fault(as->iommu_state, as->devfn, addr, perms); - trace_amdvi_page_fault(addr); - return; - } - /* go to the next lower level */ - pte_addr =3D pte & AMDVI_DEV_PT_ROOT_MASK; - /* add offset and load pte */ - pte_addr +=3D ((addr >> (3 + 9 * level)) & 0x1FF) << 3; - pte =3D amdvi_get_pte_entry(as->iommu_state, pte_addr, as->devfn); - if (!pte) { - return; - } - oldlevel =3D level; - level =3D get_pte_translation_mode(pte); - } while (level > 0 && level < 7); + /* Attempt to fetch the PTE to determine if a valid mapping exists */ + fetch_ret =3D fetch_pte(as, addr, dte[0], &pte, &pagesize); =20 - if (level =3D=3D 0x7) { - page_mask =3D pte_override_page_mask(pte); - } else { - page_mask =3D pte_get_page_mask(oldlevel); + /* + * If walking the page table results in an error of any type, returns = an + * empty PTE i.e. no mapping, or the permissions do not match, return = since + * there is no translation available. + */ + if (fetch_ret < 0 || !IOMMU_PTE_PRESENT(pte) || + perms !=3D (perms & amdvi_get_perms(pte))) { + + amdvi_page_fault(as->iommu_state, as->devfn, addr, perms); + trace_amdvi_page_fault(addr); + return; } =20 + /* A valid PTE and page size has been retrieved */ + assert(pagesize); + page_mask =3D ~(pagesize - 1); + /* get access permissions from pte */ ret->iova =3D addr & page_mask; ret->translated_addr =3D (pte & AMDVI_DEV_PT_ROOT_MASK) & page_mask; @@ -1670,7 +1665,7 @@ no_remap: ret->iova =3D addr & AMDVI_PAGE_MASK_4K; ret->translated_addr =3D addr & AMDVI_PAGE_MASK_4K; ret->addr_mask =3D ~AMDVI_PAGE_MASK_4K; - ret->perm =3D amdvi_get_perms(pte); + ret->perm =3D amdvi_get_perms(dte[0]); } =20 static void amdvi_do_translate(AMDVIAddressSpace *as, hwaddr addr, --=20 2.43.5