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Thu, 01 May 2025 14:21:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 34/59] accel/tcg: Pass TCGTBCPUState to tb_lookup Date: Thu, 1 May 2025 14:20:48 -0700 Message-ID: <20250501212113.2961531-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746135014799019100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 4a405d7b56..808983e461 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -232,35 +232,33 @@ static TranslationBlock *tb_htable_lookup(CPUState *c= pu, vaddr pc, * * Returns: an existing translation block or NULL. */ -static inline TranslationBlock *tb_lookup(CPUState *cpu, vaddr pc, - uint64_t cs_base, uint32_t flags, - uint32_t cflags) +static inline TranslationBlock *tb_lookup(CPUState *cpu, TCGTBCPUState s) { TranslationBlock *tb; CPUJumpCache *jc; uint32_t hash; =20 /* we should never be trying to look up an INVALID tb */ - tcg_debug_assert(!(cflags & CF_INVALID)); + tcg_debug_assert(!(s.cflags & CF_INVALID)); =20 - hash =3D tb_jmp_cache_hash_func(pc); + hash =3D tb_jmp_cache_hash_func(s.pc); jc =3D cpu->tb_jmp_cache; =20 tb =3D qatomic_read(&jc->array[hash].tb); if (likely(tb && - jc->array[hash].pc =3D=3D pc && - tb->cs_base =3D=3D cs_base && - tb->flags =3D=3D flags && - tb_cflags(tb) =3D=3D cflags)) { + jc->array[hash].pc =3D=3D s.pc && + tb->cs_base =3D=3D s.cs_base && + tb->flags =3D=3D s.flags && + tb_cflags(tb) =3D=3D s.cflags)) { goto hit; } =20 - tb =3D tb_htable_lookup(cpu, pc, cs_base, flags, cflags); + tb =3D tb_htable_lookup(cpu, s.pc, s.cs_base, s.flags, s.cflags); if (tb =3D=3D NULL) { return NULL; } =20 - jc->array[hash].pc =3D pc; + jc->array[hash].pc =3D s.pc; qatomic_set(&jc->array[hash].tb, tb); =20 hit: @@ -268,7 +266,7 @@ hit: * As long as tb is not NULL, the contents are consistent. Therefore, * the virtual PC has to match for non-CF_PCREL translations. */ - assert((tb_cflags(tb) & CF_PCREL) || tb->pc =3D=3D pc); + assert((tb_cflags(tb) & CF_PCREL) || tb->pc =3D=3D s.pc); return tb; } =20 @@ -402,7 +400,7 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) cpu_loop_exit(cpu); } =20 - tb =3D tb_lookup(cpu, s.pc, s.cs_base, s.flags, s.cflags); + tb =3D tb_lookup(cpu, s); if (tb =3D=3D NULL) { return tcg_code_gen_epilogue; } @@ -581,7 +579,7 @@ void cpu_exec_step_atomic(CPUState *cpu) * Any breakpoint for this insn will have been recognized earlier. */ =20 - tb =3D tb_lookup(cpu, s.pc, s.cs_base, s.flags, s.cflags); + tb =3D tb_lookup(cpu, s); if (tb =3D=3D NULL) { mmap_lock(); tb =3D tb_gen_code(cpu, s.pc, s.cs_base, s.flags, s.cflags); @@ -955,7 +953,7 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc) break; } =20 - tb =3D tb_lookup(cpu, s.pc, s.cs_base, s.flags, s.cflags); + tb =3D tb_lookup(cpu, s); if (tb =3D=3D NULL) { CPUJumpCache *jc; uint32_t h; --=20 2.43.0