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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-30a476267e0sm1384573a91.39.2025.05.01.14.21.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 May 2025 14:21:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746134475; x=1746739275; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EM05DafzKajHmaQ2N4+ygLxYZEoAk2szFffhGOKpRHI=; b=nsjKT35i8c+g8lWqKt/I6r9ZX15cpZhqgOCBDp9m+vo6aDJRjvRObtSPIKnjw0zJf5 svEHik9w+Wa6ozfjH3IjvfdfkdG7AM6SUsnlcIhci4xspeOZSPH2+OVA+mbg+onPF9ut 5G/JssKl9YhQcr7p5R2Ghj2Xq3votKRHfv4quo4CWLy76qGLKJKNVQxbS50M9rEPrRqP InqWKD9hc4jZeI9dv6MiQji+470Iu7h9e1hnkltonMIubIuoYxe+3KhLmZrrF+8SViRj ZiO4vRtfuvNjRVJrmXl2Nzaty5CqvyzsSnf2vK1YudDcV3Ft+yYegojE9/91BdYTcMbU lqhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746134475; x=1746739275; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EM05DafzKajHmaQ2N4+ygLxYZEoAk2szFffhGOKpRHI=; b=rcWDLTc9vWVosXJSL+8Xo4rjE67wUcD0EcAv+LLhr/nBXcmo3Osd5hdv2k2rlQweAh dmoZJtUYklhncHyIHpMWyAS26sUCkFXPmQ8hK15SYx6Q85k5/HyPEr5MpaYlDAV1lxfK 4s4HI3rXlblT4wDFcbu573AwXjuRnAN+NmEqZL+ASywrbGiG1r6koKuX1JT9k2ZeI+uu VTxOm9kOJaRor5GNMVEK+eLUnXqw0zhiUlXSWKZNkUjpdcUyq+i07aL15fp0CM848eMg cbdjHvRw8BgbNbaRW4KpzK01mWRNcHJ674bzIGVuCzmAeSO8Wzlr5Y01QQW70rl/E/q+ tibQ== X-Gm-Message-State: AOJu0YwFUmg1QDvPJF0M9kRd+Pm1OgD7dGOWxvu/3P2+hASoFFcglbpE N1UBurgYcUgeaKHYu6BqhQW84fSTcfMxdSpKgbyt4d7+Q7Nj/r+fleRpwqZ/V+3+cOoQH3kI/Lh k X-Gm-Gg: ASbGncuVvSZvm0moGMFNci0gSfs1QdnkHDVfE839UQhrYHoEpAgW8hvn53xB2NoKNaj 46+g3aASDPsELw4z9+1g11mXS1dXgx13U41HdHKTw2RrFElXimXDTnwXnbsQHgcE6AGBH+2fOKi OiSUA/W7dcTfnwn6FcqvvR0Vz6Bxgk4/pPB/SBUsb5LUDPVNi22QQXGQMztycqP/KxsqbQEFznC vs3mVUOLRfOPCUB+Z8dydyTLvvE8GqEviGHTBaSwHEZxdv7ve8LC7EzDz0pQTpkl51kyJ79NFHo zqj67E0byg6O3bPW0fbH5lgoscBQDAsm48aPvZTtqq3JwjAWtMAGa0FzvRolHwbsDkaZVGZTW1U nnZafFYRXag== X-Google-Smtp-Source: AGHT+IHs3+THVnJvh5J5Mmjc4xkhgzHSy+3Tjf0x/4X8o933ZkQze5Djhmm+2RPXauBSu5tkMEAM3w== X-Received: by 2002:a17:90b:5184:b0:2ee:d63f:d73 with SMTP id 98e67ed59e1d1-30a4e5a1376mr974522a91.11.1746134475347; Thu, 01 May 2025 14:21:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 01/59] accel/tcg: Add CPUState argument to page_unprotect Date: Thu, 1 May 2025 14:20:15 -0700 Message-ID: <20250501212113.2961531-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746134525489019100 In the next patch, page_unprotect will need to pass the CPUState to tb_invalidate_phys_page_unwind. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/user/page-protection.h | 2 +- accel/tcg/user-exec.c | 8 +++++--- linux-user/elfload.c | 2 +- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/include/user/page-protection.h b/include/user/page-protection.h index d5c8748d49..1de72e31e6 100644 --- a/include/user/page-protection.h +++ b/include/user/page-protection.h @@ -16,7 +16,7 @@ #include "exec/target_long.h" #include "exec/translation-block.h" =20 -int page_unprotect(tb_page_addr_t address, uintptr_t pc); +int page_unprotect(CPUState *cpu, tb_page_addr_t address, uintptr_t pc); =20 int page_get_flags(target_ulong address); =20 diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 5eef8e7f18..90b345a0cf 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -128,7 +128,7 @@ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_w= rite) bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, uintptr_t host_pc, abi_ptr guest_addr) { - switch (page_unprotect(guest_addr, host_pc)) { + switch (page_unprotect(cpu, guest_addr, host_pc)) { case 0: /* * Fault not caused by a page marked unwritable to protect @@ -584,7 +584,7 @@ bool page_check_range(target_ulong start, target_ulong = len, int flags) break; } /* Asking about writable, but has been protected: undo. */ - if (!page_unprotect(start, 0)) { + if (!page_unprotect(NULL, start, 0)) { ret =3D false; break; } @@ -704,11 +704,13 @@ void tb_lock_page0(tb_page_addr_t address) * immediately exited. (We can only return 2 if the 'pc' argument is * non-zero.) */ -int page_unprotect(tb_page_addr_t address, uintptr_t pc) +int page_unprotect(CPUState *cpu, tb_page_addr_t address, uintptr_t pc) { PageFlagsNode *p; bool current_tb_invalidated; =20 + assert((cpu =3D=3D NULL) =3D=3D (pc =3D=3D 0)); + /* * Technically this isn't safe inside a signal handler. However we * know this only ever happens in a synchronous SEGV handler, so in diff --git a/linux-user/elfload.c b/linux-user/elfload.c index fbfdec2f17..87c6d3ab9f 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -4260,7 +4260,7 @@ static int wmr_page_unprotect_regions(void *opaque, t= arget_ulong start, size_t step =3D MAX(TARGET_PAGE_SIZE, qemu_real_host_page_size()); =20 while (1) { - page_unprotect(start, 0); + page_unprotect(NULL, start, 0); if (end - start <=3D step) { break; } --=20 2.43.0 From nobody Sat Nov 15 22:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746134523; cv=none; d=zohomail.com; s=zohoarc; b=FKpyP7iacT1lQ8drMzcVY6YDA01FogLru5B4J9KQpQnCbNjXt2M/tzUiDAtRu2Hh/rzpJuXWEJSmvRDmZcJcjb2+u/2QMxIhSAsoJUuN8vUSe9FodSiqO7uEX7Zk3kyGY2UbVi1BWtVM5KhOgMhV2Rt1nDrU4+CYV9xxOUDIqNg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746134523; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=NyHS8JhkVggJWYCLf21RFoGh3DyPnGZlHWJduulHrvM=; b=Ib1MKyZfaqho5RrykVxU7uHtXuzI4pAjzAqepZGxNV+xiZy7xNkzGVKNfGTog2tzMS5gk0K6cDu/JfAUAZWZt5VzXFUXYZ2Egv4HX3vHghH8MtqCc9LEvU8L6sYctlddn2R3ZLbQFt8BVOAodeNhT1x+3Zw/nncOgJcR/76CslM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746134523188425.10001795089545; Thu, 1 May 2025 14:22:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAbLc-0000q1-TO; Thu, 01 May 2025 17:21:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAbLM-0000k7-Lk for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:21 -0400 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAbLJ-0001Qi-LP for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:20 -0400 Received: by mail-pj1-x1036.google.com with SMTP id 98e67ed59e1d1-301918a4e3bso1614363a91.3 for ; Thu, 01 May 2025 14:21:17 -0700 (PDT) Received: from stoup.. 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Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/tb-internal.h | 3 ++- accel/tcg/tb-maint.c | 8 ++++---- accel/tcg/user-exec.c | 5 +++-- 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/accel/tcg/tb-internal.h b/accel/tcg/tb-internal.h index 08538e2896..1078de6c99 100644 --- a/accel/tcg/tb-internal.h +++ b/accel/tcg/tb-internal.h @@ -50,6 +50,7 @@ void tb_invalidate_phys_range_fast(ram_addr_t ram_addr, uintptr_t retaddr); #endif /* CONFIG_SOFTMMU */ =20 -bool tb_invalidate_phys_page_unwind(tb_page_addr_t addr, uintptr_t pc); +bool tb_invalidate_phys_page_unwind(CPUState *cpu, tb_page_addr_t addr, + uintptr_t pc); =20 #endif diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c index d479f53ae0..714dcaedc9 100644 --- a/accel/tcg/tb-maint.c +++ b/accel/tcg/tb-maint.c @@ -1045,7 +1045,8 @@ static void tb_invalidate_phys_page(tb_page_addr_t ad= dr) * TB (because it was modified by this store and the guest CPU has * precise-SMC semantics). */ -bool tb_invalidate_phys_page_unwind(tb_page_addr_t addr, uintptr_t pc) +bool tb_invalidate_phys_page_unwind(CPUState *cpu, tb_page_addr_t addr, + uintptr_t pc) { TranslationBlock *current_tb; bool current_tb_modified; @@ -1083,15 +1084,14 @@ bool tb_invalidate_phys_page_unwind(tb_page_addr_t = addr, uintptr_t pc) * the CPU state. */ current_tb_modified =3D true; - cpu_restore_state_from_tb(current_cpu, current_tb, pc); + cpu_restore_state_from_tb(cpu, current_tb, pc); } tb_phys_invalidate__locked(tb); } =20 if (current_tb_modified) { /* Force execution of one insn next time. */ - CPUState *cpu =3D current_cpu; - cpu->cflags_next_tb =3D 1 | CF_NOIRQ | curr_cflags(current_cpu); + cpu->cflags_next_tb =3D 1 | CF_NOIRQ | curr_cflags(cpu); return true; } return false; diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 90b345a0cf..39b76d9654 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -749,7 +749,8 @@ int page_unprotect(CPUState *cpu, tb_page_addr_t addres= s, uintptr_t pc) len =3D TARGET_PAGE_SIZE; prot =3D p->flags | PAGE_WRITE; pageflags_set_clear(start, start + len - 1, PAGE_WRITE, 0); - current_tb_invalidated =3D tb_invalidate_phys_page_unwind(star= t, pc); + current_tb_invalidated =3D + tb_invalidate_phys_page_unwind(cpu, start, pc); } else { start =3D address & -host_page_size; len =3D host_page_size; @@ -772,7 +773,7 @@ int page_unprotect(CPUState *cpu, tb_page_addr_t addres= s, uintptr_t pc) * the corresponding translated code. */ current_tb_invalidated |=3D - tb_invalidate_phys_page_unwind(addr, pc); + tb_invalidate_phys_page_unwind(cpu, addr, pc); } } if (prot & PAGE_EXEC) { --=20 2.43.0 From nobody Sat Nov 15 22:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746134850; cv=none; d=zohomail.com; s=zohoarc; b=i3993z51PKLbfvOOXdUxB9MbhQx6jqByDLwzEUx/j1QkXAI7Ly+g47c+QjrnXqb6WsxEVjJZWVGW+wDJ2etddFmph3smcmbYIZMD8pOTKMMVurEqRQg4ZQBrRL2DI9/eHoN21/RywAW9TiWEiYRJV+yIb0VnCql9Uj4Og3IrI6s= ARC-Message-Signature: i=1; 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Thu, 01 May 2025 14:21:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 03/59] accel/tcg: Add CPUState arg to tb_invalidate_phys_page_range__locked Date: Thu, 1 May 2025 14:20:17 -0700 Message-ID: <20250501212113.2961531-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746134852453019100 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/tb-maint.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c index 714dcaedc9..927e9c8ede 100644 --- a/accel/tcg/tb-maint.c +++ b/accel/tcg/tb-maint.c @@ -1100,9 +1100,12 @@ bool tb_invalidate_phys_page_unwind(CPUState *cpu, t= b_page_addr_t addr, /* * @p must be non-NULL. * Call with all @pages locked. + * (@cpu, @retaddr) may be (NULL, 0) outside of a cpu context, + * in which case precise_smc need not be detected. */ static void -tb_invalidate_phys_page_range__locked(struct page_collection *pages, +tb_invalidate_phys_page_range__locked(CPUState *cpu, + struct page_collection *pages, PageDesc *p, tb_page_addr_t start, tb_page_addr_t last, uintptr_t retaddr) @@ -1194,7 +1197,7 @@ void tb_invalidate_phys_range(tb_page_addr_t start, t= b_page_addr_t last) page_start =3D index << TARGET_PAGE_BITS; page_last =3D page_start | ~TARGET_PAGE_MASK; page_last =3D MIN(page_last, last); - tb_invalidate_phys_page_range__locked(pages, pd, + tb_invalidate_phys_page_range__locked(NULL, pages, pd, page_start, page_last, 0); } page_collection_unlock(pages); @@ -1215,7 +1218,7 @@ static void tb_invalidate_phys_page_fast__locked(stru= ct page_collection *pages, } =20 assert_page_locked(p); - tb_invalidate_phys_page_range__locked(pages, p, start, start + len - 1= , ra); + tb_invalidate_phys_page_range__locked(NULL, pages, p, start, start + l= en - 1, ra); } =20 /* --=20 2.43.0 From nobody Sat Nov 15 22:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746134930; cv=none; d=zohomail.com; s=zohoarc; b=AFzx3U069Tvn4a8m5kzCB1+B1z/cAYOzStWzOjc970TrscBbSQPf44cJANQ/WrUxQiwi6wznBdvxME132pMqxL78sxhYlD+UcdhUKMpLeBaJRCln53/wcMYd2cDjeQA6YzKAUxAMQ2jZzquA5nfHJebTaRYEGhEYQHwCMxPr/Fo= ARC-Message-Signature: i=1; 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Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/tb-maint.c | 36 +++++++++++------------------------- 1 file changed, 11 insertions(+), 25 deletions(-) diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c index 927e9c8ede..c893ea3073 100644 --- a/accel/tcg/tb-maint.c +++ b/accel/tcg/tb-maint.c @@ -1203,38 +1203,24 @@ void tb_invalidate_phys_range(tb_page_addr_t start,= tb_page_addr_t last) page_collection_unlock(pages); } =20 -/* - * Call with all @pages in the range [@start, @start + len[ locked. - */ -static void tb_invalidate_phys_page_fast__locked(struct page_collection *p= ages, - tb_page_addr_t start, - unsigned len, uintptr_t r= a) -{ - PageDesc *p; - - p =3D page_find(start >> TARGET_PAGE_BITS); - if (!p) { - return; - } - - assert_page_locked(p); - tb_invalidate_phys_page_range__locked(NULL, pages, p, start, start + l= en - 1, ra); -} - /* * len must be <=3D 8 and start must be a multiple of len. * Called via softmmu_template.h when code areas are written to with * iothread mutex not held. */ -void tb_invalidate_phys_range_fast(ram_addr_t ram_addr, - unsigned size, - uintptr_t retaddr) +void tb_invalidate_phys_range_fast(ram_addr_t start, + unsigned len, uintptr_t ra) { - struct page_collection *pages; + PageDesc *p =3D page_find(start >> TARGET_PAGE_BITS); =20 - pages =3D page_collection_lock(ram_addr, ram_addr + size - 1); - tb_invalidate_phys_page_fast__locked(pages, ram_addr, size, retaddr); - page_collection_unlock(pages); + if (p) { + ram_addr_t last =3D start + len - 1; + struct page_collection *pages =3D page_collection_lock(start, last= ); + + tb_invalidate_phys_page_range__locked(NULL, pages, p, + start, last, ra); + page_collection_unlock(pages); + } } =20 #endif /* CONFIG_USER_ONLY */ --=20 2.43.0 From nobody Sat Nov 15 22:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746135064; cv=none; d=zohomail.com; s=zohoarc; b=mjT74KzMVervbwy3zLBmSnTUBB6ldq+sODs37bog2W1nmjtuDm1RzQTd7UspZmhuaM6ms+GifPFnz3EcV2Y1M0qpMgBZWmH3Dsp5u0ntwD4+TKeAFl2HaYyjH490YPpR+w4N/Tk5hW1CJ/I4o3QRg7cSd+ce8RZZm2PeWzmKYE0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746135064; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=uWktBFOiwzYz1m9m1VKfbXX4KkdhBRM9kN+RtMXQVTs=; b=J+HOfkwXZXQsxwr7ePPYhq+2hoUn4QNuL2gAHNoT8YmkhAKZlRydY57V2e2HHFc2DMADZD/wk1zu4Bh+2VAQGXNEzSu6RmTQrgXEnMKZWNcA4qIcpeVgtkx6mdRiVu5Rw2a0wjFSTWskiP9NjJg2UjqIYDmChglAiUkrZNmA+5I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746135064462868.2829975018074; Thu, 1 May 2025 14:31:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAbLh-0000sr-6N; Thu, 01 May 2025 17:21:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAbLO-0000kv-F4 for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:23 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAbLM-0001R5-An for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:22 -0400 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-2240b4de12bso23211015ad.2 for ; Thu, 01 May 2025 14:21:19 -0700 (PDT) Received: from stoup.. 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Thu, 01 May 2025 14:21:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 05/59] accel/tcg: Add CPUState arg to tb_invalidate_phys_range Date: Thu, 1 May 2025 14:20:19 -0700 Message-ID: <20250501212113.2961531-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746135067484124100 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 3 ++- accel/tcg/tb-maint.c | 10 ++++++---- accel/tcg/translate-all.c | 2 +- accel/tcg/user-exec.c | 4 ++-- system/physmem.c | 2 +- target/arm/helper.c | 2 +- 6 files changed, 13 insertions(+), 10 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 944b579d91..bee3416e7e 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -122,7 +122,8 @@ int probe_access_full_mmu(CPUArchState *env, vaddr addr= , int size, =20 /* TranslationBlock invalidate API */ void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); -void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t last); +void tb_invalidate_phys_range(CPUState *cpu, tb_page_addr_t start, + tb_page_addr_t last); void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr); =20 #if !defined(CONFIG_USER_ONLY) diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c index c893ea3073..c7600fc6ac 100644 --- a/accel/tcg/tb-maint.c +++ b/accel/tcg/tb-maint.c @@ -1012,7 +1012,8 @@ TranslationBlock *tb_link_page(TranslationBlock *tb) * Called with mmap_lock held for user-mode emulation. * NOTE: this function must not be called while a TB is running. */ -void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t last) +void tb_invalidate_phys_range(CPUState *cpu, tb_page_addr_t start, + tb_page_addr_t last) { TranslationBlock *tb; PageForEachNext n; @@ -1035,7 +1036,7 @@ static void tb_invalidate_phys_page(tb_page_addr_t ad= dr) =20 start =3D addr & TARGET_PAGE_MASK; last =3D addr | ~TARGET_PAGE_MASK; - tb_invalidate_phys_range(start, last); + tb_invalidate_phys_range(NULL, start, last); } =20 /* @@ -1178,7 +1179,8 @@ tb_invalidate_phys_page_range__locked(CPUState *cpu, * access: the virtual CPU will exit the current TB if code is modified in= side * this TB. */ -void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t last) +void tb_invalidate_phys_range(CPUState *cpu, tb_page_addr_t start, + tb_page_addr_t last) { struct page_collection *pages; tb_page_addr_t index, index_last; @@ -1197,7 +1199,7 @@ void tb_invalidate_phys_range(tb_page_addr_t start, t= b_page_addr_t last) page_start =3D index << TARGET_PAGE_BITS; page_last =3D page_start | ~TARGET_PAGE_MASK; page_last =3D MIN(page_last, last); - tb_invalidate_phys_page_range__locked(NULL, pages, pd, + tb_invalidate_phys_page_range__locked(cpu, pages, pd, page_start, page_last, 0); } page_collection_unlock(pages); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index c007b9a190..9bf8728064 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -599,7 +599,7 @@ void tb_check_watchpoint(CPUState *cpu, uintptr_t retad= dr) cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); addr =3D get_page_addr_code(env, pc); if (addr !=3D -1) { - tb_invalidate_phys_range(addr, addr); + tb_invalidate_phys_range(cpu, addr, addr); } } } diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 39b76d9654..2b12c077e9 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -529,7 +529,7 @@ void page_set_flags(target_ulong start, target_ulong la= st, int flags) ~(reset ? 0 : PAGE_STICKY)); } if (inval_tb) { - tb_invalidate_phys_range(start, last); + tb_invalidate_phys_range(NULL, start, last); } } =20 @@ -1020,7 +1020,7 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, * be under mmap_lock() in order to prevent the creation of * another TranslationBlock in between. */ - tb_invalidate_phys_range(addr, addr + l - 1); + tb_invalidate_phys_range(NULL, addr, addr + l - 1); written =3D pwrite(fd, buf, l, (off_t)(uintptr_t)g2h_untagged(addr)); if (written !=3D l) { diff --git a/system/physmem.c b/system/physmem.c index 16cf557d1a..637f2d8532 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -2830,7 +2830,7 @@ static void invalidate_and_set_dirty(MemoryRegion *mr= , hwaddr addr, } if (dirty_log_mask & (1 << DIRTY_MEMORY_CODE)) { assert(tcg_enabled()); - tb_invalidate_phys_range(addr, addr + length - 1); + tb_invalidate_phys_range(NULL, addr, addr + length - 1); dirty_log_mask &=3D ~(1 << DIRTY_MEMORY_CODE); } cpu_physical_memory_set_dirty_range(addr, length, dirty_log_mask); diff --git a/target/arm/helper.c b/target/arm/helper.c index 7fb6e88630..c6fd290012 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4987,7 +4987,7 @@ static void ic_ivau_write(CPUARMState *env, const ARM= CPRegInfo *ri, =20 mmap_lock(); =20 - tb_invalidate_phys_range(start_address, end_address); + tb_invalidate_phys_range(env_cpu(env), start_address, end_address); =20 mmap_unlock(); } --=20 2.43.0 From nobody Sat Nov 15 22:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; 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Thu, 01 May 2025 14:21:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 06/59] accel/tcg: Add CPUState arg to tb_invalidate_phys_range_fast Date: Thu, 1 May 2025 14:20:20 -0700 Message-ID: <20250501212113.2961531-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746134646548124100 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/tb-internal.h | 5 ++--- accel/tcg/cputlb.c | 2 +- accel/tcg/tb-maint.c | 4 ++-- 3 files changed, 5 insertions(+), 6 deletions(-) diff --git a/accel/tcg/tb-internal.h b/accel/tcg/tb-internal.h index 1078de6c99..40439f03c3 100644 --- a/accel/tcg/tb-internal.h +++ b/accel/tcg/tb-internal.h @@ -45,9 +45,8 @@ void tb_unlock_pages(TranslationBlock *); #endif =20 #ifdef CONFIG_SOFTMMU -void tb_invalidate_phys_range_fast(ram_addr_t ram_addr, - unsigned size, - uintptr_t retaddr); +void tb_invalidate_phys_range_fast(CPUState *cpu, ram_addr_t ram_addr, + unsigned size, uintptr_t retaddr); #endif /* CONFIG_SOFTMMU */ =20 bool tb_invalidate_phys_page_unwind(CPUState *cpu, tb_page_addr_t addr, diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index d9fb68d719..ed6de1e96e 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1340,7 +1340,7 @@ static void notdirty_write(CPUState *cpu, vaddr mem_v= addr, unsigned size, trace_memory_notdirty_write_access(mem_vaddr, ram_addr, size); =20 if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) { - tb_invalidate_phys_range_fast(ram_addr, size, retaddr); + tb_invalidate_phys_range_fast(cpu, ram_addr, size, retaddr); } =20 /* diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c index c7600fc6ac..3837f2f633 100644 --- a/accel/tcg/tb-maint.c +++ b/accel/tcg/tb-maint.c @@ -1210,7 +1210,7 @@ void tb_invalidate_phys_range(CPUState *cpu, tb_page_= addr_t start, * Called via softmmu_template.h when code areas are written to with * iothread mutex not held. */ -void tb_invalidate_phys_range_fast(ram_addr_t start, +void tb_invalidate_phys_range_fast(CPUState *cpu, ram_addr_t start, unsigned len, uintptr_t ra) { PageDesc *p =3D page_find(start >> TARGET_PAGE_BITS); @@ -1219,7 +1219,7 @@ void tb_invalidate_phys_range_fast(ram_addr_t start, ram_addr_t last =3D start + len - 1; struct page_collection *pages =3D page_collection_lock(start, last= ); =20 - tb_invalidate_phys_page_range__locked(NULL, pages, p, + tb_invalidate_phys_page_range__locked(cpu, pages, p, start, last, ra); page_collection_unlock(pages); } --=20 2.43.0 From nobody Sat Nov 15 22:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746134622; cv=none; d=zohomail.com; s=zohoarc; b=AfBJxVwy5qwJ3Lh8uVCXV8C7v4r3KWNEWF6NVT8PhvWZ2IJhFeWeYHSEbRdoumyV1mw4FKohLik7n/710hU0dVwwvSd1wWpKdC2Bt9Mh9/q8Jfc4/vjenTSKrPcdnx28lYtQVqBAd/GjWa+MZVztubqqJkvJc4H6lGVEaZFyl0Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-30a476267e0sm1384573a91.39.2025.05.01.14.21.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 May 2025 14:21:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746134480; x=1746739280; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=R2E1hfpliYVCoOknCNn0LcMZgg8JjxDs88h3i9lSDC4=; b=QFAYL8+duN8OCY+JgscbGSZKK8r0O4Fn+oo857aTkZUW6ydwymZDCuGVF2gRspOcyg iLO2+ls+uJmyOISjFUFqnBPm7Ok3Rlpa9CCm3chau9x+Vnn2QwORcU78hQPvKW+4/ZuD j2V43+RHUCHijU/CZJDKy0ALnPPafHfBjD957KQrZnHcyuYtBPJJEStkrfibIskQfaAZ /51nrVkuiTxDt9C6l0XvmhRmwuaZgu98Psad9cUFDwn/BWD+1ACEOHryDG+zJgwu4QIY jLej56X6EwgJ7HSGeP3f98hG1SgndHokT1plXXo6ecAdUnyV8//4eSupnY/uhiVgVdMe XZhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746134480; x=1746739280; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=R2E1hfpliYVCoOknCNn0LcMZgg8JjxDs88h3i9lSDC4=; b=abpvWCzrWkzZOYxxZbMMg8/AXxkEA5PqRPbt7ZYzioN6ZEBEBo2OloUtNUNBOeMyNt gptTsSpCpAaj/oMa0O98oh5FAYkxEnJFjNU3HZeFhZDrUnqN2xRjwfzotONBg6BrA1ax NaJQx8ZmG7a2P94U3ppZFG0x8H4naVZRMJYuog0SKJrqHNbTz+bYay+zVi/C9LEYJ7AW rhHZPNFh3dPSnPthqhINu2larq9aoL9TN/Y/Vnhg/Meoq8yvBH2b33YHKmJ7zJL8ZIHy Tkw/sdGByAZ+Fw/O/qzJ3mKUTiY+TkOFeLdGTR0YzYfqN6S6k2bwLupx3f+89VY2pHnz K8GA== X-Gm-Message-State: AOJu0YxUarkr2tJh4WCHmhVOgmQZ2SPbBp2O7BuF79n8FHco0A8PaNi1 8si1PU2lvGGi1Zg8XLlLrR0t11TY2uPyy8V6NE58igg5Kz91hY4jF2s/BfW0xXASZWhc9U1S8lp / X-Gm-Gg: ASbGncswVIFHGHBoFHOuzn43KZbxngWN+/xv/kAiR6NKn+ufe/q7g39e5nENiJHpo2W qA4YoieZp88Hgxt7/+c4tB6QWLF6OKM/6nbstbshhcK0OoIVZtNqOg5rnvpZoXq4APXdwuOS8sA lrzd9wDqI8Jd1ihiBblIrv71hK75o/0DJ/E22Ur6zpvdlIRPMmb93bTDdTyknIa+eEF+g5jmSPd nb+DUkvAj9JEhu/Ys3Vnns/MUDaObtvmZMzziQib0Ih02g/ny1f8oi5ELOtzCTSdIGpjCSYzGPR Ng8DgX4qdUckbnkUwESoMR3Mb5WX1D79amzuyd700iJegdkphrt5PFWxzV34pI/tYuamTxVpucj hM6k9QfKLcQ== X-Google-Smtp-Source: AGHT+IEsLXT8TaBR+a0XNgNezqBEbQtTCmmF1nDYnHzIQZYLFQoziEz8vp3wPGbG+KLEaGZnnZr7fw== X-Received: by 2002:a17:90a:f944:b0:2ff:6aa6:47a3 with SMTP id 98e67ed59e1d1-30a4e686b6amr843643a91.25.1746134480293; Thu, 01 May 2025 14:21:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 07/59] accel/tcg: Convert TARGET_HAS_PRECISE_SMC to TCGCPUOps.precise_smc Date: Thu, 1 May 2025 14:20:21 -0700 Message-ID: <20250501212113.2961531-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746134624476124100 Instead of having a compile-time TARGET_HAS_PRECISE_SMC definition, have each target set the 'precise_smc' field in the TCGCPUOps structure. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/accel/tcg/cpu-ops.h | 7 +++++++ include/exec/poison.h | 1 - target/i386/cpu.h | 4 ---- target/s390x/cpu.h | 2 -- accel/tcg/tb-maint.c | 32 +++++++++++++------------------- accel/tcg/user-exec.c | 10 +++++----- target/i386/tcg/tcg-cpu.c | 1 + target/s390x/cpu.c | 1 + 8 files changed, 27 insertions(+), 31 deletions(-) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index 0e4352513d..60b5e97205 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -28,6 +28,13 @@ struct TCGCPUOps { */ bool mttcg_supported; =20 + /** + * @precise_smc: Stores which modify code within the current TB force + * the TB to exit; the next executed instruction will see + * the result of the store. + */ + bool precise_smc; + /** * @guest_default_memory_order: default barrier that is required * for the guest memory ordering. diff --git a/include/exec/poison.h b/include/exec/poison.h index bc422719d8..a779adbb7a 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -37,7 +37,6 @@ #pragma GCC poison TARGET_NAME #pragma GCC poison TARGET_BIG_ENDIAN #pragma GCC poison TCG_GUEST_DEFAULT_MO -#pragma GCC poison TARGET_HAS_PRECISE_SMC =20 #pragma GCC poison TARGET_LONG_BITS #pragma GCC poison TARGET_FMT_lx diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 54bf9639f1..3182ba413b 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -35,10 +35,6 @@ =20 #define XEN_NR_VIRQS 24 =20 -/* support for self modifying code even if the modified instruction is - close to the modifying instruction */ -#define TARGET_HAS_PRECISE_SMC - #ifdef TARGET_X86_64 #define I386_ELF_MACHINE EM_X86_64 #define ELF_MACHINE_UNAME "x86_64" diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index d9ca2506e2..530d97ccf1 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -35,8 +35,6 @@ =20 #define ELF_MACHINE_UNAME "S390X" =20 -#define TARGET_HAS_PRECISE_SMC - #define MMU_USER_IDX 0 =20 #define S390_MAX_CPUS 248 diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c index 3837f2f633..1596767879 100644 --- a/accel/tcg/tb-maint.c +++ b/accel/tcg/tb-maint.c @@ -28,6 +28,7 @@ #include "exec/mmap-lock.h" #include "exec/tb-flush.h" #include "exec/target_page.h" +#include "accel/tcg/cpu-ops.h" #include "tb-internal.h" #include "system/tcg.h" #include "tcg/tcg.h" @@ -1042,9 +1043,7 @@ static void tb_invalidate_phys_page(tb_page_addr_t ad= dr) /* * Called with mmap_lock held. If pc is not 0 then it indicates the * host PC of the faulting store instruction that caused this invalidate. - * Returns true if the caller needs to abort execution of the current - * TB (because it was modified by this store and the guest CPU has - * precise-SMC semantics). + * Returns true if the caller needs to abort execution of the current TB. */ bool tb_invalidate_phys_page_unwind(CPUState *cpu, tb_page_addr_t addr, uintptr_t pc) @@ -1059,10 +1058,7 @@ bool tb_invalidate_phys_page_unwind(CPUState *cpu, t= b_page_addr_t addr, * Without precise smc semantics, or when outside of a TB, * we can skip to invalidate. */ -#ifndef TARGET_HAS_PRECISE_SMC - pc =3D 0; -#endif - if (!pc) { + if (!pc || !cpu || !cpu->cc->tcg_ops->precise_smc) { tb_invalidate_phys_page(addr); return false; } @@ -1113,14 +1109,16 @@ tb_invalidate_phys_page_range__locked(CPUState *cpu, { TranslationBlock *tb; PageForEachNext n; -#ifdef TARGET_HAS_PRECISE_SMC bool current_tb_modified =3D false; - TranslationBlock *current_tb =3D retaddr ? tcg_tb_lookup(retaddr) : NU= LL; -#endif /* TARGET_HAS_PRECISE_SMC */ + TranslationBlock *current_tb =3D NULL; =20 /* Range may not cross a page. */ tcg_debug_assert(((start ^ last) & TARGET_PAGE_MASK) =3D=3D 0); =20 + if (retaddr && cpu && cpu->cc->tcg_ops->precise_smc) { + current_tb =3D tcg_tb_lookup(retaddr); + } + /* * We remove all the TBs in the range [start, last]. * XXX: see if in some cases it could be faster to invalidate all the = code @@ -1138,8 +1136,7 @@ tb_invalidate_phys_page_range__locked(CPUState *cpu, tb_last =3D tb_start + (tb_last & ~TARGET_PAGE_MASK); } if (!(tb_last < start || tb_start > last)) { -#ifdef TARGET_HAS_PRECISE_SMC - if (current_tb =3D=3D tb && + if (unlikely(current_tb =3D=3D tb) && (tb_cflags(current_tb) & CF_COUNT_MASK) !=3D 1) { /* * If we are modifying the current TB, we must stop @@ -1149,9 +1146,8 @@ tb_invalidate_phys_page_range__locked(CPUState *cpu, * restore the CPU state. */ current_tb_modified =3D true; - cpu_restore_state_from_tb(current_cpu, current_tb, retaddr= ); + cpu_restore_state_from_tb(cpu, current_tb, retaddr); } -#endif /* TARGET_HAS_PRECISE_SMC */ tb_phys_invalidate__locked(tb); } } @@ -1161,15 +1157,13 @@ tb_invalidate_phys_page_range__locked(CPUState *cpu, tlb_unprotect_code(start); } =20 -#ifdef TARGET_HAS_PRECISE_SMC - if (current_tb_modified) { + if (unlikely(current_tb_modified)) { page_collection_unlock(pages); /* Force execution of one insn next time. */ - current_cpu->cflags_next_tb =3D 1 | CF_NOIRQ | curr_cflags(current= _cpu); + cpu->cflags_next_tb =3D 1 | CF_NOIRQ | curr_cflags(cpu); mmap_unlock(); - cpu_loop_exit_noexc(current_cpu); + cpu_loop_exit_noexc(cpu); } -#endif } =20 /* diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 2b12c077e9..112292b729 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -733,12 +733,12 @@ int page_unprotect(CPUState *cpu, tb_page_addr_t addr= ess, uintptr_t pc) * this thread raced with another one which got here first and * set the page to PAGE_WRITE and did the TB invalidate for us. */ -#ifdef TARGET_HAS_PRECISE_SMC - TranslationBlock *current_tb =3D tcg_tb_lookup(pc); - if (current_tb) { - current_tb_invalidated =3D tb_cflags(current_tb) & CF_INVALID; + if (pc && cpu->cc->tcg_ops->precise_smc) { + TranslationBlock *current_tb =3D tcg_tb_lookup(pc); + if (current_tb) { + current_tb_invalidated =3D tb_cflags(current_tb) & CF_INVA= LID; + } } -#endif } else { int host_page_size =3D qemu_real_host_page_size(); target_ulong start, len, i; diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index e53aaa31bf..192812656c 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -126,6 +126,7 @@ static bool x86_debug_check_breakpoint(CPUState *cs) =20 const TCGCPUOps x86_tcg_ops =3D { .mttcg_supported =3D true, + .precise_smc =3D true, /* * The x86 has a strong memory model with some store-after-load re-ord= ering */ diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 3d644f5e23..99ff58affc 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -346,6 +346,7 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, =20 static const TCGCPUOps s390_tcg_ops =3D { .mttcg_supported =3D true, + .precise_smc =3D true, /* * The z/Architecture has a strong memory model with some * store-after-load re-ordering. --=20 2.43.0 From nobody Sat Nov 15 22:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-30a476267e0sm1384573a91.39.2025.05.01.14.21.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 May 2025 14:21:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746134481; x=1746739281; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=q8/gUh8ns0OI2KXninhYbAotAkB5LmkpT0e10M7S7xU=; b=j5b+3fwd04ZHbMTDfk3PN043Sy5sg2QsmP8B8Ut01UTXJOjj4nTIohVhKhaqBVCTXV sCy91v347pSmFV8p5B4VcCad+IrR8PYKTG0yX6ncGyHIfm2lF78gizTLJqornb0mq793 QasifpzfRk0ZQ6DJBeIpLrndyJGmKVo+fR78b6gMAMAPFSGmJUK7ap5s2KR0mM3GSm0b QYScUR7KB46g3m5n/YXJQGzzDiOmn4Ng0ZiGj9o+En07SjJfCdzmRQ5+BobtZ8L+pBuC CAFAZboASXth+3TQrxzUfrSVHFHVLFbh4vQ7RFfH1rpec+07PxIfkj23zhustn6qXhsg nFPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746134481; x=1746739281; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=q8/gUh8ns0OI2KXninhYbAotAkB5LmkpT0e10M7S7xU=; b=Cr1XcR1sLjakX28qWMIqt8dwMf1nhL8RTv749GPX6FDp5unNYuw+BVVZG6fvI9meh2 Vm+pvZjR/m5D9qy3PLwi5/M64MqT4F66+k4u88Y8GNx9WT5RGRXUkr4LjvmAhTAUe93F 1eprCFF20fxPxjQCe9k//Jxa8MiKOqxBvpw/NlGW2/isOm3hgo48LSQAtm6CifhA8xUD oDn3z4vb4nBRJCMqN/x7BhgrK03lGfVT536TxWhxOmDyJltyAP0OOZKbz0QMRJyVUjwJ KN7iiZq0KOW9jqsGWUd2b6ab3+SarxwkKSnnZhAhlCNphbxFRNHytaWFu817ShaXnvgM 2CMQ== X-Gm-Message-State: AOJu0YyIEaHxoD00Ois7VsDMzA2dhR0tTpakk6pdFoDuk3hZeNpeG/Fi MQVem64OkE3CprWSeHunaJyYMTZZNQNYCvxKnPG0BRNMM6iZxc7avVFg263waKxE+aGfYHxthII q X-Gm-Gg: ASbGncuV8cnalNNi0H6tYD7TCzcT9f8XqU+2z7UEfsy3owa5gcPHOVgm5QGOm1wSOFY 2M7cLcOVc/VhZtRWQ7YBQT8OqfDxGCPVa2yzfUKU8RYOZjlt8hoLU/n2iBX4TNYIrHBMy++PRxD t0Z93CongBf5hsQ8R4stqduZ1ihwShDpCwg3rQ4O1hIJ8xNx4n2IsWrcMR55vfGZ+irY37BD5wA brMnsBHYy1gyZ+HJPLVA/A8Hgw5K/y3+og7whewcPRCI4X9KgBtKeWEZFkE5L97H8qRCXpPjVnH TYszC8fOtscKpnvDT2ytLjsJG6FwwLojJMAWOKdOwRIMgqUmLFNPTO8nUtpC0cYKGp3QImFadZQ = X-Google-Smtp-Source: AGHT+IFFSRRRp9YOiVdtJA9S8k8T64pH04xqkieXgILhhGjBcammyjlwsBFiBRd1ZqVlDpzgVgf2CQ== X-Received: by 2002:a17:90b:4e8e:b0:2ff:53ad:a0ec with SMTP id 98e67ed59e1d1-30a4e5d58e3mr802224a91.21.1746134481210; Thu, 01 May 2025 14:21:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 08/59] accel/tcg: Simplify CPU_TLB_DYN_MAX_BITS Date: Thu, 1 May 2025 14:20:22 -0700 Message-ID: <20250501212113.2961531-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746135014773019100 Content-Type: text/plain; charset="utf-8" Stop taking TARGET_VIRT_ADDR_SPACE_BITS into account. Since we currently bound CPU_TLB_DYN_MAX_BITS to 22, the new bound with a 4k page size is 20, which isn't so different. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/tlb-bounds.h | 21 +-------------------- 1 file changed, 1 insertion(+), 20 deletions(-) diff --git a/accel/tcg/tlb-bounds.h b/accel/tcg/tlb-bounds.h index efd34d4793..f83d9ac9ee 100644 --- a/accel/tcg/tlb-bounds.h +++ b/accel/tcg/tlb-bounds.h @@ -7,26 +7,7 @@ #define ACCEL_TCG_TLB_BOUNDS_H =20 #define CPU_TLB_DYN_MIN_BITS 6 +#define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS) #define CPU_TLB_DYN_DEFAULT_BITS 8 =20 -# if HOST_LONG_BITS =3D=3D 32 -/* Make sure we do not require a double-word shift for the TLB load */ -# define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS) -# else /* HOST_LONG_BITS =3D=3D 64 */ -/* - * Assuming TARGET_PAGE_BITS=3D=3D12, with 2**22 entries we can cover 2**(= 22+12) =3D=3D - * 2**34 =3D=3D 16G of address space. This is roughly what one would expec= t a - * TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel - * Skylake's Level-2 STLB has 16 1G entries. - * Also, make sure we do not size the TLB past the guest's address space. - */ -# ifdef TARGET_PAGE_BITS_VARY -# define CPU_TLB_DYN_MAX_BITS \ - MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) -# else -# define CPU_TLB_DYN_MAX_BITS \ - MIN_CONST(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) -# endif -# endif - #endif /* ACCEL_TCG_TLB_BOUNDS_H */ --=20 2.43.0 From nobody Sat Nov 15 22:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746134700; cv=none; d=zohomail.com; s=zohoarc; b=kIhELumCxgC3swAExfTcGs4tjlOX4IJpeQgYwu68ykDljMF/9GsNUgxm+ggaFR4vmz5i7+uHgd0TN047q/qVWEzmjo7Cy+ZbjywHP6nLsCAi4a13Xjb9HcIvTUnL/UMXAkV+XEPZefeoNbI/XJ8nQodwTj7KS/yzfp1EwXg5Llk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746134700; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=AoLRODbSVmu/s22GYq49CkhKkoU0A0n4gJqgkN8qflI=; b=Y8U86erTirA2lU603fEeZUfbgmawdqQjA5oY5X+uGjuCvd/uRCrDICT2GXocMM3DutMQ7WPk6ijd/ojC/I1D8eC9XI+Hjhnz6NFMUj1Qc0WhaeMvWW97rSmJOoeKNu0TtYe0Eba+tjZ5f6cDgufs++D9sYqgffA+tI7JRp4tqpg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746134700547929.8802946861803; Thu, 1 May 2025 14:25:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAbLj-0000xT-FY; Thu, 01 May 2025 17:21:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAbLS-0000lU-GL for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:26 -0400 Received: from mail-pg1-x52f.google.com ([2607:f8b0:4864:20::52f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAbLP-0001SR-MU for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:25 -0400 Received: by mail-pg1-x52f.google.com with SMTP id 41be03b00d2f7-b0da25f5216so1008791a12.1 for ; Thu, 01 May 2025 14:21:23 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-30a476267e0sm1384573a91.39.2025.05.01.14.21.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 May 2025 14:21:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746134482; x=1746739282; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AoLRODbSVmu/s22GYq49CkhKkoU0A0n4gJqgkN8qflI=; b=e2XCnQ8hgEKkJCrlTrtDoVRqOV9rkXJe6TSEb5FMho4RuxB2Z2s/auRg91M83FHY1H eU0jRRbgGnBPLS13QrmSOIY+1sx/rDaerhzpmL7cmIpjL9ArXNBtBryDzMA/kCGM98pD KgaDEAJb8WLFJRV2sUYAs5InkyK3lbqMkwP73PmJqih9hITiS+OVY8V2PYR22WxYJ5an yaLOmD4cD46zfJp8IGak2KdboIUIniwSvLPQ9kBP2mIJodx2w/o4bE+XfYdcexvB83Cy LfrLwyT7QxJE7XdcUYGoPpZAode86BzSNnZoMOg/1QrW6b1HRe+pnas7hWsAyMUUDyyi YIzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746134482; x=1746739282; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AoLRODbSVmu/s22GYq49CkhKkoU0A0n4gJqgkN8qflI=; b=fkE2rmgOO6ppa2Blo4knEFBfU6iltVO9AOOda7YncFZHsIsXnBMuLjTwzHuoWy0F2r Sgm1jjbv/G4sIA3CQ52z/ki2H5qOggq5tFuSUOvDbUpPJEQnqC6ui9bf4AsNNbueI84H 7cgJdW6nQw4X5AJJ/YgJrW86NAHx9f9Qe74NrmYZQnn0FtT9qT/v+Mu44ltuvaZEz24G tV57eVN9s8MAhOGmKaJYxd1zNUq+1HTq8KkpO4zm7bufwKZRcs4m/X7gBIhFTtfeUqk+ zkHGNfZYjrbt4D0Py9EDDjPXggcE1OAl1e1ZAqjr9WPB71Mugl7AhgbJts5mNsN6PZP9 6mTw== X-Gm-Message-State: AOJu0YwcRt1HVvUkojGDvBQg5dpY/CwA4xsURuAbD2ngueUEliWs182+ tkw41WDTqrAQDKwQGHJF0abnRnE4KH91ToZPcOnoUF9uE9Iwu4B/NRboqssQlY4DwStS9HC0+Nj 7 X-Gm-Gg: ASbGncvwgcHtUjK/9TZGDPviltL7ZPCMZ2ztd12Mqk701hM70wj6hIwk3SfM5jqCR2Z HmAJKLXhIqstrHr+aHe6nzERoJuPw502G3JKnMAI/vH+RATOtmXrnSqX4R9M3KdcLIT28pVGeHn HltGoaKu9ob1qbClaVDzWVxsNmujjDPlzud5UkSmThaM8CPQuVMi4/Upnrc1y+kqlenjTtBR7Jp DtlJ0AE646mwuVF1jvb4mP07ZLy+YvmKICEueGjToLlw4tbsvsCnvSX5d5Sv59RAsvX1vMp5RE3 Xyzc20YOE7AQ/OShq8/sLQLNB2K+u+FGOD1haKpWmw5Bsq7gARya98XnOAcIMbR+kIcfiJqRBek = X-Google-Smtp-Source: AGHT+IHQQGP4Yl926oNf36EF9z3LcdFu3LiPPxqhsCMHmvc61KpyTh4RtkLaNE7i2BhiMUu7bn2x8Q== X-Received: by 2002:a17:90b:5704:b0:304:ec28:4437 with SMTP id 98e67ed59e1d1-30a4e6947a4mr687294a91.22.1746134482253; Thu, 01 May 2025 14:21:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 09/59] accel/tcg: Simplify L1_MAP_ADDR_SPACE_BITS Date: Thu, 1 May 2025 14:20:23 -0700 Message-ID: <20250501212113.2961531-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746134701228124100 Content-Type: text/plain; charset="utf-8" Stop taking TARGET_PHYS_ADDR_SPACE_BITS into account. Simply allow the entire ram_addr_t space. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/tb-maint.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c index 1596767879..13d0376bc7 100644 --- a/accel/tcg/tb-maint.c +++ b/accel/tcg/tb-maint.c @@ -160,11 +160,7 @@ static PageForEachNext foreach_tb_next(PageForEachNext= tb, /* * In system mode we want L1_MAP to be based on ram offsets. */ -#if HOST_LONG_BITS < TARGET_PHYS_ADDR_SPACE_BITS -# define L1_MAP_ADDR_SPACE_BITS HOST_LONG_BITS -#else -# define L1_MAP_ADDR_SPACE_BITS TARGET_PHYS_ADDR_SPACE_BITS -#endif +#define L1_MAP_ADDR_SPACE_BITS HOST_LONG_BITS =20 /* Size of the L2 (and L3, etc) page tables. */ #define V_L2_BITS 10 --=20 2.43.0 From nobody Sat Nov 15 22:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746135056; cv=none; d=zohomail.com; s=zohoarc; b=dG8hbTRYhCp43C8rxC+E3hsauCBlafhmCbIwD8wgvDC2eDm6AGXAlJ1Iq77VEQgesB2RU5lMg4yaIMBpn+KwEaLtspxzNES1j4VQeFqF979kxyZaAAAFNgd75evz7kPMUVEC+t+vF2oOx0yiWjMg6bk40QcTarzy5LV43QuXKyk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746135056; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=gx1D17kjC4RgXXRQvEjiHkImf6y4k2mPs3w7o5UMf50=; b=Gdvi5bf2SHzy5nVU4nQmVQDKv1SvcJ56jua8rb/8YRZObppti2a1Qb4cgxDiiSW9RiokAg/qY+JVXPnD7z14qWDuourdcIuWKdu3NFNmraETbWcc8/Y/6WxgIsU8WYsJsA9ymFc8yTIbpG1V/BdYH5C9Ou4M6qvDPtsgYyu0HT4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746135056947305.0204377560625; Thu, 1 May 2025 14:30:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAbLh-0000to-JF; Thu, 01 May 2025 17:21:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAbLU-0000m6-9r for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:28 -0400 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAbLS-0001Sf-4k for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:28 -0400 Received: by mail-pg1-x52d.google.com with SMTP id 41be03b00d2f7-af50f56b862so1014280a12.1 for ; Thu, 01 May 2025 14:21:24 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-30a476267e0sm1384573a91.39.2025.05.01.14.21.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 May 2025 14:21:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746134483; x=1746739283; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gx1D17kjC4RgXXRQvEjiHkImf6y4k2mPs3w7o5UMf50=; b=CYVrwFFozIX8Nq+vutC3d/tpm8WbeMDZITShY7NWpVDtkVxRquiZsTCSuJ6ODsKWpc +X9FGcEp1iWMesKpf6skXDgpYslVQCWLIs5vpZbr2Qostgnvm87gaTvy1T4pim4ugBfD xT/7XC4FlD8UGEsOjTxc+uA+VUdrqPaY+2Sblv3vuTV/obt36el4qeqPaVhyrbRySwWD wOHDR70gm3jeOgmYb2Cs8kcdCEdne71JrZYgQdGdW0HANp6nrTTD/lUsNqy2IdRfdDZo ZOlMH/Di9AOtj/Zm177TXT1dle7ZyPmbVcEA6drFUpoONskQrAvxsB/ML5w7DZ2xwnFa GCYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746134483; x=1746739283; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gx1D17kjC4RgXXRQvEjiHkImf6y4k2mPs3w7o5UMf50=; b=PPbonteN7S0ENupL1Y8n2ZlFEuot7RP/zZc8wBjLBmSYsBpRa3iRexndIq+wuFIqHC 8UGnOHml0y19WxxusZ8gBlyKyll9AVI2ztcATOS2i+QXCHroA6ThDNo3zeH/BnSXS5X6 KHS9dTRJDPswkSEPxTDjNRf9vaGRffW0nfZUs08lE/DIck+ouposdmZBIOUyuQWqj5Fj IXa/6y7hcqbHrwdFGiJZlCcv19wzh/KaK65MZ4gSUp7UKI1PefdGgPpvjoSenDSobsgI 2S/5mOLwMfdcDYL9oX98UTR3OHa5ESgvO+YUgh5FdemT+7vAVTCys3IUvdHZXU0l50I9 78AQ== X-Gm-Message-State: AOJu0YyXlZJXofkQSK8QfAiFTC31nOAHoxyBuMj9QeO2OsifGGvX5UDV ZWLP06TtrJ5lCooGSmQ3VX8jLZh4vqFgA1ONTIjqAMVWVnXlkkFoQ9c8IM5mupzBOKWZCre+1Tm o X-Gm-Gg: ASbGncvbP0ml9WIbYu2fO0drdWI3B99y7cphu0FENUjkLTF84YjQm2WM+vIozxh3dz9 6NwmSc7MH0r+D4xG+5rc/If96UXmzXSRLS4Brq1h49By4YvRBeJQ50y1Yr/pDtL+Kq2ZGXZsjX4 VHsxZyaCu3ddek8PNp+H5KKVkSTZgU3pTgJ3ngVtsFLDuEbGrtqRNYGBbJ+6wJ1CDPsKvdyHu7B Qp15gyJwC3ZopdRpamU1xwwAGDfJOAos12nkssKjWvPEtLPZgSPpC0fZyPX3zC97Ssy08QxgqIQ h0r1xT2QLtXoX6vK6yq2FcDiVozBWOTKVcr5GYBGhjVfpz8eaRDxdmZZ3aGqh6DORrXh0VF5Ya0 = X-Google-Smtp-Source: AGHT+IHzMMmbPcmEYqc+C1L/1QcPTWCILh+ZKKW26ZYnaOu92lhT6oqz00fruVW5HMPU8vPVrTsLig== X-Received: by 2002:a17:90b:2dd2:b0:301:c5cb:7b13 with SMTP id 98e67ed59e1d1-30a4e55f5c3mr829333a91.3.1746134483192; Thu, 01 May 2025 14:21:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 10/59] accel/tcg: Merge internal-target.h into internal-common.h Date: Thu, 1 May 2025 14:20:24 -0700 Message-ID: <20250501212113.2961531-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746135058630124100 There's nothing left in internal-target.h that is target specific. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/internal-common.h | 29 +++++++++++++++++++++++ accel/tcg/internal-target.h | 46 ------------------------------------- accel/tcg/cpu-exec.c | 1 - accel/tcg/cputlb.c | 1 - accel/tcg/tb-maint.c | 1 - accel/tcg/translate-all.c | 1 - accel/tcg/user-exec.c | 1 - 7 files changed, 29 insertions(+), 51 deletions(-) delete mode 100644 accel/tcg/internal-target.h diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h index 2f00560d10..573e8438c3 100644 --- a/accel/tcg/internal-common.h +++ b/accel/tcg/internal-common.h @@ -11,6 +11,7 @@ =20 #include "exec/cpu-common.h" #include "exec/translation-block.h" +#include "exec/mmap-lock.h" =20 extern int64_t max_delay; extern int64_t max_advance; @@ -108,4 +109,32 @@ static inline tb_page_addr_t get_page_addr_code(CPUArc= hState *env, return get_page_addr_code_hostp(env, addr, NULL); } =20 +/* + * Access to the various translations structures need to be serialised + * via locks for consistency. In user-mode emulation access to the + * memory related structures are protected with mmap_lock. + * In !user-mode we use per-page locks. + */ +#ifdef CONFIG_USER_ONLY +#define assert_memory_lock() tcg_debug_assert(have_mmap_lock()) +#else +#define assert_memory_lock() +#endif + +#if defined(CONFIG_SOFTMMU) && defined(CONFIG_DEBUG_TCG) +void assert_no_pages_locked(void); +#else +static inline void assert_no_pages_locked(void) { } +#endif + +#ifdef CONFIG_USER_ONLY +static inline void page_table_config_init(void) { } +#else +void page_table_config_init(void); +#endif + +#ifndef CONFIG_USER_ONLY +G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); +#endif /* CONFIG_USER_ONLY */ + #endif diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h deleted file mode 100644 index 9a9cef3140..0000000000 --- a/accel/tcg/internal-target.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Internal execution defines for qemu (target specific) - * - * Copyright (c) 2003 Fabrice Bellard - * - * SPDX-License-Identifier: LGPL-2.1-or-later - */ - -#ifndef ACCEL_TCG_INTERNAL_TARGET_H -#define ACCEL_TCG_INTERNAL_TARGET_H - -#include "cpu-param.h" -#include "exec/exec-all.h" -#include "exec/translation-block.h" -#include "tb-internal.h" -#include "exec/mmap-lock.h" - -/* - * Access to the various translations structures need to be serialised - * via locks for consistency. In user-mode emulation access to the - * memory related structures are protected with mmap_lock. - * In !user-mode we use per-page locks. - */ -#ifdef CONFIG_USER_ONLY -#define assert_memory_lock() tcg_debug_assert(have_mmap_lock()) -#else -#define assert_memory_lock() -#endif - -#if defined(CONFIG_SOFTMMU) && defined(CONFIG_DEBUG_TCG) -void assert_no_pages_locked(void); -#else -static inline void assert_no_pages_locked(void) { } -#endif - -#ifdef CONFIG_USER_ONLY -static inline void page_table_config_init(void) { } -#else -void page_table_config_init(void); -#endif - -#ifndef CONFIG_USER_ONLY -G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); -#endif /* CONFIG_USER_ONLY */ - -#endif /* ACCEL_TCG_INTERNAL_H */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 87eba83d7d..279df5fae7 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -46,7 +46,6 @@ #include "tb-context.h" #include "tb-internal.h" #include "internal-common.h" -#include "internal-target.h" =20 /* -icount align implementation. */ =20 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index ed6de1e96e..ca69128232 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -43,7 +43,6 @@ #include "tb-internal.h" #include "tlb-bounds.h" #include "internal-common.h" -#include "internal-target.h" #ifdef CONFIG_PLUGIN #include "qemu/plugin-memory.h" #endif diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c index 13d0376bc7..b144fcd4a0 100644 --- a/accel/tcg/tb-maint.c +++ b/accel/tcg/tb-maint.c @@ -36,7 +36,6 @@ #include "tb-context.h" #include "tb-internal.h" #include "internal-common.h" -#include "internal-target.h" #ifdef CONFIG_USER_ONLY #include "user/page-protection.h" #endif diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 9bf8728064..38819a507b 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -66,7 +66,6 @@ #include "tb-context.h" #include "tb-internal.h" #include "internal-common.h" -#include "internal-target.h" #include "tcg/perf.h" #include "tcg/insn-start-words.h" #include "cpu.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 112292b729..17e3be337f 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -39,7 +39,6 @@ #include "tcg/tcg-ldst.h" #include "backend-ldst.h" #include "internal-common.h" -#include "internal-target.h" #include "tb-internal.h" =20 __thread uintptr_t helper_retaddr; --=20 2.43.0 From nobody Sat Nov 15 22:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746134558; cv=none; d=zohomail.com; s=zohoarc; b=ZhS+tB3PnexPoSEcX7zZ9iIDYirH8kzYh3WK+sleauANa1AN4wCIu3PMMd2eQsQATHGakC4SbeQfz23NEVEjsWdjidfQpsTfuemFbLiGZhvA0kD3Jra7G2rcUxx+yzaCOwpCnkMWge6CMhN47b3N41WD6Qqg4T5N0Bfq3jMkcLE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746134558; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=rbjZFCK/gmi9dPEqR55ppH6qHZIOZcKl/Zq5hVKpWF4=; b=NCNh22/ShLXQ+dmMpM4e82vBQ11Js82Of1e/bxaLo1cnKDwji5/j0B2eIhC4edXJlzrsJ5EVqglu0doABIYUTMckb6gr4YoW07uHdyKOsPD/XM/gncx2o5occh/wwvKzcluacCafmZE/QfFDzQy00cYyYDlQpIRVHnw2nrV4VDk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746134558331273.04926342675594; Thu, 1 May 2025 14:22:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAbLn-00010t-6b; Thu, 01 May 2025 17:21:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAbLU-0000m5-5b for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:28 -0400 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAbLS-0001Sx-GM for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:27 -0400 Received: by mail-pj1-x1036.google.com with SMTP id 98e67ed59e1d1-30820167b47so1484239a91.0 for ; Thu, 01 May 2025 14:21:25 -0700 (PDT) Received: from stoup.. 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Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/internal-common.h | 3 +++ include/exec/exec-all.h | 2 -- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h index 573e8438c3..98c702422f 100644 --- a/accel/tcg/internal-common.h +++ b/accel/tcg/internal-common.h @@ -137,4 +137,7 @@ void page_table_config_init(void); G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); #endif /* CONFIG_USER_ONLY */ =20 +void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); +void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr); + #endif diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index bee3416e7e..24383b6aba 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -121,10 +121,8 @@ int probe_access_full_mmu(CPUArchState *env, vaddr add= r, int size, #endif /* CONFIG_TCG */ =20 /* TranslationBlock invalidate API */ -void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); void tb_invalidate_phys_range(CPUState *cpu, tb_page_addr_t start, tb_page_addr_t last); -void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr); =20 #if !defined(CONFIG_USER_ONLY) =20 --=20 2.43.0 From nobody Sat Nov 15 22:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746135053; cv=none; d=zohomail.com; s=zohoarc; b=US/pgAvib9TfcDiaA+dWnpl+PaflBwdPJueEI6tsqrOh59buOCteY4nflDA5JaUEXRMcN9kInSEzE5PpG5CWHPYCooaNo1leDxNQcjvcP5vwSHgv3hWN+jPIKaFyuNT4WXWnhNVNe55L5gfhOz10k7C0gCD+tTGJCczMYs8WGmA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746135053; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=2lQC8i/0dPaM85oLPPx0UiyxJ6AllGzTfuqWrQATKIE=; b=IBqiwEV4+FqXLoytHML7rbz/lG2sRHmZ8Iz8Wf+9K+rWGKB+XoGJg0c0jxVYpsYVItqS/HUtRDjSuVTTNc7omYss3u2gBw9RHuA/wSlQho7dYiaP9NRsFdmEGB8CWebSoBM2NZcscJWPtIM0f9keo22sZhbWZldAt/DMzxGIbkE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174613505359893.1964247034183; Thu, 1 May 2025 14:30:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAbLh-0000tO-C3; Thu, 01 May 2025 17:21:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAbLV-0000mM-Ng for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:31 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAbLS-0001T8-Go for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:29 -0400 Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-73712952e1cso1560318b3a.1 for ; Thu, 01 May 2025 14:21:25 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-30a476267e0sm1384573a91.39.2025.05.01.14.21.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 May 2025 14:21:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746134485; x=1746739285; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2lQC8i/0dPaM85oLPPx0UiyxJ6AllGzTfuqWrQATKIE=; b=ZIXxa2UhVjzbSCR5aebpby665XzQibuAU5s8DleGAVsWK3NbnBcNvzkGEvpcVsQe7f uSzMh+ch88KCccgxddg3nwjvsWlNNu27HmvMppZkD+qapAJkrxIR7z6NuvIRl8N5zySs ZZDyivJTk7DzTeReDjG2U+ahv2WzQmisBcvBhBYaJ6j7/lrx4adGPUnyL39QcS1WW5/k LOFY6mE91Cz03ZnXvVNxp2P0rWg6Rqr6ybvaYxtwtN4POcWIAKCgjlCvlsNy0c6V4hnj cpGuOGwbjYrKwQMHqPFb06I9X2qlarUsMV7Vensetv0rx7SIOhYlcsIfovKKP6nAq+wD KwSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746134485; x=1746739285; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2lQC8i/0dPaM85oLPPx0UiyxJ6AllGzTfuqWrQATKIE=; b=r+CoDhs2Y0PJvMrf/7ySAO4WPYxfM3O4HKFZcGE+ai7p8BMg4ATw7EE+3W4rcNwITR fgk3FL14W6l/4j0IYKKKiMKH4SI7l4GfzwMkXcbxSEz8UAgZC/rp/jyDMrPWxkArUx6j 7oFfH9WZkeWVTB+b9UCRohuM0GQZt39Cc4LuHmYdgbzNDXiMPsbrdbbGResOhxuQS1oR Oo0cS9hTR5ideh1WFlC9FBFnUbVNRSTohsjk/w/ZbGu4C9QBFxuJdxz9x+d15WRsZiR8 k7zRH2I4OxIVAMoLtgQUfPzzdnDl3uNKTLumez7uyuU1WEg4KkxP7ZaNQ4zatGH3wA+i lo5A== X-Gm-Message-State: AOJu0YwYMM0LtQn8eMrSaPcnIy3Z9DOIAD0n1f3//i6PNuycaJc7GT5j 8d20uEDTu6UT1jKc/E9XxQayEfCM1CGDn0x7GZG8/ih4yT96ZDkEdgMKgl+H2FWaZlj099m48Ep b X-Gm-Gg: ASbGnct9fPm1lMdZWBI/UjY1D3zGVhaxa/xK6jV3SCimzAA2GFMEARIy12qHlrkCr90 HQ7fMAG9FgTyScS37/2wRSCga46zCccctlUrn5Kb6vQb8bDqzaTpxKghCngIba3xZAd2CptVilz LDpO1Dh6MZYZqIX/WvkKPGkZxdfvc1z4munpf/2YYANDWxUXlPkLF3GcvvHYxt/3LiihRY5M7K6 uuVxjJLcF8du54vvCY/sP74GP7v2wdUTqD1Z+le+ySgPflCDYwZGSdjOrjEHk98i9HlY7fNg1zh ++xk0+l/hpdNQUhHvGlb8pLOyFwzoZXeAfpq4kSoRa2lnN5l+iDRmjNjRce+eD+66jWMW8Ub8E0 = X-Google-Smtp-Source: AGHT+IG+fXxqI3GbdBWum0Z+GAXHOm9OEuArLBSocM9lYZ5ZST9V6GT1TmZWu+ufn/1tgmocGiGnzA== X-Received: by 2002:a17:90b:2d50:b0:2fa:15ab:4df5 with SMTP id 98e67ed59e1d1-30a4e6b5788mr747383a91.34.1746134484854; Thu, 01 May 2025 14:21:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 12/59] accel/tcg: Use vaddr for walk_memory_regions callback Date: Thu, 1 May 2025 14:20:26 -0700 Message-ID: <20250501212113.2961531-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746135055029019100 Use vaddr instead of target_ulong. At the same time, use int instead of unsigned long for flags, to match page_set_flags(). Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/user/page-protection.h | 5 ++--- accel/tcg/user-exec.c | 10 +++++----- linux-user/elfload.c | 19 +++++++++---------- linux-user/syscall.c | 8 ++++---- 4 files changed, 20 insertions(+), 22 deletions(-) diff --git a/include/user/page-protection.h b/include/user/page-protection.h index 1de72e31e6..8f0b769b13 100644 --- a/include/user/page-protection.h +++ b/include/user/page-protection.h @@ -14,6 +14,7 @@ =20 #include "cpu-param.h" #include "exec/target_long.h" +#include "exec/vaddr.h" #include "exec/translation-block.h" =20 int page_unprotect(CPUState *cpu, tb_page_addr_t address, uintptr_t pc); @@ -88,9 +89,7 @@ target_ulong page_find_range_empty(target_ulong min, targ= et_ulong max, __attribute__((returns_nonnull)) void *page_get_target_data(target_ulong address); =20 -typedef int (*walk_memory_regions_fn)(void *, target_ulong, - target_ulong, unsigned long); - +typedef int (*walk_memory_regions_fn)(void *, vaddr, vaddr, int); int walk_memory_regions(void *, walk_memory_regions_fn); =20 void page_dump(FILE *f); diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 17e3be337f..25d86567e7 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -199,13 +199,13 @@ int walk_memory_regions(void *priv, walk_memory_regio= ns_fn fn) return rc; } =20 -static int dump_region(void *priv, target_ulong start, - target_ulong end, unsigned long prot) +static int dump_region(void *opaque, vaddr start, vaddr end, int prot) { - FILE *f =3D (FILE *)priv; + FILE *f =3D opaque; =20 - fprintf(f, TARGET_FMT_lx"-"TARGET_FMT_lx" "TARGET_FMT_lx" %c%c%c\n", - start, end, end - start, + fprintf(f, TARGET_ABI_FMT_ptr "-" TARGET_ABI_FMT_ptr + " " TARGET_ABI_FMT_ptr " %c%c%c\n", + (abi_ptr)start, (abi_ptr)end, (abi_ptr)(end - start), ((prot & PAGE_READ) ? 'r' : '-'), ((prot & PAGE_WRITE) ? 'w' : '-'), ((prot & PAGE_EXEC) ? 'x' : '-')); diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 87c6d3ab9f..82ebf6a212 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -4059,8 +4059,7 @@ static void bswap_note(struct elf_note *en) /* * Calculate file (dump) size of given memory region. */ -static size_t vma_dump_size(target_ulong start, target_ulong end, - unsigned long flags) +static size_t vma_dump_size(vaddr start, vaddr end, int flags) { /* The area must be readable. */ if (!(flags & PAGE_READ)) { @@ -4253,8 +4252,8 @@ static int dump_write(int fd, const void *ptr, size_t= size) return (0); } =20 -static int wmr_page_unprotect_regions(void *opaque, target_ulong start, - target_ulong end, unsigned long flag= s) +static int wmr_page_unprotect_regions(void *opaque, vaddr start, + vaddr end, int flags) { if ((flags & (PAGE_WRITE | PAGE_WRITE_ORG)) =3D=3D PAGE_WRITE_ORG) { size_t step =3D MAX(TARGET_PAGE_SIZE, qemu_real_host_page_size()); @@ -4275,8 +4274,8 @@ typedef struct { size_t size; } CountAndSizeRegions; =20 -static int wmr_count_and_size_regions(void *opaque, target_ulong start, - target_ulong end, unsigned long flag= s) +static int wmr_count_and_size_regions(void *opaque, vaddr start, + vaddr end, int flags) { CountAndSizeRegions *css =3D opaque; =20 @@ -4290,8 +4289,8 @@ typedef struct { off_t offset; } FillRegionPhdr; =20 -static int wmr_fill_region_phdr(void *opaque, target_ulong start, - target_ulong end, unsigned long flags) +static int wmr_fill_region_phdr(void *opaque, vaddr start, + vaddr end, int flags) { FillRegionPhdr *d =3D opaque; struct elf_phdr *phdr =3D d->phdr; @@ -4313,8 +4312,8 @@ static int wmr_fill_region_phdr(void *opaque, target_= ulong start, return 0; } =20 -static int wmr_write_region(void *opaque, target_ulong start, - target_ulong end, unsigned long flags) +static int wmr_write_region(void *opaque, vaddr start, + vaddr end, int flags) { int fd =3D *(int *)opaque; size_t size =3D vma_dump_size(start, end, flags); diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 5826ac3adb..23b901b713 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -8135,8 +8135,8 @@ static void open_self_maps_4(const struct open_self_m= aps_data *d, * Callback for walk_memory_regions, when read_self_maps() fails. * Proceed without the benefit of host /proc/self/maps cross-check. */ -static int open_self_maps_3(void *opaque, target_ulong guest_start, - target_ulong guest_end, unsigned long flags) +static int open_self_maps_3(void *opaque, vaddr guest_start, + vaddr guest_end, int flags) { static const MapInfo mi =3D { .is_priv =3D true }; =20 @@ -8147,8 +8147,8 @@ static int open_self_maps_3(void *opaque, target_ulon= g guest_start, /* * Callback for walk_memory_regions, when read_self_maps() succeeds. */ -static int open_self_maps_2(void *opaque, target_ulong guest_start, - target_ulong guest_end, unsigned long flags) +static int open_self_maps_2(void *opaque, vaddr guest_start, + vaddr guest_end, int flags) { const struct open_self_maps_data *d =3D opaque; uintptr_t host_start =3D (uintptr_t)g2h_untagged(guest_start); --=20 2.43.0 From nobody Sat Nov 15 22:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746134831; cv=none; d=zohomail.com; s=zohoarc; b=EJs7VoBnMRYNI5+8xoGN7RS8/rWbkn+4fUnREvpknFSy+/HWH1xKGcVCPbAigwA0fZjyCKdB69sTGYuS6MmAA02hkkKk0USFPw6iJGXEp+Enr1rnO2tQMzC2JcJRn4Gh8b6prVuGtAdkjS5+73+tICJHHt6p5XUI/HYd3PhmhnE= ARC-Message-Signature: i=1; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-30a476267e0sm1384573a91.39.2025.05.01.14.21.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 May 2025 14:21:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746134485; x=1746739285; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=entENXAMz1Bx+vUYaykE2T9Ny+7ZC4E3qmeTwzVtgpg=; b=io3RK1WZ0DG9qLe2Y3qCM+mD8IDZh/eZJ/gJ5mL91hM2bGjWtLgklBVRZZge39rT0W /V+tqw2STvvAfU/C6ZlvcSWrlXElTE8gB93gUOLYuLEUjRv3UUTAUtol/oMoEKE/m4mW 2lRV44IwUID8mAnmseONU5J26VpoPrRHko6Bb/GRmXRzmDe24sxqFs4FyRzr5nbtPVCS qhtJqjG2QNgBtJ+juRHdbusHb5hp5t+T2RfyKxBY3ZPzS3RuoYK7oaMyu9j44FwvG2Hx Jgh/o7yzrW1379066GHLYMPFcC+59j/KnV6pjSvEbZ5/92NnGait81QxbnbcutlXm+I/ V+qg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746134485; x=1746739285; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=entENXAMz1Bx+vUYaykE2T9Ny+7ZC4E3qmeTwzVtgpg=; b=hlruEHmTAe6kvPULy7NWqqANqqx1l39BGigW5a6IniM5v0yRdYA6ouas6m8dni21lT abLg/hUAJvV0QtSElmJiWjDE9/UhKJlp/N9EqOH6D4bkuvyZ1wYTLc+f2qzUByzOomZb ChUJkqkO6O2gHl25Nmj0xlYtc1xkzsJJ1s8Tm/wnuTYfmGBdPEIBLjHIHoXym/ptTuDv CjRWC0vTXkvRWKIlmhFLcusrON4oRLnsAdJi6nN/8lc+g2XD57K5SzsLYZVq+BOabjA4 zS40evzVPCvC+X71driH+C3Pj/RNR/+rdVHtYb0a/7cH6l6jx+2sjkKpu/6NKERFLQF6 b0Kg== X-Gm-Message-State: AOJu0Yxqz1Y+UgnoqaqEZNsvPk8sUae771wvoMoKApGlIcwsmLO1XjAG VmdQYXwkaHkDufruKOfmpex8NxiS+SsNq5CaHATRgp0zZ6E2LSY6OpuLJNfgq5dV0S07e7jvkle w X-Gm-Gg: ASbGncv+DcEZNRndYc50AhnshfBpoDQp94izvBCzBOEENrNj3kVlS2S/6YCQLxnypPs wBA/5cwL5xZH+6A2a42/up4DoWEQNK/6VvAQoqWVLMwNSoWwSCUELNgynEjFjqZYA+j25DZvWjr uQFKgEUaPnu8pZ4hoO0kh0d0SVGl2FpPPmNQw+TMGep+HZJnlts91DB6BlJIp2Z7CWb1rgiUbhw HnMN6KBLqMdIAjGiopL1jS1Jg5Yf3vlCWBT+khmjt5eMRcceGBTMtO00DfGoweAHFQRmfTuWkat nONGcw+laj4NPsbojtVGJzmxSElDlpOtp9poaWOfz44DMMyDepG8JFpXKXBzwGK/9McL8VldMrU = X-Google-Smtp-Source: AGHT+IG6pDk7y141meAgXBOXqpPkGsP394BkRfh8mzLQQqKMyvLK4nfKC+zH4WgQ2nmkwcj0oV0fsQ== X-Received: by 2002:a17:90b:3a10:b0:2f2:a664:df1a with SMTP id 98e67ed59e1d1-30a4e578b51mr963025a91.2.1746134485568; Thu, 01 May 2025 14:21:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson , Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 13/59] accel/tcg: Use vaddr in user/page-protection.h Date: Thu, 1 May 2025 14:20:27 -0700 Message-ID: <20250501212113.2961531-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746134834029124100 Reviewed-by: Anton Johansson Reviewed-by: Pierrick Bouvier Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/user/page-protection.h | 17 +++++------- accel/tcg/user-exec.c | 51 ++++++++++++++++------------------ 2 files changed, 31 insertions(+), 37 deletions(-) diff --git a/include/user/page-protection.h b/include/user/page-protection.h index 8f0b769b13..86143212fd 100644 --- a/include/user/page-protection.h +++ b/include/user/page-protection.h @@ -12,14 +12,12 @@ #error Cannot include this header from system emulation #endif =20 -#include "cpu-param.h" -#include "exec/target_long.h" #include "exec/vaddr.h" #include "exec/translation-block.h" =20 int page_unprotect(CPUState *cpu, tb_page_addr_t address, uintptr_t pc); =20 -int page_get_flags(target_ulong address); +int page_get_flags(vaddr address); =20 /** * page_set_flags: @@ -32,9 +30,9 @@ int page_get_flags(target_ulong address); * The flag PAGE_WRITE_ORG is positioned automatically depending * on PAGE_WRITE. The mmap_lock should already be held. */ -void page_set_flags(target_ulong start, target_ulong last, int flags); +void page_set_flags(vaddr start, vaddr last, int flags); =20 -void page_reset_target_data(target_ulong start, target_ulong last); +void page_reset_target_data(vaddr start, vaddr last); =20 /** * page_check_range @@ -46,7 +44,7 @@ void page_reset_target_data(target_ulong start, target_ul= ong last); * Return false if any page is unmapped. Thus testing flags =3D=3D 0 is * equivalent to testing for flags =3D=3D PAGE_VALID. */ -bool page_check_range(target_ulong start, target_ulong last, int flags); +bool page_check_range(vaddr start, vaddr last, int flags); =20 /** * page_check_range_empty: @@ -58,7 +56,7 @@ bool page_check_range(target_ulong start, target_ulong la= st, int flags); * The memory lock must be held so that the caller will can ensure * the result stays true until a new mapping can be installed. */ -bool page_check_range_empty(target_ulong start, target_ulong last); +bool page_check_range_empty(vaddr start, vaddr last); =20 /** * page_find_range_empty @@ -72,8 +70,7 @@ bool page_check_range_empty(target_ulong start, target_ul= ong last); * The memory lock must be held, as the caller will want to ensure * the returned range stays empty until a new mapping can be installed. */ -target_ulong page_find_range_empty(target_ulong min, target_ulong max, - target_ulong len, target_ulong align); +vaddr page_find_range_empty(vaddr min, vaddr max, vaddr len, vaddr align); =20 /** * page_get_target_data(address) @@ -87,7 +84,7 @@ target_ulong page_find_range_empty(target_ulong min, targ= et_ulong max, * e.g. with the munmap system call. */ __attribute__((returns_nonnull)) -void *page_get_target_data(target_ulong address); +void *page_get_target_data(vaddr address); =20 typedef int (*walk_memory_regions_fn)(void *, vaddr, vaddr, int); int walk_memory_regions(void *, walk_memory_regions_fn); diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 25d86567e7..43d005e24e 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -161,7 +161,7 @@ typedef struct PageFlagsNode { =20 static IntervalTreeRoot pageflags_root; =20 -static PageFlagsNode *pageflags_find(target_ulong start, target_ulong last) +static PageFlagsNode *pageflags_find(vaddr start, vaddr last) { IntervalTreeNode *n; =20 @@ -169,8 +169,7 @@ static PageFlagsNode *pageflags_find(target_ulong start= , target_ulong last) return n ? container_of(n, PageFlagsNode, itree) : NULL; } =20 -static PageFlagsNode *pageflags_next(PageFlagsNode *p, target_ulong start, - target_ulong last) +static PageFlagsNode *pageflags_next(PageFlagsNode *p, vaddr start, vaddr = last) { IntervalTreeNode *n; =20 @@ -215,14 +214,14 @@ static int dump_region(void *opaque, vaddr start, vad= dr end, int prot) /* dump memory mappings */ void page_dump(FILE *f) { - const int length =3D sizeof(target_ulong) * 2; + const int length =3D sizeof(abi_ptr) * 2; =20 fprintf(f, "%-*s %-*s %-*s %s\n", length, "start", length, "end", length, "size", "prot"); walk_memory_regions(f, dump_region); } =20 -int page_get_flags(target_ulong address) +int page_get_flags(vaddr address) { PageFlagsNode *p =3D pageflags_find(address, address); =20 @@ -245,7 +244,7 @@ int page_get_flags(target_ulong address) } =20 /* A subroutine of page_set_flags: insert a new node for [start,last]. */ -static void pageflags_create(target_ulong start, target_ulong last, int fl= ags) +static void pageflags_create(vaddr start, vaddr last, int flags) { PageFlagsNode *p =3D g_new(PageFlagsNode, 1); =20 @@ -256,13 +255,13 @@ static void pageflags_create(target_ulong start, targ= et_ulong last, int flags) } =20 /* A subroutine of page_set_flags: remove everything in [start,last]. */ -static bool pageflags_unset(target_ulong start, target_ulong last) +static bool pageflags_unset(vaddr start, vaddr last) { bool inval_tb =3D false; =20 while (true) { PageFlagsNode *p =3D pageflags_find(start, last); - target_ulong p_last; + vaddr p_last; =20 if (!p) { break; @@ -301,8 +300,7 @@ static bool pageflags_unset(target_ulong start, target_= ulong last) * A subroutine of page_set_flags: nothing overlaps [start,last], * but check adjacent mappings and maybe merge into a single range. */ -static void pageflags_create_merge(target_ulong start, target_ulong last, - int flags) +static void pageflags_create_merge(vaddr start, vaddr last, int flags) { PageFlagsNode *next =3D NULL, *prev =3D NULL; =20 @@ -353,11 +351,11 @@ static void pageflags_create_merge(target_ulong start= , target_ulong last, #define PAGE_STICKY (PAGE_ANON | PAGE_PASSTHROUGH | PAGE_TARGET_STICKY) =20 /* A subroutine of page_set_flags: add flags to [start,last]. */ -static bool pageflags_set_clear(target_ulong start, target_ulong last, +static bool pageflags_set_clear(vaddr start, vaddr last, int set_flags, int clear_flags) { PageFlagsNode *p; - target_ulong p_start, p_last; + vaddr p_start, p_last; int p_flags, merge_flags; bool inval_tb =3D false; =20 @@ -492,7 +490,7 @@ static bool pageflags_set_clear(target_ulong start, tar= get_ulong last, return inval_tb; } =20 -void page_set_flags(target_ulong start, target_ulong last, int flags) +void page_set_flags(vaddr start, vaddr last, int flags) { bool reset =3D false; bool inval_tb =3D false; @@ -532,9 +530,9 @@ void page_set_flags(target_ulong start, target_ulong la= st, int flags) } } =20 -bool page_check_range(target_ulong start, target_ulong len, int flags) +bool page_check_range(vaddr start, vaddr len, int flags) { - target_ulong last; + vaddr last; int locked; /* tri-state: =3D0: unlocked, +1: global, -1: local */ bool ret; =20 @@ -610,17 +608,16 @@ bool page_check_range(target_ulong start, target_ulon= g len, int flags) return ret; } =20 -bool page_check_range_empty(target_ulong start, target_ulong last) +bool page_check_range_empty(vaddr start, vaddr last) { assert(last >=3D start); assert_memory_lock(); return pageflags_find(start, last) =3D=3D NULL; } =20 -target_ulong page_find_range_empty(target_ulong min, target_ulong max, - target_ulong len, target_ulong align) +vaddr page_find_range_empty(vaddr min, vaddr max, vaddr len, vaddr align) { - target_ulong len_m1, align_m1; + vaddr len_m1, align_m1; =20 assert(min <=3D max); assert(max <=3D GUEST_ADDR_MAX); @@ -661,7 +658,7 @@ target_ulong page_find_range_empty(target_ulong min, ta= rget_ulong max, void tb_lock_page0(tb_page_addr_t address) { PageFlagsNode *p; - target_ulong start, last; + vaddr start, last; int host_page_size =3D qemu_real_host_page_size(); int prot; =20 @@ -740,7 +737,7 @@ int page_unprotect(CPUState *cpu, tb_page_addr_t addres= s, uintptr_t pc) } } else { int host_page_size =3D qemu_real_host_page_size(); - target_ulong start, len, i; + vaddr start, len, i; int prot; =20 if (host_page_size <=3D TARGET_PAGE_SIZE) { @@ -756,7 +753,7 @@ int page_unprotect(CPUState *cpu, tb_page_addr_t addres= s, uintptr_t pc) prot =3D 0; =20 for (i =3D 0; i < len; i +=3D TARGET_PAGE_SIZE) { - target_ulong addr =3D start + i; + vaddr addr =3D start + i; =20 p =3D pageflags_find(addr, addr); if (p) { @@ -883,7 +880,7 @@ typedef struct TargetPageDataNode { =20 static IntervalTreeRoot targetdata_root; =20 -void page_reset_target_data(target_ulong start, target_ulong last) +void page_reset_target_data(vaddr start, vaddr last) { IntervalTreeNode *n, *next; =20 @@ -897,7 +894,7 @@ void page_reset_target_data(target_ulong start, target_= ulong last) n !=3D NULL; n =3D next, next =3D next ? interval_tree_iter_next(n, start, last) : NULL) { - target_ulong n_start, n_last, p_ofs, p_len; + vaddr n_start, n_last, p_ofs, p_len; TargetPageDataNode *t =3D container_of(n, TargetPageDataNode, itre= e); =20 if (n->start >=3D start && n->last <=3D last) { @@ -921,11 +918,11 @@ void page_reset_target_data(target_ulong start, targe= t_ulong last) } } =20 -void *page_get_target_data(target_ulong address) +void *page_get_target_data(vaddr address) { IntervalTreeNode *n; TargetPageDataNode *t; - target_ulong page, region, p_ofs; + vaddr page, region, p_ofs; =20 page =3D address & TARGET_PAGE_MASK; region =3D address & TBD_MASK; @@ -956,7 +953,7 @@ void *page_get_target_data(target_ulong address) return t->data + p_ofs * TARGET_PAGE_DATA_SIZE; } #else -void page_reset_target_data(target_ulong start, target_ulong last) { } +void page_reset_target_data(vaddr start, vaddr last) { } #endif /* TARGET_PAGE_DATA_SIZE */ =20 /* The system-mode versions of these helpers are in cputlb.c. */ --=20 2.43.0 From nobody Sat Nov 15 22:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746134680; cv=none; d=zohomail.com; s=zohoarc; b=TVzIxLNem3xwHE9bF8w93Xo1sUV3t7BPXKrSRyJErRMEQlVaTkT0ZXOldkrQoWJDkwsVBrwFMmPHv1F9qlpsQkoj/n8A7yanzozBv7nx59o3DnAv4Y+/dAmWYp9lwA/ubkKdEQT/wLgtyvwvvxptp4GvGyUNpn+/Sq9IsFFcRp4= ARC-Message-Signature: i=1; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-30a476267e0sm1384573a91.39.2025.05.01.14.21.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 May 2025 14:21:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746134486; x=1746739286; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=27xaPxYDe2r5uVdVLgh1cUarR6C7vq0+H7FwQk1GTjM=; b=zhcQimxZlzqKdj7nJqieYs6AwvfgSo8b3MsvB0LXzO88HKBv9eNMtvfieFDEBjUUO8 n1DO5YpXS0Mdw48v+YT6ZjlQsgdKQ1V9Jk5ybZIjMgKtE5k7eJjUolT+sQ1Fb0w6X2er FXT3m96KfBycVlF0AnzfRAQoTwrBdv/m2LDY5eFvvFNOUDpuqGLvOS7MAvhRmQZgFNbF qcIfIhFACQ/dt8GVCTwyJzVjfdHodjxzPAHzTce3lFVNIZS6YyBceABzYyHjJImLfAuC ERgy5LOPylM2vjEC3wcwJhrYOtFPOySFrxvQLxNCjEfNlDON+MR2yD50Glifc6yKLW2a jpbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746134486; x=1746739286; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=27xaPxYDe2r5uVdVLgh1cUarR6C7vq0+H7FwQk1GTjM=; b=GwvtaHDYzobRDgIpEpBItsTkO2jUj72pe02ESO3ycnPv+tR0O9PzpnYBHYbrSBVMMe yGViBpLK6gL6dwiLoufBY4AAQ8p+7iAJXn4STTdMbdbPh/zUC36v04wb1HlDUK+6cw+R MU9/M4nQqLcVau+Wamx8JgbQsYU/ufO9jfqojctxINngHRQWfKqrBP47oClCoHmY4RSA bVpRlpztHgqgUtcruoYU8kIPpypx+C7bEnZSgIcB3b5irq2qVh3lbm0mde87Tzj0CUdr B85tcFxFH2QShakLke3OayR91HQAAKu3TnspoyZnbmjfsYgLYTmQxhYv39zhZB4cd5VP RtuQ== X-Gm-Message-State: AOJu0Yyhawb1wHf+ZEQCbw5mhVG6dcHTaTS9M8T8UejzkrrvmA6bA7Hk 0VxMj1rpMTAvfGwyAVo9k2zUcgksHhde2gm12TjdB36Tn+IjK/3FVPHAZxrj/BwwLJhn2dUANef S X-Gm-Gg: ASbGnctO0y23yx4I2fhVnd4A2betK88lhNa8/QyTUhFd0sdT+eWLrEns4eOiyKpbrFM 2V8w34rwoOVX7gyb1JpyTL1S2NAtthCX9WV7AX+xnLpa7gepAfZiqtIu30sYVSTmm04Qn+1xNZd XOOttkLetqFlw6d1RtBjaKR94Z5VBY48gmMIeigpucgmbybVX7i44XdaSeG3RPmaXyv8KlDF367 rfJT/yWmWh3OyJVg+BHE35GyjuFDHlCzIHG0OgqrsOgGOzD6lXBrgOlxmicbCk0mgojxTB9x8dh lBisl6OvPR+YWWN4MwHMx+AC/mL3l3UL28MMpT+2G6Y9G/JKqqh8YdshEIvDqywGy8I6/tH80tq O9C2n0SE0HQ== X-Google-Smtp-Source: AGHT+IHTBwW8JXdvNTThtYvmFCvWBmIesGGr0MhROZjkIRrhpyCSn349TNU9xSGD+PMDqVG5komrDQ== X-Received: by 2002:a17:90b:2711:b0:2ee:9d49:3ae6 with SMTP id 98e67ed59e1d1-30a4e5aa625mr1040633a91.10.1746134486180; Thu, 01 May 2025 14:21:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland Subject: [PULL 14/59] include/exec: Include missing headers in exec-all.h Date: Thu, 1 May 2025 14:20:28 -0700 Message-ID: <20250501212113.2961531-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746134683182019100 From: Philippe Mathieu-Daud=C3=A9 "exec/exec-all.h" declares prototypes such: void *probe_access(CPUArchState *env, vaddr addr, int size, ^^^^^ MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); MemoryRegionSection *iotlb_to_section(CPUState *cpu, hwaddr index, ^^^^^^ MemTxAttrs attrs); ^^^^^^^^^^ vaddr is defined in "exec/vaddr.h", hwaddr in "exec/hwaddr.h" and MemTxAttrs in "exec/memattrs.h". All these headers are indirectly pulled in via "exec/translation-block.h". Since we will remove "exec/translation-block.h" in the next commit, include the missing ones, otherwise we'd get errors such: include/exec/exec-all.h:51:1: error: unknown type name 'hwaddr' 51 | hwaddr memory_region_section_get_iotlb(CPUState *cpu, | ^ Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Mark Cave-Ayland Signed-off-by: Richard Henderson Message-ID: <20250424202412.91612-5-philmd@linaro.org> --- include/exec/exec-all.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 24383b6aba..c46255e66e 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -20,8 +20,11 @@ #ifndef EXEC_ALL_H #define EXEC_ALL_H =20 +#include "exec/hwaddr.h" +#include "exec/memattrs.h" #include "exec/mmu-access-type.h" #include "exec/translation-block.h" +#include "exec/vaddr.h" =20 #if defined(CONFIG_TCG) #include "accel/tcg/getpc.h" --=20 2.43.0 From nobody Sat Nov 15 22:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746134700; cv=none; d=zohomail.com; s=zohoarc; b=SOfxFwvnfooZHQRaijvykWlWE7ojIhnQj/p0x295IgBnwo9JNfqsKe29/mnsDlGttuQsB+bApaiwKRxopIs3IlNKEP+2LHsoYhlN5rovspW4nhCo9kQJGbm1qMFDaUifteEhWrOlJGjh5+NknpuBXHdr0JzdKX8G+Yy7YX9ARAQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746134700; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=JMzLjz3HCOicg6vm+TDd7iPOiB48OiFdPHl2bMcuo4E=; b=Y3/HctWvL+FoZjk4yNWH/0IQkMeegE0qy9s3EqR9EPt4XlZYZEfnoJEvr/9I2yt2mt3aZJAsiEYqf5L7eOS3ilO/EV98gLV8RuA3gRu4x8i8894ZNFOlvRaaEhNnkQcXifv81NRgjPLnuhjE+IOmRK7EIFHdeo1fX1/499LsjFA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746134700599779.4676320530722; Thu, 1 May 2025 14:25:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAbLk-0000yk-M0; Thu, 01 May 2025 17:21:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAbLV-0000mN-QA for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:31 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAbLU-0001Ta-6r for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:29 -0400 Received: by mail-pj1-x1033.google.com with SMTP id 98e67ed59e1d1-306bf444ba2so1319899a91.1 for ; Thu, 01 May 2025 14:21:27 -0700 (PDT) Received: from stoup.. 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Thu, 01 May 2025 14:21:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 15/59] include/exec: Move tb_invalidate_phys_range to translation-block.h Date: Thu, 1 May 2025 14:20:29 -0700 Message-ID: <20250501212113.2961531-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746134703081124100 Reviewed-by: Anton Johansson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 5 ----- include/exec/translation-block.h | 4 ++++ 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index c46255e66e..4c5ad98c6a 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -23,7 +23,6 @@ #include "exec/hwaddr.h" #include "exec/memattrs.h" #include "exec/mmu-access-type.h" -#include "exec/translation-block.h" #include "exec/vaddr.h" =20 #if defined(CONFIG_TCG) @@ -123,10 +122,6 @@ int probe_access_full_mmu(CPUArchState *env, vaddr add= r, int size, #endif /* !CONFIG_USER_ONLY */ #endif /* CONFIG_TCG */ =20 -/* TranslationBlock invalidate API */ -void tb_invalidate_phys_range(CPUState *cpu, tb_page_addr_t start, - tb_page_addr_t last); - #if !defined(CONFIG_USER_ONLY) =20 /** diff --git a/include/exec/translation-block.h b/include/exec/translation-bl= ock.h index 8b8e730561..cdce399eba 100644 --- a/include/exec/translation-block.h +++ b/include/exec/translation-block.h @@ -207,4 +207,8 @@ static inline void tb_set_page_addr1(TranslationBlock *= tb, #endif } =20 +/* TranslationBlock invalidate API */ +void tb_invalidate_phys_range(CPUState *cpu, tb_page_addr_t start, + tb_page_addr_t last); + #endif /* EXEC_TRANSLATION_BLOCK_H */ --=20 2.43.0 From nobody Sat Nov 15 22:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746134679; cv=none; d=zohomail.com; s=zohoarc; b=XcJ+FTH2tOcsr0AyKmsJvH/NJAz5B97XBmm6kqoNZ5DvXZhtQ8Yb8OHE0HKeRYUqgV03vXyhRvcOubjnUg7Fwm94YqDJJfw3ArC2nVT9UzXNbrorjfbYVPuVnr0MY18qWGMHERUCc6Nf96n3U7CuL1ggx4PBiVwpy23Y7dtrpy8= ARC-Message-Signature: i=1; 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Thu, 01 May 2025 14:21:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson , Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 16/59] accel/tcg: Compile tb-maint.c twice Date: Thu, 1 May 2025 14:20:30 -0700 Message-ID: <20250501212113.2961531-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746134682076019100 Reviewed-by: Anton Johansson Reviewed-by: Pierrick Bouvier Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- accel/tcg/tb-hash.h | 3 +-- accel/tcg/tb-maint.c | 2 -- accel/tcg/meson.build | 2 +- 3 files changed, 2 insertions(+), 5 deletions(-) diff --git a/accel/tcg/tb-hash.h b/accel/tcg/tb-hash.h index 3bc5042d9d..f7b159f04c 100644 --- a/accel/tcg/tb-hash.h +++ b/accel/tcg/tb-hash.h @@ -20,8 +20,7 @@ #ifndef EXEC_TB_HASH_H #define EXEC_TB_HASH_H =20 -#include "exec/cpu-defs.h" -#include "exec/exec-all.h" +#include "exec/vaddr.h" #include "exec/target_page.h" #include "exec/translation-block.h" #include "qemu/xxhash.h" diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c index b144fcd4a0..0048316f99 100644 --- a/accel/tcg/tb-maint.c +++ b/accel/tcg/tb-maint.c @@ -20,10 +20,8 @@ #include "qemu/osdep.h" #include "qemu/interval-tree.h" #include "qemu/qtree.h" -#include "cpu.h" #include "exec/cputlb.h" #include "exec/log.h" -#include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/mmap-lock.h" #include "exec/tb-flush.h" diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 047afa49a2..3f7b127130 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -8,6 +8,7 @@ tcg_ss.add(files( 'cpu-exec-common.c', 'tcg-runtime.c', 'tcg-runtime-gvec.c', + 'tb-maint.c', 'translator.c', )) if get_option('plugins') @@ -21,7 +22,6 @@ tcg_specific_ss =3D ss.source_set() tcg_specific_ss.add(files( 'tcg-all.c', 'cpu-exec.c', - 'tb-maint.c', 'translate-all.c', )) tcg_specific_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user-exec.c'= )) --=20 2.43.0 From nobody Sat Nov 15 22:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 01 May 2025 14:21:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 17/59] accel/tcg: Remove #error for non-tcg in getpc.h Date: Thu, 1 May 2025 14:20:31 -0700 Message-ID: <20250501212113.2961531-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746134931071124100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- include/accel/tcg/getpc.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/include/accel/tcg/getpc.h b/include/accel/tcg/getpc.h index 8a97ce34e7..0fc08addcf 100644 --- a/include/accel/tcg/getpc.h +++ b/include/accel/tcg/getpc.h @@ -8,10 +8,6 @@ #ifndef ACCEL_TCG_GETPC_H #define ACCEL_TCG_GETPC_H =20 -#ifndef CONFIG_TCG -#error Can only include this header with TCG -#endif - /* GETPC is the true target of the return instruction that we'll execute. = */ #ifdef CONFIG_TCG_INTERPRETER extern __thread uintptr_t tci_tb_ptr; --=20 2.43.0 From nobody Sat Nov 15 22:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746134637; cv=none; d=zohomail.com; s=zohoarc; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-30a476267e0sm1384573a91.39.2025.05.01.14.21.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 May 2025 14:21:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746134489; x=1746739289; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DY53sbbsfhMz/uL2ST/i1QboUtxsyltjh/Yn/CjASj8=; b=zSr6z3ZgFnlXh8HI4m9IBDNV/r4KxqA8O5zXa3NVDuGPu+vIgYz5KP3rrCFnouKewT uQvclVHqrnK2WAf4xm5zNQ+Sdv4HJX/QJTlxBxl7+PdM7LbvuvlBaqbAnNUjIjXO/UEr iM55yiqhuJWLsOTTw7FQSIj7ha0x6Axq4YfvGKIXLgdxsP+q7VWqYvjhtcnkjzEXYfvN G9j5kOBe9XunOS+RF5FK1teG0bFlyRi6mdlYo8ehi2XbmIMTbiwWntZtQP6uYhKfV5jz 7GK6t+zNGe6vQaJCBj47O15pSvrvfe73Wsm5jdndulWLSmFhdJCPsGSd3H9qzFDDbgv7 zjYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746134489; x=1746739289; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DY53sbbsfhMz/uL2ST/i1QboUtxsyltjh/Yn/CjASj8=; b=BOkVm4tKm4yRABXH27lr+A/W7fujYzE8S5iF5HlPsekrOYlQbHqkdRxxF1aCVaXQ1b CzSK8D85ysQM7NskCwzSziTP0VKYYny+zFgV0j+8bZtJruBlb0je0H94Us3TVd24Xbtw K86u2PxewKYuRj2A4IO3e1kRLu8I1gPODI1tb977fa0ZxhNe/hilW5bgnQ9OBQx4Qk+9 qCIGffvxeu46F4Gy3LRw5TPeQO8ZuIOpohhpXjZpzS5TKcP+G96rlAxvIxQOJDhHe1uP LAjrsLsrdPYqq8jnVGbli82N7hhmJQN37ObAU6dH+9DvS5XaBCfIAMbFoqfdzIHAf92n S0fg== X-Gm-Message-State: AOJu0YwYuuWkDa2MShyC7iyuL5VJFiKU5lCyKYkory476Z58HUVUP9Fu ivBuZqQQY7MBrHEjAGMv0o03VvwKtJfsW6Wkl40/wy1uQV6dwuKp0eCKOjs9NbxUUKuw6HM66YJ k X-Gm-Gg: ASbGnctNZdpEcIOBsf1AlBpZPiWUlJRl1PG/rRTSXNm351suboKx7rlNid4fXrcdJv6 xu/uYvnZcU/9xCotnXk/B3E/4BouIrbYSvwSMdKcxCnkekB6KVg7F/oTGMlry7Tod02hKJmFxUJ asF1BZ9mQCSkwqJ8N9gbxDMnwjrQlZXR2Fara5yNJJbHpvKYIVSyNKmOnKq8Pex3Ytu/aYxlxsh GTOPQHi8AwL44DKAXVF5dNFCTPiiWiKcneMPGL0xsZASFSlNrYhD2GbEQveCjg8va3jKkcJuTEV FORESXHws0mHWab0JAxSnFvpBncrKq1AtjcbticarFyyHdti7Are8np75Mhc8mhlSOhZmdz9W84 = X-Google-Smtp-Source: AGHT+IG0FVDesoCK7QnxxAAPn4ziz+8441rVXpGhO8e2XogoFFYBqGakFSFdnx3u3IDUzMD3ljWJUg== X-Received: by 2002:a17:90b:534d:b0:30a:4ce4:5287 with SMTP id 98e67ed59e1d1-30a4e42faa9mr1220926a91.0.1746134489626; Thu, 01 May 2025 14:21:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland , Alistair Francis Subject: [PULL 18/59] target/riscv: Include missing 'accel/tcg/getpc.h' in csr.c Date: Thu, 1 May 2025 14:20:32 -0700 Message-ID: <20250501212113.2961531-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746134639625019100 From: Philippe Mathieu-Daud=C3=A9 "accel/tcg/getpc.h" is pulled in indirectly. Include it explicitly to avoid when refactoring unrelated headers: target/riscv/csr.c:2117:25: error: call to undeclared function 'GETPC' [-= Wimplicit-function-declaration] 2117 | if ((val & RVC) && (GETPC() & ~3) !=3D 0) { | ^ Note the TODO comment around GETPC() added upon introduction in commit f18637cd611 ("RISC-V: Add misa runtime write support"): 2099 static RISCVException write_misa(CPURISCVState *env, int csrno, 2100 target_ulong val) 2101 { ... 2113 /* 2114 * Suppress 'C' if next instruction is not aligned 2115 * TODO: this should check next_pc 2116 */ 2117 if ((val & RVC) && (GETPC() & ~3) !=3D 0) { 2118 val &=3D ~RVC; 2119 } Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Mark Cave-Ayland Acked-by: Alistair Francis Signed-off-by: Richard Henderson Message-ID: <20250424202412.91612-8-philmd@linaro.org> --- target/riscv/csr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c52c87faae..1308643855 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -28,6 +28,7 @@ #include "exec/cputlb.h" #include "exec/tb-flush.h" #include "exec/icount.h" +#include "accel/tcg/getpc.h" #include "qemu/guest-random.h" #include "qapi/error.h" #include --=20 2.43.0 From nobody Sat Nov 15 22:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746134744; cv=none; d=zohomail.com; s=zohoarc; b=UDIjoBZlbd91lpc4aFS/po/wvr2iGsM6aNxtjLdoyTfE+58ZbxiWY5a8V8Kdo9yPOHNALOElCWEY5jkMsepml6M5tRfYeN3432DAxiGojsRQJoU86oA2/0bnzMsCztOTkSB8punprIbBck34E4TUxcEguzDnj/xsJc7D37QrCGY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746134744; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=3IM3WNY4+mvaPjMT/1TSQTeg+RIG05hYdcLT8hVpAu0=; b=eUWyN4WH//pQirCBVA/tZESI0kK0861KO9K36A1gucfH6UtEyqbGhTf40A5weRrf2BAfYrlgGZsauQdbR06/qFSVdmfmbTKE8KDM41rLQzcdgV1ap2khGTw45HFzh9eP4Gx2px0mhcTNuSXUadVUz97WZclArc7cPD94nFghKFw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746134744968482.9481200033773; Thu, 1 May 2025 14:25:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAbLj-0000xY-Fg; Thu, 01 May 2025 17:21:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAbLa-0000oF-Hs for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:35 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAbLY-0001V6-1B for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:34 -0400 Received: by mail-pj1-x1033.google.com with SMTP id 98e67ed59e1d1-306b6ae4fb2so1303104a91.3 for ; Thu, 01 May 2025 14:21:31 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-30a476267e0sm1384573a91.39.2025.05.01.14.21.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 May 2025 14:21:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746134490; x=1746739290; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3IM3WNY4+mvaPjMT/1TSQTeg+RIG05hYdcLT8hVpAu0=; b=EebyiA8H9f4uQTKXGXQezAQeq++zKQhPeQnrzctxbzwgRgIfVZpDYMXvUKH4opYU7C 7kW6F62vznf402v04HRYOKS5+Vg1+kYH4Umy5hUJJREpwvaGvLGH+s60dPcFNrHastTO U3qVA4b9IHFPxIwWyocmjqTw2M1Kn+PiQgMjR249G1gsxvWOWh0v16B9FbXIMrmVoznj D4shaf3BL62chfS2AfpdSuhba6c5y0MzEQCsfOsCpjd5HndfJBG13knI021bxkcA1OB8 Q/1XsEPk5uNKbmOCPXdb+9UQtlTloeM5tNq5EkHWiIEe65fGo41p0Z5AQHQy1BTTFVta jhQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746134490; x=1746739290; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3IM3WNY4+mvaPjMT/1TSQTeg+RIG05hYdcLT8hVpAu0=; b=c2u6h7okki2gHE96PNzRdJ3wByPG4ADJBTs850JXVXOkvBYfq23bxPF9pr6Vvo9lgi NqSRKHKM3EY9s9k0zyVJe4qQBCOYljrQ6CiSaaQpbJFEtwQvip6QecoWWJfSPpgKNJo7 lAP6tugLBCS2ys+8yUTVZan0vV4RsCjq5LM+FK6G2vxa4PxMWgsVFWi6hVJcyKzAXhym /aCCcLIpf92KPBVNHEu9QS7AYxmntvhJbIgYDrGQ95PyYc5wjZn4X/CKXp9Ew7H+tDvh yuP6YvNkz0qwkgVErV88R4V5RVbYkyR1saYlS4r17ws+JPVpAvmiX/CR0qTFG9vaKwte kPAw== X-Gm-Message-State: AOJu0YzRoQWVF61+uohCEu5SJmbN5nTzE/WCYm3GREGm5Q8dUhJL3Oo2 2IE+j0voPjj/a8n7PlL805n34Ekf33+ThVTX4WQ4KUEB9exVI7bDbujOUAtL24dKzT/yhfXRPAo L X-Gm-Gg: ASbGncuD9JHTt2LYF1fn4L0M89loFFLUEeUpGLXUygeQsZt5QKS/L1LN740h9PjYoRf RotZGiHBKN8ICBh2xKadgZQuSYrmX++DdHPz4uOkCH8+oG5eiLYyjWBBSAOZ5FPooveQMhc9ZRF ZJXATIsWVjaSC3akFs5JxAMNAc6ubF86FBvvzWy7cX7aZ7+SN45IktmZeXTxXlS7xsG83Y2S8ST ObncsJ1zYjBotA9B/upgtfhmANgTzmuZ7ZVWcm0mOG5/5emUbpqOMYnVWPeX1SKw2HmXTym76LD sjatY/wbbkluU1YFxENre/nH8oCkGtsVCqSjPjcvssGKKgyyswa2Pe/591DMEjLO67C3GkXCsLE = X-Google-Smtp-Source: AGHT+IGit4o1KJyAFXlSDsyoKIM8udhg6Umqt241SC/XoNvyFEOdLW18VRudmTHyH1UwzYSd7serSA== X-Received: by 2002:a17:90b:3c4e:b0:2ff:502e:62d4 with SMTP id 98e67ed59e1d1-30a4e6b55d2mr720455a91.32.1746134490648; Thu, 01 May 2025 14:21:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 19/59] accel/tcg: Include 'accel/tcg/getpc.h' in 'exec/helper-proto' Date: Thu, 1 May 2025 14:20:33 -0700 Message-ID: <20250501212113.2961531-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746134747295124100 From: Philippe Mathieu-Daud=C3=A9 Most files including "exec/helper-proto.h" call GETPC(). Include it there (in the common part) instead of the unspecific "exec/exec-all.h" header. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-ID: <20250424202412.91612-10-philmd@linaro.org> --- include/exec/exec-all.h | 1 - include/exec/helper-proto-common.h | 2 ++ accel/tcg/translate-all.c | 1 + target/avr/helper.c | 1 - 4 files changed, 3 insertions(+), 2 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 4c5ad98c6a..816274bf90 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -26,7 +26,6 @@ #include "exec/vaddr.h" =20 #if defined(CONFIG_TCG) -#include "accel/tcg/getpc.h" =20 /** * probe_access: diff --git a/include/exec/helper-proto-common.h b/include/exec/helper-proto= -common.h index 16782ef46c..76e6c25bec 100644 --- a/include/exec/helper-proto-common.h +++ b/include/exec/helper-proto-common.h @@ -13,4 +13,6 @@ #include "exec/helper-proto.h.inc" #undef HELPER_H =20 +#include "accel/tcg/getpc.h" + #endif /* HELPER_PROTO_COMMON_H */ diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 38819a507b..0408e2522a 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -61,6 +61,7 @@ #include "system/tcg.h" #include "qapi/error.h" #include "accel/tcg/cpu-ops.h" +#include "accel/tcg/getpc.h" #include "tb-jmp-cache.h" #include "tb-hash.h" #include "tb-context.h" diff --git a/target/avr/helper.c b/target/avr/helper.c index afa591470f..b9cd6d5ef2 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -23,7 +23,6 @@ #include "qemu/error-report.h" #include "cpu.h" #include "accel/tcg/cpu-ops.h" -#include "accel/tcg/getpc.h" #include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/target_page.h" --=20 2.43.0 From nobody Sat Nov 15 22:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746134741; cv=none; d=zohomail.com; s=zohoarc; b=X8ekTsMLo9fk/76m6aBvHkKZdNefoyyZLDtkVYU+e34fjixvtiMp1amvNTxouURNgVnj++tN6QMreG1zjWsBSKAoplN/rUQ6FTk9OOMU2LnPlKqGcWJm0Efa2aB+Wb6JKSioZiNinVpWtZY8cgKOeWLMsHyUPtBr+Nt8gJsZLSY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746134741; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=8XmMNqwTRqPm7obbru05k0G3eZkUfqGrtagb3Klv4NE=; b=dihIwzmjnYXf77ZkuO7lgHmdJxH0zEtmtwYnrCzQEYsOmDTlRfOy0jyzFrMDz1O2F/wMCHsCiArVjMg4T68eIw56ABQ6d70gozH82q/elvg/8vEi6hqgE3xklvjwl4RslR6x5eNY68+/YU9kRrksPhAnIvmZEQB/ZXUAxC3CNoU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746134741089468.0337185445693; Thu, 1 May 2025 14:25:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAbLq-00012P-Ej; Thu, 01 May 2025 17:21:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAbLb-0000om-BO for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:35 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAbLZ-0001VV-E6 for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:34 -0400 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-22423adf751so16207745ad.2 for ; Thu, 01 May 2025 14:21:32 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-30a476267e0sm1384573a91.39.2025.05.01.14.21.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 May 2025 14:21:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746134492; x=1746739292; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8XmMNqwTRqPm7obbru05k0G3eZkUfqGrtagb3Klv4NE=; b=y/E16Q9pXXvmTwu7x3bSQI7RWuk5O+S61jdJnml606vwgU5jUuSIZxoRcw7vVBEURl hoNAMrCOPjtwuRg2t6VBVX5y39IzvM6sxuESzdMIvQvbIVLgju1vCRixVo/WV8L1v2br 1TKE5Pe1+El91U2uViQ8j1Yx9DoB+asiLhuUjTCNnwQNNr2M9adEDg/fpKE6DgS6xHv4 I7llmxtUGeN6pjcbFLo0ojkNhDcLMqJkTjtAas40GRANa1SPJ/0zdqNrNM8/JFpHAyCp J/ocdOhMH3ezsrTCNHCYmETbJ2HVAI5jc4m1FGww+oHHB/b/4gLLr0u3htlkX1aLHZY0 9yQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746134492; x=1746739292; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8XmMNqwTRqPm7obbru05k0G3eZkUfqGrtagb3Klv4NE=; b=skkfnV5IVpPymKVVDWU/Y74BDjMgaTfzYcuBpqJBKa7/G74eelL8k/OQmb6dduhPb2 ZFJu0vpaUQA4rsFUORauyjMFYl7B1/bwYDRWdst6rI+uBIiy/E51yv0amiOql5re7Yox 9ASqZjObq9FIaNr/LUUTbMeeZe4V5v48NnzhXqSrXzSKpuRw8bbAe5Pcz6AUpAAWVaXf doFLFPQsdi67VGSCvtpC0+McWPo6Fl0DX4hkyBA5Gd8axQiVqYP7Z4L58o39CFSASmu7 NbUlY0QyFpaENc2gIOv8/+VC3SH+mUsV7YooTCegMLkzL7QoviESlmMOCEQEZQO4KlZJ 2Lsg== X-Gm-Message-State: AOJu0YzeLetSj/LtybbOvm5SuN5j9hfWLy99EbXSFYhhwpuOU7ckEu35 kPBcKa9mblL11ygM6X1f7qBcO3chYin4u1N6wWrwChCiYwIllukUN4e8uNaZ+exqBRMov73+0I0 d X-Gm-Gg: ASbGnctnA6kWNGFZBjMcZ405tdSGPF64GQWokK6iPo+PfJQgw/MEuDTyN0m5GOBqZxU QOfrebK4nz9kJPYqfd0nzy0HG/P3wBaX2WuJtKN2yKH/c8fIpg388bMUKaccDyRMUVr6ZuJetiI 9/ZB33oiS2w8wmjyzt8iV4R8rJJfn04lWOdy77ki7imFLWCtXn3GgAsVfKiR5ANdH1aiAvukL31 be2ZoW3f/ti8Y2vbz2Ma24I6Dv9UnRg3mFoLtbUOBQDVuPr7Q+SpF7U0R+BpW6P5glb9h+A+Q3a YgQJr+pghbyYBwhxiWRQiAJUJX8EhGiNL/Fr4UjlvgfOxIANWpOcOooMtn+gW/yzvi/4xdnp6m1 Es9kinaHepQ== X-Google-Smtp-Source: AGHT+IH0eIBKu20G2jK/riFwqZiFDTEE6ua8h70MjMGKQlEsPu2xLyK+9ZEkpyJKToxPZathwwxCLQ== X-Received: by 2002:a17:90b:2541:b0:305:5f55:899 with SMTP id 98e67ed59e1d1-30a4e5a579cmr972045a91.11.1746134491778; Thu, 01 May 2025 14:21:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland Subject: [PULL 20/59] physmem: Move TCG IOTLB methods around Date: Thu, 1 May 2025 14:20:34 -0700 Message-ID: <20250501212113.2961531-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746134743437124100 From: Philippe Mathieu-Daud=C3=A9 The next commit will restrict TCG specific code in physmem.c using some #ifdef'ry. In order to keep it simple, move iotlb_to_section() and memory_region_section_get_iotlb() around close together. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Mark Cave-Ayland Signed-off-by: Richard Henderson Message-ID: <20250424202412.91612-11-philmd@linaro.org> --- system/physmem.c | 50 ++++++++++++++++++++++++------------------------ 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/system/physmem.c b/system/physmem.c index 637f2d8532..ccbeae241c 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -746,6 +746,31 @@ translate_fail: return &d->map.sections[PHYS_SECTION_UNASSIGNED]; } =20 +MemoryRegionSection *iotlb_to_section(CPUState *cpu, + hwaddr index, MemTxAttrs attrs) +{ + int asidx =3D cpu_asidx_from_attrs(cpu, attrs); + CPUAddressSpace *cpuas =3D &cpu->cpu_ases[asidx]; + AddressSpaceDispatch *d =3D cpuas->memory_dispatch; + int section_index =3D index & ~TARGET_PAGE_MASK; + MemoryRegionSection *ret; + + assert(section_index < d->map.sections_nb); + ret =3D d->map.sections + section_index; + assert(ret->mr); + assert(ret->mr->ops); + + return ret; +} + +/* Called from RCU critical section */ +hwaddr memory_region_section_get_iotlb(CPUState *cpu, + MemoryRegionSection *section) +{ + AddressSpaceDispatch *d =3D flatview_to_dispatch(section->fv); + return section - d->map.sections; +} + void cpu_address_space_init(CPUState *cpu, int asidx, const char *prefix, MemoryRegion *mr) { @@ -1002,14 +1027,6 @@ bool cpu_physical_memory_snapshot_get_dirty(DirtyBit= mapSnapshot *snap, return false; } =20 -/* Called from RCU critical section */ -hwaddr memory_region_section_get_iotlb(CPUState *cpu, - MemoryRegionSection *section) -{ - AddressSpaceDispatch *d =3D flatview_to_dispatch(section->fv); - return section - d->map.sections; -} - static int subpage_register(subpage_t *mmio, uint32_t start, uint32_t end, uint16_t section); static subpage_t *subpage_init(FlatView *fv, hwaddr base); @@ -2669,23 +2686,6 @@ static uint16_t dummy_section(PhysPageMap *map, Flat= View *fv, MemoryRegion *mr) return phys_section_add(map, §ion); } =20 -MemoryRegionSection *iotlb_to_section(CPUState *cpu, - hwaddr index, MemTxAttrs attrs) -{ - int asidx =3D cpu_asidx_from_attrs(cpu, attrs); - CPUAddressSpace *cpuas =3D &cpu->cpu_ases[asidx]; - AddressSpaceDispatch *d =3D cpuas->memory_dispatch; - int section_index =3D index & ~TARGET_PAGE_MASK; - MemoryRegionSection *ret; - - assert(section_index < d->map.sections_nb); - ret =3D d->map.sections + section_index; - assert(ret->mr); - assert(ret->mr->ops); - - return ret; -} - static void io_mem_init(void) { memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, N= ULL, --=20 2.43.0 From nobody Sat Nov 15 22:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746134575; cv=none; d=zohomail.com; s=zohoarc; b=BwacM/OCURkSNhfd25O9Sc742r+vr+zqcKol6WKrkt0U/c34FoEtMrxntXLUl+z0Syj3v5VXy9hqIPqjlNw2NwHUHn28KGONRxV0qFNaO0DgGWXx8ta7z0ZhFcpLAYkUkSujBKtv78HCAvU3Dq5bwrI1aF+m6ALWy4tV6z6rdQk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746134575; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=5XCisJMSzoKwJaTo6CumWuz7waKPmfF+7nJJv4gwzPo=; b=WHBJNJYVfrmm6awHNa8B4CHnPIpfDuKWmd5nD6varwyqEVxSj0f77P+miQFd+tOxoQTMpbJKnI/xJQPr68XQ8JosylGWiWqBOdhSUWiVxOVITdCLLiAbsqdqsPQ0smlj65tjV1lzVcsqHNDJ91LtaVxgbuOhmQB2ueDOOOOSaQY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746134575513464.79410601616974; Thu, 1 May 2025 14:22:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAbLl-0000zG-Hv; Thu, 01 May 2025 17:21:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAbLc-0000q2-Df for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:36 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAbLa-0001Vv-9L for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:36 -0400 Received: by mail-pg1-x535.google.com with SMTP id 41be03b00d2f7-b0b2d1f2845so1026963a12.3 for ; Thu, 01 May 2025 14:21:33 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-30a476267e0sm1384573a91.39.2025.05.01.14.21.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 May 2025 14:21:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746134493; x=1746739293; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5XCisJMSzoKwJaTo6CumWuz7waKPmfF+7nJJv4gwzPo=; b=gQDFj0PRpNhuGnXOZiolqMs1sqL2o66utY1lkFVLoh9r5f7OJ12WK41XOAJlZec0fe JqgJ1+4LXbo6hHWxDNTRBuYQ5Ei8/jgpgdnqVMAHEV5jnbSFfDbRcP+/VZ2MDuaUH31e K9yZYGgWamnUH5JUOqjsHPgfVzNpQmr2umz0j7LVomhgPhocxeO+NytPYzeIXbxQVD+E qYBwH/dCb7TrVOEGKzhcLawUar6rVHD/KPJ9Gdl6sYxlsNjLti+nnmUCtt9UwzhVn3Kf NYvYApqC6LjBSY9YpKernje++42K2ZpUZ05IHjblLjYM8PJ1soPOa2pwB42Tu8IwFC2G wXPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746134493; x=1746739293; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5XCisJMSzoKwJaTo6CumWuz7waKPmfF+7nJJv4gwzPo=; b=WLb7cy7JKXpDP16wEPggVoH1c/a91g1fqotcqCT/gRXEw5cBSipTnZLtxpOePyMlHC u0z+BkJo997DdOWWr2KXWgUzHrbHrxsOj4wl/Ump1ie+K8gYM0+nSwg/Hn5GfAbIxcMp 8qtLO41FkkTXhEX/GwlRc0BK7Sws69OquR+cGUCbCS4zuPNxvZFVWFhcqeV4p5xhm7fT KSzdBEW9EFyVFqxP/Au6uYQprw7mhL0mrqhrLxUPByCOEcqJLqlzYKvg1/pPOT1Gww16 PzfR3iI+GyYx5urb7Vs5hSg9MyTRTFcjTC3cLC6tEdO4/qZfTbGfg9vi854hMOfsDtB2 yaVQ== X-Gm-Message-State: AOJu0Yw599CLfuoGHtc/ci4QHuJ5zywUWVfyq87liYj9PApXH86Ua7Bq M5Qx4n+8yqnDP3X5f4/KW/hGD6orTrQj3kvkvVYA6RXlsDUL3PbtuueD0nVSYWQTocer6Ou9gxs J X-Gm-Gg: ASbGncsVr/rreehSsv6Rf4g92lVcJD6j79X9JR2ddTXPgm+hI1ur6f3BnlSpOB/YeVh yK5QO8S19fo6tgpBUd+NohaePTX6w+Rga7Szkj8tB+mTWt03dRriuChrQu6S02GukM5/RTd9t+6 krKhbZixg1uH2es4HlMW15+Szw7CoVS0634vOAlnVoOtXcElUhCdwt+VcQRGNZD2BOf9ywiLn9o +PHMjwAI9kk9gzoajDrUMp2oxxtLH68B3bUZv9hXr54wEmzqY7I2JdxdBpkBW1R8142Z71iKTd0 9e3grakVRWUYyW0UFPctjEIwFdPaP4LEJWZUUaC+pmXAIMIQ942//8q+3vHFFo+b4LMF0OLir98 = X-Google-Smtp-Source: AGHT+IG+B+fCp9BHXpA85+JfCT/B9Wm2aSQ+NGermkStlPIky2NclQgNsiOe3XGZz2AGANuwAIa9yQ== X-Received: by 2002:a17:90b:55c5:b0:2ee:bc7b:9237 with SMTP id 98e67ed59e1d1-30a4e6238fcmr790482a91.27.1746134492684; Thu, 01 May 2025 14:21:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 21/59] physmem: Restrict TCG IOTLB code to TCG accel Date: Thu, 1 May 2025 14:20:35 -0700 Message-ID: <20250501212113.2961531-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746134578029124100 From: Philippe Mathieu-Daud=C3=A9 Restrict iotlb_to_section(), address_space_translate_for_iotlb() and memory_region_section_get_iotlb() to TCG. Declare them in the new "accel/tcg/iommu.h" header. Declare iotlb_to_section() using the MemoryRegionSection typedef. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-ID: <20250424202412.91612-12-philmd@linaro.org> --- include/accel/tcg/iommu.h | 41 +++++++++++++++++++++++++++++++++++++++ include/exec/exec-all.h | 26 ------------------------- accel/tcg/cputlb.c | 1 + system/physmem.c | 5 +++++ MAINTAINERS | 2 +- 5 files changed, 48 insertions(+), 27 deletions(-) create mode 100644 include/accel/tcg/iommu.h diff --git a/include/accel/tcg/iommu.h b/include/accel/tcg/iommu.h new file mode 100644 index 0000000000..90cfd6c0ed --- /dev/null +++ b/include/accel/tcg/iommu.h @@ -0,0 +1,41 @@ +/* + * TCG IOMMU translations. + * + * Copyright (c) 2003 Fabrice Bellard + * SPDX-License-Identifier: LGPL-2.1-or-later + */ +#ifndef ACCEL_TCG_IOMMU_H +#define ACCEL_TCG_IOMMU_H + +#ifdef CONFIG_USER_ONLY +#error Cannot include accel/tcg/iommu.h from user emulation +#endif + +#include "exec/hwaddr.h" +#include "exec/memattrs.h" + +/** + * iotlb_to_section: + * @cpu: CPU performing the access + * @index: TCG CPU IOTLB entry + * + * Given a TCG CPU IOTLB entry, return the MemoryRegionSection that + * it refers to. @index will have been initially created and returned + * by memory_region_section_get_iotlb(). + */ +MemoryRegionSection *iotlb_to_section(CPUState *cpu, + hwaddr index, MemTxAttrs attrs); + +MemoryRegionSection *address_space_translate_for_iotlb(CPUState *cpu, + int asidx, + hwaddr addr, + hwaddr *xlat, + hwaddr *plen, + MemTxAttrs attrs, + int *prot); + +hwaddr memory_region_section_get_iotlb(CPUState *cpu, + MemoryRegionSection *section); + +#endif + diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 816274bf90..b9eb9bc4b6 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -21,7 +21,6 @@ #define EXEC_ALL_H =20 #include "exec/hwaddr.h" -#include "exec/memattrs.h" #include "exec/mmu-access-type.h" #include "exec/vaddr.h" =20 @@ -121,29 +120,4 @@ int probe_access_full_mmu(CPUArchState *env, vaddr add= r, int size, #endif /* !CONFIG_USER_ONLY */ #endif /* CONFIG_TCG */ =20 -#if !defined(CONFIG_USER_ONLY) - -/** - * iotlb_to_section: - * @cpu: CPU performing the access - * @index: TCG CPU IOTLB entry - * - * Given a TCG CPU IOTLB entry, return the MemoryRegionSection that - * it refers to. @index will have been initially created and returned - * by memory_region_section_get_iotlb(). - */ -struct MemoryRegionSection *iotlb_to_section(CPUState *cpu, - hwaddr index, MemTxAttrs attr= s); -#endif - -#if !defined(CONFIG_USER_ONLY) - -MemoryRegionSection * -address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr, - hwaddr *xlat, hwaddr *plen, - MemTxAttrs attrs, int *prot); -hwaddr memory_region_section_get_iotlb(CPUState *cpu, - MemoryRegionSection *section); -#endif - #endif diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index ca69128232..d11989f567 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu/main-loop.h" #include "accel/tcg/cpu-ops.h" +#include "accel/tcg/iommu.h" #include "exec/exec-all.h" #include "exec/page-protection.h" #include "system/memory.h" diff --git a/system/physmem.c b/system/physmem.c index ccbeae241c..f1ec0902c7 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -29,6 +29,7 @@ =20 #ifdef CONFIG_TCG #include "accel/tcg/cpu-ops.h" +#include "accel/tcg/iommu.h" #endif /* CONFIG_TCG */ =20 #include "exec/exec-all.h" @@ -587,6 +588,8 @@ MemoryRegion *flatview_translate(FlatView *fv, hwaddr a= ddr, hwaddr *xlat, return mr; } =20 +#ifdef CONFIG_TCG + typedef struct TCGIOMMUNotifier { IOMMUNotifier n; MemoryRegion *mr; @@ -771,6 +774,8 @@ hwaddr memory_region_section_get_iotlb(CPUState *cpu, return section - d->map.sections; } =20 +#endif /* CONFIG_TCG */ + void cpu_address_space_init(CPUState *cpu, int asidx, const char *prefix, MemoryRegion *mr) { diff --git a/MAINTAINERS b/MAINTAINERS index b3f9f2680b..f3f491c8c2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -168,7 +168,7 @@ F: include/exec/helper*.h.inc F: include/exec/helper-info.c.inc F: include/exec/page-protection.h F: include/system/tcg.h -F: include/accel/tcg/cpu-ops.h +F: include/accel/tcg/ F: host/include/*/host/cpuinfo.h F: util/cpuinfo-*.c F: include/tcg/ --=20 2.43.0 From nobody Sat Nov 15 22:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-30a476267e0sm1384573a91.39.2025.05.01.14.21.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 May 2025 14:21:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746134494; x=1746739294; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gYlB/hdthsZsiNz/pGKUzFCgJM+f0Tn0SC8QpO7LBr0=; b=sde7V2HsSJkNcdRm1tx5Ue0tbgogWSXX+WBXvfhMnPcc+mh1i8nAfw6lcyPL0HcXFV fKXNMPcOsYQfVMQOoxvdK49JiIo5N7vzXV1eydrgL4ZJ0RmxFx0bzFtb/GwumxDyGkrG ZULDdH3pLvNQdKvTJ52KQ0ALXWf2sMid11J/IsR9wozipuJr0Nt4kIwCy35MBNWLqyDV JS9dIcuMG+2l55e9+pxFX8GUtg/6ADCUPmPDGWx81Ivm5hBvqXzX1ak04aP4MmZ1EBaR jVqpzOH6wJeSKs9HuNpfcjsQpY5DbHVHKmdNaWBTftnkZd+IdrwpMF8UEjOqIDXjas+8 0q2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746134494; x=1746739294; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gYlB/hdthsZsiNz/pGKUzFCgJM+f0Tn0SC8QpO7LBr0=; b=xJgbSsEc4x/9EIdEBgA48+RfRJ9QpkI2yjL83YpR+q/UgLVebzgHwlut81akjgiN2s hIv4qxTooiMEhp/iBYHck5FXkNvxmC+wSz+kJneJJrsCanCMyndCjE9mmiVBrBBkZ/9x NKLTwb2KO2cimrZCUjbEhf1EXJVG4koUFO3GHGL7PlkL0QprSynuere/jedhtkD8EKUi kSNF/98GE66JiHmDA1NXjRO0rNAFxxMcxPEmnye0HhBrhXujGFptu6+44L6mUhdCD03C LzdlzluBDi6jZolMDii1TYP+tfr6f405Tob8YrrOTNzLYiAynJRgvmt2QucwdJ8pGhxW t6ZA== X-Gm-Message-State: AOJu0YyYjFdEVAwoBCauObNFoZL0W4jTbW8JiEmGTlc/ZYSjFwN3KrJn 1j4MaUZTO8iaXpIuHu577fUuFGWYEJquVQPI+fWKtqfF8O4C5eY4+y90sIdbkXAuKOLkwLKoche 6 X-Gm-Gg: ASbGnct938v4GSz3eYDldG3fQu06k676t8fTOqEdruc+df84nFpJ1waiMLaUwpOpGAw RciGTzurcSJuAJNdIwbiGdD9ItpONvwb/UbQthYzpIXDr9CJhMLP0mqulUx+P53FcNMWSk3qqtg 9fjQssNig739FCp7/UeTOTvbTFt9DWrj7tY1oPavd9EG79eRthWucLvE4AYpV7BwzhbHjPwC9kk /BZIEZ9DV5y9OsfJyPQKVkfbU8C6GxNF6vfAptdCRxFdTZPTMj2XfhSUtjhoQHx9SLANg7STIys zSGwEUw5ZtmWet1ZtgNCcXcIpNvUwge9uWOzzn5ohw9ThhK23gz9cyO/kYG8CMC4PVdcksWe0s8 = X-Google-Smtp-Source: AGHT+IGP5wuCz6yc6JnzqjHAHq1nerW7cb/r00stE8rg5IGKHKQvoYi2+RuqkPEvHoiGkzR7Ruhmjw== X-Received: by 2002:a17:90b:2d48:b0:301:1c29:a1d9 with SMTP id 98e67ed59e1d1-30a4e5be430mr795403a91.21.1746134493669; Thu, 01 May 2025 14:21:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland Subject: [PULL 22/59] accel/tcg: Extract probe API out of 'exec/exec-all.h' Date: Thu, 1 May 2025 14:20:36 -0700 Message-ID: <20250501212113.2961531-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746135143320124100 From: Philippe Mathieu-Daud=C3=A9 Declare probe methods in "accel/tcg/probe.h" to emphasize they are specific to TCG accelerator. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Mark Cave-Ayland Signed-off-by: Richard Henderson Message-ID: <20250424202412.91612-13-philmd@linaro.org> --- include/accel/tcg/probe.h | 106 +++++++++++++++++++++++++++ include/exec/exec-all.h | 100 ------------------------- target/hexagon/mmvec/macros.h | 1 + accel/tcg/cputlb.c | 1 + accel/tcg/user-exec.c | 1 + semihosting/uaccess.c | 1 + target/arm/helper.c | 1 + target/arm/ptw.c | 1 + target/arm/tcg/helper-a64.c | 1 + target/arm/tcg/mte_helper.c | 1 + target/arm/tcg/op_helper.c | 1 + target/arm/tcg/sve_helper.c | 1 + target/hexagon/op_helper.c | 1 + target/hppa/mem_helper.c | 1 + target/hppa/op_helper.c | 1 + target/i386/tcg/access.c | 1 + target/i386/tcg/seg_helper.c | 1 + target/i386/tcg/system/excp_helper.c | 1 + target/mips/tcg/msa_helper.c | 1 + target/ppc/mem_helper.c | 1 + target/riscv/op_helper.c | 1 + target/riscv/vector_helper.c | 1 + target/s390x/tcg/mem_helper.c | 1 + target/xtensa/mmu_helper.c | 1 + 24 files changed, 128 insertions(+), 100 deletions(-) create mode 100644 include/accel/tcg/probe.h diff --git a/include/accel/tcg/probe.h b/include/accel/tcg/probe.h new file mode 100644 index 0000000000..177bd1608d --- /dev/null +++ b/include/accel/tcg/probe.h @@ -0,0 +1,106 @@ +/* + * Probe guest virtual addresses for access permissions. + * + * Copyright (c) 2003 Fabrice Bellard + * SPDX-License-Identifier: LGPL-2.1-or-later + */ +#ifndef ACCEL_TCG_PROBE_H +#define ACCEL_TCG_PROBE_H + +#include "exec/mmu-access-type.h" +#include "exec/vaddr.h" + +/** + * probe_access: + * @env: CPUArchState + * @addr: guest virtual address to look up + * @size: size of the access + * @access_type: read, write or execute permission + * @mmu_idx: MMU index to use for lookup + * @retaddr: return address for unwinding + * + * Look up the guest virtual address @addr. Raise an exception if the + * page does not satisfy @access_type. Raise an exception if the + * access (@addr, @size) hits a watchpoint. For writes, mark a clean + * page as dirty. + * + * Finally, return the host address for a page that is backed by RAM, + * or NULL if the page requires I/O. + */ +void *probe_access(CPUArchState *env, vaddr addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retad= dr); + +static inline void *probe_write(CPUArchState *env, vaddr addr, int size, + int mmu_idx, uintptr_t retaddr) +{ + return probe_access(env, addr, size, MMU_DATA_STORE, mmu_idx, retaddr); +} + +static inline void *probe_read(CPUArchState *env, vaddr addr, int size, + int mmu_idx, uintptr_t retaddr) +{ + return probe_access(env, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr); +} + +/** + * probe_access_flags: + * @env: CPUArchState + * @addr: guest virtual address to look up + * @size: size of the access + * @access_type: read, write or execute permission + * @mmu_idx: MMU index to use for lookup + * @nonfault: suppress the fault + * @phost: return value for host address + * @retaddr: return address for unwinding + * + * Similar to probe_access, loosely returning the TLB_FLAGS_MASK for + * the page, and storing the host address for RAM in @phost. + * + * If @nonfault is set, do not raise an exception but return TLB_INVALID_M= ASK. + * Do not handle watchpoints, but include TLB_WATCHPOINT in the returned f= lags. + * Do handle clean pages, so exclude TLB_NOTDIRY from the returned flags. + * For simplicity, all "mmio-like" flags are folded to TLB_MMIO. + */ +int probe_access_flags(CPUArchState *env, vaddr addr, int size, + MMUAccessType access_type, int mmu_idx, + bool nonfault, void **phost, uintptr_t retaddr); + +#ifndef CONFIG_USER_ONLY + +/** + * probe_access_full: + * Like probe_access_flags, except also return into @pfull. + * + * The CPUTLBEntryFull structure returned via @pfull is transient + * and must be consumed or copied immediately, before any further + * access or changes to TLB @mmu_idx. + * + * This function will not fault if @nonfault is set, but will + * return TLB_INVALID_MASK if the page is not mapped, or is not + * accessible with @access_type. + * + * This function will return TLB_MMIO in order to force the access + * to be handled out-of-line if plugins wish to instrument the access. + */ +int probe_access_full(CPUArchState *env, vaddr addr, int size, + MMUAccessType access_type, int mmu_idx, + bool nonfault, void **phost, + CPUTLBEntryFull **pfull, uintptr_t retaddr); + +/** + * probe_access_full_mmu: + * Like probe_access_full, except: + * + * This function is intended to be used for page table accesses by + * the target mmu itself. Since such page walking happens while + * handling another potential mmu fault, this function never raises + * exceptions (akin to @nonfault true for probe_access_full). + * Likewise this function does not trigger plugin instrumentation. + */ +int probe_access_full_mmu(CPUArchState *env, vaddr addr, int size, + MMUAccessType access_type, int mmu_idx, + void **phost, CPUTLBEntryFull **pfull); + +#endif /* !CONFIG_USER_ONLY */ + +#endif diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index b9eb9bc4b6..9ef7569a0b 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -20,104 +20,4 @@ #ifndef EXEC_ALL_H #define EXEC_ALL_H =20 -#include "exec/hwaddr.h" -#include "exec/mmu-access-type.h" -#include "exec/vaddr.h" - -#if defined(CONFIG_TCG) - -/** - * probe_access: - * @env: CPUArchState - * @addr: guest virtual address to look up - * @size: size of the access - * @access_type: read, write or execute permission - * @mmu_idx: MMU index to use for lookup - * @retaddr: return address for unwinding - * - * Look up the guest virtual address @addr. Raise an exception if the - * page does not satisfy @access_type. Raise an exception if the - * access (@addr, @size) hits a watchpoint. For writes, mark a clean - * page as dirty. - * - * Finally, return the host address for a page that is backed by RAM, - * or NULL if the page requires I/O. - */ -void *probe_access(CPUArchState *env, vaddr addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retad= dr); - -static inline void *probe_write(CPUArchState *env, vaddr addr, int size, - int mmu_idx, uintptr_t retaddr) -{ - return probe_access(env, addr, size, MMU_DATA_STORE, mmu_idx, retaddr); -} - -static inline void *probe_read(CPUArchState *env, vaddr addr, int size, - int mmu_idx, uintptr_t retaddr) -{ - return probe_access(env, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr); -} - -/** - * probe_access_flags: - * @env: CPUArchState - * @addr: guest virtual address to look up - * @size: size of the access - * @access_type: read, write or execute permission - * @mmu_idx: MMU index to use for lookup - * @nonfault: suppress the fault - * @phost: return value for host address - * @retaddr: return address for unwinding - * - * Similar to probe_access, loosely returning the TLB_FLAGS_MASK for - * the page, and storing the host address for RAM in @phost. - * - * If @nonfault is set, do not raise an exception but return TLB_INVALID_M= ASK. - * Do not handle watchpoints, but include TLB_WATCHPOINT in the returned f= lags. - * Do handle clean pages, so exclude TLB_NOTDIRY from the returned flags. - * For simplicity, all "mmio-like" flags are folded to TLB_MMIO. - */ -int probe_access_flags(CPUArchState *env, vaddr addr, int size, - MMUAccessType access_type, int mmu_idx, - bool nonfault, void **phost, uintptr_t retaddr); - -#ifndef CONFIG_USER_ONLY - -/** - * probe_access_full: - * Like probe_access_flags, except also return into @pfull. - * - * The CPUTLBEntryFull structure returned via @pfull is transient - * and must be consumed or copied immediately, before any further - * access or changes to TLB @mmu_idx. - * - * This function will not fault if @nonfault is set, but will - * return TLB_INVALID_MASK if the page is not mapped, or is not - * accessible with @access_type. - * - * This function will return TLB_MMIO in order to force the access - * to be handled out-of-line if plugins wish to instrument the access. - */ -int probe_access_full(CPUArchState *env, vaddr addr, int size, - MMUAccessType access_type, int mmu_idx, - bool nonfault, void **phost, - CPUTLBEntryFull **pfull, uintptr_t retaddr); - -/** - * probe_access_full_mmu: - * Like probe_access_full, except: - * - * This function is intended to be used for page table accesses by - * the target mmu itself. Since such page walking happens while - * handling another potential mmu fault, this function never raises - * exceptions (akin to @nonfault true for probe_access_full). - * Likewise this function does not trigger plugin instrumentation. - */ -int probe_access_full_mmu(CPUArchState *env, vaddr addr, int size, - MMUAccessType access_type, int mmu_idx, - void **phost, CPUTLBEntryFull **pfull); - -#endif /* !CONFIG_USER_ONLY */ -#endif /* CONFIG_TCG */ - #endif diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h index c1a88392c0..c7840fbf2e 100644 --- a/target/hexagon/mmvec/macros.h +++ b/target/hexagon/mmvec/macros.h @@ -22,6 +22,7 @@ #include "arch.h" #include "mmvec/system_ext_mmvec.h" #include "accel/tcg/getpc.h" +#include "accel/tcg/probe.h" =20 #ifndef QEMU_GENERATE #define VdV (*(MMVector *restrict)(VdV_void)) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index d11989f567..b346af942a 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -21,6 +21,7 @@ #include "qemu/main-loop.h" #include "accel/tcg/cpu-ops.h" #include "accel/tcg/iommu.h" +#include "accel/tcg/probe.h" #include "exec/exec-all.h" #include "exec/page-protection.h" #include "system/memory.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 43d005e24e..697fdf1824 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -27,6 +27,7 @@ #include "qemu/bitops.h" #include "qemu/rcu.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/probe.h" #include "user/cpu_loop.h" #include "qemu/main-loop.h" #include "user/page-protection.h" diff --git a/semihosting/uaccess.c b/semihosting/uaccess.c index 81ffecaaba..ebbb300f86 100644 --- a/semihosting/uaccess.c +++ b/semihosting/uaccess.c @@ -9,6 +9,7 @@ =20 #include "qemu/osdep.h" #include "accel/tcg/cpu-mmu-index.h" +#include "accel/tcg/probe.h" #include "exec/exec-all.h" #include "exec/target_page.h" #include "exec/tlb-flags.h" diff --git a/target/arm/helper.c b/target/arm/helper.c index c6fd290012..2f039b2db3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -30,6 +30,7 @@ #include "qapi/error.h" #include "qemu/guest-random.h" #ifdef CONFIG_TCG +#include "accel/tcg/probe.h" #include "semihosting/common-semi.h" #endif #include "cpregs.h" diff --git a/target/arm/ptw.c b/target/arm/ptw.c index e0e82ae507..87d707b592 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -14,6 +14,7 @@ #include "exec/page-protection.h" #include "exec/target_page.h" #include "exec/tlb-flags.h" +#include "accel/tcg/probe.h" #include "cpu.h" #include "internals.h" #include "cpu-features.h" diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 842d9e6000..cfe5faba19 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -31,6 +31,7 @@ #include "exec/cpu-common.h" #include "exec/exec-all.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/probe.h" #include "exec/target_page.h" #include "exec/tlb-flags.h" #include "qemu/int128.h" diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 7dc5fb776b..8fbdcc8fb9 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -30,6 +30,7 @@ #include "system/ram_addr.h" #endif #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/probe.h" #include "exec/helper-proto.h" #include "exec/tlb-flags.h" #include "accel/tcg/cpu-ops.h" diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 38d49cbb9d..d50b8720ad 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -25,6 +25,7 @@ #include "cpu-features.h" #include "exec/exec-all.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/probe.h" #include "cpregs.h" =20 #define SIGNBIT (uint32_t)0x80000000 diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 87b6b4b3e6..50aca54eaa 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -32,6 +32,7 @@ #include "sve_ldst_internal.h" #include "accel/tcg/cpu-ldst.h" #include "accel/tcg/cpu-ops.h" +#include "accel/tcg/probe.h" #ifdef CONFIG_USER_ONLY #include "user/page-protection.h" #endif diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 3f3d86db2b..dd726b4318 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -19,6 +19,7 @@ #include "qemu/log.h" #include "exec/exec-all.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/probe.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" #include "cpu.h" diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 554d7bf4d1..a5f73aedf8 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -23,6 +23,7 @@ #include "exec/exec-all.h" #include "exec/cputlb.h" #include "accel/tcg/cpu-mmu-index.h" +#include "accel/tcg/probe.h" #include "exec/page-protection.h" #include "exec/target_page.h" #include "exec/helper-proto.h" diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 2398ce2c64..32207c1a4c 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -23,6 +23,7 @@ #include "exec/exec-all.h" #include "exec/helper-proto.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/probe.h" #include "qemu/timer.h" #include "trace.h" #ifdef CONFIG_USER_ONLY diff --git a/target/i386/tcg/access.c b/target/i386/tcg/access.c index 0fdd587edd..ee5b451459 100644 --- a/target/i386/tcg/access.c +++ b/target/i386/tcg/access.c @@ -4,6 +4,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/probe.h" #include "exec/exec-all.h" #include "exec/target_page.h" #include "access.h" diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index 3af902e0ec..e45d71fa1a 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -24,6 +24,7 @@ #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/probe.h" #include "exec/log.h" #include "helper-tcg.h" #include "seg_helper.h" diff --git a/target/i386/tcg/system/excp_helper.c b/target/i386/tcg/system/= excp_helper.c index 93614aa3e5..c162621587 100644 --- a/target/i386/tcg/system/excp_helper.c +++ b/target/i386/tcg/system/excp_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/probe.h" #include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/target_page.h" diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index e349344647..fde34a39e1 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -23,6 +23,7 @@ #include "tcg/tcg.h" #include "exec/exec-all.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/probe.h" #include "exec/helper-proto.h" #include "exec/memop.h" #include "exec/target_page.h" diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index d7e8d678f4..50f05a915e 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -25,6 +25,7 @@ #include "exec/helper-proto.h" #include "helper_regs.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/probe.h" #include "internal.h" #include "qemu/atomic128.h" =20 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 5b0db2c45a..abb1d284dc 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -24,6 +24,7 @@ #include "exec/exec-all.h" #include "exec/cputlb.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/probe.h" #include "exec/helper-proto.h" #include "exec/tlb-flags.h" #include "trace.h" diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index b8ae704457..5ccb294e31 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -23,6 +23,7 @@ #include "exec/memop.h" #include "exec/exec-all.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/probe.h" #include "exec/page-protection.h" #include "exec/helper-proto.h" #include "exec/tlb-flags.h" diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 0cdfd380ce..9e77cde81b 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -29,6 +29,7 @@ #include "exec/cputlb.h" #include "exec/page-protection.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/probe.h" #include "exec/target_page.h" #include "exec/tlb-flags.h" #include "accel/tcg/cpu-ops.h" diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c index a7dd810055..182c6e35c1 100644 --- a/target/xtensa/mmu_helper.c +++ b/target/xtensa/mmu_helper.c @@ -34,6 +34,7 @@ #include "qemu/host-utils.h" #include "exec/cputlb.h" #include "accel/tcg/cpu-mmu-index.h" +#include "accel/tcg/probe.h" #include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/target_page.h" --=20 2.43.0 From nobody Sat Nov 15 22:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-30a476267e0sm1384573a91.39.2025.05.01.14.21.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 May 2025 14:21:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746134495; x=1746739295; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bZxdsuk2tjSm8+6tPF1Vj9VTRnXgE0dDbo5Gk3+nWRQ=; b=r1QRrHsIaWQCXg0cxfKo6pWB6DtKeQJp1SSmnSkLk8XxXuZ+hVZB9wQYfmEXa66ybM FPgQ9XAFqzLloFv9w3GuRv9M1BVwIqvJD5sc8nAt50uuzk/iM8TaI2wgyQ8K94rmRBnM TuyHgy732SNMhOJgGypC98iQ2HQ/fiCi/Qi7AHRd5g54nd+18rz4eBfUxjYjvWWgP7H3 NEfZKc/Tg1nrlEYKaHteBonciAZ6XFK5m9MfDAQ/QmU0cUb+3UXZAz6/fiQzLacTDMyY KFpjz1md2TMiU4jbHesj3XkJzO0E3FpxAeWNcXz4ldTq3m7xhVnfF9WxxyEzvQHkOA/p 9j4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746134495; x=1746739295; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bZxdsuk2tjSm8+6tPF1Vj9VTRnXgE0dDbo5Gk3+nWRQ=; b=QGtb+5k7cL6JB/8RtepCSqiXaXpMn7HMTOawbHv1L4E/EUANt90Olj84t4j/CAYJks BunMSIMhtvvfU1yBC2Uwm72pDqJJrW6riDXc66rA6E42FwXx3zz05ZUKNuiV84g6ASRC 34wngv1T0exa0MkRYiS+/0K/b8fkKfe5aGlAWsyi4IAyi4Z6vpa/t0eNOAwt/fiO/6im IYpeEpOGsLxyITJSVLqYDkYGpwz//zh4VFA6ZWEvjyughKlZqfXsrxR+qNPAONgQIdaV iR0f4IYDnpFuxPuNTCShVP00DLZFzu6KzNyD5houObMjFSa4PKP3nAu+CChcDFz6vqn3 y0Kg== X-Gm-Message-State: AOJu0Yz1gZJe0FMV+4Kq8LJNCDzEad2OpNE9hB/yge+5GFdrgNvW/Unc sCbHIcw9zRHoJHiuB7e6NXYi9bvYU1gFWBT9eQszjOj74kKPegqSq/DsbnyLNkNJLhmLdH6tqP8 N X-Gm-Gg: ASbGncuM2s1Xo/0QHbD/hp1xxDxlJ8TtIQaVkwHjtSMDkTH7J0PloRfB39Cz1LXyBcb 6AT3i9LzjpVGKdzESeYYOaCQ/ss4nYFqUUcXSqmM43dHDg72WRLmjCDqinlOGVjsJTxSRevbWGK 88TV1zbjWDQ/kfTYhgLS6B/sp4frstfeji1+IRc2/CsFvRBNbLHq1RptV//Y2eAdle4DIvPAKkm pyP6k9c9GwSbY/gYFhREmmhuqEqI98rHpfP605AA2qt0cuzfYLSdnbXKJZGyQsjj2YID+CjPl+a gU0yYt501J/M0RuvkEEVW1syz/HEB40n+2k6GTALm9dNeAfNdscOORKxsNQkJCud47FkoVjQVBw = X-Google-Smtp-Source: AGHT+IFPHOgMAV0RD6EORJhbMYWNELJ66i5932ZxzSVy9f/Nqy47StM/1LEHkl6lcg0414oj626TdQ== X-Received: by 2002:a17:90b:4ec3:b0:2fa:42f3:e3e4 with SMTP id 98e67ed59e1d1-30a42e52f4fmr5406854a91.3.1746134494495; Thu, 01 May 2025 14:21:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland Subject: [PULL 23/59] include: Remove 'exec/exec-all.h' Date: Thu, 1 May 2025 14:20:37 -0700 Message-ID: <20250501212113.2961531-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746134766396019100 From: Philippe Mathieu-Daud=C3=A9 "exec/exec-all.h" is now fully empty, let's remove it. Mechanical change running: $ sed -i '/exec\/exec-all.h/d' $(git grep -wl exec/exec-all.h) Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Mark Cave-Ayland Signed-off-by: Richard Henderson Message-ID: <20250424202412.91612-14-philmd@linaro.org> --- bsd-user/qemu.h | 1 - include/exec/exec-all.h | 23 ----------------------- include/system/ram_addr.h | 1 - linux-user/user-internals.h | 1 - target/arm/tcg/translate.h | 1 - target/i386/tcg/helper-tcg.h | 1 - accel/hvf/hvf-accel-ops.c | 1 - accel/tcg/cputlb.c | 1 - accel/tcg/translate-all.c | 1 - accel/tcg/user-exec.c | 1 - bsd-user/main.c | 1 - hw/ppc/spapr_nested.c | 1 - hw/riscv/riscv-iommu-sys.c | 1 - hw/sh4/sh7750.c | 1 - linux-user/main.c | 1 - semihosting/uaccess.c | 1 - system/physmem.c | 1 - target/alpha/cpu.c | 1 - target/alpha/fpu_helper.c | 1 - target/alpha/int_helper.c | 1 - target/alpha/mem_helper.c | 1 - target/alpha/translate.c | 1 - target/alpha/vax_helper.c | 1 - target/arm/cpu.c | 1 - target/arm/debug_helper.c | 1 - target/arm/helper.c | 1 - target/arm/ptw.c | 1 - target/arm/tcg/helper-a64.c | 1 - target/arm/tcg/m_helper.c | 1 - target/arm/tcg/mte_helper.c | 1 - target/arm/tcg/mve_helper.c | 1 - target/arm/tcg/op_helper.c | 1 - target/arm/tcg/pauth_helper.c | 1 - target/arm/tcg/sme_helper.c | 1 - target/arm/tcg/sve_helper.c | 1 - target/arm/tcg/tlb_helper.c | 1 - target/arm/tcg/translate-a64.c | 1 - target/avr/cpu.c | 1 - target/avr/translate.c | 1 - target/hexagon/cpu.c | 1 - target/hexagon/op_helper.c | 1 - target/hppa/cpu.c | 1 - target/hppa/fpu_helper.c | 1 - target/hppa/helper.c | 1 - target/hppa/mem_helper.c | 1 - target/hppa/op_helper.c | 1 - target/hppa/sys_helper.c | 1 - target/hppa/translate.c | 1 - target/i386/tcg/access.c | 1 - target/i386/tcg/excp_helper.c | 1 - target/i386/tcg/int_helper.c | 1 - target/i386/tcg/mem_helper.c | 1 - target/i386/tcg/mpx_helper.c | 1 - target/i386/tcg/seg_helper.c | 1 - target/i386/tcg/system/bpt_helper.c | 1 - target/i386/tcg/translate.c | 1 - target/i386/tcg/user/excp_helper.c | 1 - target/i386/tcg/user/seg_helper.c | 1 - target/loongarch/cpu.c | 1 - target/loongarch/tcg/fpu_helper.c | 1 - target/loongarch/tcg/iocsr_helper.c | 1 - target/loongarch/tcg/op_helper.c | 1 - target/loongarch/tcg/tlb_helper.c | 1 - target/loongarch/tcg/vec_helper.c | 1 - target/m68k/fpu_helper.c | 1 - target/m68k/helper.c | 1 - target/m68k/op_helper.c | 1 - target/m68k/translate.c | 1 - target/microblaze/cpu.c | 1 - target/microblaze/op_helper.c | 1 - target/microblaze/translate.c | 1 - target/mips/cpu.c | 1 - target/mips/system/physaddr.c | 1 - target/mips/tcg/exception.c | 1 - target/mips/tcg/fpu_helper.c | 1 - target/mips/tcg/ldst_helper.c | 1 - target/mips/tcg/msa_helper.c | 1 - target/mips/tcg/op_helper.c | 1 - target/mips/tcg/system/special_helper.c | 1 - target/mips/tcg/system/tlb_helper.c | 1 - target/openrisc/cpu.c | 1 - target/openrisc/exception.c | 1 - target/openrisc/exception_helper.c | 1 - target/openrisc/fpu_helper.c | 1 - target/openrisc/interrupt.c | 1 - target/openrisc/interrupt_helper.c | 1 - target/openrisc/sys_helper.c | 1 - target/openrisc/translate.c | 1 - target/ppc/excp_helper.c | 1 - target/ppc/fpu_helper.c | 1 - target/ppc/machine.c | 1 - target/ppc/mem_helper.c | 1 - target/ppc/misc_helper.c | 1 - target/ppc/mmu-hash32.c | 1 - target/ppc/mmu-hash64.c | 1 - target/ppc/mmu-radix64.c | 1 - target/ppc/mmu_common.c | 1 - target/ppc/mmu_helper.c | 1 - target/ppc/power8-pmu.c | 1 - target/ppc/tcg-excp_helper.c | 1 - target/ppc/timebase_helper.c | 1 - target/ppc/translate.c | 1 - target/ppc/user_only_helper.c | 1 - target/riscv/cpu.c | 1 - target/riscv/cpu_helper.c | 1 - target/riscv/crypto_helper.c | 1 - target/riscv/csr.c | 1 - target/riscv/debug.c | 1 - target/riscv/fpu_helper.c | 1 - target/riscv/m128_helper.c | 1 - target/riscv/op_helper.c | 1 - target/riscv/tcg/tcg-cpu.c | 1 - target/riscv/translate.c | 1 - target/riscv/vcrypto_helper.c | 1 - target/riscv/vector_helper.c | 1 - target/riscv/zce_helper.c | 1 - target/rx/op_helper.c | 1 - target/rx/translate.c | 1 - target/s390x/interrupt.c | 1 - target/s390x/mmu_helper.c | 1 - target/s390x/sigp.c | 1 - target/s390x/tcg/cc_helper.c | 1 - target/s390x/tcg/crypto_helper.c | 1 - target/s390x/tcg/excp_helper.c | 1 - target/s390x/tcg/fpu_helper.c | 1 - target/s390x/tcg/int_helper.c | 1 - target/s390x/tcg/mem_helper.c | 1 - target/s390x/tcg/misc_helper.c | 1 - target/s390x/tcg/translate.c | 1 - target/s390x/tcg/vec_fpu_helper.c | 1 - target/s390x/tcg/vec_helper.c | 1 - target/sh4/cpu.c | 1 - target/sh4/helper.c | 1 - target/sh4/op_helper.c | 1 - target/sh4/translate.c | 1 - target/sparc/cpu.c | 1 - target/sparc/fop_helper.c | 1 - target/sparc/helper.c | 1 - target/sparc/ldst_helper.c | 1 - target/sparc/machine.c | 1 - target/sparc/translate.c | 1 - target/sparc/win_helper.c | 1 - target/tricore/cpu.c | 1 - target/tricore/op_helper.c | 1 - target/tricore/translate.c | 1 - target/xtensa/dbg_helper.c | 1 - target/xtensa/exc_helper.c | 1 - target/xtensa/fpu_helper.c | 1 - target/xtensa/mmu_helper.c | 1 - target/xtensa/op_helper.c | 1 - target/xtensa/translate.c | 1 - target/xtensa/win_helper.c | 1 - MAINTAINERS | 1 - 153 files changed, 175 deletions(-) delete mode 100644 include/exec/exec-all.h diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h index 244670dd24..93388e7c34 100644 --- a/bsd-user/qemu.h +++ b/bsd-user/qemu.h @@ -23,7 +23,6 @@ #include "cpu.h" #include "qemu/units.h" #include "accel/tcg/cpu-ldst.h" -#include "exec/exec-all.h" =20 #include "user/abitypes.h" #include "user/cpu_loop.h" diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h deleted file mode 100644 index 9ef7569a0b..0000000000 --- a/include/exec/exec-all.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * internal execution defines for qemu - * - * Copyright (c) 2003 Fabrice Bellard - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ - -#ifndef EXEC_ALL_H -#define EXEC_ALL_H - -#endif diff --git a/include/system/ram_addr.h b/include/system/ram_addr.h index b4e4425acb..15a1b1a4fa 100644 --- a/include/system/ram_addr.h +++ b/include/system/ram_addr.h @@ -24,7 +24,6 @@ #include "exec/cputlb.h" #include "exec/ramlist.h" #include "system/ramblock.h" -#include "exec/exec-all.h" #include "system/memory.h" #include "exec/target_page.h" #include "qemu/rcu.h" diff --git a/linux-user/user-internals.h b/linux-user/user-internals.h index 4aa253b566..691b9a1775 100644 --- a/linux-user/user-internals.h +++ b/linux-user/user-internals.h @@ -19,7 +19,6 @@ #define LINUX_USER_USER_INTERNALS_H =20 #include "user/thunk.h" -#include "exec/exec-all.h" #include "qemu/log.h" =20 extern char *exec_path; diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 53e485d28a..1bfdb0fb9b 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -4,7 +4,6 @@ #include "cpu.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" -#include "exec/exec-all.h" #include "exec/translator.h" #include "exec/translation-block.h" #include "exec/helper-gen.h" diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index 54d845379c..6b3f19855f 100644 --- a/target/i386/tcg/helper-tcg.h +++ b/target/i386/tcg/helper-tcg.h @@ -20,7 +20,6 @@ #ifndef I386_HELPER_TCG_H #define I386_HELPER_TCG_H =20 -#include "exec/exec-all.h" #include "qemu/host-utils.h" =20 /* Maximum instruction code size */ diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c index 5375de7bcf..b8b6116bc8 100644 --- a/accel/hvf/hvf-accel-ops.c +++ b/accel/hvf/hvf-accel-ops.c @@ -51,7 +51,6 @@ #include "qemu/error-report.h" #include "qemu/main-loop.h" #include "system/address-spaces.h" -#include "exec/exec-all.h" #include "gdbstub/enums.h" #include "hw/boards.h" #include "system/accel-ops.h" diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index b346af942a..5b6d6f7975 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -22,7 +22,6 @@ #include "accel/tcg/cpu-ops.h" #include "accel/tcg/iommu.h" #include "accel/tcg/probe.h" -#include "exec/exec-all.h" #include "exec/page-protection.h" #include "system/memory.h" #include "accel/tcg/cpu-ldst.h" diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 0408e2522a..31c7f9927f 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -21,7 +21,6 @@ =20 #include "trace.h" #include "disas/disas.h" -#include "exec/exec-all.h" #include "tcg/tcg.h" #if defined(CONFIG_USER_ONLY) #include "qemu.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 697fdf1824..70feee8df9 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -21,7 +21,6 @@ #include "disas/disas.h" #include "cpu.h" #include "exec/vaddr.h" -#include "exec/exec-all.h" #include "exec/tlb-flags.h" #include "tcg/tcg.h" #include "qemu/bitops.h" diff --git a/bsd-user/main.c b/bsd-user/main.c index fdb160bed0..fa7645a56e 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -36,7 +36,6 @@ #include "qemu/help_option.h" #include "qemu/module.h" #include "qemu/plugin.h" -#include "exec/exec-all.h" #include "user/guest-base.h" #include "user/page-protection.h" #include "tcg/startup.h" diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c index 820f752b9e..10cf634da1 100644 --- a/hw/ppc/spapr_nested.c +++ b/hw/ppc/spapr_nested.c @@ -1,6 +1,5 @@ #include "qemu/osdep.h" #include "qemu/cutils.h" -#include "exec/exec-all.h" #include "exec/cputlb.h" #include "exec/target_long.h" #include "helper_regs.h" diff --git a/hw/riscv/riscv-iommu-sys.c b/hw/riscv/riscv-iommu-sys.c index be2e3944dc..74e76b94a5 100644 --- a/hw/riscv/riscv-iommu-sys.c +++ b/hw/riscv/riscv-iommu-sys.c @@ -26,7 +26,6 @@ #include "qemu/host-utils.h" #include "qemu/module.h" #include "qom/object.h" -#include "exec/exec-all.h" #include "trace.h" =20 #include "riscv-iommu.h" diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c index 41306fb600..300eabc595 100644 --- a/hw/sh4/sh7750.c +++ b/hw/sh4/sh7750.c @@ -36,7 +36,6 @@ #include "sh7750_regnames.h" #include "hw/sh4/sh_intc.h" #include "hw/timer/tmu012.h" -#include "exec/exec-all.h" #include "exec/cputlb.h" #include "trace.h" =20 diff --git a/linux-user/main.c b/linux-user/main.c index e2ec5970be..4af7f49f38 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -40,7 +40,6 @@ #include "qemu/plugin.h" #include "user/guest-base.h" #include "user/page-protection.h" -#include "exec/exec-all.h" #include "exec/gdbstub.h" #include "gdbstub/user.h" #include "tcg/startup.h" diff --git a/semihosting/uaccess.c b/semihosting/uaccess.c index ebbb300f86..4554844e15 100644 --- a/semihosting/uaccess.c +++ b/semihosting/uaccess.c @@ -10,7 +10,6 @@ #include "qemu/osdep.h" #include "accel/tcg/cpu-mmu-index.h" #include "accel/tcg/probe.h" -#include "exec/exec-all.h" #include "exec/target_page.h" #include "exec/tlb-flags.h" #include "semihosting/uaccess.h" diff --git a/system/physmem.c b/system/physmem.c index f1ec0902c7..3f4fd69d9a 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -32,7 +32,6 @@ #include "accel/tcg/iommu.h" #endif /* CONFIG_TCG */ =20 -#include "exec/exec-all.h" #include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/target_page.h" diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 27e2008a4e..68414af8d3 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -23,7 +23,6 @@ #include "qapi/error.h" #include "qemu/qemu-print.h" #include "cpu.h" -#include "exec/exec-all.h" #include "exec/translation-block.h" #include "exec/target_page.h" #include "fpu/softfloat.h" diff --git a/target/alpha/fpu_helper.c b/target/alpha/fpu_helper.c index 6aefb9b851..30f3c7fd18 100644 --- a/target/alpha/fpu_helper.c +++ b/target/alpha/fpu_helper.c @@ -19,7 +19,6 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" =20 diff --git a/target/alpha/int_helper.c b/target/alpha/int_helper.c index 5672696f6f..6bfe63500e 100644 --- a/target/alpha/int_helper.c +++ b/target/alpha/int_helper.c @@ -19,7 +19,6 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" =20 diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c index a4d5adb40c..2113fe33ae 100644 --- a/target/alpha/mem_helper.c +++ b/target/alpha/mem_helper.c @@ -20,7 +20,6 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" #include "accel/tcg/cpu-ldst.h" =20 static void do_unaligned_access(CPUAlphaState *env, vaddr addr, uintptr_t = retaddr) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 7f3195a5dc..cebab0318c 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -21,7 +21,6 @@ #include "cpu.h" #include "system/cpus.h" #include "qemu/host-utils.h" -#include "exec/exec-all.h" #include "tcg/tcg-op.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" diff --git a/target/alpha/vax_helper.c b/target/alpha/vax_helper.c index f94fb519db..c1d201e7b4 100644 --- a/target/alpha/vax_helper.c +++ b/target/alpha/vax_helper.c @@ -19,7 +19,6 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5e951675c6..7b801eb3aa 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -33,7 +33,6 @@ #endif /* CONFIG_TCG */ #include "internals.h" #include "cpu-features.h" -#include "exec/exec-all.h" #include "exec/target_page.h" #include "hw/qdev-properties.h" #if !defined(CONFIG_USER_ONLY) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 473ee2af38..de7999f6a9 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -11,7 +11,6 @@ #include "internals.h" #include "cpu-features.h" #include "cpregs.h" -#include "exec/exec-all.h" #include "exec/helper-proto.h" #include "exec/watchpoint.h" #include "system/tcg.h" diff --git a/target/arm/helper.c b/target/arm/helper.c index 2f039b2db3..8de4eb2c1f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -20,7 +20,6 @@ #include "qemu/bitops.h" #include "qemu/qemu-print.h" #include "exec/cputlb.h" -#include "exec/exec-all.h" #include "exec/translation-block.h" #include "hw/irq.h" #include "system/cpu-timers.h" diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 87d707b592..1040a18962 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -10,7 +10,6 @@ #include "qemu/log.h" #include "qemu/range.h" #include "qemu/main-loop.h" -#include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/target_page.h" #include "exec/tlb-flags.h" diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index cfe5faba19..9cffda07cd 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -29,7 +29,6 @@ #include "internals.h" #include "qemu/crc32c.h" #include "exec/cpu-common.h" -#include "exec/exec-all.h" #include "accel/tcg/cpu-ldst.h" #include "accel/tcg/probe.h" #include "exec/target_page.h" diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index 37dc98dc35..6614719832 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -15,7 +15,6 @@ #include "qemu/main-loop.h" #include "qemu/bitops.h" #include "qemu/log.h" -#include "exec/exec-all.h" #include "exec/page-protection.h" #ifdef CONFIG_TCG #include "accel/tcg/cpu-ldst.h" diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 8fbdcc8fb9..13d7ac0097 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -21,7 +21,6 @@ #include "qemu/log.h" #include "cpu.h" #include "internals.h" -#include "exec/exec-all.h" #include "exec/page-protection.h" #ifdef CONFIG_USER_ONLY #include "user/cpu_loop.h" diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c index f9f67d1f88..506d1c3475 100644 --- a/target/arm/tcg/mve_helper.c +++ b/target/arm/tcg/mve_helper.c @@ -23,7 +23,6 @@ #include "vec_internal.h" #include "exec/helper-proto.h" #include "accel/tcg/cpu-ldst.h" -#include "exec/exec-all.h" #include "tcg/tcg.h" #include "fpu/softfloat.h" #include "crypto/clmul.h" diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index d50b8720ad..dc3f83c37d 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -23,7 +23,6 @@ #include "exec/target_page.h" #include "internals.h" #include "cpu-features.h" -#include "exec/exec-all.h" #include "accel/tcg/cpu-ldst.h" #include "accel/tcg/probe.h" #include "cpregs.h" diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index 59bf27541d..c591c3052c 100644 --- a/target/arm/tcg/pauth_helper.c +++ b/target/arm/tcg/pauth_helper.c @@ -21,7 +21,6 @@ #include "cpu.h" #include "internals.h" #include "cpu-features.h" -#include "exec/exec-all.h" #include "accel/tcg/cpu-ldst.h" #include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index 96b84c37a2..3226895cae 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -23,7 +23,6 @@ #include "tcg/tcg-gvec-desc.h" #include "exec/helper-proto.h" #include "accel/tcg/cpu-ldst.h" -#include "exec/exec-all.h" #include "qemu/int128.h" #include "fpu/softfloat.h" #include "vec_internal.h" diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 50aca54eaa..9f20ecb51d 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -20,7 +20,6 @@ #include "qemu/osdep.h" #include "cpu.h" #include "internals.h" -#include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/helper-proto.h" #include "exec/target_page.h" diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 8841f039bc..5ea4d6590f 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -9,7 +9,6 @@ #include "cpu.h" #include "internals.h" #include "cpu-features.h" -#include "exec/exec-all.h" #include "exec/helper-proto.h" =20 =20 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index d9305f9d26..52cf47e775 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -17,7 +17,6 @@ * License along with this library; if not, see . */ #include "qemu/osdep.h" -#include "exec/exec-all.h" #include "exec/target_page.h" #include "translate.h" #include "translate-a64.h" diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 3f261c6fec..69fface7e9 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -21,7 +21,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/qemu-print.h" -#include "exec/exec-all.h" #include "exec/translation-block.h" #include "system/address-spaces.h" #include "cpu.h" diff --git a/target/avr/translate.c b/target/avr/translate.c index b9c592c899..804b0b21db 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -22,7 +22,6 @@ #include "qemu/qemu-print.h" #include "tcg/tcg.h" #include "cpu.h" -#include "exec/exec-all.h" #include "exec/translation-block.h" #include "tcg/tcg-op.h" #include "exec/helper-proto.h" diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index a5d31c33bd..c1bfa80252 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -19,7 +19,6 @@ #include "qemu/qemu-print.h" #include "cpu.h" #include "internal.h" -#include "exec/exec-all.h" #include "exec/translation-block.h" #include "qapi/error.h" #include "hw/qdev-properties.h" diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index dd726b4318..444799d3ad 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -17,7 +17,6 @@ =20 #include "qemu/osdep.h" #include "qemu/log.h" -#include "exec/exec-all.h" #include "accel/tcg/cpu-ldst.h" #include "accel/tcg/probe.h" #include "exec/helper-proto.h" diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index b792cb247a..b083693b57 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -24,7 +24,6 @@ #include "qemu/timer.h" #include "cpu.h" #include "qemu/module.h" -#include "exec/exec-all.h" #include "exec/translation-block.h" #include "exec/target_page.h" #include "fpu/softfloat.h" diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c index a62d9d3083..ddd0a343d6 100644 --- a/target/hppa/fpu_helper.c +++ b/target/hppa/fpu_helper.c @@ -19,7 +19,6 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" =20 diff --git a/target/hppa/helper.c b/target/hppa/helper.c index ac7f58f0af..d7f8495d98 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -21,7 +21,6 @@ #include "qemu/log.h" #include "cpu.h" #include "fpu/softfloat.h" -#include "exec/exec-all.h" #include "exec/helper-proto.h" #include "qemu/qemu-print.h" #include "hw/hppa/hppa_hardware.h" diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index a5f73aedf8..9bdd0a6f23 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -20,7 +20,6 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" -#include "exec/exec-all.h" #include "exec/cputlb.h" #include "accel/tcg/cpu-mmu-index.h" #include "accel/tcg/probe.h" diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 32207c1a4c..0458378abb 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -20,7 +20,6 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" -#include "exec/exec-all.h" #include "exec/helper-proto.h" #include "accel/tcg/cpu-ldst.h" #include "accel/tcg/probe.h" diff --git a/target/hppa/sys_helper.c b/target/hppa/sys_helper.c index 052a6a88a2..6e65fadcc7 100644 --- a/target/hppa/sys_helper.c +++ b/target/hppa/sys_helper.c @@ -20,7 +20,6 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" -#include "exec/exec-all.h" #include "exec/helper-proto.h" #include "qemu/timer.h" #include "system/runstate.h" diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 88a7d339eb..7a81cfcb88 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -20,7 +20,6 @@ #include "qemu/osdep.h" #include "cpu.h" #include "qemu/host-utils.h" -#include "exec/exec-all.h" #include "exec/page-protection.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" diff --git a/target/i386/tcg/access.c b/target/i386/tcg/access.c index ee5b451459..97e3f0e756 100644 --- a/target/i386/tcg/access.c +++ b/target/i386/tcg/access.c @@ -5,7 +5,6 @@ #include "cpu.h" #include "accel/tcg/cpu-ldst.h" #include "accel/tcg/probe.h" -#include "exec/exec-all.h" #include "exec/target_page.h" #include "access.h" =20 diff --git a/target/i386/tcg/excp_helper.c b/target/i386/tcg/excp_helper.c index de71e68f98..6fb8036d98 100644 --- a/target/i386/tcg/excp_helper.c +++ b/target/i386/tcg/excp_helper.c @@ -19,7 +19,6 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" #include "qemu/log.h" #include "system/runstate.h" #include "exec/helper-proto.h" diff --git a/target/i386/tcg/int_helper.c b/target/i386/tcg/int_helper.c index 1a02e9d843..46741d9f68 100644 --- a/target/i386/tcg/int_helper.c +++ b/target/i386/tcg/int_helper.c @@ -20,7 +20,6 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" -#include "exec/exec-all.h" #include "qemu/host-utils.h" #include "exec/helper-proto.h" #include "qapi/error.h" diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c index 84a0815217..9e7c2d8029 100644 --- a/target/i386/tcg/mem_helper.c +++ b/target/i386/tcg/mem_helper.c @@ -20,7 +20,6 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" #include "accel/tcg/cpu-ldst.h" #include "qemu/int128.h" #include "qemu/atomic128.h" diff --git a/target/i386/tcg/mpx_helper.c b/target/i386/tcg/mpx_helper.c index a0f816dfae..fa8abcc482 100644 --- a/target/i386/tcg/mpx_helper.c +++ b/target/i386/tcg/mpx_helper.c @@ -21,7 +21,6 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "accel/tcg/cpu-ldst.h" -#include "exec/exec-all.h" #include "exec/target_page.h" #include "helper-tcg.h" =20 diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index e45d71fa1a..0ca081b286 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -22,7 +22,6 @@ #include "cpu.h" #include "qemu/log.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" #include "accel/tcg/cpu-ldst.h" #include "accel/tcg/probe.h" #include "exec/log.h" diff --git a/target/i386/tcg/system/bpt_helper.c b/target/i386/tcg/system/b= pt_helper.c index 08ccd3f5e6..aebb5caac3 100644 --- a/target/i386/tcg/system/bpt_helper.c +++ b/target/i386/tcg/system/bpt_helper.c @@ -19,7 +19,6 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" #include "exec/helper-proto.h" #include "exec/watchpoint.h" #include "tcg/helper-tcg.h" diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 8a641951cd..8c3023407d 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -21,7 +21,6 @@ #include "qemu/host-utils.h" #include "cpu.h" #include "accel/tcg/cpu-mmu-index.h" -#include "exec/exec-all.h" #include "exec/translation-block.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" diff --git a/target/i386/tcg/user/excp_helper.c b/target/i386/tcg/user/excp= _helper.c index b3bdb7831a..98fab4cbc3 100644 --- a/target/i386/tcg/user/excp_helper.c +++ b/target/i386/tcg/user/excp_helper.c @@ -19,7 +19,6 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" #include "tcg/helper-tcg.h" =20 void x86_cpu_record_sigsegv(CPUState *cs, vaddr addr, diff --git a/target/i386/tcg/user/seg_helper.c b/target/i386/tcg/user/seg_h= elper.c index 5692dd5195..263f59937f 100644 --- a/target/i386/tcg/user/seg_helper.c +++ b/target/i386/tcg/user/seg_helper.c @@ -21,7 +21,6 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" #include "accel/tcg/cpu-ldst.h" #include "tcg/helper-tcg.h" #include "tcg/seg_helper.h" diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 8ad45b453d..c083ad4fd9 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -15,7 +15,6 @@ #include "system/kvm.h" #include "kvm/kvm_loongarch.h" #include "hw/qdev-properties.h" -#include "exec/exec-all.h" #include "exec/translation-block.h" #include "cpu.h" #include "internals.h" diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_h= elper.c index fc3fd0561e..fc9c64c20a 100644 --- a/target/loongarch/tcg/fpu_helper.c +++ b/target/loongarch/tcg/fpu_helper.c @@ -8,7 +8,6 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" #include "accel/tcg/cpu-ldst.h" #include "fpu/softfloat.h" #include "internals.h" diff --git a/target/loongarch/tcg/iocsr_helper.c b/target/loongarch/tcg/ioc= sr_helper.c index e62170de3c..c155f48564 100644 --- a/target/loongarch/tcg/iocsr_helper.c +++ b/target/loongarch/tcg/iocsr_helper.c @@ -9,7 +9,6 @@ #include "cpu.h" #include "qemu/host-utils.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" #include "accel/tcg/cpu-ldst.h" =20 #define GET_MEMTXATTRS(cas) \ diff --git a/target/loongarch/tcg/op_helper.c b/target/loongarch/tcg/op_hel= per.c index 94e3b28016..16ac0d43bc 100644 --- a/target/loongarch/tcg/op_helper.c +++ b/target/loongarch/tcg/op_helper.c @@ -10,7 +10,6 @@ #include "cpu.h" #include "qemu/host-utils.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" #include "accel/tcg/cpu-ldst.h" #include "internals.h" #include "qemu/crc32c.h" diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index af208d75ae..dc48b0f4d2 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -13,7 +13,6 @@ #include "internals.h" #include "exec/helper-proto.h" #include "exec/cputlb.h" -#include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/target_page.h" #include "accel/tcg/cpu-ldst.h" diff --git a/target/loongarch/tcg/vec_helper.c b/target/loongarch/tcg/vec_h= elper.c index 3faf52cbc4..a270998e63 100644 --- a/target/loongarch/tcg/vec_helper.c +++ b/target/loongarch/tcg/vec_helper.c @@ -7,7 +7,6 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" #include "internals.h" diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c index ac4a0d85be..56012863c8 100644 --- a/target/m68k/fpu_helper.c +++ b/target/m68k/fpu_helper.c @@ -21,7 +21,6 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" #include "accel/tcg/cpu-ldst.h" #include "softfloat.h" =20 diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 3b880dd4d9..15f110fa7a 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -21,7 +21,6 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/cputlb.h" -#include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/target_page.h" #include "exec/gdbstub.h" diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 242aecccbb..f29ae12af8 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -20,7 +20,6 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" #include "accel/tcg/cpu-ldst.h" #include "semihosting/semihost.h" =20 diff --git a/target/m68k/translate.c b/target/m68k/translate.c index b1266a7875..97afceb129 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -20,7 +20,6 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" #include "exec/translation-block.h" #include "exec/target_page.h" #include "tcg/tcg-op.h" diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 00a2730de4..2720e5c1d2 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -27,7 +27,6 @@ #include "cpu.h" #include "qemu/module.h" #include "hw/qdev-properties.h" -#include "exec/exec-all.h" #include "accel/tcg/cpu-ldst.h" #include "exec/gdbstub.h" #include "exec/translation-block.h" diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 4624ce5b67..9e838dfa15 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -23,7 +23,6 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" -#include "exec/exec-all.h" #include "accel/tcg/cpu-ldst.h" #include "fpu/softfloat.h" =20 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 23f1037236..671b1ae4db 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -20,7 +20,6 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" #include "accel/tcg/cpu-ldst.h" #include "tcg/tcg-op.h" #include "exec/helper-proto.h" diff --git a/target/mips/cpu.c b/target/mips/cpu.c index d13361a150..96fe4da255 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -29,7 +29,6 @@ #include "qemu/module.h" #include "system/kvm.h" #include "system/qtest.h" -#include "exec/exec-all.h" #include "hw/qdev-properties.h" #include "hw/qdev-clock.h" #include "fpu_helper.h" diff --git a/target/mips/system/physaddr.c b/target/mips/system/physaddr.c index 505781d84c..b8e1a5ac98 100644 --- a/target/mips/system/physaddr.c +++ b/target/mips/system/physaddr.c @@ -18,7 +18,6 @@ */ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" #include "exec/page-protection.h" #include "../internal.h" =20 diff --git a/target/mips/tcg/exception.c b/target/mips/tcg/exception.c index 1a8902ea1b..d32bcebf46 100644 --- a/target/mips/tcg/exception.c +++ b/target/mips/tcg/exception.c @@ -23,7 +23,6 @@ #include "cpu.h" #include "internal.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" #include "exec/translation-block.h" =20 target_ulong exception_resume_pc(CPUMIPSState *env) diff --git a/target/mips/tcg/fpu_helper.c b/target/mips/tcg/fpu_helper.c index 45d593de48..36af980802 100644 --- a/target/mips/tcg/fpu_helper.c +++ b/target/mips/tcg/fpu_helper.c @@ -24,7 +24,6 @@ #include "cpu.h" #include "internal.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" #include "fpu/softfloat.h" #include "fpu_helper.h" =20 diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c index 2fb879fcbc..10319bf03a 100644 --- a/target/mips/tcg/ldst_helper.c +++ b/target/mips/tcg/ldst_helper.c @@ -23,7 +23,6 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" #include "accel/tcg/cpu-ldst.h" #include "exec/memop.h" #include "internal.h" diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index fde34a39e1..f554b3d10e 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -21,7 +21,6 @@ #include "cpu.h" #include "internal.h" #include "tcg/tcg.h" -#include "exec/exec-all.h" #include "accel/tcg/cpu-ldst.h" #include "accel/tcg/probe.h" #include "exec/helper-proto.h" diff --git a/target/mips/tcg/op_helper.c b/target/mips/tcg/op_helper.c index 65403f1a87..b906d10204 100644 --- a/target/mips/tcg/op_helper.c +++ b/target/mips/tcg/op_helper.c @@ -22,7 +22,6 @@ #include "cpu.h" #include "internal.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" #include "exec/memop.h" #include "fpu_helper.h" =20 diff --git a/target/mips/tcg/system/special_helper.c b/target/mips/tcg/syst= em/special_helper.c index 3ce3ae1e12..b54cbe88a3 100644 --- a/target/mips/tcg/system/special_helper.c +++ b/target/mips/tcg/system/special_helper.c @@ -22,7 +22,6 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" #include "exec/translation-block.h" #include "internal.h" =20 diff --git a/target/mips/tcg/system/tlb_helper.c b/target/mips/tcg/system/t= lb_helper.c index e477ef812a..eccaf3624c 100644 --- a/target/mips/tcg/system/tlb_helper.c +++ b/target/mips/tcg/system/tlb_helper.c @@ -22,7 +22,6 @@ #include "cpu.h" #include "internal.h" #include "exec/cputlb.h" -#include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/target_page.h" #include "accel/tcg/cpu-ldst.h" diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 2ec267efec..8c8165d666 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -21,7 +21,6 @@ #include "qapi/error.h" #include "qemu/qemu-print.h" #include "cpu.h" -#include "exec/exec-all.h" #include "exec/translation-block.h" #include "fpu/softfloat-helpers.h" #include "tcg/tcg.h" diff --git a/target/openrisc/exception.c b/target/openrisc/exception.c index 8699c3dcea..e213be36b6 100644 --- a/target/openrisc/exception.c +++ b/target/openrisc/exception.c @@ -19,7 +19,6 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" #include "exception.h" =20 G_NORETURN void raise_exception(OpenRISCCPU *cpu, uint32_t excp) diff --git a/target/openrisc/exception_helper.c b/target/openrisc/exception= _helper.c index 1f5be4bed9..c2c9d13652 100644 --- a/target/openrisc/exception_helper.c +++ b/target/openrisc/exception_helper.c @@ -19,7 +19,6 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" #include "exec/helper-proto.h" #include "exception.h" =20 diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c index 8b81d2f62f..dba997255c 100644 --- a/target/openrisc/fpu_helper.c +++ b/target/openrisc/fpu_helper.c @@ -20,7 +20,6 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" =20 diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index b3b5b40577..486823094c 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -20,7 +20,6 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" -#include "exec/exec-all.h" #include "gdbstub/helpers.h" #include "qemu/host-utils.h" #ifndef CONFIG_USER_ONLY diff --git a/target/openrisc/interrupt_helper.c b/target/openrisc/interrupt= _helper.c index ab4ea88b69..1553ebc71b 100644 --- a/target/openrisc/interrupt_helper.c +++ b/target/openrisc/interrupt_helper.c @@ -20,7 +20,6 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" #include "exec/helper-proto.h" =20 void HELPER(rfe)(CPUOpenRISCState *env) diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 92badf017f..951f8e247a 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -20,7 +20,6 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" #include "exec/cputlb.h" #include "exec/target_page.h" #include "exec/helper-proto.h" diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index baadea4448..5ab3bc7021 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -21,7 +21,6 @@ #include "qemu/osdep.h" #include "cpu.h" #include "accel/tcg/cpu-mmu-index.h" -#include "exec/exec-all.h" #include "tcg/tcg-op.h" #include "qemu/log.h" #include "qemu/bitops.h" diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index da8b525a41..1efdc4066e 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -24,7 +24,6 @@ #include "system/system.h" #include "system/runstate.h" #include "cpu.h" -#include "exec/exec-all.h" #include "internal.h" #include "helper_regs.h" #include "hw/ppc/ppc.h" diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index d93cfed17b..07b782f971 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -19,7 +19,6 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" #include "internal.h" #include "fpu/softfloat.h" =20 diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 98df5b4a3a..d72e5ecb94 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -1,6 +1,5 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" #include "system/kvm.h" #include "system/tcg.h" #include "helper_regs.h" diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 50f05a915e..aa1af44d22 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -19,7 +19,6 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" #include "exec/target_page.h" #include "qemu/host-utils.h" #include "exec/helper-proto.h" diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index 46ae454afd..e7d9462518 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -20,7 +20,6 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" -#include "exec/exec-all.h" #include "exec/cputlb.h" #include "exec/helper-proto.h" #include "qemu/error-report.h" diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c index 5bd3efe70e..8b980a5aa9 100644 --- a/target/ppc/mmu-hash32.c +++ b/target/ppc/mmu-hash32.c @@ -20,7 +20,6 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/target_page.h" #include "system/kvm.h" diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 3ba4810497..dd337558aa 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -20,7 +20,6 @@ #include "qemu/osdep.h" #include "qemu/units.h" #include "cpu.h" -#include "exec/exec-all.h" #include "exec/page-protection.h" #include "qemu/error-report.h" #include "qemu/qemu-print.h" diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c index 4ab5f3bb92..33ac341290 100644 --- a/target/ppc/mmu-radix64.c +++ b/target/ppc/mmu-radix64.c @@ -19,7 +19,6 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" #include "exec/page-protection.h" #include "qemu/error-report.h" #include "system/kvm.h" diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 394a0c9bb6..52d48615ac 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -24,7 +24,6 @@ #include "kvm_ppc.h" #include "mmu-hash64.h" #include "mmu-hash32.h" -#include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/target_page.h" #include "exec/log.h" diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 2138666122..ac60705402 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -25,7 +25,6 @@ #include "mmu-hash64.h" #include "mmu-hash32.h" #include "exec/cputlb.h" -#include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/target_page.h" #include "exec/log.h" diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index db9ee8e96b..2a7a5b493a 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -13,7 +13,6 @@ #include "qemu/osdep.h" #include "cpu.h" #include "helper_regs.h" -#include "exec/exec-all.h" #include "exec/helper-proto.h" #include "qemu/error-report.h" #include "qemu/timer.h" diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c index 2b15e5f2f0..f835be5156 100644 --- a/target/ppc/tcg-excp_helper.c +++ b/target/ppc/tcg-excp_helper.c @@ -21,7 +21,6 @@ #include "qemu/log.h" #include "target/ppc/cpu.h" #include "accel/tcg/cpu-ldst.h" -#include "exec/exec-all.h" #include "exec/helper-proto.h" #include "system/runstate.h" =20 diff --git a/target/ppc/timebase_helper.c b/target/ppc/timebase_helper.c index 73120323b4..7209b418fb 100644 --- a/target/ppc/timebase_helper.c +++ b/target/ppc/timebase_helper.c @@ -20,7 +20,6 @@ #include "cpu.h" #include "hw/ppc/ppc.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" #include "qemu/log.h" #include "qemu/main-loop.h" =20 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 62dd008e36..27f90c3cc5 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -21,7 +21,6 @@ #include "qemu/osdep.h" #include "cpu.h" #include "internal.h" -#include "exec/exec-all.h" #include "exec/target_page.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" diff --git a/target/ppc/user_only_helper.c b/target/ppc/user_only_helper.c index a4d07a0d0d..ae210eb847 100644 --- a/target/ppc/user_only_helper.c +++ b/target/ppc/user_only_helper.c @@ -20,7 +20,6 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" #include "internal.h" =20 void ppc_cpu_record_sigsegv(CPUState *cs, vaddr address, diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e0604f4c78..d92874baa0 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -24,7 +24,6 @@ #include "cpu.h" #include "cpu_vendorid.h" #include "internals.h" -#include "exec/exec-all.h" #include "qapi/error.h" #include "qapi/visitor.h" #include "qemu/error-report.h" diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 619c76cc00..f2e90a9889 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -24,7 +24,6 @@ #include "internals.h" #include "pmu.h" #include "exec/cputlb.h" -#include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/target_page.h" #include "system/memory.h" diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c index bb084e00ef..a0fb54bc50 100644 --- a/target/riscv/crypto_helper.c +++ b/target/riscv/crypto_helper.c @@ -19,7 +19,6 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" #include "exec/helper-proto.h" #include "crypto/aes.h" #include "crypto/aes-round.h" diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 1308643855..a32e1455c9 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -24,7 +24,6 @@ #include "tcg/tcg-cpu.h" #include "pmu.h" #include "time_helper.h" -#include "exec/exec-all.h" #include "exec/cputlb.h" #include "exec/tb-flush.h" #include "exec/icount.h" diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 8564f0b371..5664466749 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -28,7 +28,6 @@ #include "qapi/error.h" #include "cpu.h" #include "trace.h" -#include "exec/exec-all.h" #include "exec/helper-proto.h" #include "exec/watchpoint.h" #include "system/cpu-timers.h" diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index 91b1a56d10..706bdfa61d 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -19,7 +19,6 @@ #include "qemu/osdep.h" #include "cpu.h" #include "qemu/host-utils.h" -#include "exec/exec-all.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" #include "internals.h" diff --git a/target/riscv/m128_helper.c b/target/riscv/m128_helper.c index ec14aaa901..7d9b83b1b2 100644 --- a/target/riscv/m128_helper.c +++ b/target/riscv/m128_helper.c @@ -19,7 +19,6 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" #include "exec/helper-proto.h" =20 target_ulong HELPER(divu_i128)(CPURISCVState *env, diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index abb1d284dc..05316f2088 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -21,7 +21,6 @@ #include "qemu/osdep.h" #include "cpu.h" #include "internals.h" -#include "exec/exec-all.h" #include "exec/cputlb.h" #include "accel/tcg/cpu-ldst.h" #include "accel/tcg/probe.h" diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 54ac54f2e1..2f757c2a5e 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -18,7 +18,6 @@ */ =20 #include "qemu/osdep.h" -#include "exec/exec-all.h" #include "exec/translation-block.h" #include "tcg-cpu.h" #include "cpu.h" diff --git a/target/riscv/translate.c b/target/riscv/translate.c index cef61b5b29..85128f997b 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -20,7 +20,6 @@ #include "qemu/log.h" #include "cpu.h" #include "tcg/tcg-op.h" -#include "exec/exec-all.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" #include "exec/target_page.h" diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 1526de96f5..9a0d9b4f53 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -26,7 +26,6 @@ #include "crypto/aes-round.h" #include "crypto/sm4.h" #include "exec/memop.h" -#include "exec/exec-all.h" #include "exec/helper-proto.h" #include "internals.h" #include "vector_internals.h" diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 5ccb294e31..8eea3e6df0 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -21,7 +21,6 @@ #include "qemu/bitops.h" #include "cpu.h" #include "exec/memop.h" -#include "exec/exec-all.h" #include "accel/tcg/cpu-ldst.h" #include "accel/tcg/probe.h" #include "exec/page-protection.h" diff --git a/target/riscv/zce_helper.c b/target/riscv/zce_helper.c index 50d65f386c..55221f5f37 100644 --- a/target/riscv/zce_helper.c +++ b/target/riscv/zce_helper.c @@ -18,7 +18,6 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" #include "exec/helper-proto.h" #include "accel/tcg/cpu-ldst.h" =20 diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c index a2f1f3824d..2b190a4b2c 100644 --- a/target/rx/op_helper.c +++ b/target/rx/op_helper.c @@ -19,7 +19,6 @@ #include "qemu/osdep.h" #include "qemu/bitops.h" #include "cpu.h" -#include "exec/exec-all.h" #include "exec/helper-proto.h" #include "accel/tcg/cpu-ldst.h" #include "fpu/softfloat.h" diff --git a/target/rx/translate.c b/target/rx/translate.c index bbda703be8..19a9584a82 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -20,7 +20,6 @@ #include "qemu/bswap.h" #include "qemu/qemu-print.h" #include "cpu.h" -#include "exec/exec-all.h" #include "tcg/tcg-op.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" diff --git a/target/s390x/interrupt.c b/target/s390x/interrupt.c index 4ae6e2ddea..1dca835c5d 100644 --- a/target/s390x/interrupt.c +++ b/target/s390x/interrupt.c @@ -11,7 +11,6 @@ #include "cpu.h" #include "kvm/kvm_s390x.h" #include "s390x-internal.h" -#include "exec/exec-all.h" #include "system/kvm.h" #include "system/tcg.h" #include "hw/s390x/ioinst.h" diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index 0e133cb9a5..00946e9c0f 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -23,7 +23,6 @@ #include "kvm/kvm_s390x.h" #include "system/kvm.h" #include "system/tcg.h" -#include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/target_page.h" #include "hw/hw.h" diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c index a3347f1236..5e95c4978f 100644 --- a/target/s390x/sigp.c +++ b/target/s390x/sigp.c @@ -16,7 +16,6 @@ #include "system/runstate.h" #include "system/address-spaces.h" #include "exec/cputlb.h" -#include "exec/exec-all.h" #include "system/tcg.h" #include "trace.h" #include "qapi/qapi-types-machine.h" diff --git a/target/s390x/tcg/cc_helper.c b/target/s390x/tcg/cc_helper.c index b36f8cdc8b..6595ac763c 100644 --- a/target/s390x/tcg/cc_helper.c +++ b/target/s390x/tcg/cc_helper.c @@ -22,7 +22,6 @@ #include "cpu.h" #include "s390x-internal.h" #include "tcg_s390x.h" -#include "exec/exec-all.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" =20 diff --git a/target/s390x/tcg/crypto_helper.c b/target/s390x/tcg/crypto_hel= per.c index 642c1b18c4..4447bb66ee 100644 --- a/target/s390x/tcg/crypto_helper.c +++ b/target/s390x/tcg/crypto_helper.c @@ -17,7 +17,6 @@ #include "s390x-internal.h" #include "tcg_s390x.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" #include "accel/tcg/cpu-ldst.h" =20 static uint64_t R(uint64_t x, int c) diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index 6cd813e1ab..e4c75d0ce0 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -23,7 +23,6 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/cputlb.h" -#include "exec/exec-all.h" #include "exec/target_page.h" #include "exec/watchpoint.h" #include "s390x-internal.h" diff --git a/target/s390x/tcg/fpu_helper.c b/target/s390x/tcg/fpu_helper.c index 5041c13962..1ba43715ac 100644 --- a/target/s390x/tcg/fpu_helper.c +++ b/target/s390x/tcg/fpu_helper.c @@ -22,7 +22,6 @@ #include "cpu.h" #include "s390x-internal.h" #include "tcg_s390x.h" -#include "exec/exec-all.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" =20 diff --git a/target/s390x/tcg/int_helper.c b/target/s390x/tcg/int_helper.c index 253c036415..fbda396f5b 100644 --- a/target/s390x/tcg/int_helper.c +++ b/target/s390x/tcg/int_helper.c @@ -22,7 +22,6 @@ #include "cpu.h" #include "s390x-internal.h" #include "tcg_s390x.h" -#include "exec/exec-all.h" #include "qemu/host-utils.h" #include "exec/helper-proto.h" #include "accel/tcg/cpu-ldst.h" diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 9e77cde81b..857005b120 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -25,7 +25,6 @@ #include "tcg_s390x.h" #include "exec/helper-proto.h" #include "exec/cpu-common.h" -#include "exec/exec-all.h" #include "exec/cputlb.h" #include "exec/page-protection.h" #include "accel/tcg/cpu-ldst.h" diff --git a/target/s390x/tcg/misc_helper.c b/target/s390x/tcg/misc_helper.c index d5088493ea..f7101be574 100644 --- a/target/s390x/tcg/misc_helper.c +++ b/target/s390x/tcg/misc_helper.c @@ -26,7 +26,6 @@ #include "qemu/host-utils.h" #include "exec/helper-proto.h" #include "qemu/timer.h" -#include "exec/exec-all.h" #include "exec/cputlb.h" #include "accel/tcg/cpu-ldst.h" #include "exec/target_page.h" diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index a714f9c0c2..c7e8574438 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -31,7 +31,6 @@ #include "qemu/osdep.h" #include "cpu.h" #include "s390x-internal.h" -#include "exec/exec-all.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" #include "qemu/log.h" diff --git a/target/s390x/tcg/vec_fpu_helper.c b/target/s390x/tcg/vec_fpu_h= elper.c index 1bbaa82fe8..744f800fb6 100644 --- a/target/s390x/tcg/vec_fpu_helper.c +++ b/target/s390x/tcg/vec_fpu_helper.c @@ -15,7 +15,6 @@ #include "vec.h" #include "tcg_s390x.h" #include "tcg/tcg-gvec-desc.h" -#include "exec/exec-all.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" =20 diff --git a/target/s390x/tcg/vec_helper.c b/target/s390x/tcg/vec_helper.c index 781ccc565b..46ec4a947d 100644 --- a/target/s390x/tcg/vec_helper.c +++ b/target/s390x/tcg/vec_helper.c @@ -17,7 +17,6 @@ #include "tcg/tcg-gvec-desc.h" #include "exec/helper-proto.h" #include "accel/tcg/cpu-ldst.h" -#include "exec/exec-all.h" =20 void HELPER(gvec_vbperm)(void *v1, const void *v2, const void *v3, uint32_t desc) diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 57d7b5fbc8..1885e7d5b2 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -24,7 +24,6 @@ #include "qemu/qemu-print.h" #include "cpu.h" #include "migration/vmstate.h" -#include "exec/exec-all.h" #include "exec/translation-block.h" #include "fpu/softfloat-helpers.h" #include "tcg/tcg.h" diff --git a/target/sh4/helper.c b/target/sh4/helper.c index b41d14d5d7..fb7642bda1 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -21,7 +21,6 @@ =20 #include "cpu.h" #include "exec/cputlb.h" -#include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/target_page.h" #include "exec/log.h" diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index e7fcad3c1b..557b1bf497 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -19,7 +19,6 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" #include "accel/tcg/cpu-ldst.h" #include "fpu/softfloat.h" =20 diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 712117be22..bf8828fce8 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -19,7 +19,6 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" #include "tcg/tcg-op.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index bc753d5f62..690e74f109 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -23,7 +23,6 @@ #include "qemu/module.h" #include "qemu/qemu-print.h" #include "accel/tcg/cpu-mmu-index.h" -#include "exec/exec-all.h" #include "exec/translation-block.h" #include "hw/qdev-properties.h" #include "qapi/visitor.h" diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index c25097d07f..a49334150d 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -19,7 +19,6 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" =20 diff --git a/target/sparc/helper.c b/target/sparc/helper.c index 7846ddd6f6..9163b9d46a 100644 --- a/target/sparc/helper.c +++ b/target/sparc/helper.c @@ -19,7 +19,6 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" #include "qemu/timer.h" #include "qemu/host-utils.h" #include "exec/helper-proto.h" diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 4c5dba19d1..2c63eb9e03 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -23,7 +23,6 @@ #include "cpu.h" #include "tcg/tcg.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" #include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/target_page.h" diff --git a/target/sparc/machine.c b/target/sparc/machine.c index 222e5709c5..4dd75aff74 100644 --- a/target/sparc/machine.c +++ b/target/sparc/machine.c @@ -1,6 +1,5 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" #include "qemu/timer.h" =20 #include "migration/cpu.h" diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 63dd90447b..b922e53bf1 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -22,7 +22,6 @@ =20 #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" #include "exec/target_page.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" diff --git a/target/sparc/win_helper.c b/target/sparc/win_helper.c index 0c4b09f2c1..9ad9d01e8b 100644 --- a/target/sparc/win_helper.c +++ b/target/sparc/win_helper.c @@ -20,7 +20,6 @@ #include "qemu/osdep.h" #include "qemu/main-loop.h" #include "cpu.h" -#include "exec/exec-all.h" #include "exec/helper-proto.h" #include "trace.h" =20 diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 098cd06c54..9f19e903bc 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -20,7 +20,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "cpu.h" -#include "exec/exec-all.h" #include "exec/translation-block.h" #include "qemu/error-report.h" #include "tcg/debug-assert.h" diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c index ae559b6922..9910c13f4b 100644 --- a/target/tricore/op_helper.c +++ b/target/tricore/op_helper.c @@ -18,7 +18,6 @@ #include "cpu.h" #include "qemu/host-utils.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" #include "accel/tcg/cpu-ldst.h" #include /* for crc32 */ =20 diff --git a/target/tricore/translate.c b/target/tricore/translate.c index ba36c9fcc8..3d0e7a10bd 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -20,7 +20,6 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" #include "tcg/tcg-op.h" #include "accel/tcg/cpu-ldst.h" #include "qemu/qemu-print.h" diff --git a/target/xtensa/dbg_helper.c b/target/xtensa/dbg_helper.c index c4f4298a50..3b91f7c38a 100644 --- a/target/xtensa/dbg_helper.c +++ b/target/xtensa/dbg_helper.c @@ -30,7 +30,6 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" -#include "exec/exec-all.h" #include "exec/watchpoint.h" #include "system/address-spaces.h" =20 diff --git a/target/xtensa/exc_helper.c b/target/xtensa/exc_helper.c index ca629f071d..b611c9bf97 100644 --- a/target/xtensa/exc_helper.c +++ b/target/xtensa/exc_helper.c @@ -32,7 +32,6 @@ #include "exec/helper-proto.h" #include "qemu/host-utils.h" #include "qemu/atomic.h" -#include "exec/exec-all.h" =20 void HELPER(exception)(CPUXtensaState *env, uint32_t excp) { diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c index 53fc7cfd2a..5358060c50 100644 --- a/target/xtensa/fpu_helper.c +++ b/target/xtensa/fpu_helper.c @@ -30,7 +30,6 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" -#include "exec/exec-all.h" #include "fpu/softfloat.h" =20 enum { diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c index 182c6e35c1..71330fc84b 100644 --- a/target/xtensa/mmu_helper.c +++ b/target/xtensa/mmu_helper.c @@ -35,7 +35,6 @@ #include "exec/cputlb.h" #include "accel/tcg/cpu-mmu-index.h" #include "accel/tcg/probe.h" -#include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/target_page.h" #include "system/memory.h" diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c index c125fa4946..fc47ebaaf5 100644 --- a/target/xtensa/op_helper.c +++ b/target/xtensa/op_helper.c @@ -30,7 +30,6 @@ #include "exec/helper-proto.h" #include "exec/page-protection.h" #include "qemu/host-utils.h" -#include "exec/exec-all.h" #include "system/memory.h" #include "qemu/atomic.h" #include "qemu/timer.h" diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 2af83c07c2..34ae2f4e16 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -31,7 +31,6 @@ #include "qemu/osdep.h" =20 #include "cpu.h" -#include "exec/exec-all.h" #include "tcg/tcg-op.h" #include "qemu/log.h" #include "qemu/qemu-print.h" diff --git a/target/xtensa/win_helper.c b/target/xtensa/win_helper.c index ec9ff44db0..4b25f8f4de 100644 --- a/target/xtensa/win_helper.c +++ b/target/xtensa/win_helper.c @@ -30,7 +30,6 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" -#include "exec/exec-all.h" =20 static void copy_window_from_phys(CPUXtensaState *env, uint32_t window, uint32_t phys, uint32_t= n) diff --git a/MAINTAINERS b/MAINTAINERS index f3f491c8c2..3706601ea5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -493,7 +493,6 @@ M: Richard Henderson R: Paolo Bonzini S: Maintained F: include/exec/cpu*.h -F: include/exec/exec-all.h F: include/exec/target_long.h F: include/qemu/accel.h F: include/system/accel-*.h --=20 2.43.0 From nobody Sat Nov 15 22:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 279df5fae7..8ff4a34509 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -732,10 +732,10 @@ static inline bool cpu_handle_exception(CPUState *cpu= , int *ret) * If user mode only, we simulate a fake exception which will be * handled outside the cpu execution loop. */ -#if defined(TARGET_I386) const TCGCPUOps *tcg_ops =3D cpu->cc->tcg_ops; - tcg_ops->fake_user_interrupt(cpu); -#endif /* TARGET_I386 */ + if (tcg_ops->fake_user_interrupt) { + tcg_ops->fake_user_interrupt(cpu); + } *ret =3D cpu->exception_index; cpu->exception_index =3D -1; return true; --=20 2.43.0 From nobody Sat Nov 15 22:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746134657; cv=none; d=zohomail.com; s=zohoarc; b=ROsrL6TgmDMFKRfQE2hFi4f42CpOUQGob2LfDfxJ7H8d3ALgDo84QKJdXP7szWn/Z6WKQH1ZEHmy2MclTYJDzh8/5cH2GhsUiOyN/tdtGF3B8AL776rLbWuip0hoUmr50Wu2wYDd1X4NSIJ6jGHEKlMXP3eN9/jgorV+CIY78pM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746134657; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=m8QQZQVqZoC308ckvLV+kB4d6m4SiPb0nD+im6xT08U=; b=avANiau1MBjuUsegDb0ojdk5fpUBdru1QpnepkLgz4gKWA0oEshbCJycluVGTkPPW3W3FIZssCILoAbSu+micwetzklFupyWYwmLvOTtTACiqnfvslk63QfCYN58uLHNlE0HUlYIywGCsf2pbKeQZvDbrq8g0oGADcKee1xM3gA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174613465702046.992570095398264; Thu, 1 May 2025 14:24:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAbLz-000199-VA; Thu, 01 May 2025 17:21:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAbLg-0000su-JV for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:40 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAbLd-0001X1-Kz for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:40 -0400 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-2255003f4c6so16095775ad.0 for ; Thu, 01 May 2025 14:21:37 -0700 (PDT) Received: from stoup.. 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This is similar to other places like cpu-target.c which use CPU_DUMP_CCOP unconditionally. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 8ff4a34509..ff979a2c57 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -285,14 +285,11 @@ static void log_cpu_exec(vaddr pc, CPUState *cpu, if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) { FILE *logfile =3D qemu_log_trylock(); if (logfile) { - int flags =3D 0; + int flags =3D CPU_DUMP_CCOP; =20 if (qemu_loglevel_mask(CPU_LOG_TB_FPU)) { flags |=3D CPU_DUMP_FPU; } -#if defined(TARGET_I386) - flags |=3D CPU_DUMP_CCOP; -#endif if (qemu_loglevel_mask(CPU_LOG_TB_VPU)) { flags |=3D CPU_DUMP_VPU; } --=20 2.43.0 From nobody Sat Nov 15 22:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746134555; cv=none; d=zohomail.com; s=zohoarc; b=DJz6t1e49t/jCqj9xd7FIKrKCvkHqEK9mKrUT/aVrxfsB3N0FfCQ0CoAI6VsWT3Tbi63yqpl8Cn46EP9Z2Ne4vielmdvxOx9cFV3G1J+TiFGa0zs9UMSSXJr0UBSIec62QvaO/j/WzAWAno3st45tDRcoOppl6EOEPJwjhqNZSQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746134555; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=JFC0lIwrLvv96xyWA8HMukwFYVh25GBIzBMcz0FbVPQ=; b=bfrmTEoxD6knfUHcutaYPC6hSVY65CP7j9tVis7WE7Wcw3nHUGRhn3k6rou8VWdWw1sV8ToH1do75VIslZP8lhQJn3UlvnR7nmEcp2A0cHp6htUmzSsWiBx9aq4uAqF1u2RNtGI/QGxR4sLuijhRTzrBnuM2bJM3e7mjeUY1K7s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746134555487239.6370782192365; Thu, 1 May 2025 14:22:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAbLz-00018d-NN; Thu, 01 May 2025 17:21:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAbLh-0000sz-3S for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:41 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAbLe-0001XL-FG for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:40 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-22c33e4fdb8so13910655ad.2 for ; Thu, 01 May 2025 14:21:38 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-30a476267e0sm1384573a91.39.2025.05.01.14.21.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 May 2025 14:21:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746134497; x=1746739297; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JFC0lIwrLvv96xyWA8HMukwFYVh25GBIzBMcz0FbVPQ=; b=r+qXRz1KUqy/ZK3x+sOD0gz5rCBsxyqEb7L7DE4fxeiyLtT9x/wP9Gv/WQ7zioEBqK clRuFSJjlygs2uwAiFKgrMSwTUOhlSdmhCAukrcHWc7ZwKO9OHYMU3iDfDz1n/LW66Qq XG9qgrsr5u7IOa+6ubPlBt2VEfpRLENrhOuJ80YFLWwO0ea92ADCdeA4cnKCs4QOjHtU HKPiVmz516PeNyrM+d/SXErvelkpbClWATa3glqdXX4Fpjo7lLLKLWet0VTYXkHVyz9A Mb1wjpWJqOhTV9SnP+pTem2aMnAAWP2+3wXAzM1Fxlgqzap2Xt8n/2A/T/FfWedDvN+v nP2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746134497; x=1746739297; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JFC0lIwrLvv96xyWA8HMukwFYVh25GBIzBMcz0FbVPQ=; b=sZ8aw1aqSmd/+VovThDOa4Y0B4vF0rjDoozlBNp3ECRI4eRfZKNuWy/KToXJBoV79k KFnFOb7gIwZqcqzOYDBg1x7eOS/lCgB/k9mh2Auv7EBPFx7hdXGzdwyVh1DjF2yAUFVm w/Fwss4ihgOZzQHC4eoGuTPt/lt3guW/BrC6IPPPFGbnHx75M+WWNgyPVZxCqpz1qCbI ZWRm0gA/OYijAa3VFv117crt1CESkoiO2TVc6qQfitvETkjr2IebYPWlf9Zl6uZvBEfh z9oJLgGdWykV+WO5L7swXkjLn4U3NefEk/EdDnE42x6RKgKEWhuFo+lYkDeb3CgaT8gI LK2Q== X-Gm-Message-State: AOJu0YyUB6ZGBrK1hbH3SpAETFLKPYzWH5O3q6ICNIC31Hd1X3Xm0Tvn o/uIQpEjmeTwlo8TMCLlSX3W1lxnVUzp/oSj1rzpAxaDiUZkpmEVfQUy40iaXcUuO87AqOSV1jZ F X-Gm-Gg: ASbGnctvUIaMsX/ctY3okZ+oZ2VYsPf4uSTsu2q14SMHl+pVZ9Ssp4nK23X/oaaPQrA +DuHGfIqyN9cKqwobGhL6qG4OYzXXhLsccUXMOwBLpbGwk2RbcKDSC3CNQjpGCjjcPNbG4I9uAK UQ9I6NlCnH4HhvwtqbPgk9zJBaNpn/5/KTNFbupNRC+UZKvLNCi5kdtZ5sxcheD2WIVdyc0/vVj wgOdz4uHrB8JoaUhZg1fFSUgGbVKvGG3HW2929vaNH7tM68Laf1GrtyVuGOeVV4OEwWCulIOTh4 sLpNLigVPTx7QjbKXc6Z1gEoiY/CYQN7F4eZVSLLO4jn0Ec40mtO61CnZUWypLhesWO+uAJMVqo = X-Google-Smtp-Source: AGHT+IGnoFRjyv+CU27rnylKBkALxUwkiqlD0wIrWgzFzwgBigWjc1hgmmWL6vAwHG15IL7zJtr4QA== X-Received: by 2002:a17:90b:53d0:b0:309:f5bc:1935 with SMTP id 98e67ed59e1d1-30a4e61f527mr724556a91.23.1746134496705; Thu, 01 May 2025 14:21:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 26/59] accel/tcg: Introduce TCGCPUOps.cpu_exec_reset Date: Thu, 1 May 2025 14:20:40 -0700 Message-ID: <20250501212113.2961531-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746134558598019100 Initialize all instances with cpu_reset(), so that there is no functional change. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/accel/tcg/cpu-ops.h | 2 ++ accel/tcg/cpu-exec.c | 3 ++- target/alpha/cpu.c | 1 + target/arm/cpu.c | 1 + target/arm/tcg/cpu-v7m.c | 1 + target/avr/cpu.c | 1 + target/hppa/cpu.c | 1 + target/i386/tcg/tcg-cpu.c | 1 + target/loongarch/cpu.c | 1 + target/m68k/cpu.c | 1 + target/microblaze/cpu.c | 1 + target/mips/cpu.c | 1 + target/openrisc/cpu.c | 1 + target/ppc/cpu_init.c | 1 + target/riscv/tcg/tcg-cpu.c | 1 + target/rx/cpu.c | 1 + target/s390x/cpu.c | 1 + target/sh4/cpu.c | 1 + target/sparc/cpu.c | 1 + target/tricore/cpu.c | 1 + target/xtensa/cpu.c | 1 + 21 files changed, 23 insertions(+), 1 deletion(-) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index 60b5e97205..3ff72b8d9d 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -155,6 +155,8 @@ struct TCGCPUOps { void (*do_interrupt)(CPUState *cpu); /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exe= c */ bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); + /** @cpu_exec_reset: Callback for reset in cpu_exec. */ + void (*cpu_exec_reset)(CPUState *cpu); /** * @cpu_exec_halt: Callback for handling halt in cpu_exec. * diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index ff979a2c57..010f38edaa 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -834,7 +834,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, #else else if (interrupt_request & CPU_INTERRUPT_RESET) { replay_interrupt(); - cpu_reset(cpu); + cpu->cc->tcg_ops->cpu_exec_reset(cpu); bql_unlock(); return true; } @@ -1070,6 +1070,7 @@ bool tcg_exec_realizefn(CPUState *cpu, Error **errp) #ifndef CONFIG_USER_ONLY assert(tcg_ops->cpu_exec_halt); assert(tcg_ops->cpu_exec_interrupt); + assert(tcg_ops->cpu_exec_reset); #endif /* !CONFIG_USER_ONLY */ assert(tcg_ops->translate_code); assert(tcg_ops->mmu_index); diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 68414af8d3..d4e66aa432 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -251,6 +251,7 @@ static const TCGCPUOps alpha_tcg_ops =3D { .tlb_fill =3D alpha_cpu_tlb_fill, .cpu_exec_interrupt =3D alpha_cpu_exec_interrupt, .cpu_exec_halt =3D alpha_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D alpha_cpu_do_interrupt, .do_transaction_failed =3D alpha_cpu_do_transaction_failed, .do_unaligned_access =3D alpha_cpu_do_unaligned_access, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7b801eb3aa..3dde70b04a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2705,6 +2705,7 @@ static const TCGCPUOps arm_tcg_ops =3D { .tlb_fill_align =3D arm_cpu_tlb_fill_align, .cpu_exec_interrupt =3D arm_cpu_exec_interrupt, .cpu_exec_halt =3D arm_cpu_exec_halt, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D arm_cpu_do_interrupt, .do_transaction_failed =3D arm_cpu_do_transaction_failed, .do_unaligned_access =3D arm_cpu_do_unaligned_access, diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index b34b657857..5c8c374885 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -250,6 +250,7 @@ static const TCGCPUOps arm_v7m_tcg_ops =3D { .tlb_fill_align =3D arm_cpu_tlb_fill_align, .cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt, .cpu_exec_halt =3D arm_cpu_exec_halt, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D arm_v7m_cpu_do_interrupt, .do_transaction_failed =3D arm_cpu_do_transaction_failed, .do_unaligned_access =3D arm_cpu_do_unaligned_access, diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 69fface7e9..50b835e1ae 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -232,6 +232,7 @@ static const TCGCPUOps avr_tcg_ops =3D { .mmu_index =3D avr_cpu_mmu_index, .cpu_exec_interrupt =3D avr_cpu_exec_interrupt, .cpu_exec_halt =3D avr_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .tlb_fill =3D avr_cpu_tlb_fill, .do_interrupt =3D avr_cpu_do_interrupt, }; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index b083693b57..60b618a22b 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -271,6 +271,7 @@ static const TCGCPUOps hppa_tcg_ops =3D { .tlb_fill_align =3D hppa_cpu_tlb_fill_align, .cpu_exec_interrupt =3D hppa_cpu_exec_interrupt, .cpu_exec_halt =3D hppa_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D hppa_cpu_do_interrupt, .do_unaligned_access =3D hppa_cpu_do_unaligned_access, .do_transaction_failed =3D hppa_cpu_do_transaction_failed, diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 192812656c..5d1c758ae3 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -147,6 +147,7 @@ const TCGCPUOps x86_tcg_ops =3D { .do_interrupt =3D x86_cpu_do_interrupt, .cpu_exec_halt =3D x86_cpu_exec_halt, .cpu_exec_interrupt =3D x86_cpu_exec_interrupt, + .cpu_exec_reset =3D cpu_reset, .do_unaligned_access =3D x86_cpu_do_unaligned_access, .debug_excp_handler =3D breakpoint_handler, .debug_check_breakpoint =3D x86_debug_check_breakpoint, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index c083ad4fd9..c64cba72dd 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -877,6 +877,7 @@ static const TCGCPUOps loongarch_tcg_ops =3D { .tlb_fill =3D loongarch_cpu_tlb_fill, .cpu_exec_interrupt =3D loongarch_cpu_exec_interrupt, .cpu_exec_halt =3D loongarch_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D loongarch_cpu_do_interrupt, .do_transaction_failed =3D loongarch_cpu_do_transaction_failed, #endif diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 6f33b86c7d..f446c6c8f7 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -602,6 +602,7 @@ static const TCGCPUOps m68k_tcg_ops =3D { .tlb_fill =3D m68k_cpu_tlb_fill, .cpu_exec_interrupt =3D m68k_cpu_exec_interrupt, .cpu_exec_halt =3D m68k_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D m68k_cpu_do_interrupt, .do_transaction_failed =3D m68k_cpu_transaction_failed, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 2720e5c1d2..f305ed04f6 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -440,6 +440,7 @@ static const TCGCPUOps mb_tcg_ops =3D { .tlb_fill =3D mb_cpu_tlb_fill, .cpu_exec_interrupt =3D mb_cpu_exec_interrupt, .cpu_exec_halt =3D mb_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D mb_cpu_do_interrupt, .do_transaction_failed =3D mb_cpu_transaction_failed, .do_unaligned_access =3D mb_cpu_do_unaligned_access, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 96fe4da255..09ed330027 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -563,6 +563,7 @@ static const TCGCPUOps mips_tcg_ops =3D { .tlb_fill =3D mips_cpu_tlb_fill, .cpu_exec_interrupt =3D mips_cpu_exec_interrupt, .cpu_exec_halt =3D mips_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D mips_cpu_do_interrupt, .do_transaction_failed =3D mips_cpu_do_transaction_failed, .do_unaligned_access =3D mips_cpu_do_unaligned_access, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 8c8165d666..94776e0ad8 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -255,6 +255,7 @@ static const TCGCPUOps openrisc_tcg_ops =3D { .tlb_fill =3D openrisc_cpu_tlb_fill, .cpu_exec_interrupt =3D openrisc_cpu_exec_interrupt, .cpu_exec_halt =3D openrisc_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D openrisc_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ }; diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index b0973b6df9..3a01731402 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7492,6 +7492,7 @@ static const TCGCPUOps ppc_tcg_ops =3D { .tlb_fill =3D ppc_cpu_tlb_fill, .cpu_exec_interrupt =3D ppc_cpu_exec_interrupt, .cpu_exec_halt =3D ppc_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D ppc_cpu_do_interrupt, .cpu_exec_enter =3D ppc_cpu_exec_enter, .cpu_exec_exit =3D ppc_cpu_exec_exit, diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 2f757c2a5e..50782e0f0e 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -153,6 +153,7 @@ const TCGCPUOps riscv_tcg_ops =3D { .tlb_fill =3D riscv_cpu_tlb_fill, .cpu_exec_interrupt =3D riscv_cpu_exec_interrupt, .cpu_exec_halt =3D riscv_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D riscv_cpu_do_interrupt, .do_transaction_failed =3D riscv_cpu_do_transaction_failed, .do_unaligned_access =3D riscv_cpu_do_unaligned_access, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index a51b543028..de2e6a22ff 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -217,6 +217,7 @@ static const TCGCPUOps rx_tcg_ops =3D { =20 .cpu_exec_interrupt =3D rx_cpu_exec_interrupt, .cpu_exec_halt =3D rx_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D rx_cpu_do_interrupt, }; =20 diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 99ff58affc..71338aae77 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -365,6 +365,7 @@ static const TCGCPUOps s390_tcg_ops =3D { .tlb_fill =3D s390_cpu_tlb_fill, .cpu_exec_interrupt =3D s390_cpu_exec_interrupt, .cpu_exec_halt =3D s390_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D s390_cpu_do_interrupt, .debug_excp_handler =3D s390x_cpu_debug_excp_handler, .do_unaligned_access =3D s390x_cpu_do_unaligned_access, diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 1885e7d5b2..681237c511 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -275,6 +275,7 @@ static const TCGCPUOps superh_tcg_ops =3D { .tlb_fill =3D superh_cpu_tlb_fill, .cpu_exec_interrupt =3D superh_cpu_exec_interrupt, .cpu_exec_halt =3D superh_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D superh_cpu_do_interrupt, .do_unaligned_access =3D superh_cpu_do_unaligned_access, .io_recompile_replay_branch =3D superh_io_recompile_replay_branch, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 690e74f109..bbdea8556a 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -1034,6 +1034,7 @@ static const TCGCPUOps sparc_tcg_ops =3D { .tlb_fill =3D sparc_cpu_tlb_fill, .cpu_exec_interrupt =3D sparc_cpu_exec_interrupt, .cpu_exec_halt =3D sparc_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D sparc_cpu_do_interrupt, .do_transaction_failed =3D sparc_cpu_do_transaction_failed, .do_unaligned_access =3D sparc_cpu_do_unaligned_access, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 9f19e903bc..0fcac697f6 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -182,6 +182,7 @@ static const TCGCPUOps tricore_tcg_ops =3D { .tlb_fill =3D tricore_cpu_tlb_fill, .cpu_exec_interrupt =3D tricore_cpu_exec_interrupt, .cpu_exec_halt =3D tricore_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, }; =20 static void tricore_cpu_class_init(ObjectClass *c, const void *data) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 27d6e40195..9dcb883208 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -246,6 +246,7 @@ static const TCGCPUOps xtensa_tcg_ops =3D { .tlb_fill =3D xtensa_cpu_tlb_fill, .cpu_exec_interrupt =3D xtensa_cpu_exec_interrupt, .cpu_exec_halt =3D xtensa_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D xtensa_cpu_do_interrupt, .do_transaction_failed =3D xtensa_cpu_do_transaction_failed, .do_unaligned_access =3D xtensa_cpu_do_unaligned_access, --=20 2.43.0 From nobody Sat Nov 15 22:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746135112; cv=none; d=zohomail.com; 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Therefore we can handle the new TCGCPUOps.cpu_exec_reset hook. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 39 ++++++++++++++------------------------- target/i386/tcg/tcg-cpu.c | 11 ++++++++++- 2 files changed, 24 insertions(+), 26 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 010f38edaa..c21c5d202d 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -819,33 +819,22 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, cpu->exception_index =3D EXCP_HLT; bql_unlock(); return true; - } -#if defined(TARGET_I386) - else if (interrupt_request & CPU_INTERRUPT_INIT) { - X86CPU *x86_cpu =3D X86_CPU(cpu); - CPUArchState *env =3D &x86_cpu->env; - replay_interrupt(); - cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, 0, 0); - do_cpu_init(x86_cpu); - cpu->exception_index =3D EXCP_HALTED; - bql_unlock(); - return true; - } -#else - else if (interrupt_request & CPU_INTERRUPT_RESET) { - replay_interrupt(); - cpu->cc->tcg_ops->cpu_exec_reset(cpu); - bql_unlock(); - return true; - } -#endif /* !TARGET_I386 */ - /* The target hook has 3 exit conditions: - False when the interrupt isn't processed, - True when it is, and we should restart on a new TB, - and via longjmp via cpu_loop_exit. */ - else { + } else { const TCGCPUOps *tcg_ops =3D cpu->cc->tcg_ops; =20 + if (interrupt_request & CPU_INTERRUPT_RESET) { + replay_interrupt(); + tcg_ops->cpu_exec_reset(cpu); + bql_unlock(); + return true; + } + + /* + * The target hook has 3 exit conditions: + * False when the interrupt isn't processed, + * True when it is, and we should restart on a new TB, + * and via longjmp via cpu_loop_exit. + */ if (tcg_ops->cpu_exec_interrupt(cpu, interrupt_request)) { if (!tcg_ops->need_replay_interrupt || tcg_ops->need_replay_interrupt(interrupt_request)) { diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 5d1c758ae3..f3f0380e70 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -120,6 +120,15 @@ static bool x86_debug_check_breakpoint(CPUState *cs) /* RF disables all architectural breakpoints. */ return !(env->eflags & RF_MASK); } + +static void x86_cpu_exec_reset(CPUState *cs) +{ + CPUArchState *env =3D cpu_env(cs); + + cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, 0, 0); + do_cpu_init(env_archcpu(env)); + cs->exception_index =3D EXCP_HALTED; +} #endif =20 #include "accel/tcg/cpu-ops.h" @@ -147,7 +156,7 @@ const TCGCPUOps x86_tcg_ops =3D { .do_interrupt =3D x86_cpu_do_interrupt, .cpu_exec_halt =3D x86_cpu_exec_halt, .cpu_exec_interrupt =3D x86_cpu_exec_interrupt, - .cpu_exec_reset =3D cpu_reset, + .cpu_exec_reset =3D x86_cpu_exec_reset, .do_unaligned_access =3D x86_cpu_do_unaligned_access, .debug_excp_handler =3D breakpoint_handler, .debug_check_breakpoint =3D x86_debug_check_breakpoint, --=20 2.43.0 From nobody Sat Nov 15 22:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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For other targets, move the inline definition out of line. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/accel/tcg/cpu-ops.h | 3 ++ target/alpha/cpu.h | 11 ------ target/arm/cpu.h | 3 -- target/avr/cpu.h | 18 ---------- target/hexagon/cpu.h | 15 -------- target/hppa/cpu.h | 3 -- target/i386/cpu.h | 14 -------- target/loongarch/cpu.h | 12 ------- target/m68k/cpu.h | 16 --------- target/microblaze/cpu.h | 8 ----- target/mips/cpu.h | 9 ----- target/openrisc/cpu.h | 10 ------ target/ppc/cpu.h | 13 ------- target/riscv/cpu.h | 3 -- target/rx/cpu.h | 9 ----- target/s390x/cpu.h | 9 ----- target/sh4/cpu.h | 15 -------- target/sparc/cpu.h | 3 -- target/tricore/cpu.h | 12 ------- target/xtensa/cpu.h | 68 ----------------------------------- target/alpha/cpu.c | 14 ++++++-- target/arm/helper.c | 1 + target/avr/cpu.c | 21 +++++++++-- target/hexagon/cpu.c | 18 ++++++++-- target/hppa/cpu.c | 3 +- target/i386/tcg/tcg-cpu.c | 17 +++++++-- target/loongarch/cpu.c | 15 ++++++-- target/m68k/cpu.c | 19 ++++++++-- target/microblaze/cpu.c | 11 ++++-- target/mips/cpu.c | 9 +++++ target/openrisc/cpu.c | 13 +++++-- target/ppc/helper_regs.c | 16 ++++----- target/rx/cpu.c | 12 +++++-- target/s390x/cpu.c | 1 + target/sh4/cpu.c | 18 ++++++++-- target/tricore/cpu.c | 15 ++++++-- target/xtensa/cpu.c | 71 +++++++++++++++++++++++++++++++++++-- 37 files changed, 243 insertions(+), 285 deletions(-) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index 3ff72b8d9d..f5e5746976 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -18,6 +18,9 @@ #include "exec/vaddr.h" #include "tcg/tcg-mo.h" =20 +void cpu_get_tb_cpu_state(CPUArchState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags); + struct TCGCPUOps { /** * mttcg_supported: multi-threaded TCG is supported diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 849f673489..45944e46b5 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -464,17 +464,6 @@ void alpha_cpu_do_transaction_failed(CPUState *cs, hwa= ddr physaddr, MemTxResult response, uintptr_t retad= dr); #endif =20 -static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflag= s) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *pflags =3D env->flags & ENV_FLAG_TB_MASK; -#ifdef CONFIG_USER_ONLY - *pflags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; -#endif -} - #ifdef CONFIG_USER_ONLY /* Copied from linux ieee_swcr_to_fpcr. */ static inline uint64_t alpha_ieee_swcr_to_fpcr(uint64_t swcr) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index fdcf8cd1ae..be4449ca06 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3119,9 +3119,6 @@ static inline bool bswap_code(bool sctlr_b) #endif } =20 -void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags); - enum { QEMU_PSCI_CONDUIT_DISABLED =3D 0, QEMU_PSCI_CONDUIT_SMC =3D 1, diff --git a/target/avr/cpu.h b/target/avr/cpu.h index d6666175a9..518e243d81 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -205,24 +205,6 @@ enum { TB_FLAGS_SKIP =3D 2, }; =20 -static inline void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflag= s) -{ - uint32_t flags =3D 0; - - *pc =3D env->pc_w * 2; - *cs_base =3D 0; - - if (env->fullacc) { - flags |=3D TB_FLAGS_FULL_ACCESS; - } - if (env->skip) { - flags |=3D TB_FLAGS_SKIP; - } - - *pflags =3D flags; -} - static inline int cpu_interrupts_enabled(CPUAVRState *env) { return env->sregI !=3D 0; diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index c065fa8ddc..43a854f517 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -137,21 +137,6 @@ G_NORETURN void hexagon_raise_exception_err(CPUHexagon= State *env, uint32_t exception, uintptr_t pc); =20 -static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - uint32_t hex_flags =3D 0; - *pc =3D env->gpr[HEX_REG_PC]; - *cs_base =3D 0; - if (*pc =3D=3D env->gpr[HEX_REG_SA0]) { - hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1); - } - *flags =3D hex_flags; - if (*pc & PCALIGN_MASK) { - hexagon_raise_exception_err(env, HEX_CAUSE_PC_NOT_ALIGNED, 0); - } -} - typedef HexagonCPU ArchCPU; =20 void hexagon_translate_init(void); diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index acc9937240..11d59d11ca 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -351,9 +351,6 @@ hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr); #define CS_BASE_DIFFPAGE (1 << 12) #define CS_BASE_DIFFSPACE (1 << 13) =20 -void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags); - target_ulong cpu_hppa_get_psw(CPUHPPAState *env); void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong); void update_gva_offset_mask(CPUHPPAState *env); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 3182ba413b..4f8ed8868e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2599,20 +2599,6 @@ static inline bool is_mmu_index_32(int mmu_index) #include "hw/i386/apic.h" #endif =20 -static inline void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *flags =3D env->hflags | - (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)= ); - if (env->hflags & HF_CS64_MASK) { - *cs_base =3D 0; - *pc =3D env->eip; - } else { - *cs_base =3D env->segs[R_CS].base; - *pc =3D (uint32_t)(*cs_base + env->eip); - } -} - void do_cpu_init(X86CPU *cpu); =20 #define MCE_INJECT_BROADCAST 1 diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 70ff56e60c..262bf87f7b 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -492,18 +492,6 @@ static inline void set_pc(CPULoongArchState *env, uint= 64_t value) #define HW_FLAGS_VA32 0x20 #define HW_FLAGS_EUEN_ASXE 0x40 =20 -static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); - *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_F= PE; - *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_S= XE; - *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_= ASXE; - *flags |=3D is_va32(env) * HW_FLAGS_VA32; -} - #define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU =20 void loongarch_cpu_post_init(Object *obj); diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 39d0b9d6d7..d9db6a486a 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -605,22 +605,6 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr = physaddr, vaddr addr, #define TB_FLAGS_TRACE 16 #define TB_FLAGS_TRACE_BIT (1 << TB_FLAGS_TRACE) =20 -static inline void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D (env->macsr >> 4) & TB_FLAGS_MACSR; - if (env->sr & SR_S) { - *flags |=3D TB_FLAGS_MSR_S; - *flags |=3D (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_= S; - *flags |=3D (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_= S; - } - if (M68K_SR_TRACE(env->sr) =3D=3D M68K_SR_TRACE_ANY_INS) { - *flags |=3D TB_FLAGS_TRACE; - } -} - void dump_mmu(CPUM68KState *env); =20 #endif diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index d511f22a55..6ad8643f2e 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -419,14 +419,6 @@ static inline bool mb_cpu_is_big_endian(CPUState *cs) return !cpu->cfg.endi; } =20 -static inline void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *flags =3D (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK); - *cs_base =3D (*flags & IMM_FLAG ? env->imm : 0); -} - #if !defined(CONFIG_USER_ONLY) bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, diff --git a/target/mips/cpu.h b/target/mips/cpu.h index d16f9a7220..5cd4c6c818 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1366,15 +1366,6 @@ void cpu_mips_clock_init(MIPSCPU *cpu); /* helper.c */ target_ulong exception_resume_pc(CPUMIPSState *env); =20 -static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->active_tc.PC; - *cs_base =3D 0; - *flags =3D env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | - MIPS_HFLAG_HWRENA_ULR); -} - /** * mips_cpu_create_with_clock: * @typename: a MIPS CPU type. diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 569819bfb0..f4bcf00b07 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -349,16 +349,6 @@ static inline void cpu_set_gpr(CPUOpenRISCState *env, = int i, uint32_t val) env->shadow_gpr[0][i] =3D val; } =20 -static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D (env->dflag ? TB_FLAGS_DFLAG : 0) - | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) - | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); -} - static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env) { return (env->sr diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 13115a89ff..6b90543811 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2751,19 +2751,6 @@ void cpu_write_xer(CPUPPCState *env, target_ulong xe= r); */ #define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B)) =20 -#ifdef CONFIG_DEBUG_TCG -void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags); -#else -static inline void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->nip; - *cs_base =3D 0; - *flags =3D env->hflags; -} -#endif - G_NORETURN void raise_exception_err_ra(CPUPPCState *env, uint32_t exceptio= n, uint32_t error_code, uintptr_t radd= r); =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 167909c89b..c66ac3bc27 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -802,9 +802,6 @@ static inline uint32_t vext_get_vlmax(uint32_t vlenb, u= int32_t vsew, return vlen >> (vsew + 3 - lmul); } =20 -void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags); - bool riscv_cpu_is_32bit(RISCVCPU *cpu); =20 bool riscv_cpu_virt_mem_enabled(CPURISCVState *env); diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 5c19c83219..ba5761b647 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -153,15 +153,6 @@ void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, = int rte); #define RX_CPU_IRQ 0 #define RX_CPU_FIR 1 =20 -static inline void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D FIELD_DP32(0, PSW, PM, env->psw_pm); - *flags =3D FIELD_DP32(*flags, PSW, U, env->psw_u); -} - static inline uint32_t rx_cpu_pack_psw(CPURXState *env) { uint32_t psw =3D 0; diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 530d97ccf1..aa931cb674 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -411,15 +411,6 @@ static inline int s390x_env_mmu_index(CPUS390XState *e= nv, bool ifetch) #endif } =20 -#ifdef CONFIG_TCG - -#include "tcg/tcg_s390x.h" - -void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags); - -#endif /* CONFIG_TCG */ - /* PER bits from control register 9 */ #define PER_CR9_EVENT_BRANCH 0x80000000 #define PER_CR9_EVENT_IFETCH 0x40000000 diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 906f99ddf0..c41ab70dd7 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -380,19 +380,4 @@ static inline void cpu_write_sr(CPUSH4State *env, targ= et_ulong sr) env->sr =3D sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T)); } =20 -static inline void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - /* For a gUSA region, notice the end of the region. */ - *cs_base =3D env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0; - *flags =3D env->flags - | (env->fpscr & TB_FLAG_FPSCR_MASK) - | (env->sr & TB_FLAG_SR_MASK) - | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ -#ifdef CONFIG_USER_ONLY - *flags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; -#endif -} - #endif /* SH4_CPU_H */ diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 37fd1e066e..31cb3d97eb 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -741,9 +741,6 @@ trap_state* cpu_tsptr(CPUSPARCState* env); #define TB_FLAG_FSR_QNE (1 << 8) #define TB_FLAG_ASI_SHIFT 24 =20 -void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags); - static inline bool tb_fpu_enabled(int tb_flags) { #if defined(CONFIG_USER_ONLY) diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index c76e65f818..82085fbc32 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -258,18 +258,6 @@ void tricore_tcg_init(void); void tricore_translate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, vaddr pc, void *host_pc); =20 -static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - uint32_t new_flags =3D 0; - *pc =3D env->PC; - *cs_base =3D 0; - - new_flags |=3D FIELD_DP32(new_flags, TB_FLAGS, PRIV, - extract32(env->PSW, 10, 2)); - *flags =3D new_flags; -} - #define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU =20 /* helpers.c */ diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index c03ed71c94..74122ebe15 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -733,74 +733,6 @@ static inline uint32_t xtensa_replicate_windowstart(CP= UXtensaState *env) #define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000 #define XTENSA_CSBASE_LBEG_OFF_SHIFT 16 =20 -static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D 0; - *flags |=3D xtensa_get_ring(env); - if (env->sregs[PS] & PS_EXCM) { - *flags |=3D XTENSA_TBFLAG_EXCM; - } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) { - target_ulong lend_dist =3D - env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS)); - - /* - * 0 in the csbase_lend field means that there may not be a loopba= ck - * for any instruction that starts inside this page. Any other val= ue - * means that an instruction that ends at this offset from the page - * start may loop back and will need loopback code to be generated. - * - * lend_dist is 0 when LEND points to the start of the page, but - * no instruction that starts inside this page may end at offset 0, - * so it's still correct. - * - * When an instruction ends at a page boundary it may only start in - * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE - * for the TB that contains this instruction. - */ - if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_s= ize) { - target_ulong lbeg_off =3D env->sregs[LEND] - env->sregs[LBEG]; - - *cs_base =3D lend_dist; - if (lbeg_off < 256) { - *cs_base |=3D lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT; - } - } - } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && - (env->sregs[LITBASE] & 1)) { - *flags |=3D XTENSA_TBFLAG_LITBASE; - } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) { - if (xtensa_get_cintlevel(env) < env->config->debug_level) { - *flags |=3D XTENSA_TBFLAG_DEBUG; - } - if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { - *flags |=3D XTENSA_TBFLAG_ICOUNT; - } - } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { - *flags |=3D env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; - } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER= ) && - (env->sregs[PS] & (PS_WOE | PS_EXCM)) =3D=3D PS_WOE) { - uint32_t windowstart =3D xtensa_replicate_windowstart(env) >> - (env->sregs[WINDOW_BASE] + 1); - uint32_t w =3D ctz32(windowstart | 0x8); - - *flags |=3D (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE; - *flags |=3D extract32(env->sregs[PS], PS_CALLINC_SHIFT, - PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT; - } else { - *flags |=3D 3 << XTENSA_TBFLAG_WINDOW_SHIFT; - } - if (env->yield_needed) { - *flags |=3D XTENSA_TBFLAG_YIELD; - } -} - XtensaCPU *xtensa_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk); =20 diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index d4e66aa432..134806e755 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -25,6 +25,7 @@ #include "cpu.h" #include "exec/translation-block.h" #include "exec/target_page.h" +#include "accel/tcg/cpu-ops.h" #include "fpu/softfloat.h" =20 =20 @@ -40,6 +41,17 @@ static vaddr alpha_cpu_get_pc(CPUState *cs) return env->pc; } =20 +void cpu_get_tb_cpu_state(CPUAlphaState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *pflags =3D env->flags & ENV_FLAG_TB_MASK; +#ifdef CONFIG_USER_ONLY + *pflags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#endif +} + static void alpha_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -231,8 +243,6 @@ static const struct SysemuCPUOps alpha_sysemu_ops =3D { }; #endif =20 -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps alpha_tcg_ops =3D { /* Alpha processors have a weak memory model */ .guest_default_memory_order =3D 0, diff --git a/target/arm/helper.c b/target/arm/helper.c index 8de4eb2c1f..98adeb7086 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -30,6 +30,7 @@ #include "qemu/guest-random.h" #ifdef CONFIG_TCG #include "accel/tcg/probe.h" +#include "accel/tcg/cpu-ops.h" #include "semihosting/common-semi.h" #endif #include "cpregs.h" diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 50b835e1ae..d9fecb272e 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -27,6 +27,7 @@ #include "disas/dis-asm.h" #include "tcg/debug-assert.h" #include "hw/qdev-properties.h" +#include "accel/tcg/cpu-ops.h" =20 static void avr_cpu_set_pc(CPUState *cs, vaddr value) { @@ -53,6 +54,24 @@ static int avr_cpu_mmu_index(CPUState *cs, bool ifetch) return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; } =20 +void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + uint32_t flags =3D 0; + + *pc =3D env->pc_w * 2; + *cs_base =3D 0; + + if (env->fullacc) { + flags |=3D TB_FLAGS_FULL_ACCESS; + } + if (env->skip) { + flags |=3D TB_FLAGS_SKIP; + } + + *pflags =3D flags; +} + static void avr_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -220,8 +239,6 @@ static const struct SysemuCPUOps avr_sysemu_ops =3D { .get_phys_page_debug =3D avr_cpu_get_phys_page_debug, }; =20 -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps avr_tcg_ops =3D { .guest_default_memory_order =3D 0, .mttcg_supported =3D false, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index c1bfa80252..2272f1222b 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -25,6 +25,7 @@ #include "fpu/softfloat-helpers.h" #include "tcg/tcg.h" #include "exec/gdbstub.h" +#include "accel/tcg/cpu-ops.h" =20 static void hexagon_v66_cpu_init(Object *obj) { } static void hexagon_v67_cpu_init(Object *obj) { } @@ -254,6 +255,21 @@ static vaddr hexagon_cpu_get_pc(CPUState *cs) return cpu_env(cs)->gpr[HEX_REG_PC]; } =20 +void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + uint32_t hex_flags =3D 0; + *pc =3D env->gpr[HEX_REG_PC]; + *cs_base =3D 0; + if (*pc =3D=3D env->gpr[HEX_REG_SA0]) { + hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1); + } + *flags =3D hex_flags; + if (*pc & PCALIGN_MASK) { + hexagon_raise_exception_err(env, HEX_CAUSE_PC_NOT_ALIGNED, 0); + } +} + static void hexagon_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -321,8 +337,6 @@ static void hexagon_cpu_init(Object *obj) { } =20 -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps hexagon_tcg_ops =3D { /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order =3D TCG_MO_ALL, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 60b618a22b..4cdaf98ab1 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -29,6 +29,7 @@ #include "fpu/softfloat.h" #include "tcg/tcg.h" #include "hw/hppa/hppa_hardware.h" +#include "accel/tcg/cpu-ops.h" =20 static void hppa_cpu_set_pc(CPUState *cs, vaddr value) { @@ -249,8 +250,6 @@ static const struct SysemuCPUOps hppa_sysemu_ops =3D { }; #endif =20 -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps hppa_tcg_ops =3D { /* PA-RISC 1.x processors have a strong memory model. */ /* diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index f3f0380e70..bb6f82befb 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -24,6 +24,7 @@ #include "accel/accel-cpu-target.h" #include "exec/translation-block.h" #include "exec/target_page.h" +#include "accel/tcg/cpu-ops.h" #include "tcg-cpu.h" =20 /* Frob eflags into and out of the CPU temporary format. */ @@ -47,6 +48,20 @@ static void x86_cpu_exec_exit(CPUState *cs) env->eflags =3D cpu_compute_eflags(env); } =20 +void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *flags =3D env->hflags | + (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)= ); + if (env->hflags & HF_CS64_MASK) { + *cs_base =3D 0; + *pc =3D env->eip; + } else { + *cs_base =3D env->segs[R_CS].base; + *pc =3D (uint32_t)(*cs_base + env->eip); + } +} + static void x86_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -131,8 +146,6 @@ static void x86_cpu_exec_reset(CPUState *cs) } #endif =20 -#include "accel/tcg/cpu-ops.h" - const TCGCPUOps x86_tcg_ops =3D { .mttcg_supported =3D true, .precise_smc =3D true, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index c64cba72dd..be770b7e19 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -29,6 +29,7 @@ #endif #ifdef CONFIG_TCG #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/cpu-ops.h" #include "tcg/tcg.h" #endif #include "tcg/tcg_loongarch.h" @@ -335,6 +336,18 @@ static bool loongarch_cpu_exec_interrupt(CPUState *cs,= int interrupt_request) } #endif =20 +void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); + *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_F= PE; + *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_S= XE; + *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_= ASXE; + *flags |=3D is_va32(env) * HW_FLAGS_VA32; +} + static void loongarch_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -861,8 +874,6 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE= *f, int flags) } =20 #ifdef CONFIG_TCG -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps loongarch_tcg_ops =3D { .guest_default_memory_order =3D 0, .mttcg_supported =3D true, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index f446c6c8f7..2b4ec40509 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -23,6 +23,7 @@ #include "cpu.h" #include "migration/vmstate.h" #include "fpu/softfloat.h" +#include "accel/tcg/cpu-ops.h" =20 static void m68k_cpu_set_pc(CPUState *cs, vaddr value) { @@ -38,6 +39,22 @@ static vaddr m68k_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 +void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D (env->macsr >> 4) & TB_FLAGS_MACSR; + if (env->sr & SR_S) { + *flags |=3D TB_FLAGS_MSR_S; + *flags |=3D (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_= S; + *flags |=3D (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_= S; + } + if (M68K_SR_TRACE(env->sr) =3D=3D M68K_SR_TRACE_ANY_INS) { + *flags |=3D TB_FLAGS_TRACE; + } +} + static void m68k_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) @@ -586,8 +603,6 @@ static const struct SysemuCPUOps m68k_sysemu_ops =3D { }; #endif /* !CONFIG_USER_ONLY */ =20 -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps m68k_tcg_ops =3D { /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order =3D TCG_MO_ALL, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index f305ed04f6..105ede0b1e 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -31,6 +31,7 @@ #include "exec/gdbstub.h" #include "exec/translation-block.h" #include "fpu/softfloat-helpers.h" +#include "accel/tcg/cpu-ops.h" #include "tcg/tcg.h" =20 static const struct { @@ -94,6 +95,14 @@ static vaddr mb_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 +void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *flags =3D (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK); + *cs_base =3D (*flags & IMM_FLAG ? env->imm : 0); +} + static void mb_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -423,8 +432,6 @@ static const struct SysemuCPUOps mb_sysemu_ops =3D { }; #endif =20 -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps mb_tcg_ops =3D { /* MicroBlaze is always in-order. */ .guest_default_memory_order =3D TCG_MO_ALL, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 09ed330027..ab00adf86b 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -549,6 +549,15 @@ static int mips_cpu_mmu_index(CPUState *cs, bool ifunc) return mips_env_mmu_index(cpu_env(cs)); } =20 +void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->active_tc.PC; + *cs_base =3D 0; + *flags =3D env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | + MIPS_HFLAG_HWRENA_ULR); +} + static const TCGCPUOps mips_tcg_ops =3D { .mttcg_supported =3D TARGET_LONG_BITS =3D=3D 32, .guest_default_memory_order =3D 0, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 94776e0ad8..d798127d67 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -23,6 +23,7 @@ #include "cpu.h" #include "exec/translation-block.h" #include "fpu/softfloat-helpers.h" +#include "accel/tcg/cpu-ops.h" #include "tcg/tcg.h" =20 static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) @@ -40,6 +41,16 @@ static vaddr openrisc_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 +void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D (env->dflag ? TB_FLAGS_DFLAG : 0) + | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) + | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); +} + static void openrisc_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -239,8 +250,6 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = =3D { }; #endif =20 -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps openrisc_tcg_ops =3D { .guest_default_memory_order =3D 0, .mttcg_supported =3D true, diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index f211bc9830..8d248bcbb9 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -27,6 +27,7 @@ #include "power8-pmu.h" #include "cpu-models.h" #include "spr_common.h" +#include "accel/tcg/cpu-ops.h" =20 /* Swap temporary saved registers with GPRs */ void hreg_swap_gpr_tgpr(CPUPPCState *env) @@ -255,26 +256,25 @@ void hreg_update_pmu_hflags(CPUPPCState *env) env->hflags |=3D hreg_compute_pmu_hflags_value(env); } =20 -#ifdef CONFIG_DEBUG_TCG void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { uint32_t hflags_current =3D env->hflags; - uint32_t hflags_rebuilt; =20 - *pc =3D env->nip; - *cs_base =3D 0; - *flags =3D hflags_current; - - hflags_rebuilt =3D hreg_compute_hflags_value(env); +#ifdef CONFIG_DEBUG_TCG + uint32_t hflags_rebuilt =3D hreg_compute_hflags_value(env); if (unlikely(hflags_current !=3D hflags_rebuilt)) { cpu_abort(env_cpu(env), "TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n", hflags_current, hflags_rebuilt); } -} #endif =20 + *pc =3D env->nip; + *cs_base =3D 0; + *flags =3D hflags_current; +} + void cpu_interrupt_exittb(CPUState *cs) { /* diff --git a/target/rx/cpu.c b/target/rx/cpu.c index de2e6a22ff..e8b47be675 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -28,6 +28,7 @@ #include "hw/loader.h" #include "fpu/softfloat.h" #include "tcg/debug-assert.h" +#include "accel/tcg/cpu-ops.h" =20 static void rx_cpu_set_pc(CPUState *cs, vaddr value) { @@ -43,6 +44,15 @@ static vaddr rx_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 +void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D FIELD_DP32(0, PSW, PM, env->psw_pm); + *flags =3D FIELD_DP32(*flags, PSW, U, env->psw_u); +} + static void rx_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -201,8 +211,6 @@ static const struct SysemuCPUOps rx_sysemu_ops =3D { .get_phys_page_debug =3D rx_cpu_get_phys_page_debug, }; =20 -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps rx_tcg_ops =3D { /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order =3D TCG_MO_ALL, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 71338aae77..435b2034ff 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -302,6 +302,7 @@ static const Property s390x_cpu_properties[] =3D { =20 #ifdef CONFIG_TCG #include "accel/tcg/cpu-ops.h" +#include "tcg/tcg_s390x.h" =20 static int s390x_cpu_mmu_index(CPUState *cs, bool ifetch) { diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 681237c511..5fb18bf55e 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -26,6 +26,7 @@ #include "migration/vmstate.h" #include "exec/translation-block.h" #include "fpu/softfloat-helpers.h" +#include "accel/tcg/cpu-ops.h" #include "tcg/tcg.h" =20 static void superh_cpu_set_pc(CPUState *cs, vaddr value) @@ -42,6 +43,21 @@ static vaddr superh_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 +void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + /* For a gUSA region, notice the end of the region. */ + *cs_base =3D env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0; + *flags =3D env->flags + | (env->fpscr & TB_FLAG_FPSCR_MASK) + | (env->sr & TB_FLAG_SR_MASK) + | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ +#ifdef CONFIG_USER_ONLY + *flags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#endif +} + static void superh_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -258,8 +274,6 @@ static const struct SysemuCPUOps sh4_sysemu_ops =3D { }; #endif =20 -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps superh_tcg_ops =3D { /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order =3D TCG_MO_ALL, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 0fcac697f6..81b3bb6362 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -23,6 +23,7 @@ #include "exec/translation-block.h" #include "qemu/error-report.h" #include "tcg/debug-assert.h" +#include "accel/tcg/cpu-ops.h" =20 static inline void set_feature(CPUTriCoreState *env, int feature) { @@ -44,6 +45,18 @@ static vaddr tricore_cpu_get_pc(CPUState *cs) return cpu_env(cs)->PC; } =20 +void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + uint32_t new_flags =3D 0; + *pc =3D env->PC; + *cs_base =3D 0; + + new_flags |=3D FIELD_DP32(new_flags, TB_FLAGS, PRIV, + extract32(env->PSW, 10, 2)); + *flags =3D new_flags; +} + static void tricore_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -168,8 +181,6 @@ static const struct SysemuCPUOps tricore_sysemu_ops =3D= { .get_phys_page_debug =3D tricore_cpu_get_phys_page_debug, }; =20 -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps tricore_tcg_ops =3D { /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order =3D TCG_MO_ALL, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 9dcb883208..c78ef9421c 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -35,6 +35,7 @@ #include "qemu/module.h" #include "migration/vmstate.h" #include "hw/qdev-clock.h" +#include "accel/tcg/cpu-ops.h" #ifndef CONFIG_USER_ONLY #include "system/memory.h" #endif @@ -54,6 +55,74 @@ static vaddr xtensa_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 +void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D 0; + *flags |=3D xtensa_get_ring(env); + if (env->sregs[PS] & PS_EXCM) { + *flags |=3D XTENSA_TBFLAG_EXCM; + } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) { + target_ulong lend_dist =3D + env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS)); + + /* + * 0 in the csbase_lend field means that there may not be a loopba= ck + * for any instruction that starts inside this page. Any other val= ue + * means that an instruction that ends at this offset from the page + * start may loop back and will need loopback code to be generated. + * + * lend_dist is 0 when LEND points to the start of the page, but + * no instruction that starts inside this page may end at offset 0, + * so it's still correct. + * + * When an instruction ends at a page boundary it may only start in + * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE + * for the TB that contains this instruction. + */ + if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_s= ize) { + target_ulong lbeg_off =3D env->sregs[LEND] - env->sregs[LBEG]; + + *cs_base =3D lend_dist; + if (lbeg_off < 256) { + *cs_base |=3D lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT; + } + } + } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && + (env->sregs[LITBASE] & 1)) { + *flags |=3D XTENSA_TBFLAG_LITBASE; + } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) { + if (xtensa_get_cintlevel(env) < env->config->debug_level) { + *flags |=3D XTENSA_TBFLAG_DEBUG; + } + if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { + *flags |=3D XTENSA_TBFLAG_ICOUNT; + } + } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { + *flags |=3D env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; + } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER= ) && + (env->sregs[PS] & (PS_WOE | PS_EXCM)) =3D=3D PS_WOE) { + uint32_t windowstart =3D xtensa_replicate_windowstart(env) >> + (env->sregs[WINDOW_BASE] + 1); + uint32_t w =3D ctz32(windowstart | 0x8); + + *flags |=3D (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE; + *flags |=3D extract32(env->sregs[PS], PS_CALLINC_SHIFT, + PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT; + } else { + *flags |=3D 3 << XTENSA_TBFLAG_WINDOW_SHIFT; + } + if (env->yield_needed) { + *flags |=3D XTENSA_TBFLAG_YIELD; + } +} + static void xtensa_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) @@ -229,8 +298,6 @@ static const struct SysemuCPUOps xtensa_sysemu_ops =3D { }; #endif =20 -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps xtensa_tcg_ops =3D { /* Xtensa processors have a weak memory model */ .guest_default_memory_order =3D 0, --=20 2.43.0 From nobody Sat Nov 15 22:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746134771; cv=none; d=zohomail.com; s=zohoarc; b=MMCDNR7jHdRVgIpucmoSfrZRGoPnHTMEoLL/0fZXgJAl7TbDgRggY4N4Zx5IyouUuMOEjclx/QTFrnssNZiUJp5vBLHvBp+BvcbYPyUDSFJfY09SWdECRno7KheoDq58w85fvj1NsPa73hLVFmMDRiZPkQyXZDl1CPYcF//vyg0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746134771; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=nczjiIFvdSzyLMIbhTUNpKK45zc/zVkUXURaYA2dGhw=; b=U+E3kVQUcbgi9o0OLGbu5upy2jQkr1CfWm1EuY8HGm8XJhVprif4p0F0KzV+ACq9XYyfv3Pq0lva3jTTdNQal28JraEYWqIVjH4vZulw8T2YhT3j7Mqj5ZWHkElIgj+AcUP61CFixff6vPzQb99Ttu8BT6837SeJIv9X3W7lHQA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746134771238417.1467301801083; Thu, 1 May 2025 14:26:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAbLs-00014D-HU; Thu, 01 May 2025 17:21:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAbLj-0000xO-5v for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:43 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAbLg-0001YJ-HG for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:42 -0400 Received: by mail-pj1-x102a.google.com with SMTP id 98e67ed59e1d1-3031354f134so1210289a91.3 for ; Thu, 01 May 2025 14:21:40 -0700 (PDT) Received: from stoup.. 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Also move mve_no_pred, a static function only used within cpu_get_tb_cpu_state. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/helper.c | 110 ---------------------------------------- target/arm/tcg/hflags.c | 110 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 110 insertions(+), 110 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 98adeb7086..360e6ac0f5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -30,7 +30,6 @@ #include "qemu/guest-random.h" #ifdef CONFIG_TCG #include "accel/tcg/probe.h" -#include "accel/tcg/cpu-ops.h" #include "semihosting/common-semi.h" #endif #include "cpregs.h" @@ -11424,115 +11423,6 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env) return arm_mmu_idx_el(env, arm_current_el(env)); } =20 -static bool mve_no_pred(CPUARMState *env) -{ - /* - * Return true if there is definitely no predication of MVE - * instructions by VPR or LTPSIZE. (Returning false even if there - * isn't any predication is OK; generated code will just be - * a little worse.) - * If the CPU does not implement MVE then this TB flag is always 0. - * - * NOTE: if you change this logic, the "recalculate s->mve_no_pred" - * logic in gen_update_fp_context() needs to be updated to match. - * - * We do not include the effect of the ECI bits here -- they are - * tracked in other TB flags. This simplifies the logic for - * "when did we emit code that changes the MVE_NO_PRED TB flag - * and thus need to end the TB?". - */ - if (cpu_isar_feature(aa32_mve, env_archcpu(env))) { - return false; - } - if (env->v7m.vpr) { - return false; - } - if (env->v7m.ltpsize < 4) { - return false; - } - return true; -} - -void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) -{ - CPUARMTBFlags flags; - - assert_hflags_rebuild_correctly(env); - flags =3D env->hflags; - - if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) { - *pc =3D env->pc; - if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { - DP_TBFLAG_A64(flags, BTYPE, env->btype); - } - } else { - *pc =3D env->regs[15]; - - if (arm_feature(env, ARM_FEATURE_M)) { - if (arm_feature(env, ARM_FEATURE_M_SECURITY) && - FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) - !=3D env->v7m.secure) { - DP_TBFLAG_M32(flags, FPCCR_S_WRONG, 1); - } - - if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK)= && - (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) || - (env->v7m.secure && - !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))= ) { - /* - * ASPEN is set, but FPCA/SFPA indicate that there is no - * active FP context; we must create a new FP context befo= re - * executing any FP insn. - */ - DP_TBFLAG_M32(flags, NEW_FP_CTXT_NEEDED, 1); - } - - bool is_secure =3D env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MAS= K; - if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { - DP_TBFLAG_M32(flags, LSPACT, 1); - } - - if (mve_no_pred(env)) { - DP_TBFLAG_M32(flags, MVE_NO_PRED, 1); - } - } else { - /* - * Note that XSCALE_CPAR shares bits with VECSTRIDE. - * Note that VECLEN+VECSTRIDE are RES0 for M-profile. - */ - if (arm_feature(env, ARM_FEATURE_XSCALE)) { - DP_TBFLAG_A32(flags, XSCALE_CPAR, env->cp15.c15_cpar); - } else { - DP_TBFLAG_A32(flags, VECLEN, env->vfp.vec_len); - DP_TBFLAG_A32(flags, VECSTRIDE, env->vfp.vec_stride); - } - if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { - DP_TBFLAG_A32(flags, VFPEN, 1); - } - } - - DP_TBFLAG_AM32(flags, THUMB, env->thumb); - DP_TBFLAG_AM32(flags, CONDEXEC, env->condexec_bits); - } - - /* - * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine - * states defined in the ARM ARM for software singlestep: - * SS_ACTIVE PSTATE.SS State - * 0 x Inactive (the TB flag for SS is always 0) - * 1 0 Active-pending - * 1 1 Active-not-pending - * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB. - */ - if (EX_TBFLAG_ANY(flags, SS_ACTIVE) && (env->pstate & PSTATE_SS)) { - DP_TBFLAG_ANY(flags, PSTATE__SS, 1); - } - - *pflags =3D flags.flags; - *cs_base =3D flags.flags2; -} - #ifdef TARGET_AARCH64 /* * The manual says that when SVE is enabled and VQ is widened the diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index e51d9f7b15..e530f65ed7 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -10,6 +10,7 @@ #include "internals.h" #include "cpu-features.h" #include "exec/helper-proto.h" +#include "accel/tcg/cpu-ops.h" #include "cpregs.h" =20 static inline bool fgt_svc(CPUARMState *env, int el) @@ -513,3 +514,112 @@ void assert_hflags_rebuild_correctly(CPUARMState *env) } #endif } + +static bool mve_no_pred(CPUARMState *env) +{ + /* + * Return true if there is definitely no predication of MVE + * instructions by VPR or LTPSIZE. (Returning false even if there + * isn't any predication is OK; generated code will just be + * a little worse.) + * If the CPU does not implement MVE then this TB flag is always 0. + * + * NOTE: if you change this logic, the "recalculate s->mve_no_pred" + * logic in gen_update_fp_context() needs to be updated to match. + * + * We do not include the effect of the ECI bits here -- they are + * tracked in other TB flags. This simplifies the logic for + * "when did we emit code that changes the MVE_NO_PRED TB flag + * and thus need to end the TB?". + */ + if (cpu_isar_feature(aa32_mve, env_archcpu(env))) { + return false; + } + if (env->v7m.vpr) { + return false; + } + if (env->v7m.ltpsize < 4) { + return false; + } + return true; +} + +void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + CPUARMTBFlags flags; + + assert_hflags_rebuild_correctly(env); + flags =3D env->hflags; + + if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) { + *pc =3D env->pc; + if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { + DP_TBFLAG_A64(flags, BTYPE, env->btype); + } + } else { + *pc =3D env->regs[15]; + + if (arm_feature(env, ARM_FEATURE_M)) { + if (arm_feature(env, ARM_FEATURE_M_SECURITY) && + FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) + !=3D env->v7m.secure) { + DP_TBFLAG_M32(flags, FPCCR_S_WRONG, 1); + } + + if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK)= && + (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) || + (env->v7m.secure && + !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))= ) { + /* + * ASPEN is set, but FPCA/SFPA indicate that there is no + * active FP context; we must create a new FP context befo= re + * executing any FP insn. + */ + DP_TBFLAG_M32(flags, NEW_FP_CTXT_NEEDED, 1); + } + + bool is_secure =3D env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MAS= K; + if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { + DP_TBFLAG_M32(flags, LSPACT, 1); + } + + if (mve_no_pred(env)) { + DP_TBFLAG_M32(flags, MVE_NO_PRED, 1); + } + } else { + /* + * Note that XSCALE_CPAR shares bits with VECSTRIDE. + * Note that VECLEN+VECSTRIDE are RES0 for M-profile. + */ + if (arm_feature(env, ARM_FEATURE_XSCALE)) { + DP_TBFLAG_A32(flags, XSCALE_CPAR, env->cp15.c15_cpar); + } else { + DP_TBFLAG_A32(flags, VECLEN, env->vfp.vec_len); + DP_TBFLAG_A32(flags, VECSTRIDE, env->vfp.vec_stride); + } + if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { + DP_TBFLAG_A32(flags, VFPEN, 1); + } + } + + DP_TBFLAG_AM32(flags, THUMB, env->thumb); + DP_TBFLAG_AM32(flags, CONDEXEC, env->condexec_bits); + } + + /* + * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine + * states defined in the ARM ARM for software singlestep: + * SS_ACTIVE PSTATE.SS State + * 0 x Inactive (the TB flag for SS is always 0) + * 1 0 Active-pending + * 1 1 Active-not-pending + * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB. + */ + if (EX_TBFLAG_ANY(flags, SS_ACTIVE) && (env->pstate & PSTATE_SS)) { + DP_TBFLAG_ANY(flags, PSTATE__SS, 1); + } + + *pflags =3D flags.flags; + *cs_base =3D flags.flags2; +} --=20 2.43.0 From nobody Sat Nov 15 22:35:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746135047; cv=none; d=zohomail.com; s=zohoarc; b=SAaE6CSKY3bfKj6eN3M1lZqd9egh9L2iNO4NV7ZatNLU1yyp7PZxhdH2BBqbOOICU6lHAZw14J1g74lg9wsKE1pmr8Jx8a7xPScQdYXQqFF8uhl5SYLYTtNpFlyRLn3NpR327aKudPO1Jz0JQsUopwCTavObEhalESyR7swX+xg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746135047; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-30a476267e0sm1384573a91.39.2025.05.01.14.21.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 May 2025 14:21:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746134500; x=1746739300; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OXwcdw9KH2AB3C2RsE6WjSiCvh4jeWGeibDuA8DDVDs=; b=jvopjJMImp2yERBUOFE3viwgzwx4ylQsz7ALjjnJlL7NB75QXOg+I20wcM2TWe6PSL ie1LPa+Y2/ueVIMvCniHN4D9nwIUL7krd6McBbzyvfA9yzWA2Ev0szl243qt9r3nl4c2 vfjBO75mVPsOtV5BSKvm9oqlOcI1X4dznwKnAKGA+LMTA/4Xg36AvXNDcCgpTBnEOldN 8MUWPT+AOkaCSabYR1ZGwyd2S+wdlXIlVcPGmqqQ7Tkt6iwm9YsP3W3Y62KiugCRDMnV WCF8SMEInDl08ORbq9fQoLW+LoDkTZBAMoZy2QtgCBbTt/px+JFUg1L4UZ0Gb3YOt/8f TCkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746134500; x=1746739300; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OXwcdw9KH2AB3C2RsE6WjSiCvh4jeWGeibDuA8DDVDs=; b=a3UlaP4MmY9W/49FEhJLpHTjU3xogfm/fnSVSmSkFmDY55w609kK038mBKN0Vt/U2v jTAJEo+IqotHMDVsfNprVLSv+iRQb/lPPWpzTOfnr8YRslqK0ox7ONFbZDHqWl0UsgLL gY7yczAOdDeu4jdjJszO0/1oxCreo0lEIe8Q7Vj8AWpfqRnX0MS3tv05GP/Jbjl4pYoF qLcOd4kY/CtVlPy5sT7zT3tr4LuUlAJeQqxxzPECqGscL9ZqhZHfcDolkaj7NjB1g3Sd GvqJime5koLtGJ3lUQcRYAnrsxTVAKAy4G4ORlxKTzN4iPqKGLNcDt9HotZOj+oHYqtn bFSA== X-Gm-Message-State: AOJu0YyL6HSWG1/BObgbl61hTqcMZZ/tY4bOwosr4i0ODDNAswShqO7l g3J5caSoWvdTuHhOX3ITb/OAc/EGiT5WTZxMqnIwhuBzX9PH9TI+LrK9iqtQIFMhBwZgy81fEWx y X-Gm-Gg: ASbGncsFIi2oaV+iTMxHpWJ2VlLGjFM3rUZTjUbPLSZTjNCSNyTU7mxjjCM3p6Mn7xE GdtTu4O7DD6FkRY7RO5AjLeDSm5ok+OLvJ9Fd92u//sXBHXpH7CLPjWF32x6z8Fk5hYiQGpvuGW lrRX4T5jvMwijTGK0iRovDCeuvguu12X1vxtXXzqM0AyTb764tnd4UOI2788Q6QRUwqqjYytiO2 ZJrfAcahRxYJD57W1o1VYOWo4ksrlfgMaxE3AgeyBmwpNKvCwDZ6f18txqwa03VbcG3h1OuxDfQ uz6nojzQhykg0mr2gsZ9n9F6+p1upLtQsx8D+nokdvZzlNfEKfg82vyRfoqF82chvLBjupAmdE8 = X-Google-Smtp-Source: AGHT+IGXujHSgVEVHXowV4JIXG2C2kf6Mh6g31r8StoGlrDgbBb3f+AJOoocXatNo7dXLy9uxTF3pg== X-Received: by 2002:a17:90b:2644:b0:2ff:6167:e92d with SMTP id 98e67ed59e1d1-30a4e6adf1bmr753766a91.32.1746134499701; Thu, 01 May 2025 14:21:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 30/59] target/arm: Unexport assert_hflags_rebuild_correctly Date: Thu, 1 May 2025 14:20:44 -0700 Message-ID: <20250501212113.2961531-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746135050891019100 Content-Type: text/plain; charset="utf-8" This function is no longer used outside of hflags.c. We can remove the stub as well. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/internals.h | 2 -- target/arm/tcg-stubs.c | 4 ---- target/arm/tcg/hflags.c | 2 +- 3 files changed, 1 insertion(+), 7 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 4d3d84ffeb..382a4d1015 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1906,8 +1906,6 @@ static inline bool arm_fgt_active(CPUARMState *env, i= nt el) (!arm_feature(env, ARM_FEATURE_EL3) || (env->cp15.scr_el3 & SCR_FG= TEN)); } =20 -void assert_hflags_rebuild_correctly(CPUARMState *env); - /* * Although the ARM implementation of hardware assisted debugging * allows for different breakpoints per-core, the current GDB diff --git a/target/arm/tcg-stubs.c b/target/arm/tcg-stubs.c index 93a15cad61..5e5166c049 100644 --- a/target/arm/tcg-stubs.c +++ b/target/arm/tcg-stubs.c @@ -21,10 +21,6 @@ void raise_exception_ra(CPUARMState *env, uint32_t excp,= uint32_t syndrome, { g_assert_not_reached(); } -/* Temporarily while cpu_get_tb_cpu_state() is still in common code */ -void assert_hflags_rebuild_correctly(CPUARMState *env) -{ -} =20 /* TLBI insns are only used by TCG, so we don't need to do anything for KV= M */ void define_tlb_insn_regs(ARMCPU *cpu) diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index e530f65ed7..5315264c28 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -499,7 +499,7 @@ void HELPER(rebuild_hflags_a64)(CPUARMState *env, int e= l) env->hflags =3D rebuild_hflags_a64(env, el, fp_el, mmu_idx); } =20 -void assert_hflags_rebuild_correctly(CPUARMState *env) +static void assert_hflags_rebuild_correctly(CPUARMState *env) { #ifdef CONFIG_DEBUG_TCG CPUARMTBFlags c =3D env->hflags; --=20 2.43.0 From nobody Sat Nov 15 22:35:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746134929; cv=none; d=zohomail.com; s=zohoarc; b=K7GTT9bFOxCyVNJWUxTAFXH3h3RL+gE/nzAlU2osNTRP76mHs1vMaac3rq258AnSoTNkHaKpMTmXwAuyYHr+BSmz/Q4HF15C68WHhvMs8B3TJQKPAQOL3DMczNTUkEzomfoSLw5aLRWMDj6sidUAN9uQFW+Wn2MK/tcb7VwzpoM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746134929; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=SpjRSP299/Pwnlg0y40yyEXNMYiNnhME3gCevLegoTY=; b=NWenLeB2cr4DshenHtZxj6NF0MI28QaHysL37otkqrcXAciAmMx9Zrm+R2YACKsvWuSlFK4ap/+Oz/GfvyPwCY07W/80+u7BUODXtTcq4UVCe9zkQbi7iMz4mRqPXis8AoSSwZ0QOOBilhkzhzPy6IWKnWpV+xqjRu8GG0WTnJI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746134929119650.1641804593538; Thu, 1 May 2025 14:28:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAbM1-00019n-6Z; Thu, 01 May 2025 17:22:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAbLk-0000yo-Ku for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:45 -0400 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAbLi-0001Yw-53 for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:44 -0400 Received: by mail-pg1-x52c.google.com with SMTP id 41be03b00d2f7-b041afe0ee1so1365336a12.1 for ; Thu, 01 May 2025 14:21:41 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-30a476267e0sm1384573a91.39.2025.05.01.14.21.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 May 2025 14:21:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746134500; x=1746739300; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SpjRSP299/Pwnlg0y40yyEXNMYiNnhME3gCevLegoTY=; b=WTg+LwZPqm8YCo4SI3pV5buhkKl9QCRjasueFqFK1gRtkKk/2JdBMDgr7/+9Sp23oq QoYbTnp6oahzXI+6fYH7Lz+jRh5DxYWfqkw1PcTkwvJVPVwUeq/ybU+TFXlh7IG2zjv/ XQI0NeDVS7bHhRgFwKvEEn4Q2Iqw0JdhFKFhc1LoGWRDtksvoop3c26D4WNomhzBnwHN NIOBXJd+A7Z/Oc/CXDll5ofvSJBsRIkZW3BNlyrxb7m1DJYZT+VfbSHHadcQUNHBX7FJ w8LAPwv3WbHuyWa6Bihg1iW7rzcvO1Uuvu2is1nY0UYYftzHu7002ovNMOdPDSm60Ffb NBQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746134500; x=1746739300; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SpjRSP299/Pwnlg0y40yyEXNMYiNnhME3gCevLegoTY=; b=XbP58ZX5I8P0a8xNxDgJiASp2iT7SQoB8N3hS9je6dneeDgnbgqYS2n2JoLdRRNUSW kZ1KAKqQp091eK17/brkG2PPwWZEVm0jTFfFWRkBjLsnMD6usy08bWOI1iV3spL4nfAw ivT06sRARbZnlPwJzCzw2xbCCpY4AjnWQb3SB8z+0KlQMZstfxisb3ttqo/u3cfgYcfl P6zvlqa1odcS2Wz6RZLdy8cHc48mWy0xxr/CQftKlh5XMgwWFZNKviPZERzx4Jt/uaFG DI8Oefclb+cX0JmGcZ2+38k2sMWdhgvz3mqdBmh81XgZAIA8jruhIZ4Gk/OwcRHxUhRT BW4g== X-Gm-Message-State: AOJu0Yx9PNcpNQhvvfcRDgUdH4SsB/+uObyLbF/6JU/ngEHzZXaVkDYJ t4SRjQ0/lfVJ0JCXxnDfh7DmWrPbJOSLSlvPgkFiW8S97nFG9q81mSMZ0Io5SZE9BXpvnd/4APf X X-Gm-Gg: ASbGncsW2bEH08l1aGyQNsoSsCF7eKLVyJk1gMlmqkepRrv27s7Md7SmjJ21qcI5ZOn MfARmhSnrsmAua5FLstRjUBU73Iv9BLLFc8985o5q2WnLQg/r4bwgUCD4Ho7am526tb2TE1jDmL 3iA0V7sKjgY2A8b9C+5rlvmR7DO4O8x5wgUOKuawBpW1NoIkd8T2Qje6kNO1+CLv0sH2S5NThVx CtPe1//XYXy0poS0l+gVg5Evm1tZe+qa/JGSdqpwCkoeY1XDnwdl1R8O0CjOMnuGeMAEjz8q3L8 AMICRZLbs9RljKHJcEmyTz/U7+/u2kiexJlHDoRLaIdQH0Nkx/hAqZrBQlBe7kJ7hWCCEYDY+08 = X-Google-Smtp-Source: AGHT+IHFsKGUtIhT1JXqo5MPrWz4ctJEyy/RU/9Dqqj8nu6dXNfYDqX9ScgDwxzkOMUM9Jop3gVSkA== X-Received: by 2002:a17:90b:2d48:b0:2fe:8c22:48b0 with SMTP id 98e67ed59e1d1-30a4e5c6031mr938847a91.15.1746134500457; Thu, 01 May 2025 14:21:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 31/59] target/riscv: Move cpu_get_tb_cpu_state to tcg-cpu.c Date: Thu, 1 May 2025 14:20:45 -0700 Message-ID: <20250501212113.2961531-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746134931058124100 This function is only relevant to tcg. Move it to a tcg-specific file. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/riscv/cpu_helper.c | 97 ------------------------------------- target/riscv/tcg/tcg-cpu.c | 98 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 98 insertions(+), 97 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f2e90a9889..d5039f69a9 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -135,103 +135,6 @@ bool riscv_env_smode_dbltrp_enabled(CPURISCVState *en= v, bool virt) #endif } =20 -void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) -{ - RISCVCPU *cpu =3D env_archcpu(env); - RISCVExtStatus fs, vs; - uint32_t flags =3D 0; - bool pm_signext =3D riscv_cpu_virt_mem_enabled(env); - - *pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc; - *cs_base =3D 0; - - if (cpu->cfg.ext_zve32x) { - /* - * If env->vl equals to VLMAX, we can use generic vector operation - * expanders (GVEC) to accerlate the vector operations. - * However, as LMUL could be a fractional number. The maximum - * vector size can be operated might be less than 8 bytes, - * which is not supported by GVEC. So we set vl_eq_vlmax flag to t= rue - * only when maxsz >=3D 8 bytes. - */ - - /* lmul encoded as in DisasContext::lmul */ - int8_t lmul =3D sextract32(FIELD_EX64(env->vtype, VTYPE, VLMUL), 0= , 3); - uint32_t vsew =3D FIELD_EX64(env->vtype, VTYPE, VSEW); - uint32_t vlmax =3D vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul); - uint32_t maxsz =3D vlmax << vsew; - bool vl_eq_vlmax =3D (env->vstart =3D=3D 0) && (vlmax =3D=3D env->= vl) && - (maxsz >=3D 8); - flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); - flags =3D FIELD_DP32(flags, TB_FLAGS, SEW, vsew); - flags =3D FIELD_DP32(flags, TB_FLAGS, LMUL, - FIELD_EX64(env->vtype, VTYPE, VLMUL)); - flags =3D FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); - flags =3D FIELD_DP32(flags, TB_FLAGS, VTA, - FIELD_EX64(env->vtype, VTYPE, VTA)); - flags =3D FIELD_DP32(flags, TB_FLAGS, VMA, - FIELD_EX64(env->vtype, VTYPE, VMA)); - flags =3D FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart = =3D=3D 0); - } else { - flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, 1); - } - - if (cpu_get_fcfien(env)) { - /* - * For Forward CFI, only the expectation of a lpad at - * the start of the block is tracked via env->elp. env->elp - * is turned on during jalr translation. - */ - flags =3D FIELD_DP32(flags, TB_FLAGS, FCFI_LP_EXPECTED, env->elp); - flags =3D FIELD_DP32(flags, TB_FLAGS, FCFI_ENABLED, 1); - } - - if (cpu_get_bcfien(env)) { - flags =3D FIELD_DP32(flags, TB_FLAGS, BCFI_ENABLED, 1); - } - -#ifdef CONFIG_USER_ONLY - fs =3D EXT_STATUS_DIRTY; - vs =3D EXT_STATUS_DIRTY; -#else - flags =3D FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv); - - flags |=3D riscv_env_mmu_index(env, 0); - fs =3D get_field(env->mstatus, MSTATUS_FS); - vs =3D get_field(env->mstatus, MSTATUS_VS); - - if (env->virt_enabled) { - flags =3D FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); - /* - * Merge DISABLED and !DIRTY states using MIN. - * We will set both fields when dirtying. - */ - fs =3D MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); - vs =3D MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); - } - - /* With Zfinx, floating point is enabled/disabled by Smstateen. */ - if (!riscv_has_ext(env, RVF)) { - fs =3D (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) =3D=3D RISCV_EXC= P_NONE) - ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED; - } - - if (cpu->cfg.debug && !icount_enabled()) { - flags =3D FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enab= led); - } -#endif - - flags =3D FIELD_DP32(flags, TB_FLAGS, FS, fs); - flags =3D FIELD_DP32(flags, TB_FLAGS, VS, vs); - flags =3D FIELD_DP32(flags, TB_FLAGS, XL, env->xl); - flags =3D FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); - flags =3D FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env)); - flags =3D FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); - - *pflags =3D flags; -} - RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env) { #ifndef CONFIG_USER_ONLY diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 50782e0f0e..e67de7dfe2 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -36,6 +36,7 @@ #ifndef CONFIG_USER_ONLY #include "hw/boards.h" #include "system/tcg.h" +#include "exec/icount.h" #endif =20 /* Hash that stores user set extensions */ @@ -97,6 +98,103 @@ static int riscv_cpu_mmu_index(CPUState *cs, bool ifetc= h) return riscv_env_mmu_index(cpu_env(cs), ifetch); } =20 +void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + RISCVCPU *cpu =3D env_archcpu(env); + RISCVExtStatus fs, vs; + uint32_t flags =3D 0; + bool pm_signext =3D riscv_cpu_virt_mem_enabled(env); + + *pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc; + *cs_base =3D 0; + + if (cpu->cfg.ext_zve32x) { + /* + * If env->vl equals to VLMAX, we can use generic vector operation + * expanders (GVEC) to accerlate the vector operations. + * However, as LMUL could be a fractional number. The maximum + * vector size can be operated might be less than 8 bytes, + * which is not supported by GVEC. So we set vl_eq_vlmax flag to t= rue + * only when maxsz >=3D 8 bytes. + */ + + /* lmul encoded as in DisasContext::lmul */ + int8_t lmul =3D sextract32(FIELD_EX64(env->vtype, VTYPE, VLMUL), 0= , 3); + uint32_t vsew =3D FIELD_EX64(env->vtype, VTYPE, VSEW); + uint32_t vlmax =3D vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul); + uint32_t maxsz =3D vlmax << vsew; + bool vl_eq_vlmax =3D (env->vstart =3D=3D 0) && (vlmax =3D=3D env->= vl) && + (maxsz >=3D 8); + flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); + flags =3D FIELD_DP32(flags, TB_FLAGS, SEW, vsew); + flags =3D FIELD_DP32(flags, TB_FLAGS, LMUL, + FIELD_EX64(env->vtype, VTYPE, VLMUL)); + flags =3D FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); + flags =3D FIELD_DP32(flags, TB_FLAGS, VTA, + FIELD_EX64(env->vtype, VTYPE, VTA)); + flags =3D FIELD_DP32(flags, TB_FLAGS, VMA, + FIELD_EX64(env->vtype, VTYPE, VMA)); + flags =3D FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart = =3D=3D 0); + } else { + flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, 1); + } + + if (cpu_get_fcfien(env)) { + /* + * For Forward CFI, only the expectation of a lpad at + * the start of the block is tracked via env->elp. env->elp + * is turned on during jalr translation. + */ + flags =3D FIELD_DP32(flags, TB_FLAGS, FCFI_LP_EXPECTED, env->elp); + flags =3D FIELD_DP32(flags, TB_FLAGS, FCFI_ENABLED, 1); + } + + if (cpu_get_bcfien(env)) { + flags =3D FIELD_DP32(flags, TB_FLAGS, BCFI_ENABLED, 1); + } + +#ifdef CONFIG_USER_ONLY + fs =3D EXT_STATUS_DIRTY; + vs =3D EXT_STATUS_DIRTY; +#else + flags =3D FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv); + + flags |=3D riscv_env_mmu_index(env, 0); + fs =3D get_field(env->mstatus, MSTATUS_FS); + vs =3D get_field(env->mstatus, MSTATUS_VS); + + if (env->virt_enabled) { + flags =3D FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); + /* + * Merge DISABLED and !DIRTY states using MIN. + * We will set both fields when dirtying. + */ + fs =3D MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); + vs =3D MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); + } + + /* With Zfinx, floating point is enabled/disabled by Smstateen. */ + if (!riscv_has_ext(env, RVF)) { + fs =3D (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) =3D=3D RISCV_EXC= P_NONE) + ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED; + } + + if (cpu->cfg.debug && !icount_enabled()) { + flags =3D FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enab= led); + } +#endif + + flags =3D FIELD_DP32(flags, TB_FLAGS, FS, fs); + flags =3D FIELD_DP32(flags, TB_FLAGS, VS, vs); + flags =3D FIELD_DP32(flags, TB_FLAGS, XL, env->xl); + flags =3D FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); + flags =3D FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env)); + flags =3D FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); + + *pflags =3D flags; +} + static void riscv_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { --=20 2.43.0 From nobody Sat Nov 15 22:35:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746134643; cv=none; d=zohomail.com; s=zohoarc; b=YRCPunAaGmWPK86wSzHnJX86fmELDTtpnhTrZt1EHxgg4p4hctw5h7mDEbWYsycA6Z1aLyTXccA5JO8cZHs5u70XLqHFhAjw9J78050ESpEw5VrDs/cq8l6caeMD4R7a3uF1t/JgQfOF9voNrsAMNoFQq0hS65OiwQ2OeDSgzBA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746134643; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=pPC/txOy40AS11MtmiBoTw9tZsNxkjtBBKONAc1sKT4=; b=LJbY6x86TaLjvlgKIj1jnBC36WJzTC/5qj+AJdZdNNjG7gUUmR2KpT7ZN9mSw/WxhB1XHCfX9JHGu7J1fGFfEs+wJSgj2fB8ps9IrS5eW9783hdgKXlXNPl7fUrIIg3xhGCG3UOQaq5EkDmj4F7y3QZcbFl5HDw4Sie7wedamxg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746134643488678.603469894501; Thu, 1 May 2025 14:24:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAbLx-00017j-T6; Thu, 01 May 2025 17:21:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAbLn-00010n-27 for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:47 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAbLj-0001ZN-BO for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:46 -0400 Received: by mail-pj1-x102d.google.com with SMTP id 98e67ed59e1d1-3012a0c8496so1210583a91.2 for ; Thu, 01 May 2025 14:21:42 -0700 (PDT) Received: from stoup.. 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Include a cflags field in TCGTBCPUState, not filled in by cpu_get_tb_cpu_state, but used by all callers. This fills a hole in the structure and is useful in some subroutines. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/accel/tcg/cpu-ops.h | 4 +-- include/accel/tcg/tb-cpu-state.h | 18 ++++++++++ accel/tcg/cpu-exec.c | 56 +++++++++++++------------------- accel/tcg/translate-all.c | 8 ++--- target/alpha/cpu.c | 13 ++++---- target/arm/tcg/hflags.c | 17 ++++++---- target/avr/cpu.c | 9 ++--- target/hexagon/cpu.c | 15 +++++---- target/hppa/cpu.c | 10 +++--- target/i386/tcg/tcg-cpu.c | 19 +++++++---- target/loongarch/cpu.c | 20 +++++++----- target/m68k/cpu.c | 21 +++++++----- target/microblaze/cpu.c | 13 +++++--- target/mips/cpu.c | 14 ++++---- target/openrisc/cpu.c | 16 +++++---- target/ppc/helper_regs.c | 8 ++--- target/riscv/tcg/tcg-cpu.c | 12 +++---- target/rx/cpu.c | 14 ++++---- target/s390x/cpu.c | 14 ++++---- target/sh4/cpu.c | 22 +++++++++---- target/sparc/cpu.c | 17 ++++++---- target/tricore/cpu.c | 14 ++++---- target/xtensa/cpu.c | 40 +++++++++++++---------- 23 files changed, 218 insertions(+), 176 deletions(-) create mode 100644 include/accel/tcg/tb-cpu-state.h diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index f5e5746976..43a39c2e13 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -16,10 +16,10 @@ #include "exec/memop.h" #include "exec/mmu-access-type.h" #include "exec/vaddr.h" +#include "accel/tcg/tb-cpu-state.h" #include "tcg/tcg-mo.h" =20 -void cpu_get_tb_cpu_state(CPUArchState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags); +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs); =20 struct TCGCPUOps { /** diff --git a/include/accel/tcg/tb-cpu-state.h b/include/accel/tcg/tb-cpu-st= ate.h new file mode 100644 index 0000000000..8f912900ca --- /dev/null +++ b/include/accel/tcg/tb-cpu-state.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: LGPL-2.1-or-later */ +/* + * Definition of TCGTBCPUState. + */ + +#ifndef EXEC_TB_CPU_STATE_H +#define EXEC_TB_CPU_STATE_H + +#include "exec/vaddr.h" + +typedef struct TCGTBCPUState { + vaddr pc; + uint32_t flags; + uint32_t cflags; + uint64_t cs_base; +} TCGTBCPUState; + +#endif diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index c21c5d202d..f7e7e7949d 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -385,9 +385,6 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) { CPUState *cpu =3D env_cpu(env); TranslationBlock *tb; - vaddr pc; - uint64_t cs_base; - uint32_t flags, cflags; =20 /* * By definition we've just finished a TB, so I/O is OK. @@ -397,20 +394,21 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) * The next TB, if we chain to it, will clear the flag again. */ cpu->neg.can_do_io =3D true; - cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); =20 - cflags =3D curr_cflags(cpu); - if (check_for_breakpoints(cpu, pc, &cflags)) { + TCGTBCPUState s =3D cpu_get_tb_cpu_state(cpu); + s.cflags =3D curr_cflags(cpu); + + if (check_for_breakpoints(cpu, s.pc, &s.cflags)) { cpu_loop_exit(cpu); } =20 - tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); + tb =3D tb_lookup(cpu, s.pc, s.cs_base, s.flags, s.cflags); if (tb =3D=3D NULL) { return tcg_code_gen_epilogue; } =20 if (qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC)) { - log_cpu_exec(pc, cpu, tb); + log_cpu_exec(s.pc, cpu, tb); } =20 return tb->tc.ptr; @@ -560,11 +558,7 @@ static void cpu_exec_longjmp_cleanup(CPUState *cpu) =20 void cpu_exec_step_atomic(CPUState *cpu) { - CPUArchState *env =3D cpu_env(cpu); TranslationBlock *tb; - vaddr pc; - uint64_t cs_base; - uint32_t flags, cflags; int tb_exit; =20 if (sigsetjmp(cpu->jmp_env, 0) =3D=3D 0) { @@ -573,13 +567,13 @@ void cpu_exec_step_atomic(CPUState *cpu) g_assert(!cpu->running); cpu->running =3D true; =20 - cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); + TCGTBCPUState s =3D cpu_get_tb_cpu_state(cpu); + s.cflags =3D curr_cflags(cpu); =20 - cflags =3D curr_cflags(cpu); /* Execute in a serial context. */ - cflags &=3D ~CF_PARALLEL; + s.cflags &=3D ~CF_PARALLEL; /* After 1 insn, return and release the exclusive lock. */ - cflags |=3D CF_NO_GOTO_TB | CF_NO_GOTO_PTR | 1; + s.cflags |=3D CF_NO_GOTO_TB | CF_NO_GOTO_PTR | 1; /* * No need to check_for_breakpoints here. * We only arrive in cpu_exec_step_atomic after beginning execution @@ -587,16 +581,16 @@ void cpu_exec_step_atomic(CPUState *cpu) * Any breakpoint for this insn will have been recognized earlier. */ =20 - tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); + tb =3D tb_lookup(cpu, s.pc, s.cs_base, s.flags, s.cflags); if (tb =3D=3D NULL) { mmap_lock(); - tb =3D tb_gen_code(cpu, pc, cs_base, flags, cflags); + tb =3D tb_gen_code(cpu, s.pc, s.cs_base, s.flags, s.cflags); mmap_unlock(); } =20 cpu_exec_enter(cpu); /* execute the generated code */ - trace_exec_tb(tb, pc); + trace_exec_tb(tb, s.pc); cpu_tb_exec(cpu, tb, &tb_exit); cpu_exec_exit(cpu); } else { @@ -941,11 +935,8 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc) =20 while (!cpu_handle_interrupt(cpu, &last_tb)) { TranslationBlock *tb; - vaddr pc; - uint64_t cs_base; - uint32_t flags, cflags; - - cpu_get_tb_cpu_state(cpu_env(cpu), &pc, &cs_base, &flags); + TCGTBCPUState s =3D cpu_get_tb_cpu_state(cpu); + s.cflags =3D cpu->cflags_next_tb; =20 /* * When requested, use an exact setting for cflags for the next @@ -954,33 +945,32 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc) * have CF_INVALID set, -1 is a convenient invalid value that * does not require tcg headers for cpu_common_reset. */ - cflags =3D cpu->cflags_next_tb; - if (cflags =3D=3D -1) { - cflags =3D curr_cflags(cpu); + if (s.cflags =3D=3D -1) { + s.cflags =3D curr_cflags(cpu); } else { cpu->cflags_next_tb =3D -1; } =20 - if (check_for_breakpoints(cpu, pc, &cflags)) { + if (check_for_breakpoints(cpu, s.pc, &s.cflags)) { break; } =20 - tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); + tb =3D tb_lookup(cpu, s.pc, s.cs_base, s.flags, s.cflags); if (tb =3D=3D NULL) { CPUJumpCache *jc; uint32_t h; =20 mmap_lock(); - tb =3D tb_gen_code(cpu, pc, cs_base, flags, cflags); + tb =3D tb_gen_code(cpu, s.pc, s.cs_base, s.flags, s.cflags= ); mmap_unlock(); =20 /* * We add the TB in the virtual pc hash table * for the fast lookup */ - h =3D tb_jmp_cache_hash_func(pc); + h =3D tb_jmp_cache_hash_func(s.pc); jc =3D cpu->tb_jmp_cache; - jc->array[h].pc =3D pc; + jc->array[h].pc =3D s.pc; qatomic_set(&jc->array[h].tb, tb); } =20 @@ -1000,7 +990,7 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc) tb_add_jump(last_tb, tb_exit, tb); } =20 - cpu_loop_exec_tb(cpu, tb, pc, &last_tb, &tb_exit); + cpu_loop_exec_tb(cpu, tb, s.pc, &last_tb, &tb_exit); =20 /* Try to align the host and virtual clocks if the guest is in advance */ diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 31c7f9927f..f2766cedfc 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -590,13 +590,9 @@ void tb_check_watchpoint(CPUState *cpu, uintptr_t reta= ddr) /* The exception probably happened in a helper. The CPU state sho= uld have been saved before calling it. Fetch the PC from there. */ CPUArchState *env =3D cpu_env(cpu); - vaddr pc; - uint64_t cs_base; - tb_page_addr_t addr; - uint32_t flags; + TCGTBCPUState s =3D cpu_get_tb_cpu_state(cpu); + tb_page_addr_t addr =3D get_page_addr_code(env, s.pc); =20 - cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); - addr =3D get_page_addr_code(env, pc); if (addr !=3D -1) { tb_invalidate_phys_range(cpu, addr, addr); } diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 134806e755..90e3a2e748 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -41,15 +41,16 @@ static vaddr alpha_cpu_get_pc(CPUState *cs) return env->pc; } =20 -void cpu_get_tb_cpu_state(CPUAlphaState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->pc; - *cs_base =3D 0; - *pflags =3D env->flags & ENV_FLAG_TB_MASK; + CPUAlphaState *env =3D cpu_env(cs); + uint32_t flags =3D env->flags & ENV_FLAG_TB_MASK; + #ifdef CONFIG_USER_ONLY - *pflags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; + flags |=3D TB_FLAG_UNALIGN * !cs->prctl_unalign_sigbus; #endif + + return (TCGTBCPUState){ .pc =3D env->pc, .flags =3D flags }; } =20 static void alpha_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index 5315264c28..b49381924b 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -10,6 +10,7 @@ #include "internals.h" #include "cpu-features.h" #include "exec/helper-proto.h" +#include "exec/translation-block.h" #include "accel/tcg/cpu-ops.h" #include "cpregs.h" =20 @@ -544,21 +545,22 @@ static bool mve_no_pred(CPUARMState *env) return true; } =20 -void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPUARMState *env =3D cpu_env(cs); CPUARMTBFlags flags; + vaddr pc; =20 assert_hflags_rebuild_correctly(env); flags =3D env->hflags; =20 if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) { - *pc =3D env->pc; + pc =3D env->pc; if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { DP_TBFLAG_A64(flags, BTYPE, env->btype); } } else { - *pc =3D env->regs[15]; + pc =3D env->regs[15]; =20 if (arm_feature(env, ARM_FEATURE_M)) { if (arm_feature(env, ARM_FEATURE_M_SECURITY) && @@ -620,6 +622,9 @@ void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, DP_TBFLAG_ANY(flags, PSTATE__SS, 1); } =20 - *pflags =3D flags.flags; - *cs_base =3D flags.flags2; + return (TCGTBCPUState){ + .pc =3D pc, + .flags =3D flags.flags, + .cs_base =3D flags.flags2, + }; } diff --git a/target/avr/cpu.c b/target/avr/cpu.c index d9fecb272e..683195b61d 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -54,14 +54,11 @@ static int avr_cpu_mmu_index(CPUState *cs, bool ifetch) return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; } =20 -void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPUAVRState *env =3D cpu_env(cs); uint32_t flags =3D 0; =20 - *pc =3D env->pc_w * 2; - *cs_base =3D 0; - if (env->fullacc) { flags |=3D TB_FLAGS_FULL_ACCESS; } @@ -69,7 +66,7 @@ void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc, flags |=3D TB_FLAGS_SKIP; } =20 - *pflags =3D flags; + return (TCGTBCPUState){ .pc =3D env->pc_w * 2, .flags =3D flags }; } =20 static void avr_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 2272f1222b..a7f76dd089 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -255,19 +255,20 @@ static vaddr hexagon_cpu_get_pc(CPUState *cs) return cpu_env(cs)->gpr[HEX_REG_PC]; } =20 -void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPUHexagonState *env =3D cpu_env(cs); + vaddr pc =3D env->gpr[HEX_REG_PC]; uint32_t hex_flags =3D 0; - *pc =3D env->gpr[HEX_REG_PC]; - *cs_base =3D 0; - if (*pc =3D=3D env->gpr[HEX_REG_SA0]) { + + if (pc =3D=3D env->gpr[HEX_REG_SA0]) { hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1); } - *flags =3D hex_flags; - if (*pc & PCALIGN_MASK) { + if (pc & PCALIGN_MASK) { hexagon_raise_exception_err(env, HEX_CAUSE_PC_NOT_ALIGNED, 0); } + + return (TCGTBCPUState){ .pc =3D pc, .flags =3D hex_flags }; } =20 static void hexagon_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 4cdaf98ab1..40cbc191bb 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -51,11 +51,12 @@ static vaddr hppa_cpu_get_pc(CPUState *cs) env->iaoq_f & -4); } =20 -void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, - uint64_t *pcsbase, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPUHPPAState *env =3D cpu_env(cs); uint32_t flags =3D 0; uint64_t cs_base =3D 0; + vaddr pc; =20 /* * TB lookup assumes that PC contains the complete virtual address. @@ -63,7 +64,7 @@ void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, * incomplete virtual address. This also means that we must separate * out current cpu privilege from the low bits of IAOQ_F. */ - *pc =3D hppa_cpu_get_pc(env_cpu(env)); + pc =3D hppa_cpu_get_pc(env_cpu(env)); flags |=3D (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; =20 /* @@ -99,8 +100,7 @@ void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, } #endif =20 - *pcsbase =3D cs_base; - *pflags =3D flags; + return (TCGTBCPUState){ .pc =3D pc, .flags =3D flags, .cs_base =3D cs_= base }; } =20 static void hppa_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index bb6f82befb..3004fb3023 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -48,18 +48,23 @@ static void x86_cpu_exec_exit(CPUState *cs) env->eflags =3D cpu_compute_eflags(env); } =20 -void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *flags =3D env->hflags | + CPUX86State *env =3D cpu_env(cs); + uint32_t flags, cs_base; + vaddr pc; + + flags =3D env->hflags | (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)= ); if (env->hflags & HF_CS64_MASK) { - *cs_base =3D 0; - *pc =3D env->eip; + cs_base =3D 0; + pc =3D env->eip; } else { - *cs_base =3D env->segs[R_CS].base; - *pc =3D (uint32_t)(*cs_base + env->eip); + cs_base =3D env->segs[R_CS].base; + pc =3D (uint32_t)(cs_base + env->eip); } + + return (TCGTBCPUState){ .pc =3D pc, .flags =3D flags, .cs_base =3D cs_= base }; } =20 static void x86_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index be770b7e19..446cf43914 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -336,16 +336,18 @@ static bool loongarch_cpu_exec_interrupt(CPUState *cs= , int interrupt_request) } #endif =20 -void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); - *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_F= PE; - *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_S= XE; - *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_= ASXE; - *flags |=3D is_va32(env) * HW_FLAGS_VA32; + CPULoongArchState *env =3D cpu_env(cs); + uint32_t flags; + + flags =3D env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); + flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FP= E; + flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SX= E; + flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_A= SXE; + flags |=3D is_va32(env) * HW_FLAGS_VA32; + + return (TCGTBCPUState){ .pc =3D env->pc, .flags =3D flags }; } =20 static void loongarch_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 2b4ec40509..b75ed6e887 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -23,6 +23,7 @@ #include "cpu.h" #include "migration/vmstate.h" #include "fpu/softfloat.h" +#include "exec/translation-block.h" #include "accel/tcg/cpu-ops.h" =20 static void m68k_cpu_set_pc(CPUState *cs, vaddr value) @@ -39,20 +40,22 @@ static vaddr m68k_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D (env->macsr >> 4) & TB_FLAGS_MACSR; + CPUM68KState *env =3D cpu_env(cs); + uint32_t flags; + + flags =3D (env->macsr >> 4) & TB_FLAGS_MACSR; if (env->sr & SR_S) { - *flags |=3D TB_FLAGS_MSR_S; - *flags |=3D (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_= S; - *flags |=3D (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_= S; + flags |=3D TB_FLAGS_MSR_S; + flags |=3D (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S; + flags |=3D (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S; } if (M68K_SR_TRACE(env->sr) =3D=3D M68K_SR_TRACE_ANY_INS) { - *flags |=3D TB_FLAGS_TRACE; + flags |=3D TB_FLAGS_TRACE; } + + return (TCGTBCPUState){ .pc =3D env->pc, .flags =3D flags }; } =20 static void m68k_restore_state_to_opc(CPUState *cs, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 105ede0b1e..72a0d0583c 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -95,12 +95,15 @@ static vaddr mb_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->pc; - *flags =3D (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK); - *cs_base =3D (*flags & IMM_FLAG ? env->imm : 0); + CPUMBState *env =3D cpu_env(cs); + + return (TCGTBCPUState){ + .pc =3D env->pc, + .flags =3D (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MAS= K), + .cs_base =3D (env->iflags & IMM_FLAG ? env->imm : 0), + }; } =20 static void mb_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index ab00adf86b..b0f7612a64 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -549,13 +549,15 @@ static int mips_cpu_mmu_index(CPUState *cs, bool ifun= c) return mips_env_mmu_index(cpu_env(cs)); } =20 -void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->active_tc.PC; - *cs_base =3D 0; - *flags =3D env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | - MIPS_HFLAG_HWRENA_ULR); + CPUMIPSState *env =3D cpu_env(cs); + + return (TCGTBCPUState){ + .pc =3D env->active_tc.PC, + .flags =3D env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | + MIPS_HFLAG_HWRENA_ULR), + }; } =20 static const TCGCPUOps mips_tcg_ops =3D { diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index d798127d67..aba4639bbb 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -41,14 +41,16 @@ static vaddr openrisc_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D (env->dflag ? TB_FLAGS_DFLAG : 0) - | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) - | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); + CPUOpenRISCState *env =3D cpu_env(cs); + + return (TCGTBCPUState){ + .pc =3D env->pc, + .flags =3D ((env->dflag ? TB_FLAGS_DFLAG : 0) + | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) + | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE))), + }; } =20 static void openrisc_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 8d248bcbb9..ccaf2b0343 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -256,9 +256,9 @@ void hreg_update_pmu_hflags(CPUPPCState *env) env->hflags |=3D hreg_compute_pmu_hflags_value(env); } =20 -void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPUPPCState *env =3D cpu_env(cs); uint32_t hflags_current =3D env->hflags; =20 #ifdef CONFIG_DEBUG_TCG @@ -270,9 +270,7 @@ void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, } #endif =20 - *pc =3D env->nip; - *cs_base =3D 0; - *flags =3D hflags_current; + return (TCGTBCPUState){ .pc =3D env->nip, .flags =3D hflags_current }; } =20 void cpu_interrupt_exittb(CPUState *cs) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index e67de7dfe2..927153377e 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -98,17 +98,14 @@ static int riscv_cpu_mmu_index(CPUState *cs, bool ifetc= h) return riscv_env_mmu_index(cpu_env(cs), ifetch); } =20 -void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPURISCVState *env =3D cpu_env(cs); RISCVCPU *cpu =3D env_archcpu(env); RISCVExtStatus fs, vs; uint32_t flags =3D 0; bool pm_signext =3D riscv_cpu_virt_mem_enabled(env); =20 - *pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc; - *cs_base =3D 0; - if (cpu->cfg.ext_zve32x) { /* * If env->vl equals to VLMAX, we can use generic vector operation @@ -192,7 +189,10 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *p= c, flags =3D FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env)); flags =3D FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); =20 - *pflags =3D flags; + return (TCGTBCPUState){ + .pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc, + .flags =3D flags + }; } =20 static void riscv_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index e8b47be675..be778c9f65 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -44,13 +44,15 @@ static vaddr rx_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D FIELD_DP32(0, PSW, PM, env->psw_pm); - *flags =3D FIELD_DP32(*flags, PSW, U, env->psw_u); + CPURXState *env =3D cpu_env(cs); + uint32_t flags =3D 0; + + flags =3D FIELD_DP32(flags, PSW, PM, env->psw_pm); + flags =3D FIELD_DP32(flags, PSW, U, env->psw_u); + + return (TCGTBCPUState){ .pc =3D env->pc, .flags =3D flags }; } =20 static void rx_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 435b2034ff..279289f265 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -309,9 +309,9 @@ static int s390x_cpu_mmu_index(CPUState *cs, bool ifetc= h) return s390x_env_mmu_index(cpu_env(cs), ifetch); } =20 -void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPUS390XState *env =3D cpu_env(cs); uint32_t flags; =20 if (env->psw.addr & 1) { @@ -323,9 +323,6 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, tcg_s390_program_interrupt(env, PGM_SPECIFICATION, 0); } =20 - *pc =3D env->psw.addr; - *cs_base =3D env->ex_value; - flags =3D (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; if (env->psw.mask & PSW_MASK_PER) { flags |=3D env->cregs[9] & (FLAG_MASK_PER_BRANCH | @@ -342,7 +339,12 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *p= c, if (env->cregs[0] & CR0_VECTOR) { flags |=3D FLAG_MASK_VECTOR; } - *pflags =3D flags; + + return (TCGTBCPUState){ + .pc =3D env->psw.addr, + .flags =3D flags, + .cs_base =3D env->ex_value, + }; } =20 static const TCGCPUOps s390_tcg_ops =3D { diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 5fb18bf55e..cbd43b55e5 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -43,19 +43,27 @@ static vaddr superh_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->pc; - /* For a gUSA region, notice the end of the region. */ - *cs_base =3D env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0; - *flags =3D env->flags + CPUSH4State *env =3D cpu_env(cs); + uint32_t flags; + + flags =3D env->flags | (env->fpscr & TB_FLAG_FPSCR_MASK) | (env->sr & TB_FLAG_SR_MASK) | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ #ifdef CONFIG_USER_ONLY - *flags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; + flags |=3D TB_FLAG_UNALIGN * !cs->prctl_unalign_sigbus; #endif + + return (TCGTBCPUState){ + .pc =3D env->pc, + .flags =3D flags, +#ifdef CONFIG_USER_ONLY + /* For a gUSA region, notice the end of the region. */ + .cs_base =3D flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0, +#endif + }; } =20 static void superh_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index bbdea8556a..6166b81f71 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -716,13 +716,11 @@ static void sparc_cpu_synchronize_from_tb(CPUState *c= s, cpu->env.npc =3D tb->cs_base; } =20 -void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - uint32_t flags; - *pc =3D env->pc; - *cs_base =3D env->npc; - flags =3D cpu_mmu_index(env_cpu(env), false); + CPUSPARCState *env =3D cpu_env(cs); + uint32_t flags =3D cpu_mmu_index(cs, false); + #ifndef CONFIG_USER_ONLY if (cpu_supervisor_mode(env)) { flags |=3D TB_FLAG_SUPER; @@ -751,7 +749,12 @@ void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *p= c, } #endif /* !CONFIG_USER_ONLY */ #endif /* TARGET_SPARC64 */ - *pflags =3D flags; + + return (TCGTBCPUState){ + .pc =3D env->pc, + .flags =3D flags, + .cs_base =3D env->npc, + }; } =20 static void sparc_restore_state_to_opc(CPUState *cs, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 81b3bb6362..1151a812b6 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -45,16 +45,14 @@ static vaddr tricore_cpu_get_pc(CPUState *cs) return cpu_env(cs)->PC; } =20 -void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - uint32_t new_flags =3D 0; - *pc =3D env->PC; - *cs_base =3D 0; + CPUTriCoreState *env =3D cpu_env(cs); =20 - new_flags |=3D FIELD_DP32(new_flags, TB_FLAGS, PRIV, - extract32(env->PSW, 10, 2)); - *flags =3D new_flags; + return (TCGTBCPUState){ + .pc =3D env->PC, + .flags =3D FIELD_DP32(0, TB_FLAGS, PRIV, extract32(env->PSW, 10, 2= )), + }; } =20 static void tricore_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index c78ef9421c..431b7ebd7b 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -55,15 +55,15 @@ static vaddr xtensa_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D 0; - *flags |=3D xtensa_get_ring(env); + CPUXtensaState *env =3D cpu_env(cs); + uint32_t flags =3D 0; + target_ulong cs_base =3D 0; + + flags |=3D xtensa_get_ring(env); if (env->sregs[PS] & PS_EXCM) { - *flags |=3D XTENSA_TBFLAG_EXCM; + flags |=3D XTENSA_TBFLAG_EXCM; } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) { target_ulong lend_dist =3D env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS)); @@ -85,26 +85,26 @@ void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *p= c, if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_s= ize) { target_ulong lbeg_off =3D env->sregs[LEND] - env->sregs[LBEG]; =20 - *cs_base =3D lend_dist; + cs_base =3D lend_dist; if (lbeg_off < 256) { - *cs_base |=3D lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT; + cs_base |=3D lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT; } } } if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && (env->sregs[LITBASE] & 1)) { - *flags |=3D XTENSA_TBFLAG_LITBASE; + flags |=3D XTENSA_TBFLAG_LITBASE; } if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) { if (xtensa_get_cintlevel(env) < env->config->debug_level) { - *flags |=3D XTENSA_TBFLAG_DEBUG; + flags |=3D XTENSA_TBFLAG_DEBUG; } if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { - *flags |=3D XTENSA_TBFLAG_ICOUNT; + flags |=3D XTENSA_TBFLAG_ICOUNT; } } if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { - *flags |=3D env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; + flags |=3D env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; } if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER= ) && (env->sregs[PS] & (PS_WOE | PS_EXCM)) =3D=3D PS_WOE) { @@ -112,15 +112,21 @@ void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr = *pc, (env->sregs[WINDOW_BASE] + 1); uint32_t w =3D ctz32(windowstart | 0x8); =20 - *flags |=3D (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE; - *flags |=3D extract32(env->sregs[PS], PS_CALLINC_SHIFT, + flags |=3D (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE; + flags |=3D extract32(env->sregs[PS], PS_CALLINC_SHIFT, PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT; } else { - *flags |=3D 3 << XTENSA_TBFLAG_WINDOW_SHIFT; + flags |=3D 3 << XTENSA_TBFLAG_WINDOW_SHIFT; } if (env->yield_needed) { - *flags |=3D XTENSA_TBFLAG_YIELD; + flags |=3D XTENSA_TBFLAG_YIELD; } + + return (TCGTBCPUState){ + .pc =3D env->pc, + .flags =3D flags, + .cs_base =3D cs_base, + }; } =20 static void xtensa_restore_state_to_opc(CPUState *cs, --=20 2.43.0 From nobody Sat Nov 15 22:35:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/accel/tcg/cpu-ops.h | 8 ++++++-- target/arm/internals.h | 2 ++ target/ppc/internal.h | 3 +++ accel/tcg/cpu-exec.c | 7 ++++--- accel/tcg/translate-all.c | 2 +- target/alpha/cpu.c | 3 ++- target/arm/cpu.c | 1 + target/arm/tcg/cpu-v7m.c | 1 + target/arm/tcg/hflags.c | 2 +- target/avr/cpu.c | 3 ++- target/hexagon/cpu.c | 3 ++- target/hppa/cpu.c | 3 ++- target/i386/tcg/tcg-cpu.c | 3 ++- target/loongarch/cpu.c | 3 ++- target/m68k/cpu.c | 3 ++- target/microblaze/cpu.c | 3 ++- target/mips/cpu.c | 3 ++- target/openrisc/cpu.c | 3 ++- target/ppc/cpu_init.c | 2 +- target/ppc/helper_regs.c | 3 ++- target/riscv/tcg/tcg-cpu.c | 3 ++- target/rx/cpu.c | 3 ++- target/s390x/cpu.c | 3 ++- target/sh4/cpu.c | 3 ++- target/sparc/cpu.c | 3 ++- target/tricore/cpu.c | 3 ++- target/xtensa/cpu.c | 3 ++- 27 files changed, 56 insertions(+), 26 deletions(-) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index 43a39c2e13..23cd6af0b2 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -19,8 +19,6 @@ #include "accel/tcg/tb-cpu-state.h" #include "tcg/tcg-mo.h" =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs); - struct TCGCPUOps { /** * mttcg_supported: multi-threaded TCG is supported @@ -63,6 +61,12 @@ struct TCGCPUOps { */ void (*translate_code)(CPUState *cpu, TranslationBlock *tb, int *max_insns, vaddr pc, void *host_pc); + /** + * @get_tb_cpu_state: Extract CPU state for a TCG #TranslationBlock + * + * Fill in all data required to select or compile a TranslationBlock. + */ + TCGTBCPUState (*get_tb_cpu_state)(CPUState *cs); /** * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock * diff --git a/target/arm/internals.h b/target/arm/internals.h index 382a4d1015..660d3a88e0 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -28,6 +28,7 @@ #include "exec/hwaddr.h" #include "exec/vaddr.h" #include "exec/breakpoint.h" +#include "accel/tcg/tb-cpu-state.h" #include "hw/registerfields.h" #include "tcg/tcg-gvec-desc.h" #include "system/memory.h" @@ -372,6 +373,7 @@ void arm_restore_state_to_opc(CPUState *cs, const uint64_t *data); =20 #ifdef CONFIG_TCG +TCGTBCPUState arm_get_tb_cpu_state(CPUState *cs); void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); =20 /* Our implementation of TCGCPUOps::cpu_exec_halt */ diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 9012d3809c..7723350227 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -21,6 +21,7 @@ #include "exec/breakpoint.h" #include "hw/registerfields.h" #include "exec/page-protection.h" +#include "accel/tcg/tb-cpu-state.h" =20 /* PM instructions */ typedef enum { @@ -308,4 +309,6 @@ static inline int ger_pack_masks(int pmsk, int ymsk, in= t xmsk) return msk; } =20 +TCGTBCPUState ppc_get_tb_cpu_state(CPUState *cs); + #endif /* PPC_INTERNAL_H */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index f7e7e7949d..4a405d7b56 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -395,7 +395,7 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) */ cpu->neg.can_do_io =3D true; =20 - TCGTBCPUState s =3D cpu_get_tb_cpu_state(cpu); + TCGTBCPUState s =3D cpu->cc->tcg_ops->get_tb_cpu_state(cpu); s.cflags =3D curr_cflags(cpu); =20 if (check_for_breakpoints(cpu, s.pc, &s.cflags)) { @@ -567,7 +567,7 @@ void cpu_exec_step_atomic(CPUState *cpu) g_assert(!cpu->running); cpu->running =3D true; =20 - TCGTBCPUState s =3D cpu_get_tb_cpu_state(cpu); + TCGTBCPUState s =3D cpu->cc->tcg_ops->get_tb_cpu_state(cpu); s.cflags =3D curr_cflags(cpu); =20 /* Execute in a serial context. */ @@ -935,7 +935,7 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc) =20 while (!cpu_handle_interrupt(cpu, &last_tb)) { TranslationBlock *tb; - TCGTBCPUState s =3D cpu_get_tb_cpu_state(cpu); + TCGTBCPUState s =3D cpu->cc->tcg_ops->get_tb_cpu_state(cpu); s.cflags =3D cpu->cflags_next_tb; =20 /* @@ -1052,6 +1052,7 @@ bool tcg_exec_realizefn(CPUState *cpu, Error **errp) assert(tcg_ops->cpu_exec_reset); #endif /* !CONFIG_USER_ONLY */ assert(tcg_ops->translate_code); + assert(tcg_ops->get_tb_cpu_state); assert(tcg_ops->mmu_index); tcg_ops->initialize(); tcg_target_initialized =3D true; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index f2766cedfc..97aadee52c 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -590,7 +590,7 @@ void tb_check_watchpoint(CPUState *cpu, uintptr_t retad= dr) /* The exception probably happened in a helper. The CPU state sho= uld have been saved before calling it. Fetch the PC from there. */ CPUArchState *env =3D cpu_env(cpu); - TCGTBCPUState s =3D cpu_get_tb_cpu_state(cpu); + TCGTBCPUState s =3D cpu->cc->tcg_ops->get_tb_cpu_state(cpu); tb_page_addr_t addr =3D get_page_addr_code(env, s.pc); =20 if (addr !=3D -1) { diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 90e3a2e748..890b84c032 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -41,7 +41,7 @@ static vaddr alpha_cpu_get_pc(CPUState *cs) return env->pc; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState alpha_get_tb_cpu_state(CPUState *cs) { CPUAlphaState *env =3D cpu_env(cs); uint32_t flags =3D env->flags & ENV_FLAG_TB_MASK; @@ -251,6 +251,7 @@ static const TCGCPUOps alpha_tcg_ops =3D { =20 .initialize =3D alpha_translate_init, .translate_code =3D alpha_translate_code, + .get_tb_cpu_state =3D alpha_get_tb_cpu_state, .synchronize_from_tb =3D alpha_cpu_synchronize_from_tb, .restore_state_to_opc =3D alpha_restore_state_to_opc, .mmu_index =3D alpha_cpu_mmu_index, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 3dde70b04a..2020aec54a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2693,6 +2693,7 @@ static const TCGCPUOps arm_tcg_ops =3D { =20 .initialize =3D arm_translate_init, .translate_code =3D arm_translate_code, + .get_tb_cpu_state =3D arm_get_tb_cpu_state, .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, .debug_excp_handler =3D arm_debug_excp_handler, .restore_state_to_opc =3D arm_restore_state_to_opc, diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 5c8c374885..95b23d9b55 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -238,6 +238,7 @@ static const TCGCPUOps arm_v7m_tcg_ops =3D { =20 .initialize =3D arm_translate_init, .translate_code =3D arm_translate_code, + .get_tb_cpu_state =3D arm_get_tb_cpu_state, .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, .debug_excp_handler =3D arm_debug_excp_handler, .restore_state_to_opc =3D arm_restore_state_to_opc, diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index b49381924b..fd407a7b28 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -545,7 +545,7 @@ static bool mve_no_pred(CPUARMState *env) return true; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +TCGTBCPUState arm_get_tb_cpu_state(CPUState *cs) { CPUARMState *env =3D cpu_env(cs); CPUARMTBFlags flags; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 683195b61d..250241541b 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -54,7 +54,7 @@ static int avr_cpu_mmu_index(CPUState *cs, bool ifetch) return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState avr_get_tb_cpu_state(CPUState *cs) { CPUAVRState *env =3D cpu_env(cs); uint32_t flags =3D 0; @@ -241,6 +241,7 @@ static const TCGCPUOps avr_tcg_ops =3D { .mttcg_supported =3D false, .initialize =3D avr_cpu_tcg_init, .translate_code =3D avr_cpu_translate_code, + .get_tb_cpu_state =3D avr_get_tb_cpu_state, .synchronize_from_tb =3D avr_cpu_synchronize_from_tb, .restore_state_to_opc =3D avr_restore_state_to_opc, .mmu_index =3D avr_cpu_mmu_index, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index a7f76dd089..a5a04173ab 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -255,7 +255,7 @@ static vaddr hexagon_cpu_get_pc(CPUState *cs) return cpu_env(cs)->gpr[HEX_REG_PC]; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState hexagon_get_tb_cpu_state(CPUState *cs) { CPUHexagonState *env =3D cpu_env(cs); vaddr pc =3D env->gpr[HEX_REG_PC]; @@ -344,6 +344,7 @@ static const TCGCPUOps hexagon_tcg_ops =3D { .mttcg_supported =3D false, .initialize =3D hexagon_translate_init, .translate_code =3D hexagon_translate_code, + .get_tb_cpu_state =3D hexagon_get_tb_cpu_state, .synchronize_from_tb =3D hexagon_cpu_synchronize_from_tb, .restore_state_to_opc =3D hexagon_restore_state_to_opc, .mmu_index =3D hexagon_cpu_mmu_index, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 40cbc191bb..6465181543 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -51,7 +51,7 @@ static vaddr hppa_cpu_get_pc(CPUState *cs) env->iaoq_f & -4); } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState hppa_get_tb_cpu_state(CPUState *cs) { CPUHPPAState *env =3D cpu_env(cs); uint32_t flags =3D 0; @@ -262,6 +262,7 @@ static const TCGCPUOps hppa_tcg_ops =3D { =20 .initialize =3D hppa_translate_init, .translate_code =3D hppa_translate_code, + .get_tb_cpu_state =3D hppa_get_tb_cpu_state, .synchronize_from_tb =3D hppa_cpu_synchronize_from_tb, .restore_state_to_opc =3D hppa_restore_state_to_opc, .mmu_index =3D hppa_cpu_mmu_index, diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 3004fb3023..179dfdf064 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -48,7 +48,7 @@ static void x86_cpu_exec_exit(CPUState *cs) env->eflags =3D cpu_compute_eflags(env); } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState x86_get_tb_cpu_state(CPUState *cs) { CPUX86State *env =3D cpu_env(cs); uint32_t flags, cs_base; @@ -160,6 +160,7 @@ const TCGCPUOps x86_tcg_ops =3D { .guest_default_memory_order =3D TCG_MO_ALL & ~TCG_MO_ST_LD, .initialize =3D tcg_x86_init, .translate_code =3D x86_translate_code, + .get_tb_cpu_state =3D x86_get_tb_cpu_state, .synchronize_from_tb =3D x86_cpu_synchronize_from_tb, .restore_state_to_opc =3D x86_restore_state_to_opc, .mmu_index =3D x86_cpu_mmu_index, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 446cf43914..f7535d1be7 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -336,7 +336,7 @@ static bool loongarch_cpu_exec_interrupt(CPUState *cs, = int interrupt_request) } #endif =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState loongarch_get_tb_cpu_state(CPUState *cs) { CPULoongArchState *env =3D cpu_env(cs); uint32_t flags; @@ -882,6 +882,7 @@ static const TCGCPUOps loongarch_tcg_ops =3D { =20 .initialize =3D loongarch_translate_init, .translate_code =3D loongarch_translate_code, + .get_tb_cpu_state =3D loongarch_get_tb_cpu_state, .synchronize_from_tb =3D loongarch_cpu_synchronize_from_tb, .restore_state_to_opc =3D loongarch_restore_state_to_opc, .mmu_index =3D loongarch_cpu_mmu_index, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index b75ed6e887..c5196a612e 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -40,7 +40,7 @@ static vaddr m68k_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState m68k_get_tb_cpu_state(CPUState *cs) { CPUM68KState *env =3D cpu_env(cs); uint32_t flags; @@ -613,6 +613,7 @@ static const TCGCPUOps m68k_tcg_ops =3D { =20 .initialize =3D m68k_tcg_init, .translate_code =3D m68k_translate_code, + .get_tb_cpu_state =3D m68k_get_tb_cpu_state, .restore_state_to_opc =3D m68k_restore_state_to_opc, .mmu_index =3D m68k_cpu_mmu_index, =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 72a0d0583c..d069e40e70 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -95,7 +95,7 @@ static vaddr mb_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState mb_get_tb_cpu_state(CPUState *cs) { CPUMBState *env =3D cpu_env(cs); =20 @@ -442,6 +442,7 @@ static const TCGCPUOps mb_tcg_ops =3D { =20 .initialize =3D mb_tcg_init, .translate_code =3D mb_translate_code, + .get_tb_cpu_state =3D mb_get_tb_cpu_state, .synchronize_from_tb =3D mb_cpu_synchronize_from_tb, .restore_state_to_opc =3D mb_restore_state_to_opc, .mmu_index =3D mb_cpu_mmu_index, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index b0f7612a64..4cbfb9435a 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -549,7 +549,7 @@ static int mips_cpu_mmu_index(CPUState *cs, bool ifunc) return mips_env_mmu_index(cpu_env(cs)); } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState mips_get_tb_cpu_state(CPUState *cs) { CPUMIPSState *env =3D cpu_env(cs); =20 @@ -566,6 +566,7 @@ static const TCGCPUOps mips_tcg_ops =3D { =20 .initialize =3D mips_tcg_init, .translate_code =3D mips_translate_code, + .get_tb_cpu_state =3D mips_get_tb_cpu_state, .synchronize_from_tb =3D mips_cpu_synchronize_from_tb, .restore_state_to_opc =3D mips_restore_state_to_opc, .mmu_index =3D mips_cpu_mmu_index, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index aba4639bbb..054ad33360 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -41,7 +41,7 @@ static vaddr openrisc_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState openrisc_get_tb_cpu_state(CPUState *cs) { CPUOpenRISCState *env =3D cpu_env(cs); =20 @@ -258,6 +258,7 @@ static const TCGCPUOps openrisc_tcg_ops =3D { =20 .initialize =3D openrisc_translate_init, .translate_code =3D openrisc_translate_code, + .get_tb_cpu_state =3D openrisc_get_tb_cpu_state, .synchronize_from_tb =3D openrisc_cpu_synchronize_from_tb, .restore_state_to_opc =3D openrisc_restore_state_to_opc, .mmu_index =3D openrisc_cpu_mmu_index, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 3a01731402..cf88a18244 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -45,7 +45,6 @@ #include "internal.h" #include "spr_common.h" #include "power8-pmu.h" - #ifndef CONFIG_USER_ONLY #include "hw/boards.h" #include "hw/intc/intc.h" @@ -7483,6 +7482,7 @@ static const TCGCPUOps ppc_tcg_ops =3D { .guest_default_memory_order =3D 0, .initialize =3D ppc_translate_init, .translate_code =3D ppc_translate_code, + .get_tb_cpu_state =3D ppc_get_tb_cpu_state, .restore_state_to_opc =3D ppc_restore_state_to_opc, .mmu_index =3D ppc_cpu_mmu_index, =20 diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index ccaf2b0343..7e5726871e 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -28,6 +28,7 @@ #include "cpu-models.h" #include "spr_common.h" #include "accel/tcg/cpu-ops.h" +#include "internal.h" =20 /* Swap temporary saved registers with GPRs */ void hreg_swap_gpr_tgpr(CPUPPCState *env) @@ -256,7 +257,7 @@ void hreg_update_pmu_hflags(CPUPPCState *env) env->hflags |=3D hreg_compute_pmu_hflags_value(env); } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +TCGTBCPUState ppc_get_tb_cpu_state(CPUState *cs) { CPUPPCState *env =3D cpu_env(cs); uint32_t hflags_current =3D env->hflags; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 927153377e..55e00972b7 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -98,7 +98,7 @@ static int riscv_cpu_mmu_index(CPUState *cs, bool ifetch) return riscv_env_mmu_index(cpu_env(cs), ifetch); } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs) { CPURISCVState *env =3D cpu_env(cs); RISCVCPU *cpu =3D env_archcpu(env); @@ -243,6 +243,7 @@ const TCGCPUOps riscv_tcg_ops =3D { =20 .initialize =3D riscv_translate_init, .translate_code =3D riscv_translate_code, + .get_tb_cpu_state =3D riscv_get_tb_cpu_state, .synchronize_from_tb =3D riscv_cpu_synchronize_from_tb, .restore_state_to_opc =3D riscv_restore_state_to_opc, .mmu_index =3D riscv_cpu_mmu_index, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index be778c9f65..36eba75545 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -44,7 +44,7 @@ static vaddr rx_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState rx_get_tb_cpu_state(CPUState *cs) { CPURXState *env =3D cpu_env(cs); uint32_t flags =3D 0; @@ -220,6 +220,7 @@ static const TCGCPUOps rx_tcg_ops =3D { =20 .initialize =3D rx_translate_init, .translate_code =3D rx_translate_code, + .get_tb_cpu_state =3D rx_get_tb_cpu_state, .synchronize_from_tb =3D rx_cpu_synchronize_from_tb, .restore_state_to_opc =3D rx_restore_state_to_opc, .mmu_index =3D rx_cpu_mmu_index, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 279289f265..9c1158ebcc 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -309,7 +309,7 @@ static int s390x_cpu_mmu_index(CPUState *cs, bool ifetc= h) return s390x_env_mmu_index(cpu_env(cs), ifetch); } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState s390x_get_tb_cpu_state(CPUState *cs) { CPUS390XState *env =3D cpu_env(cs); uint32_t flags; @@ -358,6 +358,7 @@ static const TCGCPUOps s390_tcg_ops =3D { =20 .initialize =3D s390x_translate_init, .translate_code =3D s390x_translate_code, + .get_tb_cpu_state =3D s390x_get_tb_cpu_state, .restore_state_to_opc =3D s390x_restore_state_to_opc, .mmu_index =3D s390x_cpu_mmu_index, =20 diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index cbd43b55e5..b35f18e250 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -43,7 +43,7 @@ static vaddr superh_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState superh_get_tb_cpu_state(CPUState *cs) { CPUSH4State *env =3D cpu_env(cs); uint32_t flags; @@ -289,6 +289,7 @@ static const TCGCPUOps superh_tcg_ops =3D { =20 .initialize =3D sh4_translate_init, .translate_code =3D sh4_translate_code, + .get_tb_cpu_state =3D superh_get_tb_cpu_state, .synchronize_from_tb =3D superh_cpu_synchronize_from_tb, .restore_state_to_opc =3D superh_restore_state_to_opc, .mmu_index =3D sh4_cpu_mmu_index, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 6166b81f71..2a3e408923 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -716,7 +716,7 @@ static void sparc_cpu_synchronize_from_tb(CPUState *cs, cpu->env.npc =3D tb->cs_base; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState sparc_get_tb_cpu_state(CPUState *cs) { CPUSPARCState *env =3D cpu_env(cs); uint32_t flags =3D cpu_mmu_index(cs, false); @@ -1029,6 +1029,7 @@ static const TCGCPUOps sparc_tcg_ops =3D { =20 .initialize =3D sparc_tcg_init, .translate_code =3D sparc_translate_code, + .get_tb_cpu_state =3D sparc_get_tb_cpu_state, .synchronize_from_tb =3D sparc_cpu_synchronize_from_tb, .restore_state_to_opc =3D sparc_restore_state_to_opc, .mmu_index =3D sparc_cpu_mmu_index, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 1151a812b6..e56f90fde9 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -45,7 +45,7 @@ static vaddr tricore_cpu_get_pc(CPUState *cs) return cpu_env(cs)->PC; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState tricore_get_tb_cpu_state(CPUState *cs) { CPUTriCoreState *env =3D cpu_env(cs); =20 @@ -185,6 +185,7 @@ static const TCGCPUOps tricore_tcg_ops =3D { .mttcg_supported =3D false, .initialize =3D tricore_tcg_init, .translate_code =3D tricore_translate_code, + .get_tb_cpu_state =3D tricore_get_tb_cpu_state, .synchronize_from_tb =3D tricore_cpu_synchronize_from_tb, .restore_state_to_opc =3D tricore_restore_state_to_opc, .mmu_index =3D tricore_cpu_mmu_index, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 431b7ebd7b..91b71b6caa 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -55,7 +55,7 @@ static vaddr xtensa_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState xtensa_get_tb_cpu_state(CPUState *cs) { CPUXtensaState *env =3D cpu_env(cs); uint32_t flags =3D 0; @@ -312,6 +312,7 @@ static const TCGCPUOps xtensa_tcg_ops =3D { .initialize =3D xtensa_translate_init, .translate_code =3D xtensa_translate_code, .debug_excp_handler =3D xtensa_breakpoint_handler, + .get_tb_cpu_state =3D xtensa_get_tb_cpu_state, .restore_state_to_opc =3D xtensa_restore_state_to_opc, .mmu_index =3D xtensa_cpu_mmu_index, =20 --=20 2.43.0 From nobody Sat Nov 15 22:35:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 01 May 2025 14:21:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 34/59] accel/tcg: Pass TCGTBCPUState to tb_lookup Date: Thu, 1 May 2025 14:20:48 -0700 Message-ID: <20250501212113.2961531-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746135014799019100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 4a405d7b56..808983e461 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -232,35 +232,33 @@ static TranslationBlock *tb_htable_lookup(CPUState *c= pu, vaddr pc, * * Returns: an existing translation block or NULL. */ -static inline TranslationBlock *tb_lookup(CPUState *cpu, vaddr pc, - uint64_t cs_base, uint32_t flags, - uint32_t cflags) +static inline TranslationBlock *tb_lookup(CPUState *cpu, TCGTBCPUState s) { TranslationBlock *tb; CPUJumpCache *jc; uint32_t hash; =20 /* we should never be trying to look up an INVALID tb */ - tcg_debug_assert(!(cflags & CF_INVALID)); + tcg_debug_assert(!(s.cflags & CF_INVALID)); =20 - hash =3D tb_jmp_cache_hash_func(pc); + hash =3D tb_jmp_cache_hash_func(s.pc); jc =3D cpu->tb_jmp_cache; =20 tb =3D qatomic_read(&jc->array[hash].tb); if (likely(tb && - jc->array[hash].pc =3D=3D pc && - tb->cs_base =3D=3D cs_base && - tb->flags =3D=3D flags && - tb_cflags(tb) =3D=3D cflags)) { + jc->array[hash].pc =3D=3D s.pc && + tb->cs_base =3D=3D s.cs_base && + tb->flags =3D=3D s.flags && + tb_cflags(tb) =3D=3D s.cflags)) { goto hit; } =20 - tb =3D tb_htable_lookup(cpu, pc, cs_base, flags, cflags); + tb =3D tb_htable_lookup(cpu, s.pc, s.cs_base, s.flags, s.cflags); if (tb =3D=3D NULL) { return NULL; } =20 - jc->array[hash].pc =3D pc; + jc->array[hash].pc =3D s.pc; qatomic_set(&jc->array[hash].tb, tb); =20 hit: @@ -268,7 +266,7 @@ hit: * As long as tb is not NULL, the contents are consistent. Therefore, * the virtual PC has to match for non-CF_PCREL translations. */ - assert((tb_cflags(tb) & CF_PCREL) || tb->pc =3D=3D pc); + assert((tb_cflags(tb) & CF_PCREL) || tb->pc =3D=3D s.pc); return tb; } =20 @@ -402,7 +400,7 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) cpu_loop_exit(cpu); } =20 - tb =3D tb_lookup(cpu, s.pc, s.cs_base, s.flags, s.cflags); + tb =3D tb_lookup(cpu, s); if (tb =3D=3D NULL) { return tcg_code_gen_epilogue; } @@ -581,7 +579,7 @@ void cpu_exec_step_atomic(CPUState *cpu) * Any breakpoint for this insn will have been recognized earlier. */ =20 - tb =3D tb_lookup(cpu, s.pc, s.cs_base, s.flags, s.cflags); + tb =3D tb_lookup(cpu, s); if (tb =3D=3D NULL) { mmap_lock(); tb =3D tb_gen_code(cpu, s.pc, s.cs_base, s.flags, s.cflags); @@ -955,7 +953,7 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc) break; } =20 - tb =3D tb_lookup(cpu, s.pc, s.cs_base, s.flags, s.cflags); + tb =3D tb_lookup(cpu, s); if (tb =3D=3D NULL) { CPUJumpCache *jc; uint32_t h; --=20 2.43.0 From nobody Sat Nov 15 22:35:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746134658; cv=none; d=zohomail.com; s=zohoarc; b=kYWmgU/MzTqEri9Xw9mbm0vTpq167ph9l9aFY3IrWL9qO4NmRXfh5DWEsAOHick/iByVXRlRUwkzs4wfzgsn/hHQHAk1KB2KvhxtUFP+Ua2l03+QDIApfwUG1Kp2ceJ7k9aRSxwWaLSI0012E199L2PVwyr1Wo3WRZj7pxDQZjE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746134658; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=VSNENHYud6d4CatFFmLB8e+vJFaHLohbjF+bNPxyKN0=; b=BipLStRETAcDwkdgW/Ln3OJESuLzn+ZjLEPnTLb6ac/wF8I7ctCg5mei5tWaBZSgx0P/q1dD+GgvNJau92x0gQXOZxdvIZW0dnql4ONj+V3zcftzA7/bDpQzSb3ga9u+/VCz1lta+8Xhjt59gn0+ECWOqiCjWDbJh6MFKqM6zzo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746134658663893.2975938666411; Thu, 1 May 2025 14:24:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAbLw-00016b-Jn; Thu, 01 May 2025 17:21:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAbLm-00010f-QR for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:46 -0400 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAbLk-0001a2-Uj for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:46 -0400 Received: by mail-pj1-x1035.google.com with SMTP id 98e67ed59e1d1-2ff799d99dcso1549852a91.1 for ; Thu, 01 May 2025 14:21:44 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-30a476267e0sm1384573a91.39.2025.05.01.14.21.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 May 2025 14:21:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746134503; x=1746739303; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VSNENHYud6d4CatFFmLB8e+vJFaHLohbjF+bNPxyKN0=; b=qsQlbzu15cPm/B9PbtnhCat2e34FpVPYvOTxlTApFPjSnmXViMEABeJ1GTthR+9c+P B1qUxP9M6PsvmKNU7wKquwzBRCS7zd6QmDrv1u1VF+4jAfM0W0kzjBXJ/EffxiibBM53 wEeLzJx3e3NFnx5GzRaXSe6hSo0OGkcryUQIHE/Ke/0EnnknAzJXviXc6OkxQaM1GFiw r13UIR+ma79VsTLuaySqAmflukqTaW+I326ptIbALFQPetbO8a+2Qu6P2Hkpjz1FojG9 kuRwOcZREPxLdg7MAj125P79KQUjS9uUs6Z/A6+BwVC11UbkhuVnsGxnJOFGOk4HlsPF Hkmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746134503; x=1746739303; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VSNENHYud6d4CatFFmLB8e+vJFaHLohbjF+bNPxyKN0=; b=vSK6nX0gJcymHnF8LcpWgQGBPbK/DecQeIVnYsCre5FaXk3oIaHex5gQgYGMw1lHZ+ K1fe1LxEAmWkERrpsVwuM+0GNieWm0wkVRuQp5lZa9/iNjQrNsYM8t9HG+MdUI7/KUYr 3tur+0D3pKzLZiZ9bKCf0O3GFlQ7FupiJB1Tut+nxfmFsIwUjgwzKoE9lH1h9CL8hAh3 ll0QG/db0K9eqb2iufYYjNri8TmsmhMTR5Stu6aAPSzxKdMYr/viD6Qq6xr1m7EBXNIQ E07riiobeEckD7gQPRiiLlpmzZvAXH8tcNacTIKiJXw7k1NGbe9QBT+l4t6+6nYueOiM s5NA== X-Gm-Message-State: AOJu0YxGByEvNn3D9IprJ8F3Suq2lINQhTsjR3KCWiTtisQMxyFY63lV UtQkLu63XFa1CN9o3oDACbPE07h2FxYOz32d/lPl0rVoyp0DyGPPe6NgWPuahPlw86osztYPHPo s X-Gm-Gg: ASbGnctBSEf9besw1OU+U7Nk0NpUNM1jzMoUIApdKbNj1eupYcF725Q/x/nc0bWe6AH 2Kkr2VwoSvf1e723LQpemWYhcdYRFCY+gL85YAXhdrlO5XtvLhTfq04XcHP4B8jSH1W82sN/c+A Yc2zZlIZ36CfWhTgDpGdouqDgRhmbd8jWZ+Jwu8zUaGqX72dBBkkGHE+iIJEG2O++ktxIn6AXJC QhpjMyUN+TiKyMadzbLR6b7oNMKYjkyXy1rrzDfFT4l/0K01T/kv4yerhjC1qb0TCgL+N4IQ5oi vGgPJ8SZXyHMxlAhOc99MmAZZ8/O7I0IAB9+8Vmt1k6lALnufsjFp0qXC24ZtavqIAlgMm5kL0A = X-Google-Smtp-Source: AGHT+IFqeurWgzAdWXiCr2xo/aNnUUVo7i37e/pkV/HcufWGGogozmrYxEVK1u7RDDAVb0OD2cmCZg== X-Received: by 2002:a17:90a:e705:b0:2ff:64c3:3bd4 with SMTP id 98e67ed59e1d1-30a4e6befe1mr877791a91.31.1746134503540; Thu, 01 May 2025 14:21:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 35/59] accel/tcg: Pass TCGTBCPUState to tb_htable_lookup Date: Thu, 1 May 2025 14:20:49 -0700 Message-ID: <20250501212113.2961531-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746134659669019100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 808983e461..8e6899950e 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -195,26 +195,24 @@ static bool tb_lookup_cmp(const void *p, const void *= d) return false; } =20 -static TranslationBlock *tb_htable_lookup(CPUState *cpu, vaddr pc, - uint64_t cs_base, uint32_t flags, - uint32_t cflags) +static TranslationBlock *tb_htable_lookup(CPUState *cpu, TCGTBCPUState s) { tb_page_addr_t phys_pc; struct tb_desc desc; uint32_t h; =20 desc.env =3D cpu_env(cpu); - desc.cs_base =3D cs_base; - desc.flags =3D flags; - desc.cflags =3D cflags; - desc.pc =3D pc; - phys_pc =3D get_page_addr_code(desc.env, pc); + desc.cs_base =3D s.cs_base; + desc.flags =3D s.flags; + desc.cflags =3D s.cflags; + desc.pc =3D s.pc; + phys_pc =3D get_page_addr_code(desc.env, s.pc); if (phys_pc =3D=3D -1) { return NULL; } desc.page_addr0 =3D phys_pc; - h =3D tb_hash_func(phys_pc, (cflags & CF_PCREL ? 0 : pc), - flags, cs_base, cflags); + h =3D tb_hash_func(phys_pc, (s.cflags & CF_PCREL ? 0 : s.pc), + s.flags, s.cs_base, s.cflags); return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp); } =20 @@ -253,7 +251,7 @@ static inline TranslationBlock *tb_lookup(CPUState *cpu= , TCGTBCPUState s) goto hit; } =20 - tb =3D tb_htable_lookup(cpu, s.pc, s.cs_base, s.flags, s.cflags); + tb =3D tb_htable_lookup(cpu, s); if (tb =3D=3D NULL) { return NULL; } --=20 2.43.0 From nobody Sat Nov 15 22:35:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746134672; cv=none; d=zohomail.com; s=zohoarc; b=L0YY8qpGK2TWHG05EaMPCEQG2/SfwvLQLFSQwoK0h3c059m7rXD/8zSXum3Iaer3+b2UBG4x841ec6o4JLsfZlXSUJ/L/6Q4TFG2dE+QueDKHe+KYQCXXT52+YB3fbwq8ShHe2Xagu4vBF4YR1d/nRuYit8jeqfZ9d5TLdTSwXM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746134672; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=/BWKAEDoduJo+vm6H9IfI7womewKXVIoZxey+PglUhc=; b=bkDfV6w4xWesyoGa6ZV1GynuPNs32ZCFGVTXM3ekV6AqoYx3LBnupmEHnCuioBrzMC+v3V/JLQCYq/ldl32qaT+Lk2U37u5NHR+5yVZk+8b54oy38I+RRrGacUaiQLLk7BEhYRw/4rMYcDFC8C1LS+E6FDfaeTQsdttA6nQX/3g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746134672296271.93078469386603; Thu, 1 May 2025 14:24:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAbLw-00016G-7u; Thu, 01 May 2025 17:21:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAbLo-00011P-5E for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:48 -0400 Received: from mail-pg1-x52e.google.com ([2607:f8b0:4864:20::52e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAbLm-0001aL-9k for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:47 -0400 Received: by mail-pg1-x52e.google.com with SMTP id 41be03b00d2f7-b1396171fb1so906522a12.2 for ; Thu, 01 May 2025 14:21:45 -0700 (PDT) Received: from stoup.. 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Thu, 01 May 2025 14:21:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 36/59] accel/tcg: Use TCGTBCPUState in struct tb_desc Date: Thu, 1 May 2025 14:20:50 -0700 Message-ID: <20250501212113.2961531-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746134674013019100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 8e6899950e..4ad84c2db8 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -150,12 +150,9 @@ static void init_delay_params(SyncClocks *sc, const CP= UState *cpu) #endif /* CONFIG USER ONLY */ =20 struct tb_desc { - vaddr pc; - uint64_t cs_base; + TCGTBCPUState s; CPUArchState *env; tb_page_addr_t page_addr0; - uint32_t flags; - uint32_t cflags; }; =20 static bool tb_lookup_cmp(const void *p, const void *d) @@ -163,11 +160,11 @@ static bool tb_lookup_cmp(const void *p, const void *= d) const TranslationBlock *tb =3D p; const struct tb_desc *desc =3D d; =20 - if ((tb_cflags(tb) & CF_PCREL || tb->pc =3D=3D desc->pc) && + if ((tb_cflags(tb) & CF_PCREL || tb->pc =3D=3D desc->s.pc) && tb_page_addr0(tb) =3D=3D desc->page_addr0 && - tb->cs_base =3D=3D desc->cs_base && - tb->flags =3D=3D desc->flags && - tb_cflags(tb) =3D=3D desc->cflags) { + tb->cs_base =3D=3D desc->s.cs_base && + tb->flags =3D=3D desc->s.flags && + tb_cflags(tb) =3D=3D desc->s.cflags) { /* check next page if needed */ tb_page_addr_t tb_phys_page1 =3D tb_page_addr1(tb); if (tb_phys_page1 =3D=3D -1) { @@ -185,7 +182,7 @@ static bool tb_lookup_cmp(const void *p, const void *d) * is different for the new TB. Therefore any exception raised * here by the faulting lookup is not premature. */ - virt_page1 =3D TARGET_PAGE_ALIGN(desc->pc); + virt_page1 =3D TARGET_PAGE_ALIGN(desc->s.pc); phys_page1 =3D get_page_addr_code(desc->env, virt_page1); if (tb_phys_page1 =3D=3D phys_page1) { return true; @@ -201,11 +198,8 @@ static TranslationBlock *tb_htable_lookup(CPUState *cp= u, TCGTBCPUState s) struct tb_desc desc; uint32_t h; =20 + desc.s =3D s; desc.env =3D cpu_env(cpu); - desc.cs_base =3D s.cs_base; - desc.flags =3D s.flags; - desc.cflags =3D s.cflags; - desc.pc =3D s.pc; phys_pc =3D get_page_addr_code(desc.env, s.pc); if (phys_pc =3D=3D -1) { return NULL; --=20 2.43.0 From nobody Sat Nov 15 22:35:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746135134; cv=none; d=zohomail.com; s=zohoarc; b=Vy29xV2wWec91aIytIzr5sRKoip0iZwSFIEmiiSfjmKqvTm5qTJBYdxg1z/QPCuNkDu4W4TuuD5TvQq6Cj1PzL6mAkfP/sVK1wGcz4dGvYBhv8MGYnsjUHxOpg5xQSZQ/zBr3QflQx8dNy99wG6SbtA9PcnUSua48sVdXnoFvOM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746135134; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=gsZ8FJcLEY5U3nEVLTj99X8sj4X3vzwcgXXSB46La3Y=; b=Nmo5uYu1XFc9KVFtZNBYuy4jymzetNZm2as/2UqEl3O14xjDqYhRHG3/2BBLLQbuM/wpymtAhoVDuGt3Y/5CzV3k7WPsQqMUMHw2GoVZprtiu97ImOUJoPUm5RpDcO7+6mIr/seof3e4G88vON3lPF8eSBcSzPaFOihqmKhYy5s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746135134382688.757678559532; Thu, 1 May 2025 14:32:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAbM0-00019i-Oj; Thu, 01 May 2025 17:22:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAbLo-00011a-L5 for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:48 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAbLm-0001aW-OR for qemu-devel@nongnu.org; Thu, 01 May 2025 17:21:48 -0400 Received: by mail-pj1-x1032.google.com with SMTP id 98e67ed59e1d1-301a4d5156aso2048764a91.1 for ; Thu, 01 May 2025 14:21:46 -0700 (PDT) Received: from stoup.. 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Thu, 01 May 2025 14:21:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 37/59] accel/tcg: Pass TCGTBCPUState to tb_gen_code Date: Thu, 1 May 2025 14:20:51 -0700 Message-ID: <20250501212113.2961531-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746135136346124100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/internal-common.h | 5 ++--- accel/tcg/cpu-exec.c | 4 ++-- accel/tcg/translate-all.c | 28 +++++++++++++--------------- 3 files changed, 17 insertions(+), 20 deletions(-) diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h index 98c702422f..1dbc45dd95 100644 --- a/accel/tcg/internal-common.h +++ b/accel/tcg/internal-common.h @@ -12,6 +12,7 @@ #include "exec/cpu-common.h" #include "exec/translation-block.h" #include "exec/mmap-lock.h" +#include "accel/tcg/tb-cpu-state.h" =20 extern int64_t max_delay; extern int64_t max_advance; @@ -46,9 +47,7 @@ static inline bool cpu_plugin_mem_cbs_enabled(const CPUSt= ate *cpu) #endif } =20 -TranslationBlock *tb_gen_code(CPUState *cpu, vaddr pc, - uint64_t cs_base, uint32_t flags, - int cflags); +TranslationBlock *tb_gen_code(CPUState *cpu, TCGTBCPUState s); void page_init(void); void tb_htable_init(void); void tb_reset_jump(TranslationBlock *tb, int n); diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 4ad84c2db8..a7436d2873 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -574,7 +574,7 @@ void cpu_exec_step_atomic(CPUState *cpu) tb =3D tb_lookup(cpu, s); if (tb =3D=3D NULL) { mmap_lock(); - tb =3D tb_gen_code(cpu, s.pc, s.cs_base, s.flags, s.cflags); + tb =3D tb_gen_code(cpu, s); mmap_unlock(); } =20 @@ -951,7 +951,7 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc) uint32_t h; =20 mmap_lock(); - tb =3D tb_gen_code(cpu, s.pc, s.cs_base, s.flags, s.cflags= ); + tb =3D tb_gen_code(cpu, s); mmap_unlock(); =20 /* diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 97aadee52c..7b0bd50904 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -290,9 +290,7 @@ static int setjmp_gen_code(CPUArchState *env, Translati= onBlock *tb, } =20 /* Called with mmap_lock held for user mode emulation. */ -TranslationBlock *tb_gen_code(CPUState *cpu, - vaddr pc, uint64_t cs_base, - uint32_t flags, int cflags) +TranslationBlock *tb_gen_code(CPUState *cpu, TCGTBCPUState s) { CPUArchState *env =3D cpu_env(cpu); TranslationBlock *tb, *existing_tb; @@ -305,14 +303,14 @@ TranslationBlock *tb_gen_code(CPUState *cpu, assert_memory_lock(); qemu_thread_jit_write(); =20 - phys_pc =3D get_page_addr_code_hostp(env, pc, &host_pc); + phys_pc =3D get_page_addr_code_hostp(env, s.pc, &host_pc); =20 if (phys_pc =3D=3D -1) { /* Generate a one-shot TB with 1 insn in it */ - cflags =3D (cflags & ~CF_COUNT_MASK) | 1; + s.cflags =3D (s.cflags & ~CF_COUNT_MASK) | 1; } =20 - max_insns =3D cflags & CF_COUNT_MASK; + max_insns =3D s.cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D TCG_MAX_INSNS; } @@ -332,12 +330,12 @@ TranslationBlock *tb_gen_code(CPUState *cpu, =20 gen_code_buf =3D tcg_ctx->code_gen_ptr; tb->tc.ptr =3D tcg_splitwx_to_rx(gen_code_buf); - if (!(cflags & CF_PCREL)) { - tb->pc =3D pc; + if (!(s.cflags & CF_PCREL)) { + tb->pc =3D s.pc; } - tb->cs_base =3D cs_base; - tb->flags =3D flags; - tb->cflags =3D cflags; + tb->cs_base =3D s.cs_base; + tb->flags =3D s.flags; + tb->cflags =3D s.cflags; tb_set_page_addr0(tb, phys_pc); tb_set_page_addr1(tb, -1); if (phys_pc !=3D -1) { @@ -355,9 +353,9 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_ctx->guest_mo =3D cpu->cc->tcg_ops->guest_default_memory_order; =20 restart_translate: - trace_translate_block(tb, pc, tb->tc.ptr); + trace_translate_block(tb, s.pc, tb->tc.ptr); =20 - gen_code_size =3D setjmp_gen_code(env, tb, pc, host_pc, &max_insns, &t= i); + gen_code_size =3D setjmp_gen_code(env, tb, s.pc, host_pc, &max_insns, = &ti); if (unlikely(gen_code_size < 0)) { switch (gen_code_size) { case -1: @@ -434,10 +432,10 @@ TranslationBlock *tb_gen_code(CPUState *cpu, * For CF_PCREL, attribute all executions of the generated code * to its first mapping. */ - perf_report_code(pc, tb, tcg_splitwx_to_rx(gen_code_buf)); + perf_report_code(s.pc, tb, tcg_splitwx_to_rx(gen_code_buf)); =20 if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM) && - qemu_log_in_addr_range(pc)) { + qemu_log_in_addr_range(s.pc)) { FILE *logfile =3D qemu_log_trylock(); if (logfile) { int code_size, data_size; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-30a476267e0sm1384573a91.39.2025.05.01.14.21.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 May 2025 14:21:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746134506; x=1746739306; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=D0jG93rvSyOgsjKDUChcn5N32sYYanMJMMGrdtwKZxY=; b=QMlcc1Pz3/7mDpWe+0ru9Ov24mfZcfXAsKX7X/7lxlpLrYIeHVKRahpYDKLT0OPQMi KwwFwTFWOWa8SoF6a6okAPDaXGxmD8SkYu3B8Bf7tUZpmUIOvBxmcAV6dKnN3AkxWQzz OJquIv08SW3nqpJ79afiemp9hlizw28w/9znR+bknjiv91qYBlCwcNKSYx/6JNrZdJcd vBZ/8+1rMN8ESzjlS4sDYrlXfLM19L60IejprrGVXtgVsZtdbma/L7+Yq+5nw25sWsVU M1ozfMxtnYHIy/uN0HK6zKCsMPZrNyEwOFH2qGuIg5Mg1v1YTFegSubOXzZusuw/LRG2 iDrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746134506; x=1746739306; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=D0jG93rvSyOgsjKDUChcn5N32sYYanMJMMGrdtwKZxY=; b=ghvVfeFjy3/OYGgTf5CafEq7TdfiU2XogOaUoosG8aE2Pqys0p+wODXZ7oDyPHt6v3 1ePnZwcNnA0RphbjibzL5NejjNzjCg8QtmPp1ilKH2nil4ZEcwHqu9fz/ax9lfxIzOBQ oun41/ESISmPNb66yvSED8cx+QRb1gZ7oNpVxjfz7wCJ5+fR64szrwhadE1m1uGxdPPD Ly6PZ3nTNZL0h+9N5ooM/fmou4iF1zRXfBmfBLStwKzRRIu9h/cjc27aPI0iM1nZ/XA0 WYHw9VKFEeWIwti1WveeNzf+VdpqpbjSlO6xkkkVnm2g1EkbrBmX+p1q9919G6Co/uj4 P+qA== X-Gm-Message-State: AOJu0YwYl3mirC1tWrNv1VLEAX4QXRSFHsrxGDB8Kbcnje12O/t9K1M4 247wO67BDw8ptA2Tl+rhCBiSBq9R6LwB6SX1yEptQpWxOb8SNkcd2SD+1K2CPdQEL7x7LTAMolG t X-Gm-Gg: ASbGncvIGxGUFGcy0ITeio8qd8mYrpDFd3Gm1dnuHUDaHwrVmyG/jEUYtsEHgPpxeST SkoR/TufSmy+6eJvwjC/R3SgH0+89tUgrD8N+LdAUoEhuyJ7STZitiWdkpAiONlwQ6SEu6gzG2i ZQyiVsf7gbZ+Q7G6yRuYLYqwngvj7c8QA8qqRxWzaPDMRRDyJnVwOXUYLEJ2z1eoC9SmLPFTCyA zQ9H7FtDfiJJolVvc0S8JuqtDbUXV0pZkkyccz/UlsX6UW2UyT54jDmdhmLOXEyF/ARpSdwIAG9 DJYC3HTFvWF0EFqW+xCG5DK+G7pROtruH0hNLzYaRPgEXJxpmJOZgvT3parTyB0th+coL+uC1IE = X-Google-Smtp-Source: AGHT+IHmxZ2kTAiYA/CM6OCZj/WYwqHgAUaby0RisE9Xan19iLJtZqlWm6CnHZkWBNFIL9dqvspr4A== X-Received: by 2002:a17:90b:520a:b0:2ff:693a:7590 with SMTP id 98e67ed59e1d1-30a4e6bf082mr934344a91.33.1746134505980; Thu, 01 May 2025 14:21:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 38/59] accel/tcg: Split out accel/tcg/helper-retaddr.h Date: Thu, 1 May 2025 14:20:52 -0700 Message-ID: <20250501212113.2961531-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746134600316124100 Move set_helper_retaddr and clear_helper_retaddr to a new header file. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/accel/tcg/cpu-ldst.h | 34 ----------------------- include/accel/tcg/helper-retaddr.h | 43 ++++++++++++++++++++++++++++++ accel/tcg/cpu-exec.c | 1 + accel/tcg/user-exec.c | 1 + target/arm/tcg/helper-a64.c | 1 + target/arm/tcg/sme_helper.c | 1 + target/arm/tcg/sve_helper.c | 1 + target/ppc/mem_helper.c | 1 + target/s390x/tcg/mem_helper.c | 1 + 9 files changed, 50 insertions(+), 34 deletions(-) create mode 100644 include/accel/tcg/helper-retaddr.h diff --git a/include/accel/tcg/cpu-ldst.h b/include/accel/tcg/cpu-ldst.h index f97a730703..44a62b54da 100644 --- a/include/accel/tcg/cpu-ldst.h +++ b/include/accel/tcg/cpu-ldst.h @@ -526,38 +526,4 @@ void *tlb_vaddr_to_host(CPUArchState *env, vaddr addr, MMUAccessType access_type, int mmu_idx); #endif =20 -/* - * For user-only, helpers that use guest to host address translation - * must protect the actual host memory access by recording 'retaddr' - * for the signal handler. This is required for a race condition in - * which another thread unmaps the page between a probe and the - * actual access. - */ -#ifdef CONFIG_USER_ONLY -extern __thread uintptr_t helper_retaddr; - -static inline void set_helper_retaddr(uintptr_t ra) -{ - helper_retaddr =3D ra; - /* - * Ensure that this write is visible to the SIGSEGV handler that - * may be invoked due to a subsequent invalid memory operation. - */ - signal_barrier(); -} - -static inline void clear_helper_retaddr(void) -{ - /* - * Ensure that previous memory operations have succeeded before - * removing the data visible to the signal handler. - */ - signal_barrier(); - helper_retaddr =3D 0; -} -#else -#define set_helper_retaddr(ra) do { } while (0) -#define clear_helper_retaddr() do { } while (0) -#endif - #endif /* ACCEL_TCG_CPU_LDST_H */ diff --git a/include/accel/tcg/helper-retaddr.h b/include/accel/tcg/helper-= retaddr.h new file mode 100644 index 0000000000..037fda2b83 --- /dev/null +++ b/include/accel/tcg/helper-retaddr.h @@ -0,0 +1,43 @@ +/* + * Get user helper pc for memory unwinding. + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef ACCEL_TCG_HELPER_RETADDR_H +#define ACCEL_TCG_HELPER_RETADDR_H + +/* + * For user-only, helpers that use guest to host address translation + * must protect the actual host memory access by recording 'retaddr' + * for the signal handler. This is required for a race condition in + * which another thread unmaps the page between a probe and the + * actual access. + */ +#ifdef CONFIG_USER_ONLY +extern __thread uintptr_t helper_retaddr; + +static inline void set_helper_retaddr(uintptr_t ra) +{ + helper_retaddr =3D ra; + /* + * Ensure that this write is visible to the SIGSEGV handler that + * may be invoked due to a subsequent invalid memory operation. + */ + signal_barrier(); +} + +static inline void clear_helper_retaddr(void) +{ + /* + * Ensure that previous memory operations have succeeded before + * removing the data visible to the signal handler. + */ + signal_barrier(); + helper_retaddr =3D 0; +} +#else +#define set_helper_retaddr(ra) do { } while (0) +#define clear_helper_retaddr() do { } while (0) +#endif + +#endif /* ACCEL_TCG_HELPER_RETADDR_H */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index a7436d2873..a8fbda31ba 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -24,6 +24,7 @@ #include "hw/core/cpu.h" #include "accel/tcg/cpu-ldst.h" #include "accel/tcg/cpu-ops.h" +#include "accel/tcg/helper-retaddr.h" #include "trace.h" #include "disas/disas.h" #include "exec/cpu-common.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 70feee8df9..68e01fc584 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -26,6 +26,7 @@ #include "qemu/bitops.h" #include "qemu/rcu.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/helper-retaddr.h" #include "accel/tcg/probe.h" #include "user/cpu_loop.h" #include "qemu/main-loop.h" diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 9cffda07cd..4f618ae390 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -30,6 +30,7 @@ #include "qemu/crc32c.h" #include "exec/cpu-common.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/helper-retaddr.h" #include "accel/tcg/probe.h" #include "exec/target_page.h" #include "exec/tlb-flags.h" diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index 3226895cae..de0c6e54d4 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -23,6 +23,7 @@ #include "tcg/tcg-gvec-desc.h" #include "exec/helper-proto.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/helper-retaddr.h" #include "qemu/int128.h" #include "fpu/softfloat.h" #include "vec_internal.h" diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 9f20ecb51d..a2c363a4e1 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -30,6 +30,7 @@ #include "vec_internal.h" #include "sve_ldst_internal.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/helper-retaddr.h" #include "accel/tcg/cpu-ops.h" #include "accel/tcg/probe.h" #ifdef CONFIG_USER_ONLY diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index aa1af44d22..6ab71a6fcb 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -24,6 +24,7 @@ #include "exec/helper-proto.h" #include "helper_regs.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/helper-retaddr.h" #include "accel/tcg/probe.h" #include "internal.h" #include "qemu/atomic128.h" diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 857005b120..a03609a140 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -32,6 +32,7 @@ #include "exec/target_page.h" #include "exec/tlb-flags.h" #include "accel/tcg/cpu-ops.h" +#include "accel/tcg/helper-retaddr.h" #include "qemu/int128.h" #include "qemu/atomic128.h" =20 --=20 2.43.0 From nobody Sat Nov 15 22:35:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 01 May 2025 14:21:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 39/59] accel/tcg: Compile cpu-exec.c twice Date: Thu, 1 May 2025 14:20:53 -0700 Message-ID: <20250501212113.2961531-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746134660659124100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 2 -- accel/tcg/meson.build | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index a8fbda31ba..cc5f362305 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -22,7 +22,6 @@ #include "qapi/error.h" #include "qapi/type-helpers.h" #include "hw/core/cpu.h" -#include "accel/tcg/cpu-ldst.h" #include "accel/tcg/cpu-ops.h" #include "accel/tcg/helper-retaddr.h" #include "trace.h" @@ -37,7 +36,6 @@ #include "qemu/rcu.h" #include "exec/log.h" #include "qemu/main-loop.h" -#include "cpu.h" #include "exec/icount.h" #include "exec/replay-core.h" #include "system/tcg.h" diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 3f7b127130..0bb089299b 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -5,6 +5,7 @@ endif tcg_ss =3D ss.source_set() =20 tcg_ss.add(files( + 'cpu-exec.c', 'cpu-exec-common.c', 'tcg-runtime.c', 'tcg-runtime-gvec.c', @@ -21,7 +22,6 @@ libsystem_ss.add_all(tcg_ss) tcg_specific_ss =3D ss.source_set() tcg_specific_ss.add(files( 'tcg-all.c', - 'cpu-exec.c', 'translate-all.c', )) tcg_specific_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user-exec.c'= )) --=20 2.43.0 From nobody Sat Nov 15 22:35:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-740590610desm135897b3a.146.2025.05.01.14.24.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 May 2025 14:24:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746134687; x=1746739487; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iQ4d9VytMAyaMdEQkNc3+qF4cN/HnIg5sNtYWblQ1ok=; b=W5AvDSFVRywxzDxgULyeO141looRy6yTbT7gnj3zjZ5wbe+4FzoHRBG3PB2T73ARZP SNtdry3lsW7v/IEWJ7SbGa3sVMJ1m7MAVYtX5qWlF8y0CL5hum6hu7Y8PGht9JH/Od/Y XqNY96nd1U2ny6RZBpJ2lJWSJAi4Z1Pas/RIZodn45OE8qsnSgqDAUNozKym5hqjPxx4 NVQ9pVM0w8IhZlknhor30LEJwdv+yl0i9Eah9F0LSu26P3zSPwSb9KNHzItBAc1mbO15 s7NSKPL0HPTcdeIA+B7Ozkiap1TNUyfRxcLNQX2/7oDlC5D+5BRRBUrKeBDkxq/7nCO7 yihg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746134687; x=1746739487; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iQ4d9VytMAyaMdEQkNc3+qF4cN/HnIg5sNtYWblQ1ok=; b=nuEKubPH+XV4fi4krGbne1v4JLceFKI4vc3n7iFndM1AAswPtOFI4oQaANPs2doFXF /RE3Ht5X2Fj4/ZkfMOU3ZEDV17A9yYPkfgCJSB8uCfq2x30kRXV0NIZxLEB0hW0qbt+u 6QdbcQqv9LyjLCGx/hVNNm1pFUjnH0uB1vECWpWOboPW9jKE3mK3FoZ/bcaQ333KKelA saCFAE+CvxxiRWCfPALJ7TX0WkdbOji2srxUlyr3fD2elb2Hj2xT+2dP/gR4tc2ja12W SPLFg3JN2/d1sCC2SI0hiXWcGRKvrEYWbdUcLeJ1AQtnlP/SfiOg2PfYZlTB/hfwJoej yf5Q== X-Gm-Message-State: AOJu0YyVyS5N93DomWomhSqV7EGM1XH8fsfKuzTngcgcheaZSclEONJu eV6b+kktUOIKUjnvmBP0P3MjdrxQAWR1YALMefiqbZsaHzKCSdaNJnzOPvXtc8FKSTVakYgx5Kl K X-Gm-Gg: ASbGncvn8L0UpDRGkPu/weXVfAhQzelRDSmVYcucmx3QOgH+dPbBSoLPPexLQLb1QtZ lnlycZWaAIY8NTao0HWFwHe1Vo2d4Wb9h9kprt5QNnoyQ1xUuRrtAaTqKatc16t0rOsLlZHQ44W 0GU1fb7hJgFnasXR77XzFDQwLYO8ozuiLNPPadHWJTt9SXB2ePCE86qHqTzJbkzy97A9EKd3nkK b5khNct+qumxaCLLBXqwnW76Op5xZ5+8nXon5UhXACP51u3QQvLItpkI7MpcVedX/WLTITsHeUE oxrpk7+pZZRr9QMf7p/tSPGir0jCrvR9W82iDC3NywJ57LZThHLLJtdT+8L0LsXi27oMAxUAwvq ppWlLNGLR3w== X-Google-Smtp-Source: AGHT+IEIFvDHIPpmVOYQKZDhA6VfBbl0atE9ys4hVp5TySxvaTO4GH2W1mNMkUA+HSWdHe31e9akBQ== X-Received: by 2002:a05:6a00:4482:b0:739:4a93:a5db with SMTP id d2e1a72fcca58-74058b510aemr586109b3a.22.1746134687646; Thu, 01 May 2025 14:24:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 40/59] system/vl: Filter machine list available for a particular target binary Date: Thu, 1 May 2025 14:20:54 -0700 Message-ID: <20250501212113.2961531-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746134770763124100 From: Philippe Mathieu-Daud=C3=A9 Binaries can register a QOM type to filter their machines by filling their TargetInfo::machine_typename field. This can be used by example by main() -> machine_help_func() to filter the machines list. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- include/qemu/target-info-impl.h | 2 ++ include/qemu/target-info.h | 8 ++++++++ system/vl.c | 3 ++- target-info-stub.c | 2 ++ target-info.c | 5 +++++ 5 files changed, 19 insertions(+), 1 deletion(-) diff --git a/include/qemu/target-info-impl.h b/include/qemu/target-info-imp= l.h index d30805f7f2..d0e8c86176 100644 --- a/include/qemu/target-info-impl.h +++ b/include/qemu/target-info-impl.h @@ -14,6 +14,8 @@ typedef struct TargetInfo { /* runtime equivalent of TARGET_NAME definition */ const char *target_name; + /* QOM typename machines for this binary must implement */ + const char *machine_typename; } TargetInfo; =20 /** diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h index 58d4136897..2b6ccabb11 100644 --- a/include/qemu/target-info.h +++ b/include/qemu/target-info.h @@ -16,6 +16,14 @@ */ const char *target_name(void); =20 +/** + * target_machine_typename: + * + * Returns: Name of the QOM interface implemented by machines + * usable on this target binary. + */ +const char *target_machine_typename(void); + /** * target_cpu_type: * diff --git a/system/vl.c b/system/vl.c index 520956f4a1..7223f1ff17 100644 --- a/system/vl.c +++ b/system/vl.c @@ -27,6 +27,7 @@ #include "qemu/datadir.h" #include "qemu/units.h" #include "qemu/module.h" +#include "qemu/target-info.h" #include "exec/cpu-common.h" #include "exec/page-vary.h" #include "hw/qdev-properties.h" @@ -1564,7 +1565,7 @@ static void machine_help_func(const QDict *qdict) GSList *el; const char *type =3D qdict_get_try_str(qdict, "type"); =20 - machines =3D object_class_get_list(TYPE_MACHINE, false); + machines =3D object_class_get_list(target_machine_typename(), false); if (type) { ObjectClass *machine_class =3D OBJECT_CLASS(find_machine(type, mac= hines)); if (machine_class) { diff --git a/target-info-stub.c b/target-info-stub.c index 773a10188c..bcf834f71d 100644 --- a/target-info-stub.c +++ b/target-info-stub.c @@ -9,10 +9,12 @@ #include "qemu/osdep.h" #include "qemu/target-info.h" #include "qemu/target-info-impl.h" +#include "hw/boards.h" #include "cpu.h" =20 static const TargetInfo target_info_stub =3D { .target_name =3D TARGET_NAME, + .machine_typename =3D TYPE_MACHINE, }; =20 const TargetInfo *target_info(void) diff --git a/target-info.c b/target-info.c index 84b18931e7..0042769e3a 100644 --- a/target-info.c +++ b/target-info.c @@ -14,3 +14,8 @@ const char *target_name(void) { return target_info()->target_name; } + +const char *target_machine_typename(void) +{ + return target_info()->machine_typename; +} --=20 2.43.0 From nobody Sat Nov 15 22:35:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746134749; cv=none; d=zohomail.com; s=zohoarc; b=eMsWyrpRPMpBFytRTgJszvn3Sg5yjHa8jahZwVbcJVERfKkNNth1ZvgsbwLVJSwxQSPfpJbLsRg6t5S8uJ8yxnQ+gvQ1OI14Ps4VBxMv24DaPdI9P2BavFwOEV6jpYd+zBi0uHqt13715EyXYLUwFa8jfpETgHISdrbMF/wTlCY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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Thu, 01 May 2025 14:24:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 41/59] qemu/target_info: Add %target_cpu_type field to TargetInfo Date: Thu, 1 May 2025 14:20:55 -0700 Message-ID: <20250501212113.2961531-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746134752018019100 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/qemu/target-info-impl.h | 2 ++ target-info-stub.c | 6 +----- target-info.c | 5 +++++ 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/include/qemu/target-info-impl.h b/include/qemu/target-info-imp= l.h index d0e8c86176..76766eeaae 100644 --- a/include/qemu/target-info-impl.h +++ b/include/qemu/target-info-impl.h @@ -14,6 +14,8 @@ typedef struct TargetInfo { /* runtime equivalent of TARGET_NAME definition */ const char *target_name; + /* runtime equivalent of CPU_RESOLVING_TYPE definition */ + const char *cpu_type; /* QOM typename machines for this binary must implement */ const char *machine_typename; } TargetInfo; diff --git a/target-info-stub.c b/target-info-stub.c index bcf834f71d..86da297277 100644 --- a/target-info-stub.c +++ b/target-info-stub.c @@ -14,6 +14,7 @@ =20 static const TargetInfo target_info_stub =3D { .target_name =3D TARGET_NAME, + .cpu_type =3D CPU_RESOLVING_TYPE, .machine_typename =3D TYPE_MACHINE, }; =20 @@ -21,8 +22,3 @@ const TargetInfo *target_info(void) { return &target_info_stub; } - -const char *target_cpu_type(void) -{ - return CPU_RESOLVING_TYPE; -} diff --git a/target-info.c b/target-info.c index 0042769e3a..5f5ef1f932 100644 --- a/target-info.c +++ b/target-info.c @@ -15,6 +15,11 @@ const char *target_name(void) return target_info()->target_name; } =20 +const char *target_cpu_type(void) +{ + return target_info()->cpu_type; +} + const char *target_machine_typename(void) { return target_info()->machine_typename; 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Thu, 01 May 2025 14:24:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 42/59] qemu: Introduce target_long_bits() Date: Thu, 1 May 2025 14:20:56 -0700 Message-ID: <20250501212113.2961531-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746135077278019100 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/qemu/target-info-impl.h | 2 ++ include/qemu/target-info.h | 7 +++++++ target-info-stub.c | 1 + target-info.c | 5 +++++ 4 files changed, 15 insertions(+) diff --git a/include/qemu/target-info-impl.h b/include/qemu/target-info-imp= l.h index 76766eeaae..1b51cbcfe1 100644 --- a/include/qemu/target-info-impl.h +++ b/include/qemu/target-info-impl.h @@ -14,6 +14,8 @@ typedef struct TargetInfo { /* runtime equivalent of TARGET_NAME definition */ const char *target_name; + /* runtime equivalent of TARGET_LONG_BITS definition */ + unsigned long_bits; /* runtime equivalent of CPU_RESOLVING_TYPE definition */ const char *cpu_type; /* QOM typename machines for this binary must implement */ diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h index 2b6ccabb11..850a2958b9 100644 --- a/include/qemu/target-info.h +++ b/include/qemu/target-info.h @@ -16,6 +16,13 @@ */ const char *target_name(void); =20 +/** + * target_long_bits: + * + * Returns: number of bits in a long type for this target (i.e. 64). + */ +unsigned target_long_bits(void); + /** * target_machine_typename: * diff --git a/target-info-stub.c b/target-info-stub.c index 86da297277..fecc0e7128 100644 --- a/target-info-stub.c +++ b/target-info-stub.c @@ -14,6 +14,7 @@ =20 static const TargetInfo target_info_stub =3D { .target_name =3D TARGET_NAME, + .long_bits =3D TARGET_LONG_BITS, .cpu_type =3D CPU_RESOLVING_TYPE, .machine_typename =3D TYPE_MACHINE, }; diff --git a/target-info.c b/target-info.c index 5f5ef1f932..16fdca7aaa 100644 --- a/target-info.c +++ b/target-info.c @@ -15,6 +15,11 @@ const char *target_name(void) return target_info()->target_name; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-740590610desm135897b3a.146.2025.05.01.14.24.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 May 2025 14:24:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746134689; x=1746739489; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NOn2Y1giKBfi7cu53+t6CSfZv1TgtkzLY9Zga711y9o=; b=qykBvOiJYsNDesUUAhmFIl4hizb6mzNbxMhQlgo/pAr4sXJ2Sr1ZOY2VDs30fcHWSl nSV7iK4HTSAjNX0MT1wNr5xsGdKCSosL70hsGa7xKb/2wBsh5+QectCqVdRlrgtZXk0Z unRW2ITWaQSiRf0ELmSo0TDmG9U6iGU/sZGqOYQDgU1Q2jWwIQnb90EvTsWcVbS2Bsti r13ZXodrY99NgqNKrDgzTdfWCNJSlWj/v4Ftf0gtcZ/eH0vb6bTR3GDJ/WpU0CjoCuRK rrJNHOfC+rKTEdjvY/JgYd7m2GHlodb1xUCO5OUPP+qQScOQJEFosAfHymVS4jrFXcgx HvmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746134689; x=1746739489; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NOn2Y1giKBfi7cu53+t6CSfZv1TgtkzLY9Zga711y9o=; b=HL6QouRVbmgSU90yAF4jmkihLJQwizXtzCHIedt/2wIAEUtDSQtggMxATla2qWluq9 42KFnKkWdhFSM1ZTU7Os43pS/wmPTjshGNCnzijaPZHfb4n4SybIrk7ilFC38B68Jc8W T8EfuFJRMC5NHfmQZYtiAs1JmphV6fhmmvAxEZ4/r9xbViGB+pPFnS6FebXq5ZFsH6qQ hmF2Fniz9UCGz8DLnUPff+7zq8IjtoED4RljZ8Z6LbptutKgEKgljdT9Z2eOKZG9SSQz RuKKgSzufyx8RlJ4UgU/U0fW6aME72UGAJL1NIlcYqDzH11hS9TdKaJ4ATDUychOmaOS 91cw== X-Gm-Message-State: AOJu0Yys/cIEHjvjmeyPZ8m00CRNTcRhyhDYLX0kADEJF5NWNuKSb26M l9c7uYsbKeRwFGnTJrcjqgMsXFI/eS/CVAYYKwQEJoW9uUcoIChQ3SGt5wGnZdJYKHzJXH4e+5R x X-Gm-Gg: ASbGncvF9lVCujFYPJf+gHVSqMua9eKXIJQqw11oRHtZpZLeBaBO6Un99ALGg/ngx+Z h80sdgF38cQmkicZfVUdI5S+Mm7Qr2nMfu4EPw5kV6pc684Mjc2HDY4PBy4N+WjeCehjfCbPSDC DVooayFNIjEXjAbnQaWAIFdWLzXfYIc1lr0VjHIsTUc6RECTOufGsKfI6dWKs2QKcKumv+7y0zT zpoehoKfYmZeZH4iYhX3mr79Fd3/99KCiAw8Nj9GHjZdjbjp4nTDPmMvHV775xqs5oWZqDO9MsB 0oEVr13nPQZscVpGkne6yNGqC/kxWZYLB/jsaPfhdb8eSooC03qRrwfi2nLShtwWVJa5qMc4+hM = X-Google-Smtp-Source: AGHT+IFkNGPmDRebvaWaiBnnHgN8upUAb/HxluDke1BTFuIf80jchZ2J2uPhu6PBkLvqkvMUMaRTiQ== X-Received: by 2002:a05:6a00:2908:b0:737:6fdf:bb69 with SMTP id d2e1a72fcca58-74058a557demr647374b3a.13.1746134689461; Thu, 01 May 2025 14:24:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 43/59] tcg: Define INSN_START_WORDS as constant 3 Date: Thu, 1 May 2025 14:20:57 -0700 Message-ID: <20250501212113.2961531-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746134858503019100 Content-Type: text/plain; charset="utf-8" Use the same value for all targets. Rename TARGET_INSN_START_WORDS and do not depend on TARGET_INSN_START_EXTRA_WORDS. Remove TCGContext.insn_start_words. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/tcg/insn-start-words.h | 11 +++++------ include/tcg/tcg-op.h | 17 ++++++++++++++--- include/tcg/tcg-opc.h | 3 +-- include/tcg/tcg.h | 12 +++++++----- accel/tcg/translate-all.c | 19 +++++++++---------- target/i386/helper.c | 2 +- target/openrisc/sys_helper.c | 2 +- tcg/perf.c | 5 ++--- tcg/tcg.c | 12 +++++------- 9 files changed, 45 insertions(+), 38 deletions(-) diff --git a/include/tcg/insn-start-words.h b/include/tcg/insn-start-words.h index d416d19bcf..c52aec50a7 100644 --- a/include/tcg/insn-start-words.h +++ b/include/tcg/insn-start-words.h @@ -1,13 +1,12 @@ /* SPDX-License-Identifier: MIT */ /* - * Define TARGET_INSN_START_WORDS + * Define INSN_START_WORDS * Copyright (c) 2008 Fabrice Bellard */ =20 -#ifndef TARGET_INSN_START_WORDS +#ifndef TCG_INSN_START_WORDS +#define TCG_INSN_START_WORDS =20 -#include "cpu-param.h" +#define INSN_START_WORDS 3 =20 -# define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS) - -#endif /* TARGET_INSN_START_WORDS */ +#endif /* TCG_INSN_START_WORDS */ diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 59d19755e6..c912578fdd 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -9,6 +9,7 @@ #define TCG_TCG_OP_H =20 #include "tcg/tcg-op-common.h" +#include "tcg/insn-start-words.h" #include "exec/target_long.h" =20 #ifndef TARGET_LONG_BITS @@ -23,24 +24,34 @@ # error #endif =20 +#if INSN_START_WORDS !=3D 3 +# error Mismatch with insn-start-words.h +#endif + #if TARGET_INSN_START_EXTRA_WORDS =3D=3D 0 static inline void tcg_gen_insn_start(target_ulong pc) { - TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, 64 / TCG_TARGET_REG_BIT= S); + TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, + INSN_START_WORDS * 64 / TCG_TARGET_REG_BITS); tcg_set_insn_start_param(op, 0, pc); + tcg_set_insn_start_param(op, 1, 0); + tcg_set_insn_start_param(op, 2, 0); } #elif TARGET_INSN_START_EXTRA_WORDS =3D=3D 1 static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) { - TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, 2 * 64 / TCG_TARGET_REG= _BITS); + TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, + INSN_START_WORDS * 64 / TCG_TARGET_REG_BITS); tcg_set_insn_start_param(op, 0, pc); tcg_set_insn_start_param(op, 1, a1); + tcg_set_insn_start_param(op, 2, 0); } #elif TARGET_INSN_START_EXTRA_WORDS =3D=3D 2 static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, target_ulong a2) { - TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, 3 * 64 / TCG_TARGET_REG= _BITS); + TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, + INSN_START_WORDS * 64 / TCG_TARGET_REG_BITS); tcg_set_insn_start_param(op, 0, pc); tcg_set_insn_start_param(op, 1, a1); tcg_set_insn_start_param(op, 2, a2); diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index 995b79383e..e988edd93a 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -114,8 +114,7 @@ DEF(extrh_i64_i32, 1, 1, 0, 0) =20 #define DATA64_ARGS (TCG_TARGET_REG_BITS =3D=3D 64 ? 1 : 2) =20 -/* There are tcg_ctx->insn_start_words here, not just one. */ -DEF(insn_start, 0, 0, DATA64_ARGS, TCG_OPF_NOT_PRESENT) +DEF(insn_start, 0, 0, DATA64_ARGS * INSN_START_WORDS, TCG_OPF_NOT_PRESENT) =20 DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END | TCG_OPF_NOT_PRESE= NT) DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END | TCG_OPF_NOT_PRESE= NT) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index aa300a2f8b..a8c00c72cc 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -34,6 +34,7 @@ #include "tcg-target-reg-bits.h" #include "tcg-target.h" #include "tcg/tcg-cond.h" +#include "tcg/insn-start-words.h" #include "tcg/debug-assert.h" =20 /* XXX: make safe guess about sizes */ @@ -359,7 +360,6 @@ struct TCGContext { int page_mask; uint8_t page_bits; uint8_t tlb_dyn_max_bits; - uint8_t insn_start_words; TCGBar guest_mo; =20 TCGRegSet reserved_regs; @@ -582,18 +582,19 @@ static inline TCGv_vec temp_tcgv_vec(TCGTemp *t) return (TCGv_vec)temp_tcgv_i32(t); } =20 -static inline TCGArg tcg_get_insn_param(TCGOp *op, int arg) +static inline TCGArg tcg_get_insn_param(TCGOp *op, unsigned arg) { return op->args[arg]; } =20 -static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v) +static inline void tcg_set_insn_param(TCGOp *op, unsigned arg, TCGArg v) { op->args[arg] =3D v; } =20 -static inline uint64_t tcg_get_insn_start_param(TCGOp *op, int arg) +static inline uint64_t tcg_get_insn_start_param(TCGOp *op, unsigned arg) { + tcg_debug_assert(arg < INSN_START_WORDS); if (TCG_TARGET_REG_BITS =3D=3D 64) { return tcg_get_insn_param(op, arg); } else { @@ -602,8 +603,9 @@ static inline uint64_t tcg_get_insn_start_param(TCGOp *= op, int arg) } } =20 -static inline void tcg_set_insn_start_param(TCGOp *op, int arg, uint64_t v) +static inline void tcg_set_insn_start_param(TCGOp *op, unsigned arg, uint6= 4_t v) { + tcg_debug_assert(arg < INSN_START_WORDS); if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_set_insn_param(op, arg, v); } else { diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 7b0bd50904..fa4998b341 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -120,7 +120,7 @@ static int64_t decode_sleb128(const uint8_t **pp) /* Encode the data collected about the instructions while compiling TB. Place the data at BLOCK, and return the number of bytes consumed. =20 - The logical table consists of TARGET_INSN_START_WORDS target_ulong's, + The logical table consists of INSN_START_WORDS uint64_t's, which come from the target's insn_start data, followed by a uintptr_t which comes from the host pc of the end of the code implementing the in= sn. =20 @@ -140,13 +140,13 @@ static int encode_search(TranslationBlock *tb, uint8_= t *block) for (i =3D 0, n =3D tb->icount; i < n; ++i) { uint64_t prev, curr; =20 - for (j =3D 0; j < TARGET_INSN_START_WORDS; ++j) { + for (j =3D 0; j < INSN_START_WORDS; ++j) { if (i =3D=3D 0) { prev =3D (!(tb_cflags(tb) & CF_PCREL) && j =3D=3D 0 ? tb->= pc : 0); } else { - prev =3D insn_data[(i - 1) * TARGET_INSN_START_WORDS + j]; + prev =3D insn_data[(i - 1) * INSN_START_WORDS + j]; } - curr =3D insn_data[i * TARGET_INSN_START_WORDS + j]; + curr =3D insn_data[i * INSN_START_WORDS + j]; p =3D encode_sleb128(p, curr - prev); } prev =3D (i =3D=3D 0 ? 0 : insn_end_off[i - 1]); @@ -178,7 +178,7 @@ static int cpu_unwind_data_from_tb(TranslationBlock *tb= , uintptr_t host_pc, return -1; } =20 - memset(data, 0, sizeof(uint64_t) * TARGET_INSN_START_WORDS); + memset(data, 0, sizeof(uint64_t) * INSN_START_WORDS); if (!(tb_cflags(tb) & CF_PCREL)) { data[0] =3D tb->pc; } @@ -188,7 +188,7 @@ static int cpu_unwind_data_from_tb(TranslationBlock *tb= , uintptr_t host_pc, * at which the end of the insn exceeds host_pc. */ for (i =3D 0; i < num_insns; ++i) { - for (j =3D 0; j < TARGET_INSN_START_WORDS; ++j) { + for (j =3D 0; j < INSN_START_WORDS; ++j) { data[j] +=3D decode_sleb128(&p); } iter_pc +=3D decode_sleb128(&p); @@ -206,7 +206,7 @@ static int cpu_unwind_data_from_tb(TranslationBlock *tb= , uintptr_t host_pc, void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, uintptr_t host_pc) { - uint64_t data[TARGET_INSN_START_WORDS]; + uint64_t data[INSN_START_WORDS]; int insns_left =3D cpu_unwind_data_from_tb(tb, host_pc, data); =20 if (insns_left < 0) { @@ -349,7 +349,6 @@ TranslationBlock *tb_gen_code(CPUState *cpu, TCGTBCPUSt= ate s) tcg_ctx->page_mask =3D TARGET_PAGE_MASK; tcg_ctx->tlb_dyn_max_bits =3D CPU_TLB_DYN_MAX_BITS; #endif - tcg_ctx->insn_start_words =3D TARGET_INSN_START_WORDS; tcg_ctx->guest_mo =3D cpu->cc->tcg_ops->guest_default_memory_order; =20 restart_translate: @@ -457,7 +456,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, TCGTBCPUSt= ate s) fprintf(logfile, "OUT: [size=3D%d]\n", gen_code_size); fprintf(logfile, " -- guest addr 0x%016" PRIx64 " + tb prologue\n", - tcg_ctx->gen_insn_data[insn * TARGET_INSN_START_WORDS]= ); + tcg_ctx->gen_insn_data[insn * INSN_START_WORDS]); chunk_start =3D tcg_ctx->gen_insn_end_off[insn]; disas(logfile, tb->tc.ptr, chunk_start); =20 @@ -470,7 +469,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, TCGTBCPUSt= ate s) size_t chunk_end =3D tcg_ctx->gen_insn_end_off[insn]; if (chunk_end > chunk_start) { fprintf(logfile, " -- guest addr 0x%016" PRIx64 "\n", - tcg_ctx->gen_insn_data[insn * TARGET_INSN_STAR= T_WORDS]); + tcg_ctx->gen_insn_data[insn * INSN_START_WORDS= ]); disas(logfile, tb->tc.ptr + chunk_start, chunk_end - chunk_start); chunk_start =3D chunk_end; diff --git a/target/i386/helper.c b/target/i386/helper.c index 197fdac7dd..e0aaed3c4c 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -526,7 +526,7 @@ void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int = bank, static inline target_ulong get_memio_eip(CPUX86State *env) { #ifdef CONFIG_TCG - uint64_t data[TARGET_INSN_START_WORDS]; + uint64_t data[INSN_START_WORDS]; CPUState *cs =3D env_cpu(env); =20 if (!cpu_unwind_state_data(cs, cs->mem_io_pc, data)) { diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 951f8e247a..d96b41a01c 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -218,7 +218,7 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, targe= t_ulong rd, { OpenRISCCPU *cpu =3D env_archcpu(env); #ifndef CONFIG_USER_ONLY - uint64_t data[TARGET_INSN_START_WORDS]; + uint64_t data[INSN_START_WORDS]; MachineState *ms =3D MACHINE(qdev_get_machine()); CPUState *cs =3D env_cpu(env); int idx; diff --git a/tcg/perf.c b/tcg/perf.c index 412a987d95..4e8d2c1bee 100644 --- a/tcg/perf.c +++ b/tcg/perf.c @@ -313,7 +313,7 @@ void perf_report_code(uint64_t guest_pc, TranslationBlo= ck *tb, const void *start) { struct debuginfo_query *q; - size_t insn, start_words; + size_t insn; uint64_t *gen_insn_data; =20 if (!perfmap && !jitdump) { @@ -329,11 +329,10 @@ void perf_report_code(uint64_t guest_pc, TranslationB= lock *tb, =20 /* Query debuginfo for each guest instruction. */ gen_insn_data =3D tcg_ctx->gen_insn_data; - start_words =3D tcg_ctx->insn_start_words; =20 for (insn =3D 0; insn < tb->icount; insn++) { /* FIXME: This replicates the restore_state_to_opc() logic. */ - q[insn].address =3D gen_insn_data[insn * start_words + 0]; + q[insn].address =3D gen_insn_data[insn * INSN_START_WORDS + 0]; if (tb_cflags(tb) & CF_PCREL) { q[insn].address |=3D (guest_pc & qemu_target_page_mask()); } diff --git a/tcg/tcg.c b/tcg/tcg.c index c4e866e9c3..648333a9fb 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1989,7 +1989,6 @@ void tcg_func_start(TCGContext *s) QSIMPLEQ_INIT(&s->labels); =20 tcg_debug_assert(s->addr_type <=3D TCG_TYPE_REG); - tcg_debug_assert(s->insn_start_words > 0); } =20 static TCGTemp *tcg_temp_alloc(TCGContext *s) @@ -2943,7 +2942,7 @@ void tcg_dump_ops(TCGContext *s, FILE *f, bool have_p= refs) nb_oargs =3D 0; col +=3D ne_fprintf(f, "\n ----"); =20 - for (i =3D 0, k =3D s->insn_start_words; i < k; ++i) { + for (i =3D 0, k =3D INSN_START_WORDS; i < k; ++i) { col +=3D ne_fprintf(f, " %016" PRIx64, tcg_get_insn_start_param(op, i)); } @@ -6835,7 +6834,7 @@ static void tcg_out_st_helper_args(TCGContext *s, con= st TCGLabelQemuLdst *ldst, =20 int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start) { - int i, start_words, num_insns; + int i, num_insns; TCGOp *op; =20 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP) @@ -6925,9 +6924,8 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb,= uint64_t pc_start) QSIMPLEQ_INIT(&s->ldst_labels); s->pool_labels =3D NULL; =20 - start_words =3D s->insn_start_words; s->gen_insn_data =3D - tcg_malloc(sizeof(uint64_t) * s->gen_tb->icount * start_words); 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Cc: qemu-stable@nongnu.org Fixes: c9ad8d27caa ("tcg: Widen gen_insn_data to uint64_t") Reviewed-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index fa4998b341..acf32e6c08 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -109,7 +109,7 @@ static int64_t decode_sleb128(const uint8_t **pp) val |=3D (int64_t)(byte & 0x7f) << shift; shift +=3D 7; } while (byte & 0x80); - if (shift < TARGET_LONG_BITS && (byte & 0x40)) { + if (shift < 64 && (byte & 0x40)) { val |=3D -(int64_t)1 << shift; } =20 --=20 2.43.0 From nobody Sat Nov 15 22:35:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746135050; cv=none; d=zohomail.com; s=zohoarc; b=khxFuU7RHLWqN3L0GnmyQrr3Sd1JQrTube5EONmUJZ+ze1lP+ziN62xu2IVVe+w1g5tF+9ls9gJADWHIN8pdSgWonq8fCXT21nRPOPAvRdSnTcFjLty3/7EOaCQnQelUyd7Yqxk5BtwbsNGq8LsQ5XXnw7WlLop3EC/nGe+W42s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746135050; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=jS8XY9JGqBdyz2cH3mTsFmqEBbkq7c0hUNDy2FU3g/U=; b=a8cy5oQuhzYn+uzXRabL4vMXNDdeBdwgH5coZpT9GIC8CD19QFXooMppKL5qig9guUTvt1Jv+j8VHOWXPkx0HUR3e5ILUZ8e3w6RGuM5Wa89M/W4nsj/H41gk/d8/4mlD1nx1dOgPgIVaqziTBfqh5ms7e6q5siR8X8gWxFfx+4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746135050756916.769808971271; Thu, 1 May 2025 14:30:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAbPQ-0006DI-OZ; Thu, 01 May 2025 17:25:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAbOo-0004ZH-I0 for qemu-devel@nongnu.org; Thu, 01 May 2025 17:24:54 -0400 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAbOm-0002BR-9k for qemu-devel@nongnu.org; Thu, 01 May 2025 17:24:54 -0400 Received: by mail-pg1-x52c.google.com with SMTP id 41be03b00d2f7-b12b984e791so1268048a12.2 for ; Thu, 01 May 2025 14:24:51 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-740590610desm135897b3a.146.2025.05.01.14.24.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 May 2025 14:24:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746134690; x=1746739490; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jS8XY9JGqBdyz2cH3mTsFmqEBbkq7c0hUNDy2FU3g/U=; b=unwMRDQYJd9LKNq3OhvjKL2/IMrO2grOLLx1uuhL4PI7facdgfnKkyXnlPUx6ty7wK 7nNUWYOfnMqqOlGTH1j+no26bbkOhjQjfsuzF4vShjxJsHwPbJF7+PqbmX8rXFKvMXnB 3+YBr1FmhvYg9rldW6pX1WIsRLMAd//J7IjiDy+bZDqvPi0I8cFpxa/CUpgXifUCaHpC P0pVyIlqAPaTRzqhq0ZvRwtLbU14ACwVNjRAZvrFrzYQS9UWQ5s+BWQI6RUf9UeSvd3/ 03lIbhfNpzw4wZaoeWHppA9PK37scgPPVuPH3XEmIE7sKDKNY82LwREmK4xqrD1c8mwV WZbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746134690; x=1746739490; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jS8XY9JGqBdyz2cH3mTsFmqEBbkq7c0hUNDy2FU3g/U=; b=Dkk3pP8H+imdVKz6Fv51eIqsoDi2mF3uQ9eub2mCGwfclDUQwK+vMoDWdw6VDJrCpI X7nJHg8+HE31WAwaVHd7zeYtFuQ7ArKR6BUoWnyXcZZsCUJeRYDap2ZzFZYkvh1zxzUv sZpGzL2hKJVFqcP2b3ADAj75e50uwo8KijFDM+nRRXHtm5GsUzxm+iXCt2Vzf7TxNpr0 BhKkokgFCkOTfHzbIKHgLQngzMRVhVCUMTHECRPneQ5bBuLv98kXCK2pAtxuuGaRHYXo plZpkUp90SElNnssO4BnlWJLOU9/24f6GpNzkUY2HgV2TwomZd/Zk1i4h6yjdGVnh5aR /bGw== X-Gm-Message-State: AOJu0YwEFesCL8/OEfc5hd9re1rh5bwGQ4WLdOAt8fciFQY+GXVDqJS7 q5yTO/JTftwURd9zm2LG65af2ipiffinWK9c0DFKgrPVaNxZI5scXkCfpmnae/AO+Lr2UqTwqf8 F X-Gm-Gg: ASbGncsVe9cReTDEs/aO4UZl9JtUjdR6p6oMfgzqJznmDd+o0tqdEgcqRRwx5xA9BJ4 ueYf70MT021Ld2rjWTd+8iU5kFFTOKANyDvFxfs2wajIMTiixgtKbeksuV+cfHrNGOBJ+C4bQw1 vBWGvjvG+fkqwabOGrvaHVUh/fdvHHgOv06hT7lj2BfBW2gjwr9HmPrnbRNaxu7jRsWfiELlAkr bDrODeDPBDT4saDNeOq+87COIK5RzM5JDAuUpmRNOWSmV5EDhqT2NWSs3Ikv+vbwvHKj4B45FYA JxJZLdOx18cJU5muLdvX4lZ9lg3GKYrUppbGb9Ffqa+gV6RNRrPesT7IB63WB+lDHKP15HKYVRY = X-Google-Smtp-Source: AGHT+IGhjtPV+x2Ly++JUDH/knenrRgqxn9fjYhTeewbuSe3voXMidSiTyg+9cN/GJZvThtRaNhuKw== X-Received: by 2002:a05:6a20:ce45:b0:1f5:7280:1cf7 with SMTP id adf61e73a8af0-20cde958af1mr608448637.16.1746134690662; Thu, 01 May 2025 14:24:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 45/59] accel/tcg: Use target_long_bits() in translate-all.c Date: Thu, 1 May 2025 14:20:59 -0700 Message-ID: <20250501212113.2961531-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746135053111019100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index acf32e6c08..6b6e10be9d 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -54,6 +54,7 @@ #include "qemu/qemu-print.h" #include "qemu/main-loop.h" #include "qemu/cacheinfo.h" +#include "qemu/target-info.h" #include "qemu/timer.h" #include "exec/log.h" #include "exec/icount.h" @@ -343,7 +344,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, TCGTBCPUSt= ate s) } =20 tcg_ctx->gen_tb =3D tb; - tcg_ctx->addr_type =3D TARGET_LONG_BITS =3D=3D 32 ? TCG_TYPE_I32 : TCG= _TYPE_I64; + tcg_ctx->addr_type =3D target_long_bits() =3D=3D 32 ? TCG_TYPE_I32 : T= CG_TYPE_I64; #ifdef CONFIG_SOFTMMU tcg_ctx->page_bits =3D TARGET_PAGE_BITS; tcg_ctx->page_mask =3D TARGET_PAGE_MASK; --=20 2.43.0 From nobody Sat Nov 15 22:35:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746134767; cv=none; d=zohomail.com; s=zohoarc; b=gd6B0cVyK2D2fuwQ0og5JKm+W8bPKDl/V7++pqq6vrLoi1q8qw5LOJglcaPlNqRY9BuUJC6XzItjiblBsQpJbmXbGU2fhSpj6Qaap+dZUWtB6H96uLDZwKg73ndHEvjIPHHqDTx31FhsQwbfFVpVHo7C6CtttsTk6kPO6x8qoGc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746134767; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=nJR5rA8G7peaLdmnNfXC4dbOSl1Fc6PId1P5lzDPvoI=; b=hyxD54F+zUJqm8nTIxv3CM03Tk7bihE330R3nZs6o1u68QrX21RXyMT8d+vRvxgvahq9RpGu50z+M+gJqWt1Yk6DWtXLsEwu/0peDz5FmKZ6qEGpurxaCxN+58i3pXcXvH0szZqiLE4VoYP7r/v3NBsR4OFiXxY/yXWRNwKN8Wk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746134767867571.6498049139722; Thu, 1 May 2025 14:26:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAbPS-0006QY-IJ; Thu, 01 May 2025 17:25:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAbOo-0004b2-Ui for qemu-devel@nongnu.org; Thu, 01 May 2025 17:24:55 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAbOm-0002Bo-NB for qemu-devel@nongnu.org; Thu, 01 May 2025 17:24:54 -0400 Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-736b350a22cso1242999b3a.1 for ; Thu, 01 May 2025 14:24:52 -0700 (PDT) Received: from stoup.. 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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 32 -------------------------------- accel/tcg/meson.build | 2 +- 2 files changed, 1 insertion(+), 33 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 6b6e10be9d..451b383aa8 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -22,46 +22,15 @@ #include "trace.h" #include "disas/disas.h" #include "tcg/tcg.h" -#if defined(CONFIG_USER_ONLY) -#include "qemu.h" -#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) -#include -#if __FreeBSD_version >=3D 700104 -#define HAVE_KINFO_GETVMMAP -#define sigqueue sigqueue_freebsd /* avoid redefinition */ -#include -#include -#define _KERNEL -#include -#undef _KERNEL -#undef sigqueue -#include -#endif -#endif -#else -#include "system/ram_addr.h" -#endif - -#include "cpu-param.h" -#include "exec/cputlb.h" -#include "exec/page-protection.h" #include "exec/mmap-lock.h" #include "tb-internal.h" #include "tlb-bounds.h" -#include "exec/translator.h" #include "exec/tb-flush.h" -#include "qemu/bitmap.h" -#include "qemu/qemu-print.h" -#include "qemu/main-loop.h" #include "qemu/cacheinfo.h" #include "qemu/target-info.h" -#include "qemu/timer.h" #include "exec/log.h" #include "exec/icount.h" -#include "system/tcg.h" -#include "qapi/error.h" #include "accel/tcg/cpu-ops.h" -#include "accel/tcg/getpc.h" #include "tb-jmp-cache.h" #include "tb-hash.h" #include "tb-context.h" @@ -69,7 +38,6 @@ #include "internal-common.h" #include "tcg/perf.h" #include "tcg/insn-start-words.h" -#include "cpu.h" =20 TBContext tb_ctx; =20 diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 0bb089299b..7eb4619aea 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -10,6 +10,7 @@ tcg_ss.add(files( 'tcg-runtime.c', 'tcg-runtime-gvec.c', 'tb-maint.c', + 'translate-all.c', 'translator.c', )) if get_option('plugins') @@ -22,7 +23,6 @@ libsystem_ss.add_all(tcg_ss) tcg_specific_ss =3D ss.source_set() tcg_specific_ss.add(files( 'tcg-all.c', - 'translate-all.c', )) tcg_specific_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user-exec.c'= )) specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss) --=20 2.43.0 From nobody Sat Nov 15 22:35:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746135141; cv=none; d=zohomail.com; s=zohoarc; b=LKwr3Cmk76+l3uh2Wq7jgOnXGOocmaKzThmJz44MapcbrxMUL+lb/EXUlSdBhcASHC4WRnmc9lyDl4ckCxzlFzR5fv4EMTF28IF/zyCYAv8/c1YsmLhQDxnXb+b+rXe7Meh40BTniYACwGTeVNqH2Kg48ADvklIfWze0HJ4HOkg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746135141; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=UdM4Y9gYKdv124M5AuRleUua4qCDdrLmsMUhfkZBN+Y=; b=eWNcVV0chWY0YCcIy8tiqBE3Ncrecp7wUXkXDvn52JR12jR50SuCoqeycMelCAVEf0w4wFk3x1LN/XX67DnnNiEMBetv4k6Hq9RhO3wYZGECz4/kAdoMSK9WLfKHMyNd6ix+pP8ljEiZScmmKvbNfkkntPY9xDXosXWoWdULQdw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746135141828201.64981710074915; Thu, 1 May 2025 14:32:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAbOv-0005ES-Dd; Thu, 01 May 2025 17:25:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAbOp-0004iA-QY for qemu-devel@nongnu.org; Thu, 01 May 2025 17:24:55 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAbOn-0002C5-K2 for qemu-devel@nongnu.org; Thu, 01 May 2025 17:24:55 -0400 Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-736dd9c4b40so2446764b3a.0 for ; Thu, 01 May 2025 14:24:53 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-740590610desm135897b3a.146.2025.05.01.14.24.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 May 2025 14:24:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746134692; x=1746739492; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UdM4Y9gYKdv124M5AuRleUua4qCDdrLmsMUhfkZBN+Y=; b=U+buhxOhqcKv4gIG4oMM3fHPaLj7TO0vQSQW+vObSlpUIOOPYraUdJKklcCNOkP65r rl9hGYOVYpDKdBroUY0BdLfgPSLnDIpOe4VOzHkvbYZ3W2Ae7DaUC9k6iwAg4QV4D6Fe iz7S54HynjyPy1wnk7bZuSEbyz0f68NxqkUIxor43RD+2PbqDZfHtf6wJ1D/dz+QBPRo HTFN+CuPjqpTSnyOX4tAigcWwcBb7s0ZA4g9Fm4aJ0IAjj/mQjeaZM7SU7YUeA9BFw4V I56E9DuCL3cr5yeZAlerN+spVesjiw0ydsTz1X6Sih8y9FEoId2wUr90urseuk7uq1/X t7xQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746134692; x=1746739492; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UdM4Y9gYKdv124M5AuRleUua4qCDdrLmsMUhfkZBN+Y=; b=d8RluvNNmp9gNN18P7kmeNMoeS+P+yqha5BxWH+MtkxOEuBspc8ajpGMfS6/JRHRre JldX0zx9+oOKPzhFI72hbRd58OhujB0YFMgxc41bEx2HDx9nFFXCdCmCe/wGKMS/+0zV Vfrsbr9EY8FuPmIjcCJJ8MYda0raI2kL+XZVnCzkuyCky4Oqabh+bbH1PJDYvTF0awaq BlOeH6EYiuwyG54C3zOwBV5qXjEQrO5+v6mne461yE8rBx6sg75OfsUGb4C9uvVwuLJk ETVq/QYF4QSKTh35+gSISN3yrqpYPKia+GDRkSq9auGVejOQUoS5YfV0Vjmr/LK1FyeH ROPQ== X-Gm-Message-State: AOJu0YzvQ/UDV7vvDYXkRu22S5TAQXcK4ql3uSDGhEgH6AoWj2SLIB6y 3TzjXCgaqsGjwmN3kaauIuFSnyc4BaPmroN73BO/RRHNzusMQkbz9CZbR4N7iIUHGp8kI0XP2qS l X-Gm-Gg: ASbGnct8/YzC0mP5i7spDZeOrApBlLVCGZxWzyxB4F3QRIag/iX1EznXVxBVcpQwvF4 3h3kW8awvmXeVJIkEx0oG7gRbS4lqS9rxEGXoqzDr+6GV4Lg0dY/+gBqswO0aE7GEFFXRzpROvA Rg47W/3XwgajyC/AaNC7wVxcHB4DFa8tlQYEu2GR0RB84OIPOvEvk+DU3toP4ZM6AsPGR5gTPci 1s/Xt85xVSyLsRVaD2yxdntMmPCjeQQGR5I/ADogc3s5FgoLFIN3DFOmqMfYFm0RbwF7ijvgT95 R+AYtYWqAwe3lHDLJsBYFhKBj7pwUDA4Z5cVvCc8tW2Etmav65hRYa/GQDJUQaQ42uSlsMb42Is = X-Google-Smtp-Source: AGHT+IH93323VBd4j5bUeNeWzT80VxNCabCWP+fdM7ziIO+FBqZM2PI9t8JTMFFzCl67s7/vJasl2w== X-Received: by 2002:a05:6a20:cfa2:b0:1f3:1ba1:266a with SMTP id adf61e73a8af0-20cc905e61bmr1074870637.0.1746134691908; Thu, 01 May 2025 14:24:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 47/59] accel/tcg: Build tcg-all.c twice Date: Thu, 1 May 2025 14:21:01 -0700 Message-ID: <20250501212113.2961531-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746135144288124100 Content-Type: text/plain; charset="utf-8" Remove some unused headers. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/tcg-all.c | 6 +----- accel/tcg/meson.build | 4 +--- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 0ce34ac912..6e5dc333d5 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -36,15 +36,11 @@ #include "qapi/qapi-builtin-visit.h" #include "qemu/units.h" #include "qemu/target-info.h" -#if defined(CONFIG_USER_ONLY) -#include "hw/qdev-core.h" -#else +#ifndef CONFIG_USER_ONLY #include "hw/boards.h" -#include "system/tcg.h" #endif #include "accel/tcg/cpu-ops.h" #include "internal-common.h" -#include "cpu-param.h" =20 =20 struct TCGState { diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 7eb4619aea..d6bd304add 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -10,6 +10,7 @@ tcg_ss.add(files( 'tcg-runtime.c', 'tcg-runtime-gvec.c', 'tb-maint.c', + 'tcg-all.c', 'translate-all.c', 'translator.c', )) @@ -21,9 +22,6 @@ libuser_ss.add_all(tcg_ss) libsystem_ss.add_all(tcg_ss) =20 tcg_specific_ss =3D ss.source_set() -tcg_specific_ss.add(files( - 'tcg-all.c', -)) tcg_specific_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user-exec.c'= )) specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss) =20 --=20 2.43.0 From nobody Sat Nov 15 22:35:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746134831; cv=none; d=zohomail.com; s=zohoarc; b=hPwz3WD9nEszHBEoAl0pELqXQtV81U8fNSjYqsBU7chZDmQWyLifH2AMCZj4OD32xZ4BjHgtyarVYXL882OvQsAWM8Itbce19PBMSjt+McxGh9Xbk/gs4luWRoGXKZHhlbj8+KYfvqaLOZeBcJ+xUdEX/xyU5Q2b1CZ5QjhgP28= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746134831; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Ee3yc1GwjdX802YpUH6+ttgdvKSjZdMr+u38Re0lfBg=; b=ZeSR3v7rg21EPODPG2ROI5zcjmQS0IAlJjgRh85VnZpPLmWxS3FOFOF2NjfV4JmSxfbchfzTqcNaQxoY14UeuY1wwXICWyWrbPbDY26oS/dVvGZTv1EGQGo3k3tgueI06LHR+ZnKefZEr/X0wce/LFdQyiiAEE2gsRV0kYLUM64= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746134831670440.6647149460423; Thu, 1 May 2025 14:27:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAbPt-0008OJ-Gz; Thu, 01 May 2025 17:26:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAbOu-0005GE-HL for qemu-devel@nongnu.org; Thu, 01 May 2025 17:25:01 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAbOo-0002CN-B0 for qemu-devel@nongnu.org; Thu, 01 May 2025 17:24:59 -0400 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-72d3b48d2ffso1656473b3a.2 for ; Thu, 01 May 2025 14:24:53 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-740590610desm135897b3a.146.2025.05.01.14.24.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 May 2025 14:24:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746134692; x=1746739492; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ee3yc1GwjdX802YpUH6+ttgdvKSjZdMr+u38Re0lfBg=; b=Ud/tWVp3/qAqabq4N9jDdG9zBVqogCmL8CJAzSTK1UTd0prPGowqqABxN1RCF9wrWz svUZULI4cHjqSj73RzFwTunQ3CIg2Y2ip3rbDmRJgciFbR88txPxm2CHp6/GNcGH35jf qqPkwbDKjVIX5y7PgwsDiIuNFV+cXTt25TK6yeAHvPwpOd97huYmXlGQtCUNUaZ/3Wrw QFEPG3UDmPB3CmWhiwyKwyl+82W1SeVg4iB88deLL6eqQ9HZLxNED65EoLzm74Kc1B9r YG8G6EHNXm8EhZWXquLjHmKSPEq8OAVOszgPQclm1NC4mIbX87s8bMQhnG0+3kia6gEd sRhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746134692; x=1746739492; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ee3yc1GwjdX802YpUH6+ttgdvKSjZdMr+u38Re0lfBg=; b=k2R/QdEP/boiERqQ0ohk5ZXDh2kF8gjiNgaVtmUqdlTcw35Te+oMbKRHcpT45FFbbB CHS+cyNSkig+gA57bqQ8lecSFk8eWUXwAWt+RPS/4SKMuZap4dvg5/gtlrMwkbJ/fRVV IXjNiJLpcsBS4Im8dG+NzilV8QLRduLIeRdpAb9sam9H4ZiIMKuuxeRMKhmE7ipI94rA pAARLw/6/wtLgQ+TQkE9uswJYQN+H0PppQT+0IHVx2LKOzr5DPR668tstnZTjYvhCobr +emx25s2+AEEDA9Ae6gA0Odr4dm9/iZPIL/XQdzFwjcTh9ZR2o810akMU+a+/HVoVblZ DO1Q== X-Gm-Message-State: AOJu0YxKyTv4QLrCM0Mw5Gx0z9eXAqYB6maE5DiQsNduLJkSLufOTRIn cWF/Ys1XzPAw+0CLFRkM16YixBrEkOeU10W0s3/2kHvIgYgF+1md2WLkEYctBOSyzDd4hvKFGeW T X-Gm-Gg: ASbGncuyyHT1NFD5TnSmwvnIAa2vApSapCpYdX50bPEJ6szDH/2uCwikYq33ELEqdQ5 VnWlOHFdRgbDEnflGsDOYRZXHDXbkUhrNNb0QrJoYOAfxyZqjjEjq0ZiCsUXCv4yOfkNHavnpHM fA8o4w24sNmUa0LDhD1FCptfpt8fp8/sKUVyZKTDTmiPzgV/D5F5qjPxHPs4fwbhLrpW6QivV22 xlrs8fIl3ITuiahrXCH2ohV/qh6jrqphbWn5xyYzE6c6BVv6bYzGpMhEwdnqU6iAzdcHosRU8tJ dmB34XfRK8clWIcSx2TKypVbXjB+p4TVEv4/dMqwhOTLSVQ0WFQOGin9+H5dxzLhDM3XhJdvoBA = X-Google-Smtp-Source: AGHT+IEFq8xNX336bIFKytr/uQmtnupiSJLMOCDX+EH85BrDN4n4sUVHVy4Lgn0TxIaKXp5FCYJ01g== X-Received: by 2002:a05:6a00:4ac2:b0:736:4fe0:2661 with SMTP id d2e1a72fcca58-74058a486f4mr609164b3a.11.1746134692505; Thu, 01 May 2025 14:24:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 48/59] accel/tcg: Use vaddr in cpu_loop.h Date: Thu, 1 May 2025 14:21:02 -0700 Message-ID: <20250501212113.2961531-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746134834304019100 Content-Type: text/plain; charset="utf-8" Use vaddr instead of abi_ptr or target_ulong for a guest address. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/user/cpu_loop.h | 12 +++++------- accel/tcg/user-exec.c | 2 +- linux-user/signal.c | 4 ++-- 3 files changed, 8 insertions(+), 10 deletions(-) diff --git a/include/user/cpu_loop.h b/include/user/cpu_loop.h index 589c66543f..ad8a1d711f 100644 --- a/include/user/cpu_loop.h +++ b/include/user/cpu_loop.h @@ -20,11 +20,9 @@ #ifndef USER_CPU_LOOP_H #define USER_CPU_LOOP_H =20 -#include "exec/abi_ptr.h" +#include "exec/vaddr.h" #include "exec/mmu-access-type.h" -#include "exec/log.h" -#include "exec/target_long.h" -#include "special-errno.h" + =20 /** * adjust_signal_pc: @@ -46,7 +44,7 @@ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_wri= te); * Return true if the write fault has been handled, and should be re-tried. */ bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, - uintptr_t host_pc, abi_ptr guest_addr); + uintptr_t host_pc, vaddr guest_addr); =20 /** * cpu_loop_exit_sigsegv: @@ -59,7 +57,7 @@ bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t = *old_set, * Use the TCGCPUOps hook to record cpu state, do guest operating system * specific things to raise SIGSEGV, and jump to the main cpu loop. */ -G_NORETURN void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, +G_NORETURN void cpu_loop_exit_sigsegv(CPUState *cpu, vaddr addr, MMUAccessType access_type, bool maperr, uintptr_t ra); =20 @@ -73,7 +71,7 @@ G_NORETURN void cpu_loop_exit_sigsegv(CPUState *cpu, targ= et_ulong addr, * Use the TCGCPUOps hook to record cpu state, do guest operating system * specific things to raise SIGBUS, and jump to the main cpu loop. */ -G_NORETURN void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr, +G_NORETURN void cpu_loop_exit_sigbus(CPUState *cpu, vaddr addr, MMUAccessType access_type, uintptr_t ra); =20 diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 68e01fc584..e1f4c4eacf 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -126,7 +126,7 @@ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_w= rite) * guest, we'd end up in an infinite loop of retrying the faulting access. */ bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, - uintptr_t host_pc, abi_ptr guest_addr) + uintptr_t host_pc, vaddr guest_addr) { switch (page_unprotect(cpu, guest_addr, host_pc)) { case 0: diff --git a/linux-user/signal.c b/linux-user/signal.c index 4dafc2c3a2..cd0e7398aa 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -750,7 +750,7 @@ void force_sigsegv(int oldsig) } #endif =20 -void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, +void cpu_loop_exit_sigsegv(CPUState *cpu, vaddr addr, MMUAccessType access_type, bool maperr, uintptr= _t ra) { const TCGCPUOps *tcg_ops =3D cpu->cc->tcg_ops; @@ -766,7 +766,7 @@ void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong = addr, cpu_loop_exit_restore(cpu, ra); } =20 -void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr, +void cpu_loop_exit_sigbus(CPUState *cpu, vaddr addr, MMUAccessType access_type, uintptr_t ra) { const TCGCPUOps *tcg_ops =3D cpu->cc->tcg_ops; --=20 2.43.0 From nobody Sat Nov 15 22:35:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746134929; cv=none; d=zohomail.com; s=zohoarc; b=IJWbjNBObTe10R2oCtgPkbDZAR/HWzisduo9YX3xNxRalG2RFTgeCu1eR5hBtAfW/17Evgm+ylmvBgjYmya9EYgR4zCPRMciEyd/13D344slf8q/bf99Lz0m/2VI3B9ppamSaf8n7dL64t7rF876exulkROqKHNlZ/Dwxda4o68= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-740590610desm135897b3a.146.2025.05.01.14.24.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 May 2025 14:24:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746134693; x=1746739493; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SSbFpFjMPZ364OnkhpeAl/6b8u/xx6/tSoMMKW2aIxw=; b=MRr+wVn9Tl8I8uO8Aw57u0lPq2rgojaVKllBsBDrXowEj/4sFTBV7rnygv3lF+X5qO K56k1jbv3mIXQUgV3AqU5YVQw3BDJf1/rEZ2xojvNMnZVr7Eq7vAmRxXywRfG5PNa7d6 xvyTgkE/PBqz/e6QnvMXUkDpEDeFA5K6qAq9OVZ7vUU9KiejgCWQv8ZTrablsAwfCIlF VQL6fTEzrw9d3iEfgqcdxzqP09GPzPQ42nZOXPEJ9SRJ67T2jX4kEyallTrO10bEfmLL Y1oTvEWjs8hcMPU0mD0ezCNX7Y+Z/gHw170z//MW0SlghpC5UbloU4Amm0Evduvoncn1 DBiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746134693; x=1746739493; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SSbFpFjMPZ364OnkhpeAl/6b8u/xx6/tSoMMKW2aIxw=; b=dJW3NNfL/ANFkLYS1suztdrTWu2RRdTIMMKuJEamL5hFHVkOV9I4PJpAA+bCNuLiCP o2GtM96XAmiWIDjMnFKN2SNe6DMXJLdEDHlmBIHnILJpX3YSZrV+J4QqKHS8+rjS/PoE LLXalI3JR6eOKY5Z/EF5fk4tDqC8oLdlWF15ZXMVH/4U9ixETFb1dltbvfPXKU+ceRmY 0ggoZ8rPIzlA5JgmjHQ/SnaVp6w4wn2jtx5VXS0p49oink0O0YPSgb5eJ6Ic55uNlZYZ Ky6WQMZMB54sH90NOWOrqYnwwOUSS2d94xd/hB3GbZGKeS+V4EZezc2ghgy05uhjmNs/ Afsw== X-Gm-Message-State: AOJu0YwrQ8625GnVdHWW2WrqZU10Pj3JsQEF5EFht57Xgz8WEE3k5HBs lP6Vv9Chr4OW/NRoJeQCnQ8LJHPWEoIUQi2SNWxNlazKQtxsacer5M6nzgDEkWBXQZMDZTBYfzy a X-Gm-Gg: ASbGncvnZafs9sj+CFU3bDcNwBNi+A2mSOXk1WgMD6PSgeCqfRHRLaeFkMNqICGT4Z4 SQQrlfVWlWhWZ19j0JAK+GkWBn6oSCXhQbd1KgYQWLur4lWJGjRgNwyOD522puUnTCKaWSvqbqJ T/ys02hQHSQoojm9UT2Z84sxS073pcc59i8yh9Y4vedzKo408f8AfJp8chKeYW1SHKaDY7wkD6l CrX5nhzB+8IatCPTZ9FO6FTXYDHcr+cIXvBBQMtdTtXAIvromgFTqC1z13RNx17UeRxS1lsgAYK uDPaLvWhM6pqBmrTSGpB6Pl68jwEDuVKbpm7SjtnSq7qJ3Yzeay+wgHIe0vvUy0ZxfiaES/IFHE = X-Google-Smtp-Source: AGHT+IFcuVBoYG5HGRNf6eKJY0gPF7xPhGBG1OQas0wJlPh46gmwzS/URQP25Xrud1qO3eWORYSJdA== X-Received: by 2002:a05:6a20:2d09:b0:1f3:3ca3:8216 with SMTP id adf61e73a8af0-20cde373fb1mr587043637.5.1746134693143; Thu, 01 May 2025 14:24:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 49/59] accel/tcg: Move user-only tlb_vaddr_to_host out of line Date: Thu, 1 May 2025 14:21:03 -0700 Message-ID: <20250501212113.2961531-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746134930536019100 At the same time, fix a mis-match between user and system by using vaddr not abi_ptr for the address parameter. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/accel/tcg/cpu-ldst.h | 8 -------- accel/tcg/user-exec.c | 6 ++++++ 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/include/accel/tcg/cpu-ldst.h b/include/accel/tcg/cpu-ldst.h index 44a62b54da..00e6419e13 100644 --- a/include/accel/tcg/cpu-ldst.h +++ b/include/accel/tcg/cpu-ldst.h @@ -515,15 +515,7 @@ static inline uint64_t cpu_ldq_code(CPUArchState *env,= abi_ptr addr) * Otherwise (TLB entry is for an I/O access, guest software * TLB fill required, etc) return NULL. */ -#ifdef CONFIG_USER_ONLY -static inline void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, - MMUAccessType access_type, int mmu_i= dx) -{ - return g2h(env_cpu(env), addr); -} -#else void *tlb_vaddr_to_host(CPUArchState *env, vaddr addr, MMUAccessType access_type, int mmu_idx); -#endif =20 #endif /* ACCEL_TCG_CPU_LDST_H */ diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index e1f4c4eacf..adc5296ba5 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -850,6 +850,12 @@ void *probe_access(CPUArchState *env, vaddr addr, int = size, return size ? g2h(env_cpu(env), addr) : NULL; } =20 +void *tlb_vaddr_to_host(CPUArchState *env, vaddr addr, + MMUAccessType access_type, int mmu_idx) +{ + return g2h(env_cpu(env), addr); +} + tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, vaddr addr, void **hostp) { --=20 2.43.0 From nobody Sat Nov 15 22:35:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746134831; cv=none; d=zohomail.com; s=zohoarc; b=ST+hYkusKwfgvM0SmLWxL5N1Y5S1bbliGLUACWUZ64f4e3xvlMNSXGu4wsA0FkX7+6V62blN37GSo/8jO1Rf9ju4F8PWlM8aN3F2TCZxJb8tJv0TvK9QhHYvljfI+0qZAs1XZqh7rggoUn1nj6adzk8BJoKC7YzH+9ei8GwerLU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746134831; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ICTmvXj5A3w7ZXPfgfLwt1QtBgbPFqHkFzgva30CPac=; b=As3mioDhOJSUCiesnSGzuEL+jjDtFSFaa7Q92BkNn/AYggVXiKUYqiO1EKKtKcdGE4NE6OoHHMnjz4euX6k1AQacu1F8QBD6UOT+4hokv/s7ozrqyuMyA0fJxaX4YrK9XFcA505rEjN5RMzB3YgFsMFjwosShs5ob8C5FX+yZS4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746134831506613.7679421604304; Thu, 1 May 2025 14:27:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAbPd-0006j4-EO; Thu, 01 May 2025 17:25:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAbOr-0004rV-Kq for qemu-devel@nongnu.org; Thu, 01 May 2025 17:24:58 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAbOp-0002Cz-E1 for qemu-devel@nongnu.org; Thu, 01 May 2025 17:24:57 -0400 Received: by mail-pf1-x429.google.com with SMTP id d2e1a72fcca58-7398d65476eso1210398b3a.1 for ; Thu, 01 May 2025 14:24:54 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-740590610desm135897b3a.146.2025.05.01.14.24.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 May 2025 14:24:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746134694; x=1746739494; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ICTmvXj5A3w7ZXPfgfLwt1QtBgbPFqHkFzgva30CPac=; b=Yqai3dhuWLqYhuwcH9tQWqis/1RfSV1w0jCZ+46gv901yOqVtJfdu4BHi76153nlKa DP2NWXeVQfsP2Gx0jM6Kgee3kN6mC/h30ectwVUD9Pbuy3GZcvhtNr6TIH/WXDAMITUY N/8XGQfemS/oLRTvGqjY+upcTESDM+GoTL2c4ei0C9UTcIzKQOdWzoGO9/rv18Ar9Znx 2ANCM6MtUNY1Wh4/UltdCEsUukKM5L/5U/9SYpO9eZYFsdmpwfnKRseUkGHGWSSlMBE9 MaLVYar1XN97updlNwmVIUwSdjJY37pwus0ARg7g3Njie2Sa7yrC9eW+UKiSPoMGF/vC 6oeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746134694; x=1746739494; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ICTmvXj5A3w7ZXPfgfLwt1QtBgbPFqHkFzgva30CPac=; b=EvecX46IxwiwQW7u+JlJd+pFpjIcUmf0Tshjgzs+H4I5OHLfwcyWKzBoBtXDWQybjE 7MLyfy+VQ7j/TFGJTdhCS543w2K11zEBFgzaRmKgibYN7Rqs2yKFbxMdwIAVJM0KFrJO AK2cSvRgzwwdlnjUpTfS90sdhR7cwCpu1FdKZYL9pZb75TY2rORgftOd4a9oZp2Q6IGH B7fv6E5Uc8jxO74MWQfFAz+xC++ZOH0/R9VCjFJrPbqTFkplR/6EL4SM/0Ez/7OOqo4S ioYYZ/lUZ5axCFV8wzeOCVO9jJtlNw1Hs2DImHjXiAqck1gSyaEHUFFsJDL6+C9MSkiv GkLg== X-Gm-Message-State: AOJu0Yz/iiazplUA0he1qLxc1gv0hDxgoi73ZZ2We6Wu6ntl6l2nwoE8 u6Q+zo9hxX9nRA//0kbxjFU1vdBizZHDrYjEMrNjkDykCc+NfaJpI5X0PJFVxs/jcg2YvOQyuMm G X-Gm-Gg: ASbGncvN6yM0HZXoNQc0P4BZipi6MhyyCmMVDeUfwXScMlBxFbk5tXuU5utc+HoCurS kN4Y7UWBRRTnmlgaM7jvt3DOnGgElsxnKwkIHp3Q6tgiFFuY8KqmD5JGRCH1PCwnfcahjn27Nym v+bMsYudAGjfoPHFACm4S6X8qoHbvtKy4hw1ByBEMneLElYPKn6fLS2uYWP3ZHpFqGjPBWOTIqZ hW38JE69XBdGzqzRtJAEd1fpHUegU/78tM6/keaFjcAIE4931wDAaIaigEfKlhexlJFFLDmd2Q+ /7JAtwN5PoPrFAKZICRdn5k97BhTostjEbg/7rHO0vR3JOmqfoFoK4NZZOhMVrV53IOsL1stpPM = X-Google-Smtp-Source: AGHT+IE+kBNt/6RsI0YkznovL1BOqcBzFqX2FnW/fQgfvMip9JOn3A7Rrb2Q6xcPmSE7BtvDZhYZiQ== X-Received: by 2002:aa7:8b59:0:b0:736:b3cb:5db with SMTP id d2e1a72fcca58-74049264140mr4987140b3a.11.1746134693736; Thu, 01 May 2025 14:24:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 50/59] accel/tcg: Move tlb_vaddr_to_host declaration to probe.h Date: Thu, 1 May 2025 14:21:04 -0700 Message-ID: <20250501212113.2961531-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746134834072124100 Content-Type: text/plain; charset="utf-8" This is a probing function, not a load/store function. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/accel/tcg/cpu-ldst.h | 16 ---------------- include/accel/tcg/probe.h | 16 ++++++++++++++++ 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/include/accel/tcg/cpu-ldst.h b/include/accel/tcg/cpu-ldst.h index 00e6419e13..0de7f5eaa6 100644 --- a/include/accel/tcg/cpu-ldst.h +++ b/include/accel/tcg/cpu-ldst.h @@ -502,20 +502,4 @@ static inline uint64_t cpu_ldq_code(CPUArchState *env,= abi_ptr addr) return cpu_ldq_code_mmu(env, addr, oi, 0); } =20 -/** - * tlb_vaddr_to_host: - * @env: CPUArchState - * @addr: guest virtual address to look up - * @access_type: 0 for read, 1 for write, 2 for execute - * @mmu_idx: MMU index to use for lookup - * - * Look up the specified guest virtual index in the TCG softmmu TLB. - * If we can translate a host virtual address suitable for direct RAM - * access, without causing a guest exception, then return it. - * Otherwise (TLB entry is for an I/O access, guest software - * TLB fill required, etc) return NULL. - */ -void *tlb_vaddr_to_host(CPUArchState *env, vaddr addr, - MMUAccessType access_type, int mmu_idx); - #endif /* ACCEL_TCG_CPU_LDST_H */ diff --git a/include/accel/tcg/probe.h b/include/accel/tcg/probe.h index 177bd1608d..dd9ecbbdf1 100644 --- a/include/accel/tcg/probe.h +++ b/include/accel/tcg/probe.h @@ -103,4 +103,20 @@ int probe_access_full_mmu(CPUArchState *env, vaddr add= r, int size, =20 #endif /* !CONFIG_USER_ONLY */ =20 +/** + * tlb_vaddr_to_host: + * @env: CPUArchState + * @addr: guest virtual address to look up + * @access_type: 0 for read, 1 for write, 2 for execute + * @mmu_idx: MMU index to use for lookup + * + * Look up the specified guest virtual index in the TCG softmmu TLB. + * If we can translate a host virtual address suitable for direct RAM + * access, without causing a guest exception, then return it. + * Otherwise (TLB entry is for an I/O access, guest software + * TLB fill required, etc) return NULL. + */ +void *tlb_vaddr_to_host(CPUArchState *env, vaddr addr, + MMUAccessType access_type, int mmu_idx); + #endif --=20 2.43.0 From nobody Sat Nov 15 22:35:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746135024; cv=none; d=zohomail.com; s=zohoarc; b=TWSB4wBJIVC7wkZRqgMoqwQCfLSrL2Nabs2NMgN9OyD9Li95fCwmTK57nAGHhZo83mcF+gncJu7fdOTzrfGVmtXqt9HOeRv36298VjPIpRvlcLBzk3BuQVerZpDy/0+C22UFsZKN2v7rh9CL3RHYHDdksFVga8cjF2WUX7q2a6s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746135024; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=dLPkA6JOnUOzci2wJy576ikVBoJf3Va9Je+srdX0Qbc=; b=jMhihiVP2/lIv4aT1BfTuMGa948tSV+A94DGjp3Bj1PlLFOyRDsHwuS7I6xLSxknFiGXavMiMWQT2E2l6lGH0ws/9JT944pTAmZ5ydIC6gLJRPclmJFYGpGBErphndHvUui+FR79f9XlfgCnPS59CUqEygUT6SYF3JoQe4UytTM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746135024387661.9282324020987; Thu, 1 May 2025 14:30:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAbPl-0007Wd-Bd; Thu, 01 May 2025 17:25:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAbOs-00052Y-QZ for qemu-devel@nongnu.org; Thu, 01 May 2025 17:24:58 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAbOp-0002DL-QV for qemu-devel@nongnu.org; Thu, 01 May 2025 17:24:58 -0400 Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-7376dd56eccso1660514b3a.0 for ; Thu, 01 May 2025 14:24:55 -0700 (PDT) Received: from stoup.. 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Thu, 01 May 2025 14:24:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 51/59] accel/tcg: Use target_long_bits() in cputlb.c Date: Thu, 1 May 2025 14:21:05 -0700 Message-ID: <20250501212113.2961531-52-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746135025939124100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 5b6d6f7975..35c467aace 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -19,6 +19,7 @@ =20 #include "qemu/osdep.h" #include "qemu/main-loop.h" +#include "qemu/target-info.h" #include "accel/tcg/cpu-ops.h" #include "accel/tcg/iommu.h" #include "accel/tcg/probe.h" @@ -771,19 +772,19 @@ void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr a= ddr, =20 assert_cpu_is_self(cpu); =20 + /* If no page bits are significant, this devolves to tlb_flush. */ + if (bits < TARGET_PAGE_BITS) { + tlb_flush_by_mmuidx(cpu, idxmap); + return; + } /* * If all bits are significant, and len is small, * this devolves to tlb_flush_page. */ - if (bits >=3D TARGET_LONG_BITS && len <=3D TARGET_PAGE_SIZE) { + if (len <=3D TARGET_PAGE_SIZE && bits >=3D target_long_bits()) { tlb_flush_page_by_mmuidx(cpu, addr, idxmap); return; } - /* If no page bits are significant, this devolves to tlb_flush. */ - if (bits < TARGET_PAGE_BITS) { - tlb_flush_by_mmuidx(cpu, idxmap); - return; - } =20 /* This should already be page aligned */ d.addr =3D addr & TARGET_PAGE_MASK; @@ -809,19 +810,19 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUSta= te *src_cpu, TLBFlushRangeData d, *p; CPUState *dst_cpu; =20 + /* If no page bits are significant, this devolves to tlb_flush. */ + if (bits < TARGET_PAGE_BITS) { + tlb_flush_by_mmuidx_all_cpus_synced(src_cpu, idxmap); + return; + } /* * If all bits are significant, and len is small, * this devolves to tlb_flush_page. */ - if (bits >=3D TARGET_LONG_BITS && len <=3D TARGET_PAGE_SIZE) { + if (len <=3D TARGET_PAGE_SIZE && bits >=3D target_long_bits()) { tlb_flush_page_by_mmuidx_all_cpus_synced(src_cpu, addr, idxmap); return; } - /* If no page bits are significant, this devolves to tlb_flush. */ - if (bits < TARGET_PAGE_BITS) { - tlb_flush_by_mmuidx_all_cpus_synced(src_cpu, idxmap); - return; - } =20 /* This should already be page aligned */ d.addr =3D addr & TARGET_PAGE_MASK; --=20 2.43.0 From nobody Sat Nov 15 22:35:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746135043; cv=none; d=zohomail.com; s=zohoarc; b=BHQUBOUDEU4etwyGyRoobDvl4OMjTdwDI8krXBWq3fTk/pm86I30wPAKpUhhp8j7npzobklygesQiT74KeHY93fJw5jj/3yX+pKcFmi2E0tTRdFxhjLNYt8UqJ/mOeiQDV8BRFW2rKMfYeWzoW7ttGnt2Y85ow1Or1N7bbm4nUs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746135043; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/ldst_common.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/accel/tcg/ldst_common.c.inc b/accel/tcg/ldst_common.c.inc index 9791a4e9ef..57f3e06192 100644 --- a/accel/tcg/ldst_common.c.inc +++ b/accel/tcg/ldst_common.c.inc @@ -123,7 +123,7 @@ void helper_st_i128(CPUArchState *env, uint64_t addr, I= nt128 val, MemOpIdx oi) * Load helpers for cpu_ldst.h */ =20 -static void plugin_load_cb(CPUArchState *env, abi_ptr addr, +static void plugin_load_cb(CPUArchState *env, vaddr addr, uint64_t value_low, uint64_t value_high, MemOpIdx oi) @@ -193,7 +193,7 @@ Int128 cpu_ld16_mmu(CPUArchState *env, vaddr addr, * Store helpers for cpu_ldst.h */ =20 -static void plugin_store_cb(CPUArchState *env, abi_ptr addr, +static void plugin_store_cb(CPUArchState *env, vaddr addr, uint64_t value_low, uint64_t value_high, MemOpIdx oi) --=20 2.43.0 From nobody Sat Nov 15 22:35:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746135134; cv=none; d=zohomail.com; s=zohoarc; b=ngY2cbMpDcXCIUsyimMZNP240d0BTmNs2gLGCQdhy1EmR1ZkA/EJzkY+ZqCk7kLknI3YU2FkWFGCcsZbjm8ccGX6ddag9MWPXbOYD2PlJ1KgbJ7ZG0xIpC47NS5EldYvDAED/YGHcMFm/ktDsTD9iUeiL8LmPqBfhFYbOJ2k68M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746135134; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=0HNVWGhJHja66UOEh7K5lL2rGWNIhIiIn3A57097VKo=; b=UUfamzW0stIwZO/gD+WljU/aUSFqabPONB+72thZlg92nOhjuDvV04d3f1+Z0Nl/0q8ovVVX9+m13JGpqwiGBdglNv4F2ogOlHBCtGZx1JR8JJj/xSFi3q34ZRmGdcjm9ud1kS+6ApI2PR/AIFIP2Q6oGGez3v/Kt9OwJyE8eEg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746135134274463.83754172663146; Thu, 1 May 2025 14:32:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAbPV-0006Z9-KG; Thu, 01 May 2025 17:25:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAbOu-0005FM-D1 for qemu-devel@nongnu.org; Thu, 01 May 2025 17:25:00 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAbOs-0002EB-7w for qemu-devel@nongnu.org; Thu, 01 May 2025 17:24:59 -0400 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-739be717eddso1241859b3a.2 for ; Thu, 01 May 2025 14:24:57 -0700 (PDT) Received: from stoup.. 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Thu, 01 May 2025 14:24:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 53/59] accel/tcg: Build cputlb.c once Date: Thu, 1 May 2025 14:21:07 -0700 Message-ID: <20250501212113.2961531-54-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746135135383124100 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 3 ++- accel/tcg/meson.build | 5 +---- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 35c467aace..5f6d7c601c 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -25,7 +25,8 @@ #include "accel/tcg/probe.h" #include "exec/page-protection.h" #include "system/memory.h" -#include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/cpu-ldst-common.h" +#include "accel/tcg/cpu-mmu-index.h" #include "exec/cputlb.h" #include "exec/tb-flush.h" #include "system/ram_addr.h" diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index d6bd304add..9b86051b82 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -25,15 +25,12 @@ tcg_specific_ss =3D ss.source_set() tcg_specific_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user-exec.c'= )) specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss) =20 -specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files( - 'cputlb.c', -)) - libuser_ss.add(files( 'user-exec-stub.c', )) =20 libsystem_ss.add(files( + 'cputlb.c', 'icount-common.c', 'monitor.c', 'tcg-accel-ops.c', --=20 2.43.0 From nobody Sat Nov 15 22:35:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-740590610desm135897b3a.146.2025.05.01.14.24.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 May 2025 14:24:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746134696; x=1746739496; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fe29IZ11mCzFvm4KslVvKmO7MK48jjA31j/L8P/5R8A=; b=YdXwbRixG56l7kkFfVNyAA+iHvW8Kn4OKLpmsxieJWK83HYwDp7hvDQbVJ/Ibdb3N0 jC9L9rH3pyTX/UFTmMsmyWjMEo5ziBE0DXEyUC8rcWIyj4HfhHXAlNK5iLQbhoFDbe/+ SEflJMJ9E/8KeWilXe2J/oblWMMqQ+yc3085j5R05B/HGw1bCixKWE1DEB3kxsg0BHG8 EsgoWQqPePdAJnsWgljEMPier0ysQwRltQ5+AAhrDx66r6F+lglBdllmqoC7Z1w4i7sV Ap7dfnpg5Y6fEHM2qTHVMuplvHIbj77BXlvyrOLG8NnHRqotX5rJCSrc0x09RBdlqk8z y1aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746134696; x=1746739496; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fe29IZ11mCzFvm4KslVvKmO7MK48jjA31j/L8P/5R8A=; b=ZJTMyIdy31i81W1Po/3rZhUYFV2ft82DNrMdcqW+eRQogkBsnX7w0TjD1WhbwzCfF3 /xiPbyinGPdraLzRdLorAOPy3zWSSNVrvQdN+xaJ7ed0vWOJ/sHo3IUfOzq4rXddGR74 J486W/BhCSs23l043cXmA6ysT3oIttVZTVbV+mN8lTcbK9QYENSsqIZubuF05xmzgiOz XmTxRsdD7w0GWOLR+uit0NgT2RSR7WiYtqwEE/SPPJhvg70C7Y1gH/bauencsPt59VmJ nP9Jy8L6+NrYNJrDGXFuXnQvI+bP0hQUwP0FPyaArM4MT9Hpef98VD5ipXV8AW3UhSs2 ygJQ== X-Gm-Message-State: AOJu0Yw4ZV62yiWc6uxcItGhW/ZIiZ6uwcoUWw8FX8zvOc1eDbem6AZW 5MwovggF91eHHo3NtkfX7sBEr1WekPFyKojt4Q6m9BXmryRfuggdYpDJEzjmmQo9YdMvegUAE68 5 X-Gm-Gg: ASbGncviGj2HqhyGE8swxLnb/i8kRT9fSTRDCOjl7UyZ4WqJ11XUp87RgDV523+9S1b tVLL4vBSB/ookf6cLDw1HfW2JgZJjk60dSgwI2zW9nizJiCQJgJbSwNC3TPoGq/1chqXMfTNugF PDGLHMX4HjNIb2QRbssS/5EaKnKgJOU6GcDFksUrrCLss3Y8N19zDDr5wRsik5EOoLMfXghM2kP ocopmgXmy92Icc6Ogu1IK7fE+BRqRycDVXUevSf358nSnBVXJ6qqDdd3MnErf8liwzaOKwhHJbH R7xUoOXZ+5reBIpERWoInx3d4HClKL5k8VOtt2pf2VzPjWlPds/isly0zYjLirqz5dN99n4FDig = X-Google-Smtp-Source: AGHT+IHEUPLRLy5Zhi/tOlT1fxx/dKDNQd6ZqrlTOvuuFgCPtzmXonbnajDLWzXdGi9si5L5B9NYag== X-Received: by 2002:a05:6a00:44cb:b0:73e:1e21:b653 with SMTP id d2e1a72fcca58-740588f2301mr577758b3a.5.1746134696210; Thu, 01 May 2025 14:24:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 54/59] include/user: Convert GUEST_ADDR_MAX to a variable Date: Thu, 1 May 2025 14:21:08 -0700 Message-ID: <20250501212113.2961531-55-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746134834159124100 Content-Type: text/plain; charset="utf-8" Remove GUEST_ADDR_MAX and add guest_addr_max. Initialize it in *-user/main.c, after reserved_va. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/user/guest-host.h | 27 +++++++-------------------- accel/tcg/user-exec.c | 4 ++-- bsd-user/main.c | 8 ++++++++ linux-user/main.c | 8 ++++++++ 4 files changed, 25 insertions(+), 22 deletions(-) diff --git a/include/user/guest-host.h b/include/user/guest-host.h index 8d2079bbbb..8e10d36948 100644 --- a/include/user/guest-host.h +++ b/include/user/guest-host.h @@ -23,23 +23,11 @@ extern unsigned long reserved_va; =20 /* - * Limit the guest addresses as best we can. - * - * When not using -R reserved_va, we cannot really limit the guest - * to less address space than the host. For 32-bit guests, this - * acts as a sanity check that we're not giving the guest an address - * that it cannot even represent. For 64-bit guests... the address - * might not be what the real kernel would give, but it is at least - * representable in the guest. - * - * TODO: Improve address allocation to avoid this problem, and to - * avoid setting bits at the top of guest addresses that might need - * to be used for tags. + * The last byte of the guest address space. + * If reserved_va is non-zero, guest_addr_max matches. + * If reserved_va is zero, guest_addr_max equals the full guest space. */ -#define GUEST_ADDR_MAX_ \ - ((MIN_CONST(TARGET_VIRT_ADDR_SPACE_BITS, TARGET_ABI_BITS) <=3D 32) ? \ - UINT32_MAX : ~0ul) -#define GUEST_ADDR_MAX (reserved_va ? : GUEST_ADDR_MAX_) +extern unsigned long guest_addr_max; =20 #ifndef TARGET_TAGGED_ADDRESSES static inline abi_ptr cpu_untagged_addr(CPUState *cs, abi_ptr x) @@ -61,17 +49,16 @@ static inline void *g2h(CPUState *cs, abi_ptr x) =20 static inline bool guest_addr_valid_untagged(abi_ulong x) { - return x <=3D GUEST_ADDR_MAX; + return x <=3D guest_addr_max; } =20 static inline bool guest_range_valid_untagged(abi_ulong start, abi_ulong l= en) { - return len - 1 <=3D GUEST_ADDR_MAX && start <=3D GUEST_ADDR_MAX - len = + 1; + return len - 1 <=3D guest_addr_max && start <=3D guest_addr_max - len = + 1; } =20 #define h2g_valid(x) \ - (HOST_LONG_BITS <=3D TARGET_VIRT_ADDR_SPACE_BITS || \ - (uintptr_t)(x) - guest_base <=3D GUEST_ADDR_MAX) + ((uintptr_t)(x) - guest_base <=3D guest_addr_max) =20 #define h2g_nocheck(x) ({ \ uintptr_t __ret =3D (uintptr_t)(x) - guest_base; \ diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index adc5296ba5..f674fd875e 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -500,7 +500,7 @@ void page_set_flags(vaddr start, vaddr last, int flags) guest address space. If this assert fires, it probably indicates a missing call to h2g_valid. */ assert(start <=3D last); - assert(last <=3D GUEST_ADDR_MAX); + assert(last <=3D guest_addr_max); /* Only set PAGE_ANON with new mappings. */ assert(!(flags & PAGE_ANON) || (flags & PAGE_RESET)); assert_memory_lock(); @@ -621,7 +621,7 @@ vaddr page_find_range_empty(vaddr min, vaddr max, vaddr= len, vaddr align) vaddr len_m1, align_m1; =20 assert(min <=3D max); - assert(max <=3D GUEST_ADDR_MAX); + assert(max <=3D guest_addr_max); assert(len !=3D 0); assert(is_power_of_2(align)); assert_memory_lock(); diff --git a/bsd-user/main.c b/bsd-user/main.c index fa7645a56e..603fc80ba7 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -89,6 +89,7 @@ bool have_guest_base; #endif =20 unsigned long reserved_va; +unsigned long guest_addr_max; =20 const char *interp_prefix =3D CONFIG_QEMU_INTERP_PREFIX; const char *qemu_uname_release; @@ -500,6 +501,13 @@ int main(int argc, char **argv) /* MAX_RESERVED_VA + 1 is a large power of 2, so is aligned. */ reserved_va =3D max_reserved_va; } + if (reserved_va !=3D 0) { + guest_addr_max =3D reserved_va; + } else if (MIN(TARGET_VIRT_ADDR_SPACE_BITS, TARGET_ABI_BITS) <=3D 32) { + guest_addr_max =3D UINT32_MAX; + } else { + guest_addr_max =3D ~0ul; + } =20 if (getenv("QEMU_STRACE")) { do_strace =3D 1; diff --git a/linux-user/main.c b/linux-user/main.c index 4af7f49f38..5ac5b55dc6 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -122,6 +122,7 @@ static const char *last_log_filename; #endif =20 unsigned long reserved_va; +unsigned long guest_addr_max; =20 static void usage(int exitcode); =20 @@ -858,6 +859,13 @@ int main(int argc, char **argv, char **envp) /* MAX_RESERVED_VA + 1 is a large power of 2, so is aligned. */ reserved_va =3D max_reserved_va; } + if (reserved_va !=3D 0) { + guest_addr_max =3D reserved_va; + } else if (MIN(TARGET_VIRT_ADDR_SPACE_BITS, TARGET_ABI_BITS) <=3D 32) { + guest_addr_max =3D UINT32_MAX; + } else { + guest_addr_max =3D ~0ul; + } =20 /* * Temporarily disable --=20 2.43.0 From nobody Sat Nov 15 22:35:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746135083; cv=none; d=zohomail.com; s=zohoarc; b=JZshwKoQxyliw5vkYqYbjWIMDfBQoQ6SP7Ht45ZnDAqebSUTPf7G9EfQSVkpcaY0OvS1m7xwI2wZ7jCW1RpwEYXCYIOtmDrZbafohGq8lNyf0uQf1DRg4jBldwG9ehxhTBX/cKMiHL4c9WWN2lE1Kn5ctUYx76ES4BWYm3D/4SM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746135083; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=PA8iG/6Wck7wG5tIJ+lEJmOSQS/i8rOew0LoQTBL9os=; b=kqKm0C92vShkuRViqSGKh8bLePsGmTZg0E1SUiIFTM0thOzoGJEAO2Suerxzz0vZ+zaZFSqEaemmbi1+rBgmJ86bYWONX9z1Cw5n6tK+9QgJTwfwGpbsjlq8KobYZ7YBLJROmig1HMVk6SVxJ8MfS6sMQfdPN83BnoTW2AyfKdc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746135083544754.5842460847709; Thu, 1 May 2025 14:31:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAbPr-0008AB-KM; Thu, 01 May 2025 17:25:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAbOu-0005GJ-HL for qemu-devel@nongnu.org; Thu, 01 May 2025 17:25:01 -0400 Received: from mail-pg1-x52e.google.com ([2607:f8b0:4864:20::52e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAbOs-0002EG-Bz for qemu-devel@nongnu.org; Thu, 01 May 2025 17:25:00 -0400 Received: by mail-pg1-x52e.google.com with SMTP id 41be03b00d2f7-af5139ad9a2so1061394a12.1 for ; Thu, 01 May 2025 14:24:57 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-740590610desm135897b3a.146.2025.05.01.14.24.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 May 2025 14:24:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746134697; x=1746739497; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PA8iG/6Wck7wG5tIJ+lEJmOSQS/i8rOew0LoQTBL9os=; b=lmr4dlizquMePdz8PnI9kLCG35RvcyejyBLZfbFh6Gs+rAucS4BFjGePTZ03RLHEp6 +1OxL59zCojU7/ZGgeATU3kfV3cq3hWZb2fxq4d2Ocfs9PyKl7vBzdy9FpNmxZrYCbnS GrfXw0Fdu7cpanzY+j3KETCCtW682G968o2+5/jZ+WP03hi88HtZp7M2hwD9oCojhH37 /gDXCZr1WmzDnUbhoh6V/q09ULvYwEJKadlIQH0b9YLBScr5qJUWN6oq2+cbrIWp5lCc 3CrigixEoasinsjUhMBU4YpCaGHi6KGeImlxOG3YHxSCZvGSx6tA6PgnQF5TOB1wR6g/ 3JUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746134697; x=1746739497; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PA8iG/6Wck7wG5tIJ+lEJmOSQS/i8rOew0LoQTBL9os=; b=aqFQWgN7RUCmlGW71zTmu4Ql1nw2oCSTNCIMs5Yvh04yDnmX9qML5SntQrrzl+uSLF ibfwrLf1/kIFAWF2ZXauUEMOGDI+jyymX/m4lEeFBry+JKQprP/FLlmTKwTKdlI3+kTT Nq2mXQnTrY0WPGFMGN3kvD+kKQ5sBav7NWTUztsB+v5B/wYm22sWgqX5fziYFQ/oqeTU IBH1XscJ2gsfNrXjkqjrLZbZCRRG33XjKX6z6RHOZC16s0Lllhn0QauyCtin1/8JGJ3x otYKAKF/tmKjnEcJaaLt+iJAi45iLIjxRgQzeJ7CWV56jQ8vtjT0xHJEqXoJljmDWNbh qkIw== X-Gm-Message-State: AOJu0YxSpIUfdfJzirwKksLpE3x3uFf3PDNDnUrmToIMoxPp/HpSuZxo N9brgF42DtKKdqz0GqOi2+1fh94aC9Ex0RgTu+02WlNiBJ4qILwthsu034rwedUt5Bbl5NENrvn i X-Gm-Gg: ASbGncsjhUcmouiucb5GX4048+zv4vKSLDJ6TAsEACHoqhuBgbSGnKAlXzPyqc1pyhB NYrHE6j/XLoHr46cGlFrOpRV6Wa3q/miuH/rkM8grhmbZ72QP1bvNVZhh5YByjuN+z9bNLCtGMD 84v6fflOlTdtutJIlMJrCj/QVoMVFumD+ivFxYdIQId4C0B2UnMVAt24Q33Xd4GgBvJPsKSDpsx S55LtMpr7G1KaU2/uOk/uG04P9kWJpVIZk/BgN/KHldQfE+/Zu/RH07XvYt7ITkI9hbVTyxHmHW JOHB0JbWvK8ctYk7gTCABf4Esj5zzK5kSGahdc0o9jfKdJuFGkqaDT4fv7hzDBNzpAz2h+ayJHQ = X-Google-Smtp-Source: AGHT+IGivPy+vLNa4yiAhHOWCCzhPbkzHj7KYAZcCtrItkCDiY8rwBJ6K1I9aSsKceoO37zNILOwWA== X-Received: by 2002:a05:6a21:32a4:b0:1f5:8072:d7f3 with SMTP id adf61e73a8af0-20cdfdf5576mr740710637.30.1746134696799; Thu, 01 May 2025 14:24:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 55/59] include/user: Use vaddr in guest-host.h Date: Thu, 1 May 2025 14:21:09 -0700 Message-ID: <20250501212113.2961531-56-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746135086692124100 Content-Type: text/plain; charset="utf-8" Replace abi_ptr and abi_ulong with vaddr. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/user/guest-host.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/include/user/guest-host.h b/include/user/guest-host.h index 8e10d36948..0656f2e356 100644 --- a/include/user/guest-host.h +++ b/include/user/guest-host.h @@ -8,7 +8,7 @@ #ifndef USER_GUEST_HOST_H #define USER_GUEST_HOST_H =20 -#include "user/abitypes.h" +#include "exec/vaddr.h" #include "user/guest-base.h" #include "cpu.h" =20 @@ -30,29 +30,29 @@ extern unsigned long reserved_va; extern unsigned long guest_addr_max; =20 #ifndef TARGET_TAGGED_ADDRESSES -static inline abi_ptr cpu_untagged_addr(CPUState *cs, abi_ptr x) +static inline vaddr cpu_untagged_addr(CPUState *cs, vaddr x) { return x; } #endif =20 /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ -static inline void *g2h_untagged(abi_ptr x) +static inline void *g2h_untagged(vaddr x) { return (void *)((uintptr_t)(x) + guest_base); } =20 -static inline void *g2h(CPUState *cs, abi_ptr x) +static inline void *g2h(CPUState *cs, vaddr x) { return g2h_untagged(cpu_untagged_addr(cs, x)); } =20 -static inline bool guest_addr_valid_untagged(abi_ulong x) +static inline bool guest_addr_valid_untagged(vaddr x) { return x <=3D guest_addr_max; } =20 -static inline bool guest_range_valid_untagged(abi_ulong start, abi_ulong l= en) +static inline bool guest_range_valid_untagged(vaddr start, vaddr len) { return len - 1 <=3D guest_addr_max && start <=3D guest_addr_max - len = + 1; } @@ -62,7 +62,7 @@ static inline bool guest_range_valid_untagged(abi_ulong s= tart, abi_ulong len) =20 #define h2g_nocheck(x) ({ \ uintptr_t __ret =3D (uintptr_t)(x) - guest_base; \ - (abi_ptr)__ret; \ + (vaddr)__ret; \ }) =20 #define h2g(x) ({ \ --=20 2.43.0 From nobody Sat Nov 15 22:35:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746135094; cv=none; d=zohomail.com; s=zohoarc; b=gPh3i44tVpG68Qau5dq1i0+eEDA0ofIxun+mg8ZZiYBWX1xKKX0sDV5yfxtiAQYivI3uW4CWpvYlCBdUG5Op7prUFs0FCtVIOekd7Q1sJgeo0qrSbyhVL2AdwGkznE0KWWkmIkg7oRZk3JLOC+UtkhYY6Nlb+vcYtNXMIsDU4Qw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746135094; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=0h/3+wci/wDkfnyuxg7Yp/2Pi7Vg2ehyC2gUBcQS+UI=; b=WvvmTvU5P1BmKWCpf4oN9lknBXwBXTvV9n6o4JGKtwl9NgQ2a0QsN0F21CMq+bnqBCNC9wmlKtkcIOlF3F6Dn0BS5HlKD7uZo+PIeKFbQ/tmtOv2bhTCLs/EQWQon0uqMGK0KH12AXC42nAF7ctwa++VgjbrSn/NU8k5SG3Re7o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746135094426471.0898073739786; Thu, 1 May 2025 14:31:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAbPq-00086Y-UZ; Thu, 01 May 2025 17:25:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAbOw-0005Ng-A6 for qemu-devel@nongnu.org; Thu, 01 May 2025 17:25:02 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAbOt-0002Eb-1J for qemu-devel@nongnu.org; Thu, 01 May 2025 17:25:01 -0400 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-73c17c770a7so2106561b3a.2 for ; Thu, 01 May 2025 14:24:58 -0700 (PDT) Received: from stoup.. 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Thu, 01 May 2025 14:24:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 56/59] accel/tcg: Move TARGET_TAGGED_ADDRESSES to TCGCPUOps.untagged_addr Date: Thu, 1 May 2025 14:21:10 -0700 Message-ID: <20250501212113.2961531-57-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746135097196019100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/accel/tcg/cpu-ops.h | 7 +++++++ include/user/guest-host.h | 8 +++++--- target/arm/cpu-param.h | 7 +------ target/arm/cpu.h | 32 +------------------------------- target/arm/cpu.c | 27 ++++++++++++++++++++++++++- 5 files changed, 40 insertions(+), 41 deletions(-) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index 23cd6af0b2..cd22e5d5b9 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -157,6 +157,13 @@ struct TCGCPUOps { */ void (*record_sigbus)(CPUState *cpu, vaddr addr, MMUAccessType access_type, uintptr_t ra); + + /** + * untagged_addr: Remove an ignored tag from an address + * @cpu: cpu context + * @addr: tagged guest address + */ + vaddr (*untagged_addr)(CPUState *cs, vaddr addr); #else /** @do_interrupt: Callback for interrupt handling. */ void (*do_interrupt)(CPUState *cpu); diff --git a/include/user/guest-host.h b/include/user/guest-host.h index 0656f2e356..8f7ef75896 100644 --- a/include/user/guest-host.h +++ b/include/user/guest-host.h @@ -10,7 +10,7 @@ =20 #include "exec/vaddr.h" #include "user/guest-base.h" -#include "cpu.h" +#include "accel/tcg/cpu-ops.h" =20 /* * If non-zero, the guest virtual address space is a contiguous subset @@ -29,12 +29,14 @@ extern unsigned long reserved_va; */ extern unsigned long guest_addr_max; =20 -#ifndef TARGET_TAGGED_ADDRESSES static inline vaddr cpu_untagged_addr(CPUState *cs, vaddr x) { + const TCGCPUOps *tcg_ops =3D cs->cc->tcg_ops; + if (tcg_ops->untagged_addr) { + return tcg_ops->untagged_addr(cs, x); + } return x; } -#endif =20 /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ static inline void *g2h_untagged(vaddr x) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 5c5bc8a009..8b46c7c570 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -17,14 +17,9 @@ #endif =20 #ifdef CONFIG_USER_ONLY -# ifdef TARGET_AARCH64 -# define TARGET_TAGGED_ADDRESSES -# ifdef __FreeBSD__ -# define TARGET_PAGE_BITS 12 -# else +# if defined(TARGET_AARCH64) && defined(CONFIG_LINUX) /* Allow user-only to vary page size from 4k */ # define TARGET_PAGE_BITS_VARY -# endif # else # define TARGET_PAGE_BITS 12 # endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index be4449ca06..23720b2b17 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -783,12 +783,9 @@ typedef struct CPUArchState { #else /* CONFIG_USER_ONLY */ /* For usermode syscall translation. */ bool eabi; -#endif /* CONFIG_USER_ONLY */ - -#ifdef TARGET_TAGGED_ADDRESSES /* Linux syscall tagged address support */ bool tagged_addr_enable; -#endif +#endif /* CONFIG_USER_ONLY */ } CPUARMState; =20 static inline void set_feature(CPUARMState *env, int feature) @@ -3217,34 +3214,7 @@ extern const uint64_t pred_esz_masks[5]; #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) =20 #ifdef CONFIG_USER_ONLY - #define TARGET_PAGE_DATA_SIZE (TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1)) - -#ifdef TARGET_TAGGED_ADDRESSES -/** - * cpu_untagged_addr: - * @cs: CPU context - * @x: tagged address - * - * Remove any address tag from @x. This is explicitly related to the - * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. - * - * There should be a better place to put this, but we need this in - * include/exec/cpu_ldst.h, and not some place linux-user specific. - */ -static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) -{ - CPUARMState *env =3D cpu_env(cs); - if (env->tagged_addr_enable) { - /* - * TBI is enabled for userspace but not kernelspace addresses. - * Only clear the tag if bit 55 is clear. - */ - x &=3D sextract64(x, 0, 56); - } - return x; -} -#endif /* TARGET_TAGGED_ADDRESSES */ #endif /* CONFIG_USER_ONLY */ =20 #endif diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2020aec54a..45cb6fd7ee 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2671,7 +2671,31 @@ static const char *arm_gdb_get_core_xml_file(CPUStat= e *cs) return "arm-core.xml"; } =20 -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY +/** + * aarch64_untagged_addr: + * + * Remove any address tag from @x. This is explicitly related to the + * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. + * + * There should be a better place to put this, but we need this in + * include/exec/cpu_ldst.h, and not some place linux-user specific. + * + * Note that arm-*-user will never set tagged_addr_enable. + */ +static vaddr aarch64_untagged_addr(CPUState *cs, vaddr x) +{ + CPUARMState *env =3D cpu_env(cs); + if (env->tagged_addr_enable) { + /* + * TBI is enabled for userspace but not kernelspace addresses. + * Only clear the tag if bit 55 is clear. + */ + x &=3D sextract64(x, 0, 56); + } + return x; +} +#else #include "hw/core/sysemu-cpu-ops.h" =20 static const struct SysemuCPUOps arm_sysemu_ops =3D { @@ -2702,6 +2726,7 @@ static const TCGCPUOps arm_tcg_ops =3D { #ifdef CONFIG_USER_ONLY .record_sigsegv =3D arm_cpu_record_sigsegv, .record_sigbus =3D arm_cpu_record_sigbus, + .untagged_addr =3D aarch64_untagged_addr, #else .tlb_fill_align =3D arm_cpu_tlb_fill_align, .cpu_exec_interrupt =3D arm_cpu_exec_interrupt, --=20 2.43.0 From nobody Sat Nov 15 22:35:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746134831; cv=none; d=zohomail.com; s=zohoarc; b=GGCXed5gPs4DH0T2mxF9O3S2OEcYXWZSJeXXan/EJBncPrF32G7NOUN0SqsQzkVIvHvEHLEgh6Pc1gR75PgUn6rIDZaK6DTjfewoOWVCGeubFzo0QhIiDMXLmsxf4dP7HSD6Ke7tEuTpctPL2L/AMKXZ4uDLiGaAzqBhyQ1mgmQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746134831; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=M7zJ1IIf93+bko/Emk4HM+tkDtTMCkTvdeVlwV8Sclo=; b=ZAqvaOkAhO/o/Iih8GngPar4NER4pc8FFKExGCwhRN5F5OniFZWx5XlaVWHMsVVwWv/2SBwn9ePI7+3pnlHeYXX/rIptpzb4ZdnUuAlzcwOUxg8BRz6Unh3MZ24Yznj4wX9wv1bZMrKcjTlCD3j0PvNt6wtQuki0ehv/+N2MiEw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746134831850904.2882089029035; Thu, 1 May 2025 14:27:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAbPz-0000Yb-44; Thu, 01 May 2025 17:26:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAbOw-0005PJ-IH for qemu-devel@nongnu.org; Thu, 01 May 2025 17:25:03 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAbOt-0002Ep-Hm for qemu-devel@nongnu.org; Thu, 01 May 2025 17:25:02 -0400 Received: by mail-pg1-x533.google.com with SMTP id 41be03b00d2f7-af579e46b5dso992185a12.3 for ; Thu, 01 May 2025 14:24:59 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-740590610desm135897b3a.146.2025.05.01.14.24.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 May 2025 14:24:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746134698; x=1746739498; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=M7zJ1IIf93+bko/Emk4HM+tkDtTMCkTvdeVlwV8Sclo=; b=p/d/X0G+OhdgMhXNT0z5f5d9/uljfF4qPh2IApE6DohCGEwbpzC4r4HdhLx3ThCDVd Uu95fNxu3J73ueFYqCCAKojYVtitivjDLZHLNgqMynmVVb0IrXJRU1ERe1xg88cUq3yy TDLVrsGKQm+EQfU3YAGhZlnhbBmKyYIPH+ip0ja+7n0iUcNdDUJqGTUbEWupiDWM/C6v NCZ1W9o3owH4we6W5DuFCpi3DvFPhRYcpoFb6LrsSgoS6cig5rXI8ag8fR89iHCCbkFX 0m8h08DOC3AhbOhQ+enWeM8bECuJoXnekSdGbB9ogjGdi4gO+LeXNNhazQ6zc+9j6k1A CaPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746134698; x=1746739498; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=M7zJ1IIf93+bko/Emk4HM+tkDtTMCkTvdeVlwV8Sclo=; b=Vm5etJnxzRFFJJvFDOOADiO2Xn0rg2qVqbII9YbmMXnGe0oat1acwjpBz0p3VejNsO +Odznf31H7cYxTEKNqE0gu4ZIsNjQuqitCJQmhj9YtcY7PLKGAKUtDENfkjNoBIbX5b0 Vur27CInx+r4a9Q/r4pnSUuAZTprSbhe+I+0T6WomMb4k4j3rEY7vYt5+cHJatkTgq4c /42EAAZ02CbeVt/FLNKyLP80Jb0g2uJBBDxlUxOlLydUINIoTeUMVRYaIejlGq9M9et7 eYXnHW1odmqXa1t3/2FcDSK1J1lJ+thuZBCFAB8vZ/hSCkN5ecHpBDL923gNQS6/e2un 69bA== X-Gm-Message-State: AOJu0YxMohgJFP8vsANIL+KytJBzvEi818ZPKDubS1UZIK8WbtxsPxl6 a7lJ7qVBL6sWtCkojYJ7rkszSfKqcsKCKecgZeaDUoUaorow13TIWXDxWdAHOTOfsVKW1dnkBo+ Q X-Gm-Gg: ASbGncs1tQOEBW+k9vNmS43/IOl+d2r6nguuiS99XZY6IZUPtxbLJZnHegVf/U0Ut4A hnbpoV8sPYjCeJfGAklb76d4VFj0Jtq9/ATkQqIHt51O/kSNlKrJa8CBZISSTw1T546SO7RC1cX VMPKMPWrCY5iuarg0F1rs+dseVNS69tdOjuAxfpUy2z35xRbQPAbDgdm4WueRcdt9VAqUlLHdXq mNEVIwSPE1SjqoGCY0xFrlGIgLdsb0CGLk7LQ35p+KTiDIN5Rb6+5dVGeX7J78rPbrhGaHxXxl3 NQoFjzJ5/ADzvNZIo5vjk1JZ2o55MfF0pRmQsEXJELUeHQEkkLLb42at30W5tes40hC4SX1tfWE = X-Google-Smtp-Source: AGHT+IGiFU0TO1N1t4T3C7X1u7RBo0pCO5ATlbcj4SRwph+NLwAYoKwzdFH59cBrYwUViJpYVLRKSw== X-Received: by 2002:a05:6a21:7103:b0:204:4573:d855 with SMTP id adf61e73a8af0-20cde3746e9mr658743637.9.1746134698085; Thu, 01 May 2025 14:24:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 57/59] accel/tcg: Remove TARGET_PAGE_DATA_SIZE Date: Thu, 1 May 2025 14:21:11 -0700 Message-ID: <20250501212113.2961531-58-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746134834147124100 Content-Type: text/plain; charset="utf-8" This macro is used by only one target, and even then under unusual conditions -- AArch64 with mmap's PROT_MTE flag. Since page size for aarch64-linux-user is variable, the per-page data size is also variable. Since page_reset_target_data via target_munmap does not have ready access to CPUState, simply pass in the size from the first allocation and remember that. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/user/page-protection.h | 8 +++++--- target/arm/cpu.h | 4 ---- accel/tcg/user-exec.c | 26 ++++++++++++++++---------- target/arm/tcg/mte_helper.c | 4 ++-- 4 files changed, 23 insertions(+), 19 deletions(-) diff --git a/include/user/page-protection.h b/include/user/page-protection.h index 86143212fd..4bde664e4a 100644 --- a/include/user/page-protection.h +++ b/include/user/page-protection.h @@ -73,18 +73,20 @@ bool page_check_range_empty(vaddr start, vaddr last); vaddr page_find_range_empty(vaddr min, vaddr max, vaddr len, vaddr align); =20 /** - * page_get_target_data(address) + * page_get_target_data * @address: guest virtual address + * @size: per-page size * - * Return TARGET_PAGE_DATA_SIZE bytes of out-of-band data to associate + * Return @size bytes of out-of-band data to associate * with the guest page at @address, allocating it if necessary. The * caller should already have verified that the address is valid. + * The value of @size must be the same for every call. * * The memory will be freed when the guest page is deallocated, * e.g. with the munmap system call. */ __attribute__((returns_nonnull)) -void *page_get_target_data(vaddr address); +void *page_get_target_data(vaddr address, size_t size); =20 typedef int (*walk_memory_regions_fn)(void *, vaddr, vaddr, int); int walk_memory_regions(void *, walk_memory_regions_fn); diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 23720b2b17..6ed6409cb7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3213,8 +3213,4 @@ extern const uint64_t pred_esz_masks[5]; #define LOG2_TAG_GRANULE 4 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) =20 -#ifdef CONFIG_USER_ONLY -#define TARGET_PAGE_DATA_SIZE (TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1)) -#endif /* CONFIG_USER_ONLY */ - #endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index f674fd875e..46b1e97c30 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -870,7 +870,6 @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState *e= nv, vaddr addr, return addr; } =20 -#ifdef TARGET_PAGE_DATA_SIZE /* * Allocate chunks of target data together. For the only current user, * if we allocate one hunk per page, we have overhead of 40/128 or 40%. @@ -886,10 +885,16 @@ typedef struct TargetPageDataNode { } TargetPageDataNode; =20 static IntervalTreeRoot targetdata_root; +static size_t target_page_data_size; =20 void page_reset_target_data(vaddr start, vaddr last) { IntervalTreeNode *n, *next; + size_t size =3D target_page_data_size; + + if (likely(size =3D=3D 0)) { + return; + } =20 assert_memory_lock(); =20 @@ -920,17 +925,22 @@ void page_reset_target_data(vaddr start, vaddr last) n_last =3D MIN(last, n->last); p_len =3D (n_last + 1 - n_start) >> TARGET_PAGE_BITS; =20 - memset(t->data + p_ofs * TARGET_PAGE_DATA_SIZE, 0, - p_len * TARGET_PAGE_DATA_SIZE); + memset(t->data + p_ofs * size, 0, p_len * size); } } =20 -void *page_get_target_data(vaddr address) +void *page_get_target_data(vaddr address, size_t size) { IntervalTreeNode *n; TargetPageDataNode *t; vaddr page, region, p_ofs; =20 + /* Remember the size from the first call, and it should be constant. */ + if (unlikely(target_page_data_size !=3D size)) { + assert(target_page_data_size =3D=3D 0); + target_page_data_size =3D size; + } + page =3D address & TARGET_PAGE_MASK; region =3D address & TBD_MASK; =20 @@ -945,8 +955,7 @@ void *page_get_target_data(vaddr address) mmap_lock(); n =3D interval_tree_iter_first(&targetdata_root, page, page); if (!n) { - t =3D g_malloc0(sizeof(TargetPageDataNode) - + TPD_PAGES * TARGET_PAGE_DATA_SIZE); + t =3D g_malloc0(sizeof(TargetPageDataNode) + TPD_PAGES * size); n =3D &t->itree; n->start =3D region; n->last =3D region | ~TBD_MASK; @@ -957,11 +966,8 @@ void *page_get_target_data(vaddr address) =20 t =3D container_of(n, TargetPageDataNode, itree); p_ofs =3D (page - region) >> TARGET_PAGE_BITS; - return t->data + p_ofs * TARGET_PAGE_DATA_SIZE; + return t->data + p_ofs * size; } -#else -void page_reset_target_data(vaddr start, vaddr last) { } -#endif /* TARGET_PAGE_DATA_SIZE */ =20 /* The system-mode versions of these helpers are in cputlb.c. */ =20 diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 13d7ac0097..0efc18a181 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -37,7 +37,6 @@ #include "qemu/guest-random.h" #include "mte_helper.h" =20 - static int choose_nonexcluded_tag(int tag, int offset, uint16_t exclude) { if (exclude =3D=3D 0xffff) { @@ -63,6 +62,7 @@ uint8_t *allocation_tag_mem_probe(CPUARMState *env, int p= tr_mmu_idx, bool probe, uintptr_t ra) { #ifdef CONFIG_USER_ONLY + const size_t page_data_size =3D TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE = + 1); uint64_t clean_ptr =3D useronly_clean_ptr(ptr); int flags =3D page_get_flags(clean_ptr); uint8_t *tags; @@ -83,7 +83,7 @@ uint8_t *allocation_tag_mem_probe(CPUARMState *env, int p= tr_mmu_idx, return NULL; } =20 - tags =3D page_get_target_data(clean_ptr); + tags =3D page_get_target_data(clean_ptr, page_data_size); =20 index =3D extract32(ptr, LOG2_TAG_GRANULE + 1, TARGET_PAGE_BITS - LOG2_TAG_GRANULE - 1); --=20 2.43.0 From nobody Sat Nov 15 22:35:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746135013; cv=none; d=zohomail.com; s=zohoarc; b=MDWvRu+AlRMPNrVR5WU0+vz+evUNpIgQwzN9gRSqK8sxyWIlUZ7iJ9E9dqf+f3gdJkCiDFcZVSB3gPG6IQiOPlL3QfGikfQMFgRPv9H6VPEv4s/TnEg5bXgAaQ18vtY/pkVyP8qDVfHjEmOU10Fc9m/UMcNf4gYht6smmiUBEM8= ARC-Message-Signature: i=1; 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This will change output with small values of -R reserved_va, but shouldn't affect anything else. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/user-exec.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 46b1e97c30..085da0c036 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -29,6 +29,7 @@ #include "accel/tcg/helper-retaddr.h" #include "accel/tcg/probe.h" #include "user/cpu_loop.h" +#include "user/guest-host.h" #include "qemu/main-loop.h" #include "user/page-protection.h" #include "exec/page-protection.h" @@ -202,10 +203,19 @@ int walk_memory_regions(void *priv, walk_memory_regio= ns_fn fn) static int dump_region(void *opaque, vaddr start, vaddr end, int prot) { FILE *f =3D opaque; + uint64_t mask; + int width; =20 - fprintf(f, TARGET_ABI_FMT_ptr "-" TARGET_ABI_FMT_ptr - " " TARGET_ABI_FMT_ptr " %c%c%c\n", - (abi_ptr)start, (abi_ptr)end, (abi_ptr)(end - start), + if (guest_addr_max <=3D UINT32_MAX) { + mask =3D UINT32_MAX, width =3D 8; + } else { + mask =3D UINT64_MAX, width =3D 16; + } + + fprintf(f, "%0*" PRIx64 "-%0*" PRIx64 " %0*" PRIx64 " %c%c%c\n", + width, start & mask, + width, end & mask, + width, (end - start) & mask, ((prot & PAGE_READ) ? 'r' : '-'), ((prot & PAGE_WRITE) ? 'w' : '-'), ((prot & PAGE_EXEC) ? 'x' : '-')); @@ -215,10 +225,10 @@ static int dump_region(void *opaque, vaddr start, vad= dr end, int prot) /* dump memory mappings */ void page_dump(FILE *f) { - const int length =3D sizeof(abi_ptr) * 2; + int width =3D guest_addr_max <=3D UINT32_MAX ? 8 : 16; =20 fprintf(f, "%-*s %-*s %-*s %s\n", - length, "start", length, "end", length, "size", "prot"); + width, "start", width, "end", width, "size", "prot"); walk_memory_regions(f, dump_region); } =20 @@ -1135,7 +1145,7 @@ static uint64_t do_ld8_mmu(CPUState *cpu, vaddr addr,= MemOpIdx oi, return ret; } =20 -static Int128 do_ld16_mmu(CPUState *cpu, abi_ptr addr, +static Int128 do_ld16_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi, uintptr_t ra) { void *haddr; --=20 2.43.0 From nobody Sat Nov 15 22:35:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746135134; cv=none; d=zohomail.com; s=zohoarc; b=WdDHF+2W+hZf+2uFNiOF/i5CIiIljdwTCC+6mmKj89Pv1ojETcuef9fMjM2w5aWppWex1y8cGPqjiidZNUP6fdftURmEvGnq5zo1TrjKEaT45VKc423R8QCKyvnaAIo4KBdbeViNTv3VFuLdkjXV/3if20eVB0Sz6nV3a7JbJSA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746135134; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=D8QU7G6StI/VTOXfIkZKxNy1/7wiHIoofQ7NN/1U07c=; b=fp1xDCyUYV2dtORExGUL69WxifaXRVAtO4optKcQ4mrUZAeR6McN/r3FuV10o8TBGUrQXKnBwaCrMVl76pBaCk8o2P5VMUEwb04MIxAKw0oJdI7K3AVnu2boAjNp4hsqNDElit/dkX/0tbSwR+QZx4ZhIpavUOjsQPKNJJ8i2dQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746135134064790.8495740773368; Thu, 1 May 2025 14:32:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAbQI-00012k-Ev; Thu, 01 May 2025 17:26:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAbOx-0005TI-0Z for qemu-devel@nongnu.org; Thu, 01 May 2025 17:25:03 -0400 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAbOv-0002FC-0T for qemu-devel@nongnu.org; Thu, 01 May 2025 17:25:02 -0400 Received: by mail-pg1-x52b.google.com with SMTP id 41be03b00d2f7-7fd581c2bf4so1215954a12.3 for ; Thu, 01 May 2025 14:25:00 -0700 (PDT) Received: from stoup.. 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Thu, 01 May 2025 14:24:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 59/59] accel/tcg: Build user-exec.c once Date: Thu, 1 May 2025 14:21:13 -0700 Message-ID: <20250501212113.2961531-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746135137170019100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/user-exec.c | 5 ++--- accel/tcg/meson.build | 5 +---- 2 files changed, 3 insertions(+), 7 deletions(-) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 085da0c036..f25d80e2dc 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -19,13 +19,12 @@ #include "qemu/osdep.h" #include "accel/tcg/cpu-ops.h" #include "disas/disas.h" -#include "cpu.h" #include "exec/vaddr.h" #include "exec/tlb-flags.h" #include "tcg/tcg.h" #include "qemu/bitops.h" #include "qemu/rcu.h" -#include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/cpu-ldst-common.h" #include "accel/tcg/helper-retaddr.h" #include "accel/tcg/probe.h" #include "user/cpu_loop.h" @@ -33,7 +32,7 @@ #include "qemu/main-loop.h" #include "user/page-protection.h" #include "exec/page-protection.h" -#include "exec/helper-proto.h" +#include "exec/helper-proto-common.h" #include "qemu/atomic128.h" #include "qemu/bswap.h" #include "qemu/int128.h" diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 9b86051b82..d6f533f9a1 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -21,11 +21,8 @@ endif libuser_ss.add_all(tcg_ss) libsystem_ss.add_all(tcg_ss) =20 -tcg_specific_ss =3D ss.source_set() -tcg_specific_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user-exec.c'= )) -specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss) - libuser_ss.add(files( + 'user-exec.c', 'user-exec-stub.c', )) =20 --=20 2.43.0