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Tsirkin" , Thomas Huth , Gerd Hoffmann , Kevin Wolf , Yi Liu Subject: [PATCH 18/18] hw/i386/x86-iommu: Remove X86IOMMUState::pt_supported field Date: Thu, 1 May 2025 23:04:56 +0200 Message-ID: <20250501210456.89071-19-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250501210456.89071-1-philmd@linaro.org> References: <20250501210456.89071-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::12e; envelope-from=philmd@linaro.org; helo=mail-il1-x12e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746133861858124100 The X86IOMMUState::pt_supported boolean was only set in the hw_compat_2_9[] array, via the 'pt=3Doff' property. We removed all machines using that array, lets remove that property and all the code around it, always setting the VTD_ECAP_PT capability. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/i386/x86-iommu.h | 1 - hw/i386/amd_iommu.c | 12 ++---------- hw/i386/intel_iommu.c | 13 ++----------- hw/i386/x86-iommu.c | 1 - 4 files changed, 4 insertions(+), 23 deletions(-) diff --git a/include/hw/i386/x86-iommu.h b/include/hw/i386/x86-iommu.h index bfd21649d08..d6e52b1eb6b 100644 --- a/include/hw/i386/x86-iommu.h +++ b/include/hw/i386/x86-iommu.h @@ -63,7 +63,6 @@ struct X86IOMMUState { SysBusDevice busdev; OnOffAuto intr_supported; /* Whether vIOMMU supports IR */ bool dt_supported; /* Whether vIOMMU supports DT */ - bool pt_supported; /* Whether vIOMMU supports pass-through */ QLIST_HEAD(, IEC_Notifier) iec_notifiers; /* IEC notify list */ }; =20 diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 2cf7e24a21d..516e231bf13 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -1426,7 +1426,6 @@ static AddressSpace *amdvi_host_dma_iommu(PCIBus *bus= , void *opaque, int devfn) AMDVIState *s =3D opaque; AMDVIAddressSpace **iommu_as, *amdvi_dev_as; int bus_num =3D pci_bus_num(bus); - X86IOMMUState *x86_iommu =3D X86_IOMMU_DEVICE(s); =20 iommu_as =3D s->address_spaces[bus_num]; =20 @@ -1486,15 +1485,8 @@ static AddressSpace *amdvi_host_dma_iommu(PCIBus *bu= s, void *opaque, int devfn) AMDVI_INT_ADDR_FIRST, &amdvi_dev_as->iommu_ir, 1); =20 - if (!x86_iommu->pt_supported) { - memory_region_set_enabled(&amdvi_dev_as->iommu_nodma, false); - memory_region_set_enabled(MEMORY_REGION(&amdvi_dev_as->iommu), - true); - } else { - memory_region_set_enabled(MEMORY_REGION(&amdvi_dev_as->iommu), - false); - memory_region_set_enabled(&amdvi_dev_as->iommu_nodma, true); - } + memory_region_set_enabled(&amdvi_dev_as->iommu_nodma, false); + memory_region_set_enabled(MEMORY_REGION(&amdvi_dev_as->iommu), tru= e); } return &iommu_as[devfn]->as; } diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index c980cecb4ee..cc08dc41441 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -1066,6 +1066,7 @@ static inline bool vtd_ce_type_check(X86IOMMUState *x= 86_iommu, { switch (vtd_ce_get_type(ce)) { case VTD_CONTEXT_TT_MULTI_LEVEL: + case VTD_CONTEXT_TT_PASS_THROUGH: /* Always supported */ break; case VTD_CONTEXT_TT_DEV_IOTLB: @@ -1074,12 +1075,6 @@ static inline bool vtd_ce_type_check(X86IOMMUState *= x86_iommu, return false; } break; - case VTD_CONTEXT_TT_PASS_THROUGH: - if (!x86_iommu->pt_supported) { - error_report_once("%s: PT specified but not supported", __func= __); - return false; - } - break; default: /* Unknown type */ error_report_once("%s: unknown ce type: %"PRIu32, __func__, @@ -4520,7 +4515,7 @@ static void vtd_cap_init(IntelIOMMUState *s) { X86IOMMUState *x86_iommu =3D X86_IOMMU_DEVICE(s); =20 - s->cap =3D VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND | + s->cap =3D VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND | VTD_ECAP_PT | VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS | VTD_CAP_MGAW(s->aw_bits); if (s->dma_drain) { @@ -4548,10 +4543,6 @@ static void vtd_cap_init(IntelIOMMUState *s) s->ecap |=3D VTD_ECAP_DT; } =20 - if (x86_iommu->pt_supported) { - s->ecap |=3D VTD_ECAP_PT; - } - if (s->caching_mode) { s->cap |=3D VTD_CAP_CM; } diff --git a/hw/i386/x86-iommu.c b/hw/i386/x86-iommu.c index d34a6849f4a..ca7cd953e98 100644 --- a/hw/i386/x86-iommu.c +++ b/hw/i386/x86-iommu.c @@ -129,7 +129,6 @@ static const Property x86_iommu_properties[] =3D { DEFINE_PROP_ON_OFF_AUTO("intremap", X86IOMMUState, intr_supported, ON_OFF_AUTO_AUTO), DEFINE_PROP_BOOL("device-iotlb", X86IOMMUState, dt_supported, false), - DEFINE_PROP_BOOL("pt", X86IOMMUState, pt_supported, true), }; =20 static void x86_iommu_class_init(ObjectClass *klass, const void *data) --=20 2.47.1