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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22e0bb0e770sm7644415ad.92.2025.05.01.07.55.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 May 2025 07:55:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746111328; x=1746716128; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=K93yqXiT68gefwedjtdMyWq1+8RZcqNvsUBZSLOQy7s=; b=tV3z/Cxo0QraFqqC6MCbopKi1AxuoGsesNjyQggEs/55Q2sHn6oW661WwJPqLs25UU F9KTnT1C7PIsVS6N5SKXE8KakZf7OoWrg9FQexDRhz1n0H1MZmqfHpo0/eyObKhvrvVk LU3zqzcl8+6KvKpHuMYzT/1fCeVq/xooeSwQiMtkizaRTmvcfQRPbmq4Ef2I6Z0Zr1du 1WVXMNiSxxuIxlQtwa8pKFkiCCbq5BmuU7a/Qv07QOfXEzY3vNYBuN65jiHkLVCb4YA5 l2pmpv9KaEGnRZEIIETV+UhsEBfrfJV8VdDLlUpWzJk/wVPAsdy48z8FIkAFJ7w5z9sR gyAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746111328; x=1746716128; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=K93yqXiT68gefwedjtdMyWq1+8RZcqNvsUBZSLOQy7s=; b=nlrsf1H8md96T+qRanueVnKftMutsRk66DxSgp+hMu4X1ox1LBvFkAoEWm8KApmj+u 27LTVVU/5K+rCj1weVCD4cUdLRCnBNVG3sdY81XmD3/ekSz8dXelgsfpCKTGbGcLj9R/ Q0CUPeSgEAFxoypnEmyf5NILGYW/wFqODFbsSAVqeG0AVS+BFm9PCBffGQ4VtCXrOKuU Lav/lkQdUBk2PM+jVlNNYnoljJ4UCi4VycnZ40D+btrVosUbnJ5ZZ3wq0quyxbwcu+6O Bpw9qriCdRBDdLgA54LteFY1gM0muw1oO5Ecg+4c3jcoNuX3tae9MndCqvsXD20t1gJy 5x8g== X-Gm-Message-State: AOJu0YzWXGzYP1NUetstq4Gnd2qK3/WjvUtdVYAto2j/OFiPs4nZYH6e kLB4FyZwubwCIIBb4CHHwMHKHhX92Be3LjywYuL+9gnpZzTCCidiplAh15DwIHp+ONY9uzW7+fp t X-Gm-Gg: ASbGncvEf0yzdjuVAV5C67q2wLfYh59C2tqnmo1AeA3FSOH4+Tz/3Hlfm0x0SM0siA1 nBKfV6teqmC/U7xRTd61GeLaSA1iQpwhPEc/dMxi7BGBVqD45cgXZN+SwqV0Y2YlP4eKvrUoaHR UnFxZwgt2cTUvZH6XiT7B3xP8kEV5pNzSwQv3BTfZYbgOd5ZlZ5mUqpNN2KAWsN05RTkym4JftH qTKQQYXbX5U9RXZDM0mEl1z3pzMUuH2kOq4bSh/MYq+4M4EyBMF9MzZR95M6nk+pKOi9s83bpuJ 19EvknzCq5/PC/T5Q+wdAJ9Klu7P9zg20XNF3zlZbE2wSPBWam2jml2csQBFrSnMigpnQmrpsNp EqibSoI1rlw== X-Google-Smtp-Source: AGHT+IEPtFaQdYEKO0sb5zTzRR+efeCWapldh5RlIDBphIbC38TZ4txuMGgr1ORfJn2BTQ//yIKmFQ== X-Received: by 2002:a17:902:ce82:b0:223:5241:f5ca with SMTP id d9443c01a7336-22e040bf431mr44250755ad.20.1746111327667; Thu, 01 May 2025 07:55:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 09/11] accel/tcg: Remove TARGET_PAGE_DATA_SIZE Date: Thu, 1 May 2025 07:55:17 -0700 Message-ID: <20250501145520.2695073-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501145520.2695073-1-richard.henderson@linaro.org> References: <20250501145520.2695073-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746111420635019100 Content-Type: text/plain; charset="utf-8" This macro is used by only one target, and even then under unusual conditions -- AArch64 with mmap's PROT_MTE flag. Since page size for aarch64-linux-user is variable, the per-page data size is also variable. Since page_reset_target_data via target_munmap does not have ready access to CPUState, simply pass in the size from the first allocation and remember that. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- include/user/page-protection.h | 8 +++++--- target/arm/cpu.h | 4 ---- accel/tcg/user-exec.c | 26 ++++++++++++++++---------- target/arm/tcg/mte_helper.c | 4 ++-- 4 files changed, 23 insertions(+), 19 deletions(-) diff --git a/include/user/page-protection.h b/include/user/page-protection.h index 86143212fd..4bde664e4a 100644 --- a/include/user/page-protection.h +++ b/include/user/page-protection.h @@ -73,18 +73,20 @@ bool page_check_range_empty(vaddr start, vaddr last); vaddr page_find_range_empty(vaddr min, vaddr max, vaddr len, vaddr align); =20 /** - * page_get_target_data(address) + * page_get_target_data * @address: guest virtual address + * @size: per-page size * - * Return TARGET_PAGE_DATA_SIZE bytes of out-of-band data to associate + * Return @size bytes of out-of-band data to associate * with the guest page at @address, allocating it if necessary. The * caller should already have verified that the address is valid. + * The value of @size must be the same for every call. * * The memory will be freed when the guest page is deallocated, * e.g. with the munmap system call. */ __attribute__((returns_nonnull)) -void *page_get_target_data(vaddr address); +void *page_get_target_data(vaddr address, size_t size); =20 typedef int (*walk_memory_regions_fn)(void *, vaddr, vaddr, int); int walk_memory_regions(void *, walk_memory_regions_fn); diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 23720b2b17..6ed6409cb7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3213,8 +3213,4 @@ extern const uint64_t pred_esz_masks[5]; #define LOG2_TAG_GRANULE 4 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) =20 -#ifdef CONFIG_USER_ONLY -#define TARGET_PAGE_DATA_SIZE (TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1)) -#endif /* CONFIG_USER_ONLY */ - #endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index f674fd875e..46b1e97c30 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -870,7 +870,6 @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState *e= nv, vaddr addr, return addr; } =20 -#ifdef TARGET_PAGE_DATA_SIZE /* * Allocate chunks of target data together. For the only current user, * if we allocate one hunk per page, we have overhead of 40/128 or 40%. @@ -886,10 +885,16 @@ typedef struct TargetPageDataNode { } TargetPageDataNode; =20 static IntervalTreeRoot targetdata_root; +static size_t target_page_data_size; =20 void page_reset_target_data(vaddr start, vaddr last) { IntervalTreeNode *n, *next; + size_t size =3D target_page_data_size; + + if (likely(size =3D=3D 0)) { + return; + } =20 assert_memory_lock(); =20 @@ -920,17 +925,22 @@ void page_reset_target_data(vaddr start, vaddr last) n_last =3D MIN(last, n->last); p_len =3D (n_last + 1 - n_start) >> TARGET_PAGE_BITS; =20 - memset(t->data + p_ofs * TARGET_PAGE_DATA_SIZE, 0, - p_len * TARGET_PAGE_DATA_SIZE); + memset(t->data + p_ofs * size, 0, p_len * size); } } =20 -void *page_get_target_data(vaddr address) +void *page_get_target_data(vaddr address, size_t size) { IntervalTreeNode *n; TargetPageDataNode *t; vaddr page, region, p_ofs; =20 + /* Remember the size from the first call, and it should be constant. */ + if (unlikely(target_page_data_size !=3D size)) { + assert(target_page_data_size =3D=3D 0); + target_page_data_size =3D size; + } + page =3D address & TARGET_PAGE_MASK; region =3D address & TBD_MASK; =20 @@ -945,8 +955,7 @@ void *page_get_target_data(vaddr address) mmap_lock(); n =3D interval_tree_iter_first(&targetdata_root, page, page); if (!n) { - t =3D g_malloc0(sizeof(TargetPageDataNode) - + TPD_PAGES * TARGET_PAGE_DATA_SIZE); + t =3D g_malloc0(sizeof(TargetPageDataNode) + TPD_PAGES * size); n =3D &t->itree; n->start =3D region; n->last =3D region | ~TBD_MASK; @@ -957,11 +966,8 @@ void *page_get_target_data(vaddr address) =20 t =3D container_of(n, TargetPageDataNode, itree); p_ofs =3D (page - region) >> TARGET_PAGE_BITS; - return t->data + p_ofs * TARGET_PAGE_DATA_SIZE; + return t->data + p_ofs * size; } -#else -void page_reset_target_data(vaddr start, vaddr last) { } -#endif /* TARGET_PAGE_DATA_SIZE */ =20 /* The system-mode versions of these helpers are in cputlb.c. */ =20 diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 13d7ac0097..0efc18a181 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -37,7 +37,6 @@ #include "qemu/guest-random.h" #include "mte_helper.h" =20 - static int choose_nonexcluded_tag(int tag, int offset, uint16_t exclude) { if (exclude =3D=3D 0xffff) { @@ -63,6 +62,7 @@ uint8_t *allocation_tag_mem_probe(CPUARMState *env, int p= tr_mmu_idx, bool probe, uintptr_t ra) { #ifdef CONFIG_USER_ONLY + const size_t page_data_size =3D TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE = + 1); uint64_t clean_ptr =3D useronly_clean_ptr(ptr); int flags =3D page_get_flags(clean_ptr); uint8_t *tags; @@ -83,7 +83,7 @@ uint8_t *allocation_tag_mem_probe(CPUARMState *env, int p= tr_mmu_idx, return NULL; } =20 - tags =3D page_get_target_data(clean_ptr); + tags =3D page_get_target_data(clean_ptr, page_data_size); =20 index =3D extract32(ptr, LOG2_TAG_GRANULE + 1, TARGET_PAGE_BITS - LOG2_TAG_GRANULE - 1); --=20 2.43.0