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Wed, 30 Apr 2025 23:23:56 -0700 (PDT) From: Pierrick Bouvier To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, richard.henderson@linaro.org, alex.bennee@linaro.org, Paolo Bonzini , anjo@rev.ng, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , kvm@vger.kernel.org, Pierrick Bouvier Subject: [PATCH v3 06/33] target/arm/cpu: move arm_cpu_kvm_set_irq to kvm.c Date: Wed, 30 Apr 2025 23:23:17 -0700 Message-ID: <20250501062344.2526061-7-pierrick.bouvier@linaro.org> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250501062344.2526061-1-pierrick.bouvier@linaro.org> References: <20250501062344.2526061-1-pierrick.bouvier@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746080798223019100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/kvm_arm.h | 2 ++ target/arm/cpu.c | 31 ------------------------------- target/arm/kvm-stub.c | 5 +++++ target/arm/kvm.c | 29 +++++++++++++++++++++++++++++ 4 files changed, 36 insertions(+), 31 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 7b9c7c4a148..d156c790b66 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -221,4 +221,6 @@ int kvm_arm_set_irq(int cpu, int irqtype, int irq, int = level); =20 void kvm_arm_enable_mte(Object *cpuobj, Error **errp); =20 +void arm_cpu_kvm_set_irq(void *arm_cpu, int irq, int level); + #endif diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5e951675c60..07f279fec8c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1099,37 +1099,6 @@ static void arm_cpu_set_irq(void *opaque, int irq, i= nt level) } } =20 -static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) -{ -#ifdef CONFIG_KVM - ARMCPU *cpu =3D opaque; - CPUARMState *env =3D &cpu->env; - CPUState *cs =3D CPU(cpu); - uint32_t linestate_bit; - int irq_id; - - switch (irq) { - case ARM_CPU_IRQ: - irq_id =3D KVM_ARM_IRQ_CPU_IRQ; - linestate_bit =3D CPU_INTERRUPT_HARD; - break; - case ARM_CPU_FIQ: - irq_id =3D KVM_ARM_IRQ_CPU_FIQ; - linestate_bit =3D CPU_INTERRUPT_FIQ; - break; - default: - g_assert_not_reached(); - } - - if (level) { - env->irq_line_state |=3D linestate_bit; - } else { - env->irq_line_state &=3D ~linestate_bit; - } - kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); -#endif -} - static bool arm_cpu_virtio_is_big_endian(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c index e34d3f5e6b4..4806365cdc5 100644 --- a/target/arm/kvm-stub.c +++ b/target/arm/kvm-stub.c @@ -104,3 +104,8 @@ void kvm_arm_reset_vcpu(ARMCPU *cpu) { g_assert_not_reached(); } + +void arm_cpu_kvm_set_irq(void *arm_cpu, int irq, int level) +{ + g_assert_not_reached(); +} diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 97de8c7e939..8f68aa10298 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -2468,3 +2468,32 @@ void kvm_arm_enable_mte(Object *cpuobj, Error **errp) cpu->kvm_mte =3D true; } } + +void arm_cpu_kvm_set_irq(void *arm_cpu, int irq, int level) +{ + ARMCPU *cpu =3D arm_cpu; + CPUARMState *env =3D &cpu->env; + CPUState *cs =3D CPU(cpu); + uint32_t linestate_bit; + int irq_id; + + switch (irq) { + case ARM_CPU_IRQ: + irq_id =3D KVM_ARM_IRQ_CPU_IRQ; + linestate_bit =3D CPU_INTERRUPT_HARD; + break; + case ARM_CPU_FIQ: + irq_id =3D KVM_ARM_IRQ_CPU_FIQ; + linestate_bit =3D CPU_INTERRUPT_FIQ; + break; + default: + g_assert_not_reached(); + } + + if (level) { + env->irq_line_state |=3D linestate_bit; + } else { + env->irq_line_state &=3D ~linestate_bit; + } + kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); +} --=20 2.47.2