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Move it to a tcg-specific file. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/riscv/cpu_helper.c | 97 ------------------------------------- target/riscv/tcg/tcg-cpu.c | 98 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 98 insertions(+), 97 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f2e90a9889..d5039f69a9 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -135,103 +135,6 @@ bool riscv_env_smode_dbltrp_enabled(CPURISCVState *en= v, bool virt) #endif } =20 -void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) -{ - RISCVCPU *cpu =3D env_archcpu(env); - RISCVExtStatus fs, vs; - uint32_t flags =3D 0; - bool pm_signext =3D riscv_cpu_virt_mem_enabled(env); - - *pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc; - *cs_base =3D 0; - - if (cpu->cfg.ext_zve32x) { - /* - * If env->vl equals to VLMAX, we can use generic vector operation - * expanders (GVEC) to accerlate the vector operations. - * However, as LMUL could be a fractional number. The maximum - * vector size can be operated might be less than 8 bytes, - * which is not supported by GVEC. So we set vl_eq_vlmax flag to t= rue - * only when maxsz >=3D 8 bytes. - */ - - /* lmul encoded as in DisasContext::lmul */ - int8_t lmul =3D sextract32(FIELD_EX64(env->vtype, VTYPE, VLMUL), 0= , 3); - uint32_t vsew =3D FIELD_EX64(env->vtype, VTYPE, VSEW); - uint32_t vlmax =3D vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul); - uint32_t maxsz =3D vlmax << vsew; - bool vl_eq_vlmax =3D (env->vstart =3D=3D 0) && (vlmax =3D=3D env->= vl) && - (maxsz >=3D 8); - flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); - flags =3D FIELD_DP32(flags, TB_FLAGS, SEW, vsew); - flags =3D FIELD_DP32(flags, TB_FLAGS, LMUL, - FIELD_EX64(env->vtype, VTYPE, VLMUL)); - flags =3D FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); - flags =3D FIELD_DP32(flags, TB_FLAGS, VTA, - FIELD_EX64(env->vtype, VTYPE, VTA)); - flags =3D FIELD_DP32(flags, TB_FLAGS, VMA, - FIELD_EX64(env->vtype, VTYPE, VMA)); - flags =3D FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart = =3D=3D 0); - } else { - flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, 1); - } - - if (cpu_get_fcfien(env)) { - /* - * For Forward CFI, only the expectation of a lpad at - * the start of the block is tracked via env->elp. env->elp - * is turned on during jalr translation. - */ - flags =3D FIELD_DP32(flags, TB_FLAGS, FCFI_LP_EXPECTED, env->elp); - flags =3D FIELD_DP32(flags, TB_FLAGS, FCFI_ENABLED, 1); - } - - if (cpu_get_bcfien(env)) { - flags =3D FIELD_DP32(flags, TB_FLAGS, BCFI_ENABLED, 1); - } - -#ifdef CONFIG_USER_ONLY - fs =3D EXT_STATUS_DIRTY; - vs =3D EXT_STATUS_DIRTY; -#else - flags =3D FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv); - - flags |=3D riscv_env_mmu_index(env, 0); - fs =3D get_field(env->mstatus, MSTATUS_FS); - vs =3D get_field(env->mstatus, MSTATUS_VS); - - if (env->virt_enabled) { - flags =3D FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); - /* - * Merge DISABLED and !DIRTY states using MIN. - * We will set both fields when dirtying. - */ - fs =3D MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); - vs =3D MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); - } - - /* With Zfinx, floating point is enabled/disabled by Smstateen. */ - if (!riscv_has_ext(env, RVF)) { - fs =3D (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) =3D=3D RISCV_EXC= P_NONE) - ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED; - } - - if (cpu->cfg.debug && !icount_enabled()) { - flags =3D FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enab= led); - } -#endif - - flags =3D FIELD_DP32(flags, TB_FLAGS, FS, fs); - flags =3D FIELD_DP32(flags, TB_FLAGS, VS, vs); - flags =3D FIELD_DP32(flags, TB_FLAGS, XL, env->xl); - flags =3D FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); - flags =3D FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env)); - flags =3D FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); - - *pflags =3D flags; -} - RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env) { #ifndef CONFIG_USER_ONLY diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 50782e0f0e..e67de7dfe2 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -36,6 +36,7 @@ #ifndef CONFIG_USER_ONLY #include "hw/boards.h" #include "system/tcg.h" +#include "exec/icount.h" #endif =20 /* Hash that stores user set extensions */ @@ -97,6 +98,103 @@ static int riscv_cpu_mmu_index(CPUState *cs, bool ifetc= h) return riscv_env_mmu_index(cpu_env(cs), ifetch); } =20 +void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + RISCVCPU *cpu =3D env_archcpu(env); + RISCVExtStatus fs, vs; + uint32_t flags =3D 0; + bool pm_signext =3D riscv_cpu_virt_mem_enabled(env); + + *pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc; + *cs_base =3D 0; + + if (cpu->cfg.ext_zve32x) { + /* + * If env->vl equals to VLMAX, we can use generic vector operation + * expanders (GVEC) to accerlate the vector operations. + * However, as LMUL could be a fractional number. The maximum + * vector size can be operated might be less than 8 bytes, + * which is not supported by GVEC. So we set vl_eq_vlmax flag to t= rue + * only when maxsz >=3D 8 bytes. + */ + + /* lmul encoded as in DisasContext::lmul */ + int8_t lmul =3D sextract32(FIELD_EX64(env->vtype, VTYPE, VLMUL), 0= , 3); + uint32_t vsew =3D FIELD_EX64(env->vtype, VTYPE, VSEW); + uint32_t vlmax =3D vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul); + uint32_t maxsz =3D vlmax << vsew; + bool vl_eq_vlmax =3D (env->vstart =3D=3D 0) && (vlmax =3D=3D env->= vl) && + (maxsz >=3D 8); + flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); + flags =3D FIELD_DP32(flags, TB_FLAGS, SEW, vsew); + flags =3D FIELD_DP32(flags, TB_FLAGS, LMUL, + FIELD_EX64(env->vtype, VTYPE, VLMUL)); + flags =3D FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); + flags =3D FIELD_DP32(flags, TB_FLAGS, VTA, + FIELD_EX64(env->vtype, VTYPE, VTA)); + flags =3D FIELD_DP32(flags, TB_FLAGS, VMA, + FIELD_EX64(env->vtype, VTYPE, VMA)); + flags =3D FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart = =3D=3D 0); + } else { + flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, 1); + } + + if (cpu_get_fcfien(env)) { + /* + * For Forward CFI, only the expectation of a lpad at + * the start of the block is tracked via env->elp. env->elp + * is turned on during jalr translation. + */ + flags =3D FIELD_DP32(flags, TB_FLAGS, FCFI_LP_EXPECTED, env->elp); + flags =3D FIELD_DP32(flags, TB_FLAGS, FCFI_ENABLED, 1); + } + + if (cpu_get_bcfien(env)) { + flags =3D FIELD_DP32(flags, TB_FLAGS, BCFI_ENABLED, 1); + } + +#ifdef CONFIG_USER_ONLY + fs =3D EXT_STATUS_DIRTY; + vs =3D EXT_STATUS_DIRTY; +#else + flags =3D FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv); + + flags |=3D riscv_env_mmu_index(env, 0); + fs =3D get_field(env->mstatus, MSTATUS_FS); + vs =3D get_field(env->mstatus, MSTATUS_VS); + + if (env->virt_enabled) { + flags =3D FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); + /* + * Merge DISABLED and !DIRTY states using MIN. + * We will set both fields when dirtying. + */ + fs =3D MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); + vs =3D MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); + } + + /* With Zfinx, floating point is enabled/disabled by Smstateen. */ + if (!riscv_has_ext(env, RVF)) { + fs =3D (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) =3D=3D RISCV_EXC= P_NONE) + ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED; + } + + if (cpu->cfg.debug && !icount_enabled()) { + flags =3D FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enab= led); + } +#endif + + flags =3D FIELD_DP32(flags, TB_FLAGS, FS, fs); + flags =3D FIELD_DP32(flags, TB_FLAGS, VS, vs); + flags =3D FIELD_DP32(flags, TB_FLAGS, XL, env->xl); + flags =3D FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); + flags =3D FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env)); + flags =3D FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); + + *pflags =3D flags; +} + static void riscv_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { --=20 2.43.0